An adaptive dynamic bias, output power level segmented adjustment LDO circuit

Abstract

The application belongs to the field of integrated circuits, and particularly relates to a kind of LDO circuit of adaptive dynamic biasing, output power stage segmented adjustment, comprising: main circuit and auxiliary circuit;The main circuit is used to obtain constant output voltage according to reference voltage, input voltage input to its input end is handled, and the output voltage is output through its output end;The auxiliary circuit carries out segmented adaptive dynamic control LDO's error amplifier bias current to the input voltage, and obtains the output voltage.The LDO circuit of the application mainly controls the power tube of LDO output stage by segmentation, adaptively and dynamically controls the bias current of the error amplifier of LDO, can be adjusted according to the size of load current, adaptive bias current, and through segmented control power tube, the purpose of reducing power consumption and improving response speed is achieved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuits, and specifically relates to an LDO circuit with adaptive dynamic bias and segmented adjustment of output power stage. Background Technology

[0002] Low dropout regulators (LDOs) are widely used in system-on-chip (SoC) and high-performance power supply applications due to their low cost, low noise, high precision, and simple peripheral circuitry. They provide stable, low-noise, and low-ripple voltages to downstream systems. With the rapid development of integrated circuit systems, power management chips are playing an increasingly important role in integrated systems. The widespread adoption of consumer electronics, wearable devices, automotive electronics, and medical devices has further broadened the application scope of power management chips.

[0003] Traditional LDOs such as Figure 1 As shown, the circuit mainly consists of a reference circuit VREF, an error amplifier EA, a power transistor MP, feedback resistors R1 and R2, an output capacitor COUT, and the parasitic equivalent resistance RESR of the output capacitor. These modules form the most basic LDO loop, which is stabilized through negative feedback. When the LDO output voltage rises, the feedback is transmitted to the error amplifier, which compares it with a specific voltage at the other end. This causes the error amplifier's output to rise, thereby driving the power device to reduce its output current, which in turn lowers the LDO output voltage to stabilize the circuit. Similarly, when the LDO output voltage falls, negative feedback is used to adjust and raise the output voltage.

[0004] Traditional LDOs use a large MOSFET as their power transistor, which provides the load current regardless of whether the load is no-load, light-load, or heavy-load. Furthermore, to ensure bandwidth and response speed under maximum load current conditions, the bias current of the error amplifier in a traditional LDO is a relatively large constant current, representing maximum current and maximum power dissipation across the entire load range.

[0005] The main drawbacks of traditional LDOs are as follows:

[0006] Traditional LDOs use a single, integrated power transistor. Regardless of whether the load is no-load, light-load, or heavy-load, the power transistor remains within the feedback loop. To drive the parasitic capacitance of the entire power transistor across the entire load range, the op-amp's bias current must be designed to be a relatively large constant current, making it difficult to meet low-power requirements.

[0007] Traditional low-power LDOs have a relatively small and constant bias current. When the load current changes, the bias current cannot be dynamically adjusted, making it difficult to achieve a fast response. Summary of the Invention

[0008] To address the issue that traditional LDO circuits cannot dynamically adjust the bias current when the load current changes, making it difficult to achieve a fast response, this invention proposes an adaptive dynamic bias LDO circuit with segmented adjustment of the output power stage, comprising: a main circuit and an auxiliary circuit.

[0009] The main circuit includes: a reference voltage V REF Error amplifier EA, first voltage divider resistor R1, second voltage divider resistor R2, adaptive dynamic bias current I B Equivalent load current I L and output terminal V OUT ;

[0010] The reference voltage V REF One end of the first voltage divider resistor R1 is connected to the first voltage divider resistor R2, and the other end of the first voltage divider resistor R1 is connected to the second voltage divider resistor R2 and the negative input terminal of the error amplifier EA, respectively.

[0011] The other end of the second voltage divider resistor R2 is grounded;

[0012] The error amplifier EA's positive input terminal is connected to the equivalent load current I. L and the output terminal V OUT connect;

[0013] The adaptive dynamic bias current I B Connected to the error amplifier EA;

[0014] The auxiliary circuit includes: a first frequency compensation module Rz, a second frequency compensation module Cc, a first segmented power transistor MP1, a second segmented power transistor MP2, a third segmented power transistor MP3, a first drive buffer stage module BUF2, a second drive buffer stage module BUF3, and a switch S;

[0015] The first frequency compensation module Rz is connected in series with the second frequency compensation module Cc; the first drive buffer stage module BUF2 is connected in series with the second segmented power transistor MP2; the second drive buffer stage module BUF3 is connected in series with the third segmented power transistor MP3 and the switch S.

[0016] The first segmented power transistor MP1 is connected in parallel with the second segmented power transistor MP2, the third segmented power transistor MP3, and the first frequency compensation module Rz and the second frequency compensation module Cc connected in series.

[0017] The input terminal of the auxiliary circuit is connected to the output terminal of the error amplifier EA of the main circuit, and the output terminal of the auxiliary circuit is connected to the positive input terminal of the error amplifier EA of the main circuit.

[0018] The LDO circuit of this invention mainly achieves the purpose of reducing power consumption and improving response speed by segmenting the control of the LDO output stage power transistor and adaptively and dynamically controlling the bias current of the LDO error amplifier. It can adaptively adjust the bias current according to the load current and achieve the purpose of reducing power consumption and improving response speed by segmenting the control of the power transistor. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a traditional LDO circuit structure;

[0020] Figure 2 This is a schematic diagram of the LDO circuit structure of the present invention;

[0021] Figure 3 This is a detailed schematic diagram of the LDO circuit of the present invention;

[0022] Figure 4 This is a control diagram of the dynamic bias and switching control circuit of the LDO circuit of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] An adaptive dynamic bias LDO circuit with segmented adjustment of output power stage, as shown below. Figure 2 As shown, it includes: main circuit and auxiliary circuit;

[0025] The main circuit includes: a reference voltage V REF Error amplifier EA, first voltage divider resistor R1, second voltage divider resistor R2, adaptive dynamic bias current I B Equivalent load current I L and output terminal V OUT ;

[0026] The reference voltage V REF One end of the first voltage divider resistor R1 is connected to the first voltage divider resistor R2, and the other end of the first voltage divider resistor R1 is connected to the second voltage divider resistor R2 and the negative input terminal of the error amplifier EA, respectively.

[0027] The other end of the second voltage divider resistor R2 is grounded;

[0028] The error amplifier EA's positive input terminal is connected to the equivalent load current I. L and the output terminal V OUT connect;

[0029] The adaptive dynamic bias current I B Connected to the error amplifier EA;

[0030] The auxiliary circuit includes: a first frequency compensation module Rz, a second frequency compensation module Cc, a first segmented power transistor MP1, a second segmented power transistor MP2, a third segmented power transistor MP3, a first drive buffer stage module BUF2, a second drive buffer stage module BUF3, and a switch S;

[0031] The first frequency compensation module Rz is connected in series with the second frequency compensation module Cc; the first drive buffer stage module BUF2 is connected in series with the second segmented power transistor MP2; the second drive buffer stage module BUF3 is connected in series with the third segmented power transistor MP3 and the switch S.

[0032] The first segmented power transistor MP1 is connected in parallel with the second segmented power transistor MP2, the third segmented power transistor MP3, and the first frequency compensation module Rz and the second frequency compensation module Cc connected in series.

[0033] The input terminal of the auxiliary circuit is connected to the output terminal of the error amplifier EA of the main circuit, and the output terminal of the auxiliary circuit is connected to the positive input terminal of the error amplifier EA of the main circuit.

[0034] This LDO circuit is a unity-gain connection, with the output voltage equal to the input voltage of the op-amp. The first voltage divider resistor R1 is adjustable; by adjusting resistor R1, the reference voltage V can be adjusted. REF Adjustments are made to produce different output voltages.

[0035] The area S of the third segment power transistor MP3 MP3 >>The area S of the second segment power transistor MP2 MP2 >The area S of the first segment power transistor MP1 MP1 .

[0036] The BUF2 module is a drive buffer stage for driving the MP2 power transistor. When unloaded, BUF2 has no drive current and the MP2 transistor does not conduct.

[0037] BUF3 is the driver buffer stage for the MP3 power transistor. S is the switching transistor of BUF3, which adaptively turns on or off according to the load current; I B To provide the op-amp with an adaptive dynamic bias current that is affected by the load current, I B I changes dynamically due to the magnitude of the load current. L These are the equivalent load currents; the working process is as follows:

[0038] When I LUnder no-load conditions, the buffer stages of MP2 and MP3 transistors are not working. At this time, the error amplifier EA and power transistor MP1 form the feedback loop of the LDO; B The current is the minimum value I BMIN The LDO operates in ultra-low power mode with a current of 0.5uA, and the gate-source parasitic capacitance C of MP2 and MP3 is [not specified]. GS-MP2 C GS-MP3 and gate-drain parasitic capacitance C GD-MP2 C GD-MP3 It will not enter the LDO loop, thus maximizing the circuit startup speed; simultaneously, the main power consumption of the circuit during no-load operation is consumed by the LDO itself, therefore I B Take the minimum value I BMIN The circuit power was significantly reduced.

[0039] When I L Under light load, the buffer stage BUF2 of MP2 is active, while BUF3 remains off. EA, MP1, and MP2 form the feedback loop of the LDO. The bias current of EA increases with the increase of the load current; at this time, I B =I BMIN +α*I L I L Let be the equivalent load current value, and α be the coefficient of the mirror image MP2. At this time, the parasitic capacitance of MP2 enters C. GS-MP2 C GD-MP2 Entering the LDO loop reduces the loop's response speed. Meanwhile, the bias current I... B Increasing I can improve loop response speed. Therefore, when the load current changes from no-load to light-load, I... B With adaptive scaling, the LDO's response speed is not affected by the introduction of parasitic capacitance.

[0040] When I L Under heavy load, both BUF2 and BUF3 operate, and EA, MP1, MP2, and MP3 form the feedback loop of the LDO. To reduce circuit power consumption under load, the quiescent current cannot continuously increase; under heavy load, I... B The current no longer increases with increasing load current. The design transition point from light load to heavy load is I. L最大轻载 =0.1 ╳ I L满载 That is, when the load current reaches 0.1 times the full load current, it enters heavy load mode, I B The current no longer increases with the increase of the load current.

[0041] Example 1, as Figure 3 As shown, the LDO circuit of this invention mainly consists of 7 parts.

[0042] (1) Voltage divider resistors R1 and R2 are voltage divider resistor modules. By adjusting the resistor R1, the input value of the error operational amplifier is adjusted, thereby adjusting the output voltage.

[0043] (2) Error amplifier EA module, consisting of NMOS transistors M3, M4, M5, M6 and PMOS transistors M0, M1, M2, M7, M8, M9, M10 and bias voltage V B1 ~V B4 The structure and function of M3 and M4 are to amplify the error signal, thereby stabilizing the output voltage. The bias voltage V of M3 and M4 is also included. B3 The current increases with the increase of the load current. The bias voltage V of transistor M0... B4 It will also decrease as the load current increases, thereby increasing the bias current of transistor M0. The bias voltage V of M5 and M6... B2 and the bias voltage V of transistors M7 and M8 B1 The value is fixed and provided by the bias circuit. The gate of M0 is used to receive the dynamic bias voltage V. B4 The drain of M0 is connected to the sources of M1 and M2. The source of M0, along with the sources of M9 and M10, is connected to an external power supply VDD. The gate of M1 is connected to the first voltage divider resistor R1 and the second voltage divider resistor R2 in the main circuit. The drain of M1 is connected to the drain of M4 and the source of M6, and is also connected to one end of the first frequency compensation module Rz. The gate of M2 is connected to the drains of the segmented power transistors MP1, MP2, and MP3, as well as one end of the second frequency compensation module Cc. The drain of M2 is connected to the drain of M3 and the source of M5. The gates of M3 and M4 are connected to each other and are also connected to a bias voltage V. B3 Dynamic bias voltages are provided to M3 and M4. The source of M3 is connected to the source of M4 and together to ground GND. The drain of M5 is connected to the drain of M7 and to the gates of M9 and M10. The gates of M5 and M6 are interconnected and simultaneously connected to an external bias voltage V. B2 A fixed bias voltage is provided to M5 and M6; the drain of M6 is connected to the drain of M8, the gate of M11 in the BFU2 module, and the gate of the segmented power transistor MP1; the source of M7 is connected to the drain of M9, and the gate of M7 is connected to the gate of M8, and an external bias voltage V is applied simultaneously. B1 A fixed bias voltage is provided for M7 and M8; the source of M8 is connected to the drain of M10.

[0044] (3) The compensation unit consists of Rz and Cc connected in series. Through this compensation method, the main pole of the loop is designed to be at the output of the operational amplifier, so that the output can be stable without the need for a large output capacitor.

[0045] (4) The buffer BUF2 unit consists of NMOS transistors M12, M13, M14, and M16, PMOS transistors M11 and M16, and resistors R3, R4, and R5. When unloaded, i.e., I... L When I is zero, the current flowing through MP1 is zero, therefore the current flowing through the mirror transistor M11 is zero. At this time, the BUF2 module does not work, the source of transistor M16 is at a high level, and transistor MP2 does not work. When there is a small load current, i.e., I... L When the comparison is small, BUF2 operates, driving power transistor MP2. Specifically, the gate of M11 is connected to the error amplifier EA module; the drain of M11 is connected to the drain and gate of M12, the gate of M13, the gate of M14, and the second drive buffer module BUF3; the source of M11 is connected to one end of resistor R3, one end of resistor R4, the drain of M16, and one end of resistor R5, and is externally connected to the power supply VDD; the source of M12 is interconnected with the sources of M13 and M14 and connected to ground GND; the drain of M13 is connected to the drain and gate of M15, the other end of resistor R3, and the gate of M16; the drain of M14 is connected to the gate of the second segmented power transistor MP2, the source of M16, and the other end of resistor R5; and the source of M15 is connected to the other end of resistor R4.

[0046] (5) The buffer BUF3 unit consists of NMOS transistors M17, M18, M19, M21, M22, and M40, PMOS transistor M20, and resistor R6. Transistors M21 and M22 are the switching transistors controlling the BUF3 module, controlled by switching signals S1 and S2. The switching signals are... Figure 4 The BUF3 switch control unit controls the load current I. L When the current is high, the switching signals S1 and S2 of this module turn on the switching transistors M21 and M22, and the BUF3 module starts working, driving the high-power MP3 player. Specifically, the gate of M17 is connected to the gate of transistor M40, the gate of M18, and the first drive buffer module BUF2; the source of M17 is connected to the source of transistor M40 and the drain of M21; the drain of M17 is connected to the drain and gate of M19 and the gate of M20; the source of M18 is connected to the drain of M22; the drain of M18 is connected to the source of M20 and the gate of the third segment power transistor MP3; and the gate of M40 is connected to the gates of M17 and M18, and the BUF2 module. The source of M19 is connected to one end of resistor R6, and the other end of resistor R6 is connected to the external power supply VDD; the sources of M21 and M22 are connected to the ground VDD, and the gates of M21 and M22 are connected to the switching signals S1 and S2 respectively, serving as the switching transistors of the second drive buffer module BUF3.

[0047] (6) Segmented Power Transistor Unit. Composed of PMOS power transistors MP1, MP2, and MP3. MP1 operates under no-load conditions; MP1 and MP2 operate under light current load conditions; and MP1, MP2, and MP3 operate simultaneously under high current load conditions. The area S of MP3 is... MP3 >>MP2 power transistor area S MP2 >MP1 power transistor area S MP1 .

[0048] (7) Equivalent load current unit I L .

[0049] In an embodiment of the present invention, the LDO circuit is configured for unity gain, and the output voltage is equal to the input voltage of the operational amplifier. This is achieved by adjusting the reference voltage V. REF Adjusting the voltage divider resistors allows for control of the output voltage V. OUT The adjustment, i.e., the gate voltage V of the operational amplifier input pair transistor M1. GM1 :

[0050]

[0051]

[0052] The specific working principle is as follows:

[0053] like Figure 3 As shown, V B1 and V B2 This is the fixed bias voltage of the bias circuit product. V B3 and V B4 This is generated by the dynamic bias circuit. When there is no load or extremely light load, the power transistor MP1 has no current or a very small current. Therefore, the current flowing through the mirror transistor M11 is very small and close to zero. Similarly, M12, M13, M14, M15, and M16 have no current or only a very small current flowing through them, causing the gate potential of M15 to be close to VDD. Since no current flows through M16, the VDD of M16 is... GS The voltage is very small, so the source voltage of M16, i.e., the gate voltage of MP2, is close to VDD, and MP2 is not turned on. Output V OUT Stabilization is achieved solely through the negative feedback of the MP1 transistor and the EA loop, reducing the circuit's power consumption. At this point, the entire LDO loop's quiescent current is approximately 2μA.

[0054] When the circuit is lightly loaded, current flows through MP1. At this time, M11 also generates a mirror current, which flows through M12, M13, M14, M15, and M16, pulling down the gate of M15 and the source of M16, thus driving MP2 to provide load current. At this point, power transistors MP1 and MP2 together form a negative feedback loop. Switches M21 and M22 are not yet turned on, so BUF3 is not activated, and MP3 remains off.

[0055] When the load current exceeds the load capacity of power transistors MP1 and MP2, that is, when the load current increases, Figure 4 The dynamic bias and switching control circuit controls the switching transistor M21 to turn on first. Then, mirrored current flows through M17, M19, M20, and M40, pulling down the source potential of M20, i.e., the gate potential of power transistor MP3, thus driving MP3 to turn on. As the load current continues to increase, switching transistor M22 turns on again, further pulling down the gate of MP3 and driving MP3 to provide a larger current. At this point, all three power transistors MP1, MP2, and MP3 are operating. Figure 3 Chinese V B3 The voltage will increase as the load current increases, thereby increasing the op-amp bias current. V B43 The voltage will increase or decrease as the load current increases, thereby increasing the tail current of the op-amp input pair transistors and thus improving the op-amp response speed.

[0056] The following details the adaptive conduction principle of switching transistors M21 and M22 based on the load current and the adaptive adjustment principle of the operational amplifier bias current:

[0057] Figure 4 This is a circuit diagram for dynamic bias and switching control. It includes a dynamic bias adjustment unit, a power transistor sampling unit, and a BUF3 switching control unit. It contains PMOS transistors M30, M31, M32, and M33, NMOS transistors M34, M35, M36, M37, M38, and M39, and a fixed bias current I. B2 I B3 and dynamic bias voltage V B3 V B4 Together, they constitute the dynamic bias module. PMOS power transistors MP2 and MP3, and PMOS sampling transistors MS2 and MS3 constitute the power transistor sampling unit. NMOS transistors M23, M24, M25, and M26, PMOS transistors M27, M28, and M29, resistors R7, R8, and R9, and a fixed bias current I... B1 Together, they constitute the BUF3 switch control unit, providing product switch control signals S1 and S2. The resistance value of resistor R9 is R... R9 > The resistance value of resistor R8 R8 > The resistance value R of resistor R7 R7MP2 and MP3 are respectively Figure 3 Light-load power transistors and heavy-load power transistors. MS2 and MS3 mirror the current flowing through MP2 and MP3 transistors, respectively.

[0058] Figure 4 Detailed principle of the BUF3 switch control unit: Under light load, since the current in the image transistors MS2 and MS3 is very small or there is no current flowing through them, the current in M23 to M26 is supplied by the fixed bias current I of M23. B1 Decision made. The width-to-length ratio (W / L) of the M27 pipe is designed. M27 = Width-to-length ratio of M28 pipe (W / L) M28 = Width-to-length ratio of M29 pipe (W / L) M29 Design the width-to-length ratio (W / L) of the M23 pipe. M23 = Width-to-length ratio of M24 pipe (W / L) M24 = Width-to-length ratio of M25 pipe (W / L) M25 = Width-to-length ratio of M26 pipe (W / L) M26 Because R R9 >R R8 >R R7 Then the initial current I of transistor M29 M29 < Initial current I of M28 transistor M28 < Initial current I of transistor M27 M27 Since the width-to-length ratios of M23, M24, M25, and M26 are equal, their initial currents are also equal, i.e., I0. M23 =I M24 =I M25 =I M26 Therefore, the initial current I of M25 M25 >The initial current I of M28 M28 The initial current I of M26 M26 >The initial current I of M29 M29 To ensure that the final current of the same branch is equal, the voltage levels of S1 and S2 must be pulled low to maintain the equal branch current. Therefore, S1 and S2 are at low levels under light load current. Figure 3 Transistors M21 and M22 are in the off state. When the output current continues to increase, i.e., the current flowing through MP2 increases, the current in the mirror transistor MS2 increases synchronously, and the current flowing through R7 increases. Therefore, the source potential of M27 decreases. Since the current in M27 is determined by transistor M24, the Vo of transistor M27... SG27 If the value is constant, then the gate potential of M27 decreases along with the source potential of M27, which leads to the V of M28 and M29... SG28 and V SG29 The current flowing through M28 initially increases as the current increases. When the current flowing through M28 exceeds the fixed bias current of M25, i.e., when I... M28 >I M25At this time, S1 changes from low to high. As the load current flowing through MP1 and MP2 continues to increase, the current in the mirror transistors MS2 and MS3 also continues to increase. When the current flowing through M29 exceeds the fixed bias current of M26, that is, when I... M29 >I M26 At that time, S2 changes from low level to high level. Figure 3 When transistors M21 and M22 are turned on, the BUF3 module starts working, thereby driving the MP3 to output a large current. This achieves the purpose of adaptive segmented control of the power transistors.

[0059] Figure 4 Detailed principle of the dynamic bias adjustment unit: Figure 4 The PMOS transistors M30, M31, M32, M33, and MS4, the NMOS transistors M34, M35, M36, M37, M38, and M39, and the fixed bias current I B2 I B3 This constitutes a dynamic bias generation circuit. B2 The bias current and bias voltage for transistors M34, M35, and M36 are provided through the mirror transistors M31 and M30. When there is no load or a very light load, i.e., the current flowing through MP1 is zero or extremely small, the current in the sampling transistor MS4 is close to zero. Figure 3 The tail current transistor M0 of the middle EA unit is biased by Figure 4 Fixed bias current I in B3 V generated by mirroring M38, M37, M34, and M32 B4 Voltage provided. Figure 3 The bias voltages of the bias transistors M3 and M4 in the EA unit are also changed by... Figure 4 I in B3 V generated by mirroring M38, M37, M34, M32, M33, and M39 B3 Voltage supply. As the load current of MP2 increases, the current of MS4 gradually increases, and the gate and source voltages of M35 and M34 will also increase, thereby increasing the drain-source voltage V of M37 and M36. DS36 and V DS37 Current formula:

[0060]

[0061] From equation (3), it can be seen that as V DS36 and V DS37 The increase in current I of transistors M37 and M36 D36 I D37 This will also increase, thus increasing the current in the M32 and M39 transistors, causing... Figure 3The increased current in the tail current transistor M0 and the bias transistors M3 and M4 of the EA circuit improves the loop response speed and bandwidth. This also improves the LDO loop bandwidth GBW and large-signal setup speed S. R for:

[0062]

[0063]

[0064] As can be seen from equation (4), with the bias current I of transistor M0 M0 As the load current of MP2 increases, the unity-gain bandwidth of the loop also increases. That is, as the load current of MP2 increases, the small-signal response speed of the loop improves. It can be seen from equation (5) that as the bias current I of M4 increases... M4 The increase in size, design I M4 The increased current is greater than I M0 The increased current, i.e., ΔIM4 > ΔIM0, can ensure the large signal establishment speed S R This also leads to an improvement in LDO response speed.

[0065] The above analysis shows that as the load current of MP2 increases, the bandwidth and settling speed of the LDO loop will adaptively increase accordingly.

[0066] As the load current of MP2 continues to increase, the Vo of M36 and M37 transistors... DS36 and V DS37 Once the maximum value is reached, the current of transistors M37 and M36 will no longer increase, thus ensuring that the current of transistors M0, M3, and M4 in the EA module will not keep increasing. This ensures that the overall static current of the LDO is within a controllable range, achieving the goals of low power consumption and fast response.

[0067] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An LDO circuit with adaptive dynamic bias and segmented adjustment of output power stage, characterized in that, include: Main circuit and auxiliary circuit; The main circuit includes: a reference voltage V REF Error amplifier EA, first voltage divider resistor R1, second voltage divider resistor R2, adaptive dynamic bias current I B Equivalent load current I L and output terminal V OUT ; The reference voltage V REF One end of the first voltage divider resistor R1 is connected to the first voltage divider resistor R2, and the other end of the first voltage divider resistor R1 is connected to the second voltage divider resistor R2 and the negative input terminal of the error amplifier EA, respectively. The other end of the second voltage divider resistor R2 is grounded; The error amplifier EA's positive input terminal is connected to the equivalent load current I. L and the output terminal V OUT connect; The adaptive dynamic bias current I B Connected to the error amplifier EA; The auxiliary circuit includes: a first frequency compensation module Rz, a second frequency compensation module Cc, a first segmented power transistor MP1, a second segmented power transistor MP2, a third segmented power transistor MP3, a first drive buffer stage module BUF2, a second drive buffer stage module BUF3, and a switch S; The first frequency compensation module Rz is connected in series with the second frequency compensation module Cc; the first drive buffer stage module BUF2 is connected in series with the second segmented power transistor MP2; the second drive buffer stage module BUF3 is connected in series with the third segmented power transistor MP3 and the switch S. The first segmented power transistor MP1 is connected in parallel with the second segmented power transistor MP2, the third segmented power transistor MP3, and the first frequency compensation module Rz and the second frequency compensation module Cc connected in series. The input terminal of the auxiliary circuit is connected to the output terminal of the error amplifier EA of the main circuit, and the output terminal of the auxiliary circuit is connected to the positive input terminal of the error amplifier EA of the main circuit. The first drive buffer module BUF2 includes: NMOS transistors M12, M13, M14, and M16, PMOS transistors M11 and M15, and resistors R3, R4, and R5; The gate of M11 is connected to the error amplifier EA module. The drain of M11 is connected to the drain and gate of M12, the gate of M13, the gate of M14 and the second drive buffer module BUF3. The source of M11 is connected to one end of resistor R3, one end of resistor R4, the drain of M16 and one end of resistor R5 and externally connected to the power supply VDD. The source of M12 is interconnected with the source of M13 and the source of M14 and connected to ground GND. The drain of M13 is connected to the drain and gate of M15, the other end of resistor R3, and the gate of M16. The drain of M14 is connected to the gate of the second segment power transistor MP2, the source of M16, and the other end of resistor R5. The source of M15 is connected to the other end of resistor R4.

2. The LDO circuit with adaptive dynamic bias and segmented adjustment of output power stage according to claim 1, characterized in that, This LDO circuit is a unity-gain connection, with the output voltage equal to the input voltage of the op-amp. The first voltage divider resistor R1 is adjustable; by adjusting resistor R1, the reference voltage V can be adjusted. REF Adjustments are made to produce different output voltages.

3. The LDO circuit with adaptive dynamic bias and segmented adjustment of output power stage according to claim 1, characterized in that, The area S of the third segment power transistor MP3 MP3 >>The area S of the second segmented power transistor MP2 MP2 >The area S of the first segmented power transistor MP1 MP1 .

4. The LDO circuit with adaptive dynamic bias and segmented adjustment of output power stage according to claim 1, characterized in that, The adaptive dynamic bias current I B Subject to the equivalent load current I L The magnitude of the influence changes dynamically, providing the op-amp with load current I. L The adaptive dynamic bias current is affected.

5. The LDO circuit with adaptive dynamic bias and segmented adjustment of output power stage according to claim 1, characterized in that, The error amplifier EA includes: NMOS transistors M3, M4, M5, M6 and PMOS transistors M0, M1, M2, M7, M8, M9, M10, and a bias voltage V. B1 ~V B4 ; The gate of M0 is used to receive the dynamic bias voltage V. B4 The drain of M0 is connected to the source of MI and M2, and the source of M0, together with the sources of M9 and M10, is connected to the external power supply VDD. The gate of M1 is connected to the first voltage divider resistor R1 and the second voltage divider resistor R2 in the main circuit. The drain of M1 is connected to the drain of M4 and the source of M6 and is also connected to one end of the first frequency compensation module Rz. The gate of M2 is connected to the drain of segmented power transistors MP1, MP2, and MP3, as well as one end of the second frequency compensation module Cc. The drain of M2 is connected to the drain of M3 and the source of M5. The gates of M3 and M4 are interconnected and simultaneously connected to a bias voltage V. B3 Provide dynamic bias voltage to M3 and M4. The source of M3 is connected to the source of M4 and together connected to ground GND. The drain of M5 is connected to the drain of M7, and is also connected to the gate of M9 and the gate of M10. The gates of M5 and M6 are interconnected and simultaneously connected to an external bias voltage V. B2 Provide a fixed bias voltage to M5 and M6; The drain of M6 is connected to the drain of M8, the gate of M11 in the BFU2 module, and the gate of the segmented power transistor MP1. The source of M7 is connected to the drain of M9, and the gate of M7 is connected to the gate of M8. An external bias voltage V is also applied. B1 Provide a fixed bias voltage to M7 and M8; The source of M8 is connected to the drain of M10.

6. The LDO circuit with adaptive dynamic bias and segmented adjustment of output power stage according to claim 1, characterized in that, The second drive buffer module BUF3 includes: NMOS transistors M17, M18, M20, M21, M22, M40 and PMOS transistor M19, resistor R6 and switching signals S1 and S2; The gates of M17, M18, and M40 are connected to the first drive buffer module BUF2; the source of M17 is connected to the source of M40 and the drain of M21; the drain of M17 is connected to the drain and gate of M19 and the gate of M20. The source of M18 is connected to the drain of M22, and the drain of M18 is connected to the source of M20, the drain of M40, and the gate of the third segment power transistor MP3. The source of M19 is connected to one end of resistor R6, and the other end of resistor R6 is connected to the external power supply VDD. The source of M21 and the source of M22 are connected to the ground VDD. The gates of M21 and M22 are connected to the switching signals S1 and S2, respectively, and serve as the switching transistors of the second drive buffer module BUF3.

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