Wafer edge defect detection method and apparatus

Abstract

The application discloses a wafer edge defect detection method, a wafer edge defect detection device and electronic equipment, and belongs to the technical field of wafer edge defect detection, wherein the method comprises the following steps: extracting an edge mask image from a wafer template image; extracting an edge region from a wafer image to be detected based on the edge mask image; intercepting a plurality of sub-regions in the edge region along the length direction of an edge straight line; and performing statistical analysis on pixel points in the sub-regions to extract defect points. The method can find a local abnormal region and reduce the dependence on a template by extracting the edge region through the edge mask image. Then, the defect points are extracted by intercepting a plurality of sub-regions, a plurality of small-range defect point detection regions are intercepted from a large-range defect point detection region for processing, the detection region is optimized and split, the detection difficulty is reduced by intercepting the sub-regions, the detection precision is improved, and the generation of over-detection points can be avoided.

Description

Technical Field

[0001] The present application belongs to the technical field of wafer edge defect detection, and specifically relates to a wafer edge defect detection method, a wafer edge defect detection device and an electronic device. Background Art

[0002] With the continuous development and advancement of the semiconductor industry, semiconductor packaging and testing equipment and technologies have also evolved, and the requirements for equipment inspection accuracy have also increased. Wafer appearance defect detection is an inevitable process in the semiconductor packaging and testing process. In current defect detection processes, differential algorithms are frequently used due to their fast computational speed and strong adaptability. However, because differential algorithms rely on a golden template, they cannot be used in some inspection cases where the golden template fails (such as DIE with random background).

[0003] The existing technical solution uses gradient information when generating the boundary area mask. By setting the gradient threshold range, the boundary contour detection area is filtered pixel by pixel. As a result, the generated detection area is closely related to the quality of the golden template. The grayscale abnormal jump points around the boundary of the golden template image will be filtered out on the mask, making the point unable to be detected.

[0004] When using the differential algorithm to perform color classification on the calculated Blob connected area, the template DIE image and the DIE image to be detected are required to be aligned pixel by pixel. However, during the DIE image acquisition process, there may be a deviation between the DIE image and the template image, resulting in a deviation between the DIE to be detected and the template DIE image. Therefore, it is necessary to calculate the position deviation between the template DIE image and the DIE image to be detected, otherwise the Blob color cannot be judged. Summary of the Invention

[0005] The purpose of this application is to provide a wafer edge defect detection method, a wafer edge defect detection device and an electronic device to solve the problem that wafer edge defect detection is greatly affected by template quality.

[0006] According to a first aspect of an embodiment of the present application, a method for detecting wafer edge defects is provided. The method may include:

[0007] extracting an edge mask image from a wafer template image;

[0008] extracting an edge region from the wafer image to be measured based on the edge mask image;

[0009] Cutting out a plurality of sub-regions in the edge region along the length direction of the edge straight line;

[0010] Statistical analysis is performed on the pixels within the sub-area to extract defect points.

[0011] In some optional embodiments of the present application, performing statistical analysis on the pixels within the sub-region to extract defect points includes:

[0012] Obtain the mean grayscale value of all pixels in the sub-region;

[0013] Obtain the standard deviation of the grayscale values ​​of all pixels in the sub-region;

[0014] Obtain a first difference between the grayscale value of each pixel in the sub-region and the mean value;

[0015] Pixels whose absolute value of the first difference is greater than or equal to K times the standard deviation are regarded as defective points; where K is a positive number.

[0016] In some optional embodiments of the present application, the sub-region is rectangular, and the edge straight line is located at the center of the sub-region.

[0017] In some optional embodiments of the present application, extracting an edge mask image from a wafer template image includes:

[0018] Selecting a region of interest from the wafer template image, wherein the region of interest includes the edge line;

[0019] Extracting initial edge contour points located on the edge straight line from the region of interest using a Canny algorithm;

[0020] Screening the initial edge contour points to obtain target edge contour points;

[0021] The target edge contour points are binarized to obtain a mask image.

[0022] In some optional embodiments of the present application, extracting initial edge contour points located on the edge line from the region of interest using a Canny algorithm includes:

[0023] Denoising the region of interest by Gaussian filtering;

[0024] Calculate the gradient amplitude of each pixel in the region of interest after denoising by using the Sobel algorithm;

[0025] The pixel point with the largest gradient amplitude in the gradient direction is selected as the edge point to be detected by the non-maximum suppression method;

[0026] The edge points to be detected are screened based on a double-threshold detection method to obtain the initial edge contour points.

[0027] In some optional embodiments of the present application, screening the edge points to be detected based on a dual threshold detection method to obtain the initial edge contour points includes:

[0028] Extracting points greater than or equal to a first threshold from the edge points to be detected as first edge points;

[0029] Extracting points smaller than a first threshold and greater than or equal to a second threshold from the edge points to be detected as second edge points;

[0030] Extracting a point connected to the first edge point from the second edge points as a third edge point;

[0031] Extracting points located on the same straight line from the first edge point and the third edge point as the initial contour points;

[0032] The first threshold is greater than the second threshold.

[0033] In some optional embodiments of the present application, screening the initial edge contour points to obtain target edge contour points includes:

[0034] Performing gradient calculation on the region of interest using the Sobel algorithm;

[0035] Taking the absolute value of the result of the gradient calculation to obtain the Sobel image;

[0036] Acquire a detection straight line passing through the initial edge contour point in the region of interest along a direction perpendicular to the edge straight line;

[0037] Obtaining a second difference in grayscale values ​​of adjacent pixels on the detection line;

[0038] The initial edge contour point whose absolute value of the second difference is smaller than the preset difference is obtained as the target edge contour point.

[0039] In some optional embodiments of the present application, binarizing the target edge contour points to obtain a mask image includes:

[0040] Binarizing the target edge contour points to obtain an initial mask image;

[0041] Performing morphological dilation on the initial mask image to obtain an extended mask image;

[0042] Morphological corrosion is performed on the extended mask image to cut off both ends of the edge line to obtain the mask image.

[0043] In some optional embodiments of the present application, before cutting out a plurality of sub-regions in the edge region along the length direction of the edge straight line, the method further includes:

[0044] The edge region is preprocessed by a three-frame difference algorithm.

[0045] In some optional embodiments of the present application, before intercepting a plurality of sub-regions in the edge region along the length direction of the edge straight line, the method further comprises:

[0046] Filtering the pre-processed edge region through a box filter.

[0047] In some optional embodiments of the present application, after extracting the defect points by statistical analysis in the sub-regions, the method further comprises:

[0048] Obtaining a pixel gray mean value of a neighboring region of the defect point in the wafer image to be detected;

[0049] Determining whether the pixel gray value of the defect point is greater than the pixel gray mean value, if yes, the color of the defect point is white, and if no, the defect point is black.

[0050] According to the second aspect of the embodiments of the present application, a wafer edge defect detection device is provided, comprising:

[0051] A first obtaining module configured to extract an edge mask image from a wafer template image;

[0052] A second obtaining module configured to extract an edge region from a wafer image to be detected based on the edge mask image;

[0053] An intercepting module configured to intercept a plurality of sub-regions in the edge region along the length direction of the edge straight line;

[0054] An analyzing module configured to extract defect points by statistical analysis in the sub-regions.

[0055] According to the third aspect of the embodiments of the present application, an electronic device is provided, which can comprise:

[0056] A processor;

[0057] A memory for storing processor-executable instructions;

[0058] The processor is configured to execute the instructions to implement the wafer edge defect detection method as shown in any one of the embodiments of the first aspect.

[0059] The above technical solutions of the present application have the following beneficial technical effects:

[0060] The wafer edge defect detection method provided by the embodiments of the present application can find local abnormal regions by extracting an edge region through an edge mask image, reduce the dependence on a template, further improve the detection accuracy by extracting defect points through intercepting a plurality of sub-regions, and avoid the generation of over-checking points. BRIEF DESCRIPTION OF DRAWINGS

[0061] Figure 1 FIG. 1 is a flowchart of a wafer edge defect detection method according to an example embodiment of the present application;

[0062] Figure 2 FIG. 2 is a wafer image to be detected according to an example embodiment of the present application;

[0063] Figure 3 FIG. 3 is a wafer template image according to an example embodiment of the present application;

[0064] Figure 4 FIG. 4 is a flowchart of step S104 according to an example embodiment of the present application;

[0065] Figure 5 FIG. 5 is a sub-region diagram according to an example embodiment of the present application;

[0066] Figure 6 FIG. 6 is a flowchart of step S101 according to an example embodiment of the present application;

[0067] Figure 7 FIG. 7 is a flowchart of step S1012 according to an example embodiment of the present application;

[0068] Figure 8 FIG. 8 is a gradient direction diagram according to an example embodiment of the present application;

[0069] Figure 9 FIG. 9 is a double-threshold detection division diagram according to an example embodiment of the present application;

[0070] Figure 10 FIG. 10 is a flowchart of step S10124 according to an example embodiment of the present application;

[0071] Figure 11 FIG. 11 is a flowchart of step S1013 according to an example embodiment of the present application;

[0072] Figure 12a FIG. 12 is a horizontal direction gradient calculation diagram according to an example embodiment of the present application;

[0073] Figure 12b FIG. 13 is a horizontal direction gradient calculation diagram according to an example embodiment of the present application;

[0074] Figure 13 FIG. 14 is a straight line detection diagram according to an example embodiment of the present application;

[0075] Figure 14 FIG. 15 is a flowchart of step S1014 according to an example embodiment of the present application;

[0076] Figure 15 FIG. 16 is a flowchart of pre-processing according to an example embodiment of the present application;

[0077] Figure 16 is a flow chart of a three-frame difference algorithm in an exemplary embodiment of the present application;

[0078] Figure 17 is a flowchart of filtering in an exemplary embodiment of the present application;

[0079] Figure 18 is a schematic diagram of a filter in an exemplary embodiment of the present application;

[0080] Figure 19 is a schematic diagram of a process for color classification of defect points in an exemplary embodiment of the present application;

[0081] Figure 20 1 is a schematic diagram of a detection effect of a wafer edge defect detection method in an exemplary embodiment of the present application;

[0082] Figure 21 is a schematic diagram of the detection effect of a wafer edge defect detection method in another exemplary embodiment of the present application;

[0083] Figure 22 This is a schematic structural diagram of a wafer edge defect detection device in an exemplary embodiment of the present application;

[0084] Figure 23 is a schematic structural diagram of an electronic device in an exemplary embodiment of the present application;

[0085] Figure 24 It is a schematic diagram of the hardware structure of an electronic device in an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0086] To make the objectives, technical solutions, and advantages of this application more clearly understood, this application is further described below in conjunction with specific embodiments and with reference to the accompanying drawings. It should be understood that these descriptions are merely illustrative and are not intended to limit the scope of this application. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion in the concepts of this application.

[0087] The accompanying drawings illustrate schematic diagrams of layer structures according to embodiments of the present application. These figures are not drawn to scale; for clarity, some details are exaggerated and some details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0088] Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0089] In the description of this application, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance.

[0090] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0091] Research has found that existing wafer defect detection methods typically use differential algorithms for defect detection. On some wafer images that produce random backgrounds, the golden template fails, resulting in the inability to detect edge defects. Existing wafer defect detection methods typically use gradient thresholds to generate a mask image for the boundary detection area. If a single pixel's grayscale abnormally fluctuates on the golden template, the mask will filter it out, forming a partially missed area on the wafer to be inspected. Existing wafer defect detection methods typically compare the grayscale value of the defect point on the golden template with the grayscale value at the defect site, and use the comparison results to distinguish the color of the defect point. When the detection image has splicing errors or positioning errors, the color judgment of the defect point will be abnormal. Therefore, it is necessary to reduce the impact of the golden template quality on detection.

[0092] The wafer edge defect detection method, wafer edge defect detection device and electronic device provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings through specific embodiments and their application scenarios.

[0093] like Figure 1 As shown, in a first aspect of an embodiment of the present application, a method for detecting wafer edge defects is provided, which may include:

[0094] Step S101: extracting an edge mask image from a wafer template image;

[0095] Step S102: extracting an edge region from the image of the wafer to be tested based on the edge mask image;

[0096] Step S103: cutting out a plurality of sub-regions in the edge region along the length direction of the edge straight line;

[0097] Step S104: performing statistical analysis on the pixels within the sub-region to extract defect points.

[0098] In this embodiment, Figure 2 As shown, the wafer image to be tested can be a rectangular grain image, such as Figure 3As shown, the wafer template image can be the golden reference image of the grain, and the edge mask image is used to extract the area where the edge contour of the wafer template image is located. The edge straight line is within the edge area, and the size of the edge area can be set according to actual needs. The edge straight line can be located at the center of the sub-area. The sub-area can be a rectangle of preset size, and multiple sub-areas are obtained by continuous interception along the length direction of the edge straight line. This embodiment extracts defect points based on the difference in pixel value of each pixel point in the sub-area. A wafer edge defect detection method provided by this embodiment first extracts the edge area through the edge mask image, which can find the local abnormal area and reduce the dependence on the template, and then extracts the defect points by intercepting multiple sub-areas, and intercepts multiple small-scale defect point detection areas from the large-scale defect point detection area for processing, thereby realizing the optimization and splitting of the detection area. By intercepting the sub-areas, the detection difficulty is reduced, the detection accuracy is improved, and it helps to avoid the generation of over-inspection points.

[0099] like Figure 4 As shown, in some embodiments, step S104: performing statistical analysis on pixels within the sub-region to extract defect points may include:

[0100] Step S1041: Obtain the mean grayscale value of all pixels in the sub-region;

[0101] Step S1042: Obtain the standard deviation of the grayscale values ​​of all pixels in the sub-region;

[0102] Step S1043: Obtain a first difference between the grayscale value of each pixel in the sub-region and the mean value;

[0103] Step S1044: Pixels whose absolute value of the first difference is greater than or equal to K times the standard deviation are regarded as defective points;

[0104] In this embodiment, K is a positive number. Figure 5 As shown, the Rect1 area is a sub-area. In the length direction of the edge line, the length of the Rect1 area is used as the interval to calculate the mean Mean and standard deviation Std of the grayscale values ​​of all pixels in the Rect1 area. All pixel points in the Rect1 area are traversed, and the absolute value of the grayscale value minus the mean Mean is greater than K times Std as the binarization standard to obtain the defect point.

[0105] The calculation formula for the mean grayscale value of pixels in the Rect1 area is:

[0106]

[0107] Where X ij[n] is the grayscale value of the pixel at position (i, j) in the Rect1 area, i∈(0, w-1), j∈(0, h-1). The width of the Rect1 area is w, the height is h, and the average grayscale value of the pixels in the Rect1 area is

[0108] The formula for calculating the standard deviation within the Rect1 area is:

[0109]

[0110] The standard deviation of the grayscale values ​​of pixels within the Rect1 area is δ. The formula for binarizing defect points is as follows.

[0111]

[0112] Where K is the standard deviation factor, which is the gray value minus the mean Pixels whose absolute values ​​are greater than K times Std are considered defective points.

[0113] Existing solutions typically use differential algorithms for defect detection. However, in some grain images that generate random backgrounds, the golden template fails, making it impossible to detect edge defects. This embodiment uses statistical analysis to extract defect points, reducing the reliance on templates for wafer edge defect detection. It can accurately locate defect points while avoiding over-detection points.

[0114] like Figure 6 As shown, in some embodiments, step S101: extracting an edge mask image from a wafer template image may include:

[0115] Step S1011: selecting a region of interest from the wafer template image, where the region of interest includes an edge line;

[0116] Step S1012: extracting initial edge contour points located on the edge line from the region of interest using the Canny algorithm;

[0117] Step S1013: screening the initial edge contour points to obtain target edge contour points;

[0118] Step S1014: binarizing the target edge contour points to obtain a mask image.

[0119] This embodiment extracts initial edge contour points using the Canny algorithm, reduces the error rate by introducing non-maximum suppression and double threshold processing, and makes the initial edge contour points closer to the edge line.

[0120] like Figure 7As shown, in some embodiments, step S1012: extracting initial edge contour points located on the edge line from the region of interest using the Canny algorithm may include:

[0121] Step S10121: De-noising the region of interest using Gaussian filtering;

[0122] Step S10122: Calculate the gradient amplitude of each pixel in the denoised region of interest using the Sobel algorithm;

[0123] Step S10123: Filter out the pixel point with the maximum gradient amplitude in the gradient direction as the edge point to be detected by the non-maximum suppression method;

[0124] Step S10124: Screening the edge points to be detected based on the double-threshold detection method to obtain initial edge contour points.

[0125] In this embodiment, the Canny algorithm includes the following steps: eliminating noise in the region of interest through Gaussian filtering, obtaining the gradient direction and magnitude of the boundary of the region of interest through Sobel gradient calculation, removing non-boundary points in the region of interest through non-maximum suppression, retaining points above the first threshold and discarding points below the second threshold through double threshold detection, wherein the first threshold is greater than the second threshold, and screening out interconnected points by suppressing isolated points with weak edges.

[0126] Specifically, the following Gaussian function formula (1) is used to denoise the region of interest.

[0127]

[0128] Among them, σ represents the Gaussian kernel coefficient, G σ Represents the weight of the non-anchor coordinate position (x, y) within the Gaussian kernel. Using a Gaussian kernel for image filtering can smooth the image to remove noise.

[0129] Sobel algorithm's x-direction and y-direction convolution template s x 、s y , and the neighborhood point labeling matrix K of the point to be processed is as shown in formula (2).

[0130]

[0131] The magnitude of the gradient of each pixel in the image can be calculated from formula (2), as shown in formulas (3)-(5).

[0132]

[0133] s x =(a2+2a3+a4)-(a0+2a7+a6)(4)

[0134] s v =(a0+2a1+a2)-(a6+2a5+a4)(5)

[0135] Figure 8 is a schematic diagram of the gradient direction, where and The angle θ is the gradient phase angle of point P. Using non-maximum suppression, the gradient modulus of each pixel is compared with the two adjacent pixels in the gradient direction, and the pixel point with the maximum gradient is retained as the edge point to be tested.

[0136] Figure 9 This is a diagram of dual-threshold detection division. Dual-threshold detection is used. The first threshold is greater than the second threshold. The edge extracted by the first threshold is taken as the main edge. The second threshold edge connected to the main edge is added to the edge defect part to determine the real and potential edges, forming a complete edge information to obtain the edge points to be tested after screening.

[0137] Then, edge point detection is completed by suppressing isolated weak edge points. According to the gradient direction of the filtered edge points to be tested and their mutual distances, points with the same gradient direction are extracted from the filtered edge points to be tested, and points located on the same straight line are found as initial edge contour points.

[0138] like Figure 10 As shown, in some embodiments, step S10124: screening the edge points to be detected based on the dual threshold detection method to obtain initial edge contour points may include:

[0139] Step S101241: extracting points greater than or equal to a first threshold from the edge points to be detected as first edge points;

[0140] Step S101242: extracting points smaller than the first threshold and greater than or equal to the second threshold from the edge points to be detected as second edge points;

[0141] Step S101243: extracting points connected to the first edge point from the second edge points as third edge points;

[0142] Step S101244: extract points located on the same straight line from the first edge point and the third edge point as initial contour points.

[0143] In this embodiment, the first threshold is greater than the second threshold. In this embodiment, dual threshold detection can exclude the background area by the first threshold and then smooth the edge contour by the second threshold, so that the extracted initial contour points can be connected to form a complete edge line.

[0144] like Figure 11As shown, in some embodiments, step S1013: screening the initial edge contour points to obtain the target edge contour points may include:

[0145] Step S10131: performing gradient calculation on the region of interest using the Sobel algorithm;

[0146] Step S10132: taking the absolute value of the gradient calculation result to obtain the Sobel image;

[0147] Step S10133: obtaining a detection line passing through the initial edge contour point in the region of interest along a direction perpendicular to the edge line;

[0148] Step S10134: obtaining a second difference between the grayscale values ​​of adjacent pixels on the detection line;

[0149] Step S10135: Acquire initial edge contour points whose absolute values ​​of the second difference values ​​are all smaller than the preset difference value as target edge contour points.

[0150] In this embodiment, the absolute value of the difference between the maximum and minimum Sobel gradient values ​​in the adjacent range is used as the screening condition. If the value is less than a fixed value, that is, the preset difference, the initial edge contour point is discarded as the endpoint, which helps to improve the consistency of the area to be detected.

[0151] Specifically, if Figure 12a 、 12b As shown in the figure, the Sobel algorithm is used in the horizontal and vertical directions to calculate the gradient of the entire region of interest, and the absolute value of the calculation result is taken to obtain the Sobel image. On the Sobel image, the edge line is calculated as the center, and the initial edge contour point whose absolute value of the gray value difference between adjacent pixels on the detection line is less than the preset value is obtained as the target edge contour point. Figure 13 As shown in the figure, the gray squares are used to represent the edge lines, and the rectangular boxes are used to represent the detection lines.

[0152] like Figure 14 As shown, in some embodiments, step S1014: performing binarization processing on the target edge contour points to obtain a mask image may include:

[0153] Step S10141: binarizing the target edge contour points to obtain an initial mask image;

[0154] Step S10142: performing morphological dilation on the initial mask image to obtain an expanded mask image;

[0155] Step S10143: Perform morphological corrosion on the extended mask image to cut off both ends of the edge line to obtain a mask image.

[0156] In this embodiment, it is assumed that A and B are Z2 For two sets of , the morphological expansion of B to A (A⊕B) can be expressed as follows.

[0157]

[0158] The morphological dilation of A by B is represented as the set of all displacements z, The foreground element of A must overlap with at least one element of A. Performing a morphological dilation operation on the initial mask image can connect the target edge contour points within 3 pixels to obtain a boundary contour line, and widen the detection area of ​​the mask image around the boundary contour line to obtain an extended mask image.

[0159] Assume A and B are Z 2 Two sets of B, morphological corrosion of A It can be expressed as follows.

[0160]

[0161] Where A is a set of foreground pixels, B is a structuring element, and z is the foreground pixel value. Erosion of the extended mask image can remove the endpoints of the boundary contour, preventing over-detection linearity caused by endpoint anomalies.

[0162] In the existing technical solutions, when generating the boundary area mask, the boundary contour detection area is usually filtered pixel by pixel by setting the gradient threshold range, resulting in a large correlation between the generated detection area and the quality of the golden template. The grayscale abnormal jump points around the boundary of the golden template image will be filtered out on the mask, resulting in the inability to detect the points. In order to solve the above problems, the wafer edge defect detection method provided in this embodiment uses a boundary contour detection algorithm to preliminarily generate a set of target edge contour points during the generation of the edge mask image, and then uses a morphological method to remove the endpoints of long straight lines, so that the detection area generation range of the mask image is controllable. During actual detection, the detection area can be selected in the vicinity of the edge straight line as needed, and the detection area of ​​the generated mask image is less affected by the quality of the wafer template image.

[0163] like Figure 15 As shown, in some embodiments, before step S103: intercepting multiple sub-regions in the edge region along the length direction of the edge straight line, the method further includes:

[0164] Step S110: pre-processing the edge area using a three-frame difference algorithm.

[0165] In this embodiment, the edge area is extracted by the three-frame difference algorithm. Compared with the gradient feature, the three-frame difference algorithm has a better feature extraction effect on the weak defect points around the long straight line. Figure 16As shown, the first column is the range of a horizontal straight line in the edge area. Rect1 frame, Rect2 frame, and Rect3 frame images of the same size are selected. Rect2 is used as the reference frame, Rect1 and Rect3 are used as adjacent frames, and the reference frame is bitwise differentiated with the adjacent frames. Then, the minimum value of the same position of the differential result is taken to obtain the preprocessed edge area, and the preprocessed edge area is used for subsequent detection steps.

[0166] like Figure 17 As shown, in some embodiments, before step S103: intercepting multiple sub-regions in the edge region along the length direction of the edge straight line, the method further includes:

[0167] Step S111: filtering the pre-processed edge area using a box filter.

[0168] In this embodiment, Figure 18 As shown in the figure, a 3*3 box filter is used to filter the edge areas after preprocessing using the three-frame difference algorithm. This suppresses abnormal fluctuations in pixel thresholds around the boundaries caused by imaging issues. The 3*3 box filter can filter out local single-pixel feature mutation points, reducing over-inspection issues caused by image quality issues.

[0169] like Figure 19 As shown, in some embodiments, after step S104: performing statistical analysis on the pixels within the sub-region to extract defect points, the following further comprises:

[0170] Step S112: obtaining the average grayscale value of pixels in the area adjacent to the defect point in the wafer image to be tested;

[0171] Step S113: Determine whether the pixel grayscale value of the defective point is greater than the pixel grayscale mean value. If so, the color of the defective point is white; if not, the color of the defective point is black.

[0172] Existing technical solutions usually use differential algorithms to perform color classification on the calculated defect points, requiring the template grain image and the image of the grain to be detected to be aligned pixel by pixel. However, during the grain image acquisition process, there may be deviations between the grain image and the template image, resulting in deviations between the image of the grain to be detected and the template grain image. Therefore, it is necessary to calculate the position deviation between the template grain image and the image of the grain to be detected, otherwise the color of the defect point cannot be judged. In order to solve the above problem, this solution adopts the method of obtaining the grayscale value of the defect area near the detection line direction to obtain the color information of the defect point. Compared with the existing method, this method can avoid the problem of deviation of the defect position between the golden template and the detection area caused by image positioning, splicing, etc. This embodiment classifies the defect points by color based on the mean grayscale value of the pixels in the adjacent areas, so that the color classification of the defect points does not depend on the template, and can avoid the detection problem caused by the position deviation between the template and the wafer image to be tested.

[0173] Figure 20 、 Figure 21 An example diagram of a wafer edge defect detection method provided for executing the first method embodiment of the present application. Figure 20 、 Figure 21 As shown, a wafer edge defect detection method provided by an embodiment of the present application utilizes a three-frame differencing algorithm to initially extract features, then uses a mean filter to filter out abnormal fluctuation points, and finally uses a statistical analysis method to identify defect points with abnormal local variations (i.e., areas with higher grayscale values ​​in the image after statistical calculation). This method reduces the detection process's reliance on golden templates and, through statistical analysis, can accurately locate defect points while avoiding the generation of over-detection points.

[0174] like Figure 22 As shown, in a second aspect of an embodiment of the present application, a wafer edge defect detection device is provided, comprising:

[0175] A first acquisition module 11 is used to extract an edge mask image from a wafer template image;

[0176] A second acquisition module 12 is configured to extract an edge region from the image of the wafer to be tested based on the edge mask image;

[0177] A cutting module 13 is configured to cut out a plurality of sub-regions in the edge region along the length direction of the edge straight line;

[0178] The analysis module 14 is used to perform statistical analysis on the sub-regions to extract defect points.

[0179] The wafer edge defect detection device in the embodiment of the present application may also be a component, integrated circuit, or chip in a terminal. The device may be a mobile electronic device or a non-mobile electronic device. For example, the mobile electronic device may be a mobile phone, a tablet computer, a laptop computer, a PDA, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (PDA), etc. The non-mobile electronic device may be a server, a network attached storage (NAS), a personal computer (PC), a television (TV), an ATM, or an kiosks, etc., which are not specifically limited in the embodiment of the present application.

[0180] The wafer edge defect detection device provided in the embodiment of the present application can implement each process of a wafer edge defect detection method provided in any of the above embodiments. To avoid repetition, they will not be described here.

[0181] Alternatively, as Figure 23 As shown, an embodiment of the present application also provides an electronic device 1100, including a processor 1101, a memory 1102, and a program or instruction stored in the memory 1102 and executable on the processor 1101. When the program or instruction is executed by the processor 1101, each process of the above-mentioned wafer edge defect detection method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0182] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0183] Figure 24 A schematic diagram of the hardware structure of an electronic device implementing an embodiment of the present application.

[0184] The electronic device 1200 includes but is not limited to: a radio frequency unit 1201, a network module 1202, an audio output unit 1203, an input unit 1204, a sensor 1205, a display unit 1206, a user input unit 1207, an interface unit 1208, a memory 1209, and a processor 1210.

[0185] Those skilled in the art will understand that the electronic device 1200 may also include a power source (such as a battery) to power each component, and the power source may be logically connected to the processor 1210 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system. Figure 16 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be repeated here.

[0186] It should be understood that in an embodiment of the present application, the input unit 1204 may include a graphics processing unit (GPU) 12041 and a microphone 12042, and the graphics processor 12041 processes the image data of a static picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 1206 may include a display panel 12061, and the display panel 12061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1207 includes a touch panel 12071 and other input devices 12072. The touch panel 12071 is also called a touch screen. The touch panel 12071 may include two parts: a touch detection device and a touch controller. Other input devices 12072 may include but are not limited to a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and an operating stick, which will not be repeated here. The memory 1209 can be used to store software programs and various data, including but not limited to applications and operating systems. The processor 1210 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understood that the modem processor may not be integrated into the processor 1210.

[0187] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned wafer edge defect detection method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0188] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0189] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned wafer edge defect detection method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0190] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0191] It should be noted that, in this article, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element. In addition, it should be noted that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in the opposite order according to the functions involved. For example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0192] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0193] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A wafer edge defect detection method, characterized in that: include: extracting an edge mask image from a wafer template image; extracting an edge region from the wafer image to be measured based on the edge mask image; Cutting out a plurality of sub-regions in the edge region along the length direction of the edge straight line; Performing statistical analysis on the pixels within the sub-area to extract defect points; Extract edge mask images from wafer template images, including: Selecting a region of interest from the wafer template image, wherein the region of interest includes the edge line; Extracting initial edge contour points located on the edge straight line from the region of interest using a Canny algorithm; Screening the initial edge contour points to obtain target edge contour points; Binarizing the target edge contour points to obtain a mask image; Binarizing the target edge contour points to obtain a mask image, including: Binarizing the target edge contour points to obtain an initial mask image; Performing morphological dilation on the initial mask image to obtain an extended mask image; Morphological corrosion is performed on the extended mask image to cut off both ends of the edge line to obtain the mask image.

2. The wafer edge defect detection method according to claim 1, wherein: Performing statistical analysis on the pixels within the sub-area to extract defect points includes: Obtain the mean grayscale value of all pixels in the sub-region; Obtain the standard deviation of the grayscale values ​​of all pixels in the sub-region; Obtain a first difference between the grayscale value of each pixel in the sub-region and the mean value; Pixels whose absolute value of the first difference is greater than or equal to K times the standard deviation are regarded as defective points; Wherein, K is a positive number.

3. The wafer edge defect detection method according to claim 1, wherein: The sub-region is rectangular, and the edge straight line is located at the center of the sub-region.

4. The wafer edge defect detection method according to claim 1, wherein: Extracting initial edge contour points located on the edge straight line from the region of interest using a Canny algorithm includes: Denoising the region of interest by Gaussian filtering; Calculate the gradient amplitude of each pixel in the region of interest after denoising by using the Sobel algorithm; The pixel point with the largest gradient amplitude in the gradient direction is selected as the edge point to be detected by the non-maximum suppression method; The edge points to be detected are screened based on a double-threshold detection method to obtain the initial edge contour points.

5. The wafer edge defect detection method according to claim 4, wherein: The edge points to be detected are screened based on a double threshold detection method to obtain the initial edge contour points, including: Extracting a point greater than or equal to a first threshold from the edge points to be detected as a first edge point; Extracting points smaller than a first threshold and greater than or equal to a second threshold from the edge points to be detected as second edge points; Extracting a point connected to the first edge point from the second edge points as a third edge point; Extracting points located on the same straight line from the first edge point and the third edge point as the initial edge contour points; The first threshold is greater than the second threshold.

6. The wafer edge defect detection method according to claim 1, wherein: Screening the initial edge contour points to obtain target edge contour points includes: Performing gradient calculation on the region of interest using the Sobel algorithm; Taking the absolute value of the result of the gradient calculation to obtain the Sobel image; Acquire a detection straight line passing through the initial edge contour point in the region of interest along a direction perpendicular to the edge straight line; Obtaining a second difference in grayscale values ​​of adjacent pixels on the detection line; The initial edge contour point whose absolute value of the second difference is smaller than the preset difference is obtained as the target edge contour point.

7. The wafer edge defect detection method according to claim 1, wherein: Before cutting out a plurality of sub-regions in the edge region along the length direction of the edge straight line, the method further includes: The edge region is preprocessed by a three-frame difference algorithm.

8. The wafer edge defect detection method according to claim 7, characterized in that: Before cutting out a plurality of sub-regions in the edge region along the length direction of the edge straight line, the method further includes: The pre-processed edge region is filtered using a box filter.

9. The wafer edge defect detection method according to claim 1, wherein: After performing statistical analysis on the sub-areas to extract defect points, the method further includes: Obtaining a grayscale mean value of pixels in an area adjacent to the defect point in the wafer image to be tested; It is determined whether the pixel grayscale value of the defective point is greater than the pixel grayscale mean value. If so, the color of the defective point is white; if not, the color of the defective point is black.

10. A wafer edge defect detection device, characterized in that: include: A first acquisition module is used to extract an edge mask image from a wafer template image; A second acquisition module is used to extract an edge area from the wafer image to be tested based on the edge mask image; A cutting module, configured to cut out a plurality of sub-regions in the edge region along the length direction of the edge straight line; An analysis module, configured to perform statistical analysis on the sub-areas to extract defect points; Extract edge mask images from wafer template images, including: Selecting a region of interest from the wafer template image, wherein the region of interest includes the edge line; Extracting initial edge contour points located on the edge straight line from the region of interest using a Canny algorithm; Screening the initial edge contour points to obtain target edge contour points; Binarizing the target edge contour points to obtain a mask image; Binarizing the target edge contour points to obtain a mask image, including: Binarizing the target edge contour points to obtain an initial mask image; Performing morphological dilation on the initial mask image to obtain an extended mask image; Morphological corrosion is performed on the extended mask image to cut off both ends of the edge line to obtain the mask image.

11. An electronic device, characterized in that: include: A processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements a wafer edge defect detection method as described in any one of claims 1 to 9.

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