Resonant converter control based on zero current detection

Abstract

The present application is directed to resonant converter control based on zero current detection. A GaN resonant circuit is disclosed. The GaN resonant circuit includes a power switch configured to selectively conduct according to one or more gate signals and configured to generate a switch signal indicating the value of a current flowing through the power switch. The GaN resonant circuit also includes a power switch driver configured to generate the gate signal in response to one or more control signals, wherein the power switch driver is configured to cause the power switch to become non-conductive in response to the switch signal indicating that the value of the current flowing through the power switch has transitioned across a threshold.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the Chinese invention patent application with application number 201911115077.2, application date November 14, 2019, and invention name “Resonant converter control based on zero current detection”.

[0003] Cross-Related Application References

[0004] This patent application claims priority to U.S. Patent Application No. 16 / 190,794, filed on November 14, 2018, entitled “RESONANT CONVERTER CONTROL BASED ON ZERO CURRENT DETECTION” and also U.S. Patent Application No. 16 / 378,529, filed on April 8, 2019. The contents of each of the foregoing publications are hereby incorporated by reference in their entirety. Technical Field

[0005] The present invention relates generally to power conversion circuits, and in particular to power conversion circuits utilizing one or more GaN-based semiconductor devices. Background Art

[0006] Electronic devices such as computers, servers, and televisions use one or more power conversion circuits to convert one form of power to another. Some power conversion circuits use a circuit topology called a half-bridge converter to convert a high DC voltage to a lower DC voltage. Because many electronic devices are sensitive to the size and efficiency of power conversion circuits, new half-bridge converter circuits and components may be needed to meet the needs of new electronic devices. Summary of the invention

[0007] One inventive aspect is a GaN resonant circuit. The GaN resonant circuit includes a power switch configured to selectively conduct according to one or more gate signals and configured to generate a switch signal indicating a value of a current flowing through the power switch. The GaN resonant circuit also includes a power switch driver configured to generate a gate signal in response to one or more control signals, wherein the power switch driver is configured to cause the power switch to become non-conductive in response to the switch signal indicating that the value of the current flowing through the power switch has transitioned across a threshold.

[0008] Another inventive aspect is a method of operating a GaN resonant circuit. The method includes providing one or more gate signals to cause a power switch to become selectively conductive. The method also includes generating, with the power switch, a switch signal indicating a value of a current flowing through the power switch. The method also includes generating, with a power switch driver, the gate signal in response to one or more control signals. The method also includes causing, with the power switch driver, the power switch to become non-conductive in response to the switch signal indicating that the value of the current flowing through the power switch has transitioned across a threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a simplified schematic diagram of a half-bridge power conversion circuit according to an embodiment of the present invention;

[0010] Figure 2 yes Figure 1 A simplified schematic diagram of the circuitry within the low-side control circuit described in;

[0011] Figure 3 yes Figure 1 A schematic diagram of a first level-shift transistor as described in ;

[0012] Figure 4 yes Figure 1 A schematic diagram of the level shift driving circuit described in ;

[0013] Figure 5 yes Figure 1 A schematic diagram of the blanking pulse generator circuit described in ;

[0014] Figure 6 yes Figure 5 An example of a waveform within a blanking pulse generator as described in;

[0015] Figure 7 yes Figure 1 A schematic diagram of the bootstrap transistor drive circuit described in ;

[0016] Figure 8 yes Figure 1 Block diagram of the low-side transistor driver circuit described in

[0017] Fig. 9 yes Figure 1 A schematic diagram of the starting circuit described in ;

[0018] Fig.10 Can be used as Fig. 9 Schematic diagram of a diode clamp with a series of diode-connected GaN-based enhancement mode transistors;

[0019] Fig.11 yes Figure 1 A schematic diagram of the UVLO circuit described in ;

[0020] Fig.12 yes Figure 1 A schematic diagram of the bootstrap capacitor charging circuit described in ;

[0021] Fig.13 Compared to Fig.12 A schematic diagram of an alternative bootstrap capacitor charging circuit to the circuit described in;

[0022] Fig.14 yes Figure 1 A schematic diagram of the high-side logic and control circuit described in;

[0023] Fig.15 yes Fig.14 a schematic diagram of a first level shift receiver circuit as described in;

[0024] Fig.16 yes Fig.14 a schematic diagram of a second level shift receiver circuit as described in ;

[0025] Fig.17 yes Fig.14 A schematic diagram of the pull-up trigger circuit described in ;

[0026] Fig.18 yes Fig.14 Schematic diagram of the high-side UVLO circuit described in;

[0027] Fig.19 yes Fig.14 A schematic diagram of a high-side transistor driver circuit as described in;

[0028] Fig. 20 yes Fig.14 A schematic diagram of a high-side reference voltage generating circuit as described in;

[0029] Fig.21 is a simplified schematic diagram of a half-bridge power conversion circuit according to another embodiment of the present invention;

[0030] Fig. 22 yes Fig.21 A simplified schematic diagram of the circuitry within the low-side control circuit described in;

[0031] Fig.23 yes Fig. 22 A schematic diagram of a first level-shift transistor as described in ;

[0032] Fig.24 yes Fig. 22 A schematic diagram of the inverter / buffer circuit described in ;

[0033] Fig.25 yes Fig. 22A schematic diagram of the on-pulse generator circuit described in ;

[0034] Fig.26 yes Fig. 22 A schematic diagram of the turn-off pulse generator circuit described in ;

[0035] Fig. 27 yes Fig. 22 A schematic diagram of the blanking pulse generator circuit described in ;

[0036] Fig.28 yes Fig. 22 A schematic diagram of a low-side transistor driver circuit as described in;

[0037] Fig.29 yes Fig.21 A simplified schematic diagram of the circuitry within the high-side control circuit described in;

[0038] Fig.30 yes Fig.29 A schematic diagram of the level shift 1 receiver circuit described in ;

[0039] Fig.31 yes Fig.29 A schematic diagram of the level shift 2 receiver circuit described in ;

[0040] Fig.32 yes Fig.29 Schematic diagram of the high-side UVLO circuit described in;

[0041] Fig.33 yes Fig.29 A schematic diagram of a high-side transistor driver circuit as described in;

[0042] Fig.34 is a schematic diagram of an electrostatic discharge (ESD) clamping circuit according to an embodiment of the present invention;

[0043] Fig.35 is a schematic diagram of an electrostatic discharge (ESD) clamping circuit according to an embodiment of the present invention;

[0044] Fig.36 is an illustration of a portion of an electronic package according to an embodiment of the present invention;

[0045] Fig.37 yes Fig.36 Illustration of an electronic package;

[0046] Fig.38 is an illustration of a half-bridge power conversion circuit according to an embodiment of the present invention.

[0047] Fig.39 Yes Description Fig.38 The operating waveform of the half-bridge power conversion circuit.

[0048] Fig.40 is a schematic illustration of a current sense FET.

[0049] Fig.41 is a layout diagram of an embodiment of a current sensing FET.

[0050] Fig.42 is a schematic diagram of the driver circuit.

[0051] Fig.43 Description Fig.42 A waveform diagram of the operation of the driver circuit.

[0052] Fig.44 is an illustration of a buck half-bridge power conversion circuit.

[0053] Fig.45 Yes Description Fig.44 The operating waveform of the half-bridge power conversion circuit.

[0054] Fig.46 is a schematic illustration of a circuit that may be used in a switching converter;

[0055] Fig.47 Description Fig.46 A waveform diagram of the operation of the driver circuit;

[0056] Fig.48 is a schematic illustration of a circuit that may be used in a switching converter;

[0057] Fig.49 Description Fig.48 A waveform diagram of the operation of the driver circuit. DETAILED DESCRIPTION

[0058] Certain embodiments of the present invention are directed to half-bridge power conversion circuits using one or more gallium nitride (GaN) devices. While the present invention may be applicable to a wide variety of half-bridge circuits, some embodiments of the present invention are particularly applicable to half-bridge circuits designed to operate at high frequency and / or high efficiency with integrated driver circuits, integrated level shifting circuits, integrated bootstrap capacitor charging circuits, integrated startup circuits, and / or hybrid solutions using GaN and silicon devices, as described in more detail below.

[0059] Half-bridge circuit #1

[0060] Reference Figure 1In some embodiments, circuit 100 may include a pair of complementary power transistors (also referred to herein as switches) controlled by one or more control circuits configured to regulate power delivered to a load. In some embodiments, the high-side power transistor along with a portion of the control circuit is disposed on a high-side device, and the low-side power transistor along with a portion of the control circuit is disposed on a low-side device, as described in more detail below.

[0061] Figure 1 The integrated half-bridge power conversion circuit 100 illustrated in FIG. 1 includes a low-side GaN device 103, a high-side GaN device 105, a load 107, a bootstrap capacitor 110, and other circuit elements, as illustrated and discussed in more detail below. Some embodiments may also have an external controller (in the example of FIG. 1 ) that provides one or more inputs to the circuit 100 to regulate the operation of the circuit. Figure 1 Circuit 100 is for illustrative purposes only, and other variations and configurations are within the scope of the present invention.

[0062] In one embodiment, the low-side GaN device 103 may have a GaN-based low-side circuit 104 including a low-side power transistor 115 having a low-side control gate 117. The low-side circuit 104 may further include an integrated low-side transistor driver 120 having an output 123 connected to the low-side transistor control gate 117. In another embodiment, the high-side GaN device 105 may have a GaN-based high-side circuit 106 including a high-side power transistor 125 having a high-side control gate 127. The high-side circuit 106 may further include an integrated high-side transistor driver 130 having an output 133 connected to the high-side transistor control gate 127.

[0063] A voltage source 135 (also referred to as a mains voltage) may be connected to a drain 137 of the high-side transistor 125, and the high-side transistor may be used to control the power input into the power conversion circuit 100. The high-side transistor 125 may further have a source 140 coupled to a drain 143 of the low-side transistor 115, thereby forming a switch node 145. The low-side transistor 115 may have a source 147 connected to ground. In one embodiment, the low-side transistor 115 and the high-side transistor 125 may be GaN-based enhancement field effect transistors. In other embodiments, the low-side transistor 115 and the high-side transistor 125 may be any other type of device, including but not limited to a GaN-based depletion transistor, a GaN-based depletion transistor connected in series with a silicon-based enhancement field effect transistor, a silicon carbide-based transistor, or a silicon-based transistor, the gate of the depletion transistor being connected to the source of the silicon-based enhancement transistor.

[0064] In some embodiments, the high-side device 105 and the low-side device 103 may be made of GaN-based materials. In one embodiment, the GaN-based material may include a layer of GaN on a layer of silicon. In other embodiments, the GaN-based material may include, but is not limited to, a layer of GaN on a layer of silicon carbide, sapphire, or aluminum nitride. In one embodiment, the GaN-based layer may include, but is not limited to, a composite stack of other Group III nitrides such as aluminum nitride and indium nitride and Group III nitride alloys such as AlGaN and InGaN. In other embodiments, the GaN-based low-side circuit 104 and the GaN-based high-side circuit 106 may be disposed on a single GaN-based device. In other embodiments, the GaN-based low-side circuit 104 may be disposed on a first GaN-based device, and the GaN-based high-side circuit 106 may be disposed on a second GaN-based device. In yet other embodiments, the GaN-based low-side circuit 104 and the GaN-based high-side circuit 106 may be disposed on more than two GaN-based devices. In one embodiment, the GaN-based low-side circuit 104 and the GaN-based high-side circuit 106 may contain any number of active or passive circuit element arrangements in any configuration.

[0065] Low side device

[0066] The low-side device 103 may include a plurality of circuits for the control and operation of the low-side device and the high-side device 105. In some embodiments, the low-side device 103 may include a logic, control and level shifting circuit (low-side control circuit) 150 that controls the switching of the low-side transistor 115 and the high-side transistor 125, as discussed in more detail below. The low-side device 103 may also include a startup circuit 155, a bootstrap capacitor charging circuit 157, and a shielding capacitor 160, as also discussed in more detail below.

[0067] Reference Figure 2 , functionally illustrating the circuitry within the low-side control circuit 150. Figures 3 to 14 Each circuit within the low-side control circuit 150 is shown in more detail in . In one embodiment, the main function of the low-side control circuit 150 may be to receive one or more input signals such as PWM signals from a controller and control the operation of the low-side transistor 115 and the high-side transistor 125.

[0068] In one embodiment, the first level-shift transistor 203 and the second level-shift transistor 205 can be used to communicate with the high-side logic and control circuit 153 (see Figure 1). In some embodiments, the first level-shift transistor 203 may be a high voltage enhancement mode GaN transistor. In other embodiments, the first level-shift transistor 203 may be similar to the low-side transistor 115 (see Figure 1 ) and the high-side transistor 125, but their sizes may be much smaller (for example, the gate width of the first level-shift transistor may be tens of microns and have a minimum channel length).

[0069] In other embodiments, only high-side transistor 125 (see Figure 1 ) is turned on, the first level-shift transistor 203 may experience high voltage and high current simultaneously (i.e., the device may operate at a high power portion of the device safe operating area). Such conditions may cause relatively high power dissipation, and therefore some embodiments may involve design and device reliability considerations in the design of the first level-shift transistor 203, as discussed in more detail below. In other embodiments, a first level-shift resistor 207 may be added in series with the source 210 of the first level-shift transistor 203 to limit the gate 213 to source 210 voltage and therefore limit the maximum current through the first level-shift transistor. Other methods may be used to limit the current through the first level-shift transistor 203 and are within the scope of the present invention. The drain 215 of the first level-shift transistor 203 may be coupled to the high-side logic and control circuit 153 (see Figure 1 ), as discussed in more detail below.

[0070] In one embodiment, the first level-shift transistor 203 may include a portion of an inverter circuit having a first input and a first output and configured to receive a first input logic signal at a first input terminal and in response provide a first inverted output logic signal at a first output terminal, as discussed in more detail below. In other embodiments, the first input and first inverted output logic signals may reference different voltage potentials. In some embodiments, the first level-shift resistor 207 may be operable with a first inverted output logic signal referenced to a voltage 13 volts greater than a reference voltage of the first input logic signal. In other embodiments, it may be operable with a first inverted output logic signal referenced to a voltage 20 volts greater than the reference voltage of the first input logic signal, but in other embodiments the voltage may be between 80 and 400 volts greater than the reference voltage of the first input logic signal.

[0071] In other embodiments, the first level shift resistor 207 may be replaced by any form of current sink. For example, in one embodiment, the source 210 of the first level shift transistor 203 may be connected to a gate-to-source short depletion mode device. In another embodiment, a depletion mode device may be fabricated by replacing the enhancement gate stack with a high voltage field plate metal stacked on top of the field dielectric layer. The thickness of the field dielectric and the work function of the metal may be used to determine the pinch-off voltage of the stack.

[0072] In other embodiments, the first level shift resistor 207 may be replaced by a current sink. The current sink may be used by the startup circuit 155 ( Figure 1 155 and discussed in more detail below). Both the depletion transistor and current sink embodiments can produce significant device area reduction compared to the resistor embodiment (i.e., this is because a relatively small depletion transistor will suffice and Iref is already available from the startup circuit 155).

[0073] The second level-shift transistor 205 may be designed similarly to the first level-shift transistor 203 (e.g., in terms of voltage capability, current handling capability, heat tolerance, etc.). The second level-shift transistor 205 may also have an active current sink or resistor built in, similar to the first level-shift transistor 203. In one embodiment, the main difference from the second level-shift transistor 205 may be in its operation. In some embodiments, the main purpose of the second level-shift transistor 205 may be to prevent false triggering of the high-side transistor 125 when the low-side transistor 115 is turned off (see Figure 1 ).

[0074] In one embodiment, for example, false triggering may occur in boost operation when the turn-off of the low-side transistor 115 generates a load current flowing through the high-side transistor 125 while operating the transistor in the third quadrant with its gate shorted to its source (i.e., in synchronous rectification mode). This condition may introduce a dv / dt condition at the switch node (Vsw) 145 because the switch node is at a voltage close to ground when the low-side transistor 115 is turned on and then transitions to the mains voltage 135 in a relatively short period of time. The resulting parasitic C*dv / dt current (i.e., where C=Coss of the first level-shift transistor 203 plus any other capacitance to ground) may cause the first level-shift node 305 (see FIG. 1 ) to be energized. Figure 3 ) becomes pulled low, which will then turn on high-side transistor 125. In some embodiments, this condition may not be desirable because there may be no dead time control and breakdown may occur from both high-side transistor 125 and low-side transistor 115 being in a conductive state at the same time.

[0075] Figure 3The illustration shows one embodiment of how the first level-shift transistor 203 can be electrically coupled to the high-side device 105. The first level-shift transistor 203 located on the low-side device 103 is illustrated, along with a first level-shift transistor 203 that can be located on the high-side device 105 (see Figure 1 ) on the pull-up resistor 303. In some embodiments, the first level-shift transistor 203 can be operated as a pull-down transistor in a resistor pull-up inverter.

[0076] In other embodiments, when the level shift driver circuit 217 (see Figure 2 ) supplies a high gate signal (L1_DR) to the first level shift transistor 203, the first level shift node 305 becomes pulled low, which will be controlled by the high side logic and control circuit 153 (see Figure 1 ) is inverted. The inverted signal appears to turn on the high-side transistor 137 (see Figure 1 ), which then pulls the voltage at the switch node (Vsw) 145 close to the mains voltage 135.

[0077] Conversely, when the level shift driver circuit 217 (see Figure 2 ) supplies a low gate signal to the first level shift transistor 203, the first level shift node 305 becomes pulled to a high logic state, which is controlled by the high side logic and control circuit 153 (see Figure 1 ) is inverted. The inverted signal appears as a low logic state signal that turns off the high-side transistor 125. This scheme may result in a non-inverted gate signal to the high-side transistor 125. In further embodiments, the first level-shift transistor 203 may be designed to be large enough to pull down on the first level-shift node 305, but not so large that its drain-to-source and drain-to-substrate (i.e., semiconductor substrate) capacitances cause false triggering of the high-side logic and control circuit 153.

[0078] In some embodiments, the pull-up resistor 303 may alternatively be an enhancement mode transistor, a depletion mode transistor, or a reference current source element. In further embodiments, the pull-up resistor 303 may be coupled between the drain and the positive terminal of a floating supply (e.g., a bootstrap capacitor discussed in more detail below) referenced to a voltage rail other than ground. In still other embodiments, the first output terminal (LS_NODE) ​​305 is coupled to the switch node (Vsw) 145 (see Figure 1 ) between the first output terminal and the ground, wherein the first capacitance is greater than the second capacitance. The first capacitance may be designed so that in response to the switch node (Vsw) 145 (see Figure 1), allowing a large portion of the C*dv / dt current to conduct through the first capacitor to ensure that the voltage at the first output terminal 305 tracks the voltage at the switch node (Vsw). In some embodiments, the shielding capacitor 160 (see Figure 1 ) can be designed to act as a first capacitor as described above. In other embodiments, shielding capacitor 160 (see Figure 1 ) can be used to connect the first output terminal 305 and the switch node (Vsw) 145 (see Figure 1 ) between the generated capacitance. In yet other embodiments, the shielding capacitor 160 (see Figure 1 ) can also be used to minimize the capacitance between the first output terminal 305 and the substrate (i.e., the semiconductor substrate). More specifically, in some embodiments, a shielding capacitor 160 can be created by adding a conductive shielding layer to the device and coupling the layer to the switch node (Vsw) 145. This structure can effectively create two capacitors. One capacitor is coupled between the output terminal 305 and the switch node (Vsw) 145, and the other capacitor is coupled between the switch node and the substrate. The capacitance between the output terminal 305 and the substrate is thereby virtually eliminated. In other embodiments, the shielding capacitor 160 (see Figure 1 ) can be constructed on the low-side chip 103.

[0079] Logic, control and level shifting circuit 150 (see Figure 2 ) may have other functions and circuits, such as but not limited to a level shift driver circuit 217, a low-side transistor drive circuit 120, a blanking pulse generator 223, a bootstrap transistor drive circuit 225 and an undervoltage lockout circuit 227, as explained in more detail in separate figures below.

[0080] Reference now Figure 4 , showing the level shift driver circuit 217 in more detail. In one embodiment, the level shift driver circuit 217 may include a first inverter 405 and a second inverter 410 in a sequential chain. In other embodiments, because the level shift driver circuit 217 can drive a small gate width first level shift transistor 203, a buffer stage may not be required.

[0081] In one embodiment, the level shift driver circuit 217 is driven directly by a pulse width modulated high side signal (PWM_HS) from a controller (not shown). In some embodiments, the (PWM_HS) signal may be supplied by an external control circuit. In one embodiment, the external control circuit may be an external controller that is in the same package as the high side device 105, the low side device 103, both devices, or in its own package. In other embodiments, the level shift driver circuit 217 may also include a control circuit that controls when the level shift driver circuit is in contact with the first level shift transistor 203 (see Figure 3 ) logic for communication. In one embodiment, an optional low side under voltage lockout signal (LS_UVLO) may be generated by an under voltage lockout circuit within the level shift driver circuit 217. The low side under voltage lockout circuit may be used to shut down the level shift driver circuit 217 if (Vcc) or (Vdd) of the low side (Vdd_LS) becomes below a certain reference voltage or a portion of the reference voltage.

[0082] In another embodiment, the level shift driver circuit 217 may generate a breakdown protection signal for the low side transistor (STP_LS) to prevent breakdown from overlapping gate signals of the low side transistor 115 and the high side transistor 125. The function of the (STP_LS) signal may be to ensure that the low side driver circuit 120 (see FIG. 1 ) is turned on when the gate signal to the high side transistor 125 is low. Figure 2 ) communicates only with the gate terminal of the low-side transistor 115. In other embodiments, the output of the first inverter 405 can be used to generate a breakdown protection signal (STP_LS) for the low-side transistor 115.

[0083] In other embodiments, logic for UVLO and breakdown protection can be implemented by adding a multi-input NAND gate to the first inverter 405, where the inputs to the NAND gate are (PWM_HS), (LS_UVLO), and (STP_HS) signals. In yet other embodiments, if both (STP_HS) and (LS_UVLO) signals are high, the first inverter 405 can respond only to the (PWM_HS) signal. In other embodiments, the STP_HS signal can be generated from the low-side gate driver block 120, as explained in more detail in a separate figure.

[0084] Reference Figure 5 , the blanking pulse generator 223 may be used to generate a pulse signal corresponding to the turn-off transient of the low-side transistor 115. This pulse signal may then turn on the second level-shift transistor 205 for the duration of the pulse, which triggers the high-side device 105 (see Figure 1 ) to prevent the first level shift node 305 voltage from being pulled down incorrectly.

[0085] Figure 5 A schematic diagram illustrating an embodiment of a blanking pulse generator 223 is illustrated. In some embodiments, the low-side transistor 115 gate signal (LS_GATE) is fed to the blanking pulse generator 223 as an input. The (LS_GATE) signal is inverted by the first stage inverter 505 and then sent through the RC pulse generator 510 to generate a positive pulse. In some embodiments, an inverted signal may be required because the pulse corresponds to the falling edge of the (LS_GATE) signal. The capacitor 515 in the RC pulse generator 510 circuit can be used as a high-pass filter that allows the dv / dt at its input to appear across the resistor 520. Once the dv / dt becomes zero at the input to the RC pulse generator 510, the capacitor 515 can be slowly charged by the resistor 520, thereby generating a slow decaying voltage waveform across the resistor. A pulse can then be sent through the second inverter 525, the third inverter 530 and the buffer 535 to generate a square wave pulse of the blanking pulse (B_PULSE) signal. The duration of the pulse may be determined by the values ​​of capacitor 515 and resistor 520 in RC pulse generator 510. In some embodiments, capacitor 515 may be implemented using a drain-to-source shorted enhancement-mode GaN transistor.

[0086] Reference Figure 6 , an example waveform 600 within the blanking pulse generator 223 is illustrated for one embodiment. Trace 605 shows the falling edge of the low side gate pulse (LS_GATE). Trace 610 shows the rising edge of the output of the first stage inverter 505. Trace 615 shows the output of the RC pulse generator 510, and trace 620 shows the resulting blanking pulse (B_PULSE) signal as the output of the blanking pulse generator 223.

[0087] Reference Figure 7 , the bootstrap transistor drive circuit 225 is described in more detail. The bootstrap transistor drive circuit 225 includes an inverter 730, a first buffer 735, and a second buffer 745. The bootstrap transistor drive circuit 225 can receive a (BOOTFET_DR_IN) signal from the low-side driver circuit 120. The (BOOTFET_DR_IN) signal can be inverted relative to the LS_GATE signal. The bootstrap transistor drive circuit 225 can be configured to provide a power supply to the bootstrap charging circuit 157 (see Figure 1) provides a gate drive signal called (BOOTFET_DR), as discussed in more detail below. The (BOOTFET_DR) gate drive signal can be timed to turn on the bootstrap transistor when the low-side transistor 115 is turned on. Moreover, because the bootstrap transistor drive circuit 225 is driven by (Vcc), the output of this circuit can have a voltage that changes from 0 volts in the low state to (Vcc)+6 volts in the high state. In one embodiment, the bootstrap transistor is turned on after the low-side transistor 115 is turned on, and the bootstrap transistor is turned off before the low-side transistor is turned off.

[0088] In some embodiments, the turn-on transient of the (BOOTFET_DR) signal may be delayed by introducing a series delay resistor 705 to the input of the second buffer 745, which may be the gate of the transistor in the final buffer stage. In other embodiments, the turn-on transient of the low-side transistor 115 (see FIG. 1 ) may be delayed by adding a series resistor to the gate of the final pull-down transistor in the low-side driver circuit 120. Figure 1 ). In one embodiment, one or more capacitors may be used in the bootstrap transistor driver circuit 225 and support a voltage on the order of (Vcc), which may be, for example, 20 volts, depending on the end user requirements and the design of the circuit. In some embodiments, one or more capacitors may be fabricated with a field dielectric to GaN capacitor rather than a drain to source shorted enhancement mode transistor.

[0089] Reference Figure 8 , a block diagram of the low-side transistor driving circuit 120 is shown. The low-side transistor driving circuit 120 may include a first inverter 805, a buffer 810, a second inverter 815, a second buffer 820, and a third buffer 825. The third buffer 825 may provide a low-side transistor 115 (see Figure 1 ) provides the (LS_GATE) signal. In some embodiments, two inverter / buffer stages may be used because the low-side transistor 115 (see Figure 1 ) can be synchronized with (Vin). Therefore, (Vin) in a high state can correspond to (Vgate) of the low-side transistor 115 in a high state, and vice versa.

[0090] In other embodiments, certain portions of the low-side driver circuit 120 may have asymmetric hysteresis. Some embodiments may include asymmetric hysteresis using a resistor divider 840 with a transistor pull-down 850.

[0091] Other embodiments may have multiple input NAND gates for the (STP_LS) signal (breakdown protection on the low-side transistor 115). In one embodiment, the low-side driver circuit 120 may receive a breakdown protection signal (STP_LS) from the level-shift driver circuit 217. The purpose of the (STP_LS) signal may be similar to the (STP_HS) signal described previously. The (STP_LS) signal may ensure that the low-side transistor driver circuit 120 does not connect to the gate 117 of the low-side transistor 115 when the level-shift driver circuit 217 output is in a high state (see Figure 1 In other embodiments, the output of the first inverter stage 805 can be used as a (STP_HS) signal for the level-shift driver circuit 217 and a (BOOTFET_DR_IN) signal for the bootstrap transistor driver circuit 225.

[0092] In some embodiments, the low-side transistor driver circuit 120 may use a UVLO circuit 227 (see Figure 2 ) received (LS_UVLO) signal. Other embodiments may use a turn-off delay resistor that may be connected in series with the gate of the final pull-down transistor in the final buffer stage 825. The delay resistor is used in some embodiments to ensure that the bootstrap transistor is turned off before the low-side transistor 115 is turned off.

[0093] Reference Fig. 9 , describing the startup circuit 155 in more detail. The startup circuit 155 can be designed with numerous functionalities, as discussed in more detail below. Primarily, the startup circuit 155 can be used to provide an internal voltage (START_Vcc in this case) and provide sufficient current to support the circuit driven by (Vcc). This voltage can remain on to support the circuit until (Vcc) charges to the voltage (V+) required externally from the mains voltage 135. The startup circuit 155 can also provide a reference voltage (Vref) and a reference current sink (Iref) that can be independent of the startup voltage.

[0094] In one embodiment, the depletion mode transistor 905 may act as the main current source in the circuit. In other embodiments, the depletion mode transistor 905 may be formed by a metal layer disposed above the passivation layer. In some embodiments, the depletion mode transistor 905 may use a high voltage field plate (typically inherent to any high voltage GaN technology) as a gate metal. In other embodiments, the field dielectric may act as a gate insulator. The resulting gated transistor may be a depletion mode device with a high channel pinch-off voltage (V pinch-off) (i.e., the pinch-off voltage is proportional to the field dielectric thickness). The depletion mode transistor 905 may be designed to block a relatively high voltage between its drain (connected to V+) and its source. This connection may be referred to as a source follower connection. The depletion mode transistor 905 may have a gate 906 coupled to ground, a source 907 coupled to a first node 911, and a drain 909 coupled to a voltage source 135.

[0095] In another embodiment, a series of identical diode-connected enhancement type low voltage transistors 910 may be connected in series with the depletion type transistor 905. The series of identical diode-connected enhancement type low voltage transistors 910 may be connected in series between a first node 911 and a second node 912. One or more intermediate nodes 913 may be placed between each of the identical diode-connected enhancement type low voltage transistors 910 in series. The width to length ratio of the transistor may set the current drawn from (V+) and the voltage across each diode. In order to remove the threshold voltage and handle the variation sensitivity, the identical diode-connected enhancement type low voltage transistors 910 in series may be designed as large channel length devices. In some embodiments, the identical diode-connected enhancement type low voltage transistors 910 in series may be replaced by one or more high value resistors.

[0096] In a further embodiment, at the bottom end of the same diode-connected enhancement low voltage transistor 910 in series, a current mirror 915 may be composed of two enhancement low voltage transistors and used to generate a reference current sink (Iref). The first current mirror transistor 920 may be diode-connected, and the second current mirror transistor 925 may have a gate connected to the gate of the first current mirror transistor. The source of the first current mirror transistor 920 and the source of the second current mirror transistor 925 may be coupled and tied to ground, respectively. The drain terminal of the first current mirror transistor 920 may be coupled to the second node 912, and the source terminal of the second current mirror transistor 925 may be used as a current sink terminal. This stack of the current mirror 915 and the same diode-connected enhancement low voltage transistor 910 in series may form a device called a "source follower load" to the depletion transistor 905.

[0097] In other embodiments, when the gate 906 of the depletion-mode transistor 905 is tied to ground, the source 907 of the depletion-mode transistor may take a voltage close to (V pinch-off) when current is supplied to the "source follower load". At the same time, the voltage drop across the diode-connected transistor 920 in the current mirror 915 may be close to the threshold voltage (Vth) of the transistor. This condition implies that the voltage drop across each of the same diode-connected enhancement-mode low-voltage transistors 910 in series may be equal to (V pinch-off - Vth) / n, where 'n' is the number of diode-connected enhancement-mode transistors between the current mirror 915 and the depletion-mode transistor 905.

[0098] For example, if the gate of the start transistor 930 is connected from the bottom to the third identical diode-connected enhancement-mode low voltage transistor, the gate voltage of the start transistor may be 3*(Vpinch-Vth) / n+Vth. Therefore, the start voltage may be 3*(Vpinch-Vth) / n+Vth-Vth=3*(Vpinch-Vth) / n. As a more specific example, in one embodiment where (Vpinch)=40 volts, (Vth)=2 volts, where n=6 and (Vstart)=19 volts.

[0099] In other embodiments, the startup circuit 155 may generate a reference voltage signal (Vref). In one embodiment, the circuit generating (Vref) may be similar to the startup voltage generating circuit discussed above. The reference voltage transistor 955 may be connected between two series-connected transistors in the same diode-connected enhancement-mode low voltage transistor 910. In one embodiment, (Vref) = (Vpinch-Vth) / n.

[0100] In other embodiments, a disable pull-down transistor 935 may be connected across the gate of the enable transistor 930 to the source. When the disable signal is high, the enable transistor 930 will be disabled. A pull-down resistor 940 may be connected to the gate of the disable transistor 935 to prevent erroneous turn-on of the disable transistor. In other embodiments, a diode clamp 945 may be connected between the gate and source terminals of the enable transistor 930 to ensure that the gate-to-source voltage capability of the enable transistor is not violated during circuit operation (i.e., configured as a gate overvoltage protection device). In some embodiments, the diode clamp 945 may be fabricated with a series diode-connected GaN-based enhancement mode transistor 1050, such as Fig.10 As described in .

[0101] Reference Fig.11 , the UVLO circuit 227 is described in more detail. In some embodiments, the UVLO circuit 227 may have a differential comparator 1105, a downward level shifter 1110, and an inverter 1115. In other embodiments, the UVLO circuit 227 may be provided by the startup circuit 155 (see Fig. 9 ) are used in the differential comparator / down level shifter circuit to generate the voltage (Vref) and (Iref) fed to the level shift driver circuit 217 (see Figure 2 ) and the (LS_UVLO) signal in the low-side transistor driver circuit 120. In some embodiments, the UVLO circuit 227 can also be designed to have an asymmetric hysteresis. In other embodiments, the output of the UVLO circuit 227 can be independent of the threshold voltage. This can be achieved by selecting a differential comparator with a relatively high gain. In one embodiment, the gain can be increased by increasing the value of the pull-up resistor in the current source and the differential comparator. In some embodiments, the limit of the current and the resistor can be set by (Vref).

[0102] In other embodiments, the voltages (VA) 1120 and (VB) 1125 may be proportional to (Vcc) or (Vdd_LS) and (Vref), respectively, as indicated by the resistor divider ratio on each input. When (VA) 1120>(VB) 1125, the output of the inverting terminal becomes a low state. In a specific embodiment, the low state = (Vth) because the current source produces a source follower configuration. Similarly, when (VA) 1120<(VB) 1125, the output becomes a high state (Vref). In some embodiments, a downward level shifter 1110 may be required because the low voltage needs to be shifted downward by a threshold voltage to ensure that the low input to the next stage is below (Vth). The downward shifted output can be inverted by a simple resistor pull-up inverter 1115. The output of the inverter 1115 is the (LS_UVLO) signal.

[0103] Reference Fig.12 , the bootstrap capacitor charging circuit 157 is described in more detail. In one embodiment, the bootstrap diode and transistor circuit 157 may include a parallel connection of a high voltage diode-connected enhancement mode transistor 1205 and a high voltage bootstrap transistor 1210. In other embodiments, the high voltage diode-connected enhancement mode transistor 1205 and the high voltage bootstrap transistor 1210 may be designed to share the same drain finger. In some embodiments, the bootstrap transistor driver circuit 225 (see Figure 2 ) derives the (BOOTFET_DR) signal. As discussed above, the high voltage bootstrap transistor 1210 can be coupled to the low side transistor 115 (see Figure 1 ) are turned on in a coincident manner.

[0104] Reference Fig.13 , which can replace the above Fig.12 The bootstrap diode and transistor circuit 157 discussed in the previous section uses an alternative bootstrap diode and transistor circuit 1300. Fig.13In the embodiment illustrated in FIG. 1 , the depletion-mode device 1305 cascoded by the enhancement-mode low voltage GaN device 1310 may be connected as illustrated in the schematic 1300. In another embodiment, the gate of the depletion-mode device 1305 may be connected to ground to reduce the voltage stress on the cascoded enhancement-mode device 1310, depending on the pinch-off voltage of the depletion-mode device.

[0105] High side device

[0106] Reference Fig.14 , details an embodiment of the high-side logic and control circuit 153. In one embodiment, the high-side driver 130 receives input from the first level shift receiver 1410 and the high-side UVLO circuit 1415 and provides a high-side transistor 125 (see Figure 1 ) sends the (HS_GATE) signal. In yet other embodiments, the pull-up trigger circuit 1425 is configured to receive the (LSHIFT_1) signal and control the pull-up transistor 1435. In some embodiments, the second level shift receiving circuit 1420 is configured to control the blanking transistor 1440. Both the pull-up transistor 1435 and the blanking transistor 1440 can be connected in parallel with the pull-up resistor 1430. As discussed below and in some cases in Figures 16 to 20 Each circuit within the high-side logic and control circuit 153 is shown in more detail in FIG.

[0107] Reference Fig.15 , the first level shift receiver 1410 is described in more detail. In some embodiments, the first level shift receiver 1410 can convert the (L_SHIFT1) signal into a signal that can be driven by the high-side transistor driver 130 (see Fig.14 ) to drive the high-side transistor 125 (see Figure 1 ). In other embodiments, the first level shift receiver 1410 may have three enhancement mode transistors 1505, 1510, 1515 used in a multi-level down shifter and a plurality of diode-connected transistors 1520 acting as diode clamps, as discussed in more detail below.

[0108] In one embodiment, the first level shift receiver 1410 may shift the (L_SHIFT1) signal down by 3*Vth (e.g., each enhancement mode transistor 1505, 1510, 1515 may have a gate to source voltage close to Vth). In some embodiments, the last source follower transistor (e.g., in this case transistor 1515) may have a three-diode connected transistor clamp 1520 across its gate to source. In other embodiments, this arrangement may be used because its source voltage may only be as high as (Vdd_HS) (i.e., because its drain is connected to Vdd_HS), while its gate voltage may be as high as V(L_SHIFT1)-2*Vth. Therefore, in some embodiments, the maximum gate to source voltage on the last source follower transistor 1515 may be greater than the maximum rated gate to source voltage of the device technology. The output of the final source follower transistor 1515 is to the high side transistor driver 130 (see Figure 1 ) (i.e., the output is the LS_HSG signal). In other embodiments, more or less than three source follower transistors may be used. In still other embodiments, more or less than three diode-connected transistors may be used in clamp 1520.

[0109] Reference Fig.16 , the second level shift receiver 1420 is described in more detail. In one embodiment, the second level shift receiver 1420 may have a down level shift circuit 1605 and an inverter circuit 1610. In some embodiments, the second level shift receiver 1420 may be connected to the first level shift receiver 1410 (see Fig.15 ) except that the second level shift receiver may have only one down level shift circuit (e.g., enhancement mode transistor 1615) and a following inverter circuit 1610. In one embodiment, the down level shift circuit 1605 may be derived from the second level shift transistor 205 (see Figure 2 ) receives the (L_SHIFT2) signal. In one embodiment, the inverter circuit 1610 can be driven by the (VBOOST) signal, and the gate voltage of the pull-up transistor of the inverter can be used to drive the blanking transistor 1440 (see Fig.14 ). In some embodiments, the voltage may go from 0 volts in the low state to (Vboot + 0.5*(Vboot - Vth)) in the high state. Similar to the first level shift receiver 1410, the second level shift receiver 1420 may have a diode connected transistor clamp 1620 across the gate to source of the source follower transistor 1615. In other embodiments, the clamp 1620 may include more or less than three diode connected transistors.

[0110] Reference Fig.17, the pull-up trigger circuit 1425 is described in more detail. In one embodiment, the pull-up trigger circuit 1425 may have a first inverter 1705, a second inverter 1710, an RC pulse generator 1715, and a gate-to-source clamp 1720. In some embodiments, the pull-up trigger circuit 1425 may receive the (L_SHIFT1) signal as an input, and in response, once the (L_SHIFT1) voltage approximately transitions to the input threshold of the first inverter 1705, the pull-up trigger circuit generates a pulse. The generated pulse can be used to drive the pull-up transistor 1435 (see Fig.14 The second inverter 1710 may be driven by (Vbootstrap) instead of (Vdd_HS) because the gate voltage of the pull-up transistor 1435 may need to be greater than the (L_SHIFT1) signal voltage.

[0111] Reference Fig.18 , the high-side UVLO circuit 1415 is described in more detail. In one embodiment, the high-side UVLO circuit 1415 may have a downward level shifter 1805, a resistor pull-up inverter 1810 with asymmetric hysteresis, and a gate-to-source clamp 1815. In other embodiments, the (HS_UVLO) signal generated by the high-side UVLO circuit 1415 may be helpful to shut down the high-side driver circuit 130 (see Fig.14 ) to prevent circuit failure. In some embodiments, the bootstrap capacitor 110 voltage (Vbootstrap) (i.e., floating supply voltage) is measured, and in response, a logic signal is generated and combined with the output signal (LS_HSG) from the first level shift receiver 1410, which is then used as an input to the high-side gate drive circuit 130. More specifically, in this embodiment, for example, the UVLO circuit is designed to engage when (Vbootstrap) decreases to less than 4*Vth above the switch node (Vsw) 145 voltage. In other embodiments, different threshold levels may be used.

[0112] In other embodiments, the high-side UVLO circuit 1415 may shift (VBOOST) downward in the downward level shifter 1805 and transfer the signal to the inverter with asymmetric hysteresis 1810. The output of the inverter with asymmetric hysteresis 1810 may produce a signal that is logically combined with the output from the first level shift receiver 1410 to turn off the high-side transistor 125 (see FIG. Figure 1 ) of the HS_UVLO signal. In some embodiments, hysteresis can be used to reduce the high-side transistor 125 (see Figure 1 ) can be detrimental to the overall performance of the half-bridge circuit 100.

[0113] Reference Fig.19 , the high-side transistor driver 130 is described in more detail. The high-side transistor driver 130 may have a first inverter stage 1905 followed by a high-side driver stage 1910. The first inverter stage 1905 may enable the high-side transistor driver 130 to be driven by a level-shifted 1 receiver 1410 (see Fig.15 ) receives the down-shifted (LS_HSG) signal inverted. The down-shifted signal may then be sent through the high-side driver stage 1910. The high-side driver stage 1910 may generate a (HS_GATE) signal to drive the high-side transistor 125 (see Figure 1 In other embodiments, the first inverter stage 1905 may include a circuit that ensures that the high-side transistor 125 is turned off when (HS_UVLO) is in a high state (see Figure 1 )'s two-input NOR gate.

[0114] Reference Fig. 20 , a reference voltage generation circuit 2000 may be used to generate a high-side reference voltage from a supply rail. This circuit may be placed on the high-side GaN device 105 to generate an internal power supply for the reference switch node voltage 145. In some embodiments, the circuit 2000 may be similar to Fig. 9 145 . A difference in circuit 2000 may be the addition of a source follower capacitor 2010 connected between the first node 2011 and the second node 2012. In some embodiments, the source follower capacitor 2010 may be needed to ensure that a well-regulated voltage is generated between the first node 2011 and the second node 2012 that does not fluctuate with the dv / dt present at the switching node (Vsw) 145. In other embodiments, a reference voltage capacitor 2015 may be connected between the source of the reference voltage transistor 2055 and the second node 2012. In some embodiments, the drain of the reference voltage transistor 2055 may be connected to the (Vbootstrap) node. In some embodiments, the reference voltage capacitor 2015 may be needed to ensure that (Vref) is well-regulated and does not fluctuate with the switching node (Vsw) 145 (see Figure 1 ) in response to a high dv / dt condition at ). In yet other embodiments, another difference in circuit 2000 may be that second node 2012 may be coupled to a changing voltage, such as switch node (Vsw) 145 (see Figure 1 ) rather than passing through the current sink circuit 915 (see Fig. 9 ) is connected to the ground of the half-bridge circuit 100. In yet another embodiment, (Vref) can be used as (Vdd_HS) in the half-bridge circuit 100.

[0115] Another difference in circuit 2000 may be the addition of a high voltage diode-connected transistor 2025 coupled between the depletion-mode transistor 2005 and the same diode-connected enhancement-mode low voltage transistor 2020 in series (i.e., the gate of the transistor is coupled to the source of the transistor). More specifically, the high voltage diode-connected transistor 2025 may have a source coupled to the depletion-mode transistor 2005, a drain coupled to the first node 2011, and a gate coupled to its source. The high voltage diode-connected transistor 2025 may be used to ensure that the source follower capacitor 2010 does not discharge when the voltage at the top plate of the source follower capacitor rises above (V+). In other embodiments, the source follower capacitor 2010 may be relatively small and may be integrated on a semiconductor substrate or within an electronic package. In Fig. 20 Also shown in FIG. 1 is a bootstrap capacitor 110 that can be added externally to the half-bridge circuit.

[0116] In some embodiments, shield capacitor 160 (see Figure 1 ) can be obtained from the first level shift node 305 (see Figure 3 ) and a second level shift node (not shown) are connected to the switch node 145 to assist in reducing false triggering as discussed above. In some embodiments, the larger the value of the shielding capacitor 160, the less susceptible the circuit is to false triggering caused by parasitic capacitance to ground. However, during the off period of the high-side transistor 125, the shielding capacitor 160 can be connected to the first level shift node 305 by the pull-up resistor 303 (see Figure 3 ) discharge. This can significantly slow down the high-side transistor 125 turn-off process. In some embodiments, this consideration can be used to set an upper limit on the value of the shielding capacitor 160. In other embodiments, the first level shift node and the switch node 145 can be connected by using a clamp circuit 161 (see Figure 1 ) to prevent the first level shift node 305 (see Figure 3 ) overvoltage condition on the . In some embodiments, the clamp circuit 161 can be formed by a diode-connected transistor, wherein the drain of the transistor is connected to the first level shift node 305 (see Figure 3 ) and the gate and source are connected to the switch node (Vsw) 145 (see Figure 1 In other embodiments, the second shielding capacitor and the second clamp circuit may be placed between the second level shift node and the switch node (Vsw) 145 (see Figure 1 )between.

[0117] Half-bridge Circuit #1 Operation

[0118] The following sequence of operations of the half-bridge circuit 100 is merely an example, and other sequences may be used without departing from the invention. Figure 1 , 2and 14.

[0119] In one embodiment, when the (PWM_LS) signal from the controller is high, the low side logic, control and level shift circuit 150 sends a high signal to the low side transistor driver 120. The low side transistor driver 120 then communicates with the low side transistor 115 via the (LS_GATE) signal to turn it on. This sets the switch node voltage (Vsw) 145 to near 0 volts. When the low side transistor 115 is turned on, it provides a path for the bootstrap capacitor 110 to become charged through the charging circuit 157 connected between (Vcc) and (Vbootstrap). The charging path has a high voltage bootstrap diode 1205 (see Fig.12 ) and the parallel combination of transistor 1210. (BOOTFET_DR) signal to bootstrap transistor 1210 (see Fig.12 ) provides a drive signal that provides a low resistance path for charging the bootstrap capacitor 110.

[0120] Bootstrap diode 1205 (see Fig.12 ) can be used to ensure that there is a path for charging the bootstrap capacitor 110 during startup when there is no low-side transistor 115 gate drive signal (LS_GATE). During this time, the (PWM_HS) signal should be low. If the (PWM_HS) signal is accidentally turned on (i.e., in a high state) during this time, the (STP_HS) signal generated from the low-side transistor driver 120 will prevent the high-side transistor 125 from turning on. If the (PWM_LS) signal is turned on when the (PWM_HS) signal is turned on, the (STP_LS) signal generated from the level shift driver circuit 217 will prevent the low-side transistor 115 from turning on. Moreover, in some embodiments, the (LS_UVLO) signal can prevent the low-side transistor 115 and the high-side transistor 125 from turning on when (Vcc) or (Vdd_LS) becomes lower than a preset threshold voltage level.

[0121] In other embodiments, when the (PWM_LS) signal is low, the low-side gate signal (LS_GATE) to the low-side transistor 115 is also low. During the dead time between the (PWM_LS) signal low state to the (PWM_HS) high state transition, the inductive load will force the high-side transistor 125 or the low-side transistor 115 to turn on in the synchronous rectifier mode, depending on the direction of power flow. If the high-side transistor 125 is turned on during the dead time (e.g., during boost mode operation), the switch node (Vsw) 145 voltage can rise to close to (V+) 135 (mains voltage).

[0122] In some embodiments, due to capacitive coupling to ground, the dv / dt conditions on the switch node 145 (Vsw) may tend to level shift the first level shift node (LSHIFT_1) 305 (see Figure 3 ) to a low state. This can turn on the high-side gate drive circuit 130, causing an unintended triggering of the high-side transistor 125. In one embodiment, this does not create a dead time that could damage the half-bridge circuit 100 under a breakdown condition. In other embodiments, to prevent this condition from occurring, the blanking pulse generator 223 can sense the turn-off transient of the low-side transistor 115 and send a pulse to turn on the second level-shift transistor 205. This can pull the (L_SHIFT2) signal voltage to a low state which then communicates with the second level-shift receiver 1420 to generate a blanking pulse signal (B_PULSE) to drive the blanking transistor 1440. The blanking transistor 1440 can then act as a pull-up to prevent the first level-shift node (LSHIFT_1) 305 (see Figure 3 ) becomes a low state relative to the switching node (Vsw) 145.

[0123] In other embodiments, after the dead time, when the (PWM_HS) signal goes high, the level shift driver circuit 217 may send a high signal to the gate of the first level shift transistor 203 (via the L1_DR signal from the level shift driver circuit 217). The high signal will shift the first level shift node (LSHIFT_1) 305 (see FIG. 1 ) relative to the switch node (Vsw) 145. Figure 3 ) is pulled low, which will produce a high signal at the input of the high-side transistor 125, turning on the high-side transistor 125. The switch node voltage (Vsw) 145 will remain close to (V+) 135. In one embodiment, during this time, the bootstrap capacitor 110 can be discharged through the first level-shift transistor 203 (which is in the on state during this time).

[0124] If the high-side transistor 125 remains on for a relatively long time (i.e., a large duty cycle), the bootstrap capacitor 110 voltage will drop to a low voltage that is low enough that it will prevent the high-side transistor 125 from turning off when the (PWM_HS) signal goes low. In some embodiments, this may occur because the maximum voltage that the (L_SHIFT1) signal can reach is (Vbootstrap), which may be too low to turn off the high-side transistor 125. In some embodiments, this situation can be prevented by the high-side UVLO circuit 1415, which forcibly turns off the high-side transistor 125 by sending a high input to the high-side gate drive circuit 130 when (Vbootstrap) becomes below a certain level.

[0125] In yet other embodiments, when the (PWM_HS) signal goes low, the first level-shift transistor 203 will also be turned off (via the L1_DR signal from the level-shift driver circuit 217). This will shift the first level-shift node (LSHIFT_1) 305 (see Figure 3 ) to a high state. However, in some embodiments, this process may be relatively slow because of the high value pull-up resistor 303 (see Figure 3 ) (in some embodiments to reduce power consumption) needs to be attached to the first level shift node (L_SHIFT1) 305 (see Figure 3 ) is charged, including the output capacitance (Coss) of the first level shift transistor 213 and the shielding capacitor 160. This can increase the turn-off delay of the high-side transistor 125. In order to reduce the turn-off delay of the high-side transistor 125, the pull-up trigger circuit 1425 can be used to sense the first level shift node (L_SHIFT1) 305 (see Figure 3 ) becomes higher than (Vth). This condition may generate a (PULLUP_FET) signal applied to a pull-up transistor 1435 acting in parallel with the pull-up resistor 1430, which may significantly accelerate the first level shift node (L_SHIFT1) 305 (see Figure 3 ) voltage, thereby facilitating the shutdown process.

[0126] Half-bridge circuit #2

[0127] Reference Fig.21 , discloses a second embodiment of a half-bridge circuit 2100. The half-bridge circuit 2100 may have Figure 1 2100, however, the level-shift transistors in circuit 2100 can operate with pulsed inputs rather than continuous signals, as described in more detail below. In some embodiments, the pulsed inputs can result in lower power, reduced stress on the level-shift transistors, and reduced switching times, as discussed in more detail below.

[0128] Continue to refer Fig.21 , one embodiment includes an integrated half-bridge power conversion circuit 2100 using a low-side GaN device 2103, a high-side GaN device 2105, a load 2107, a bootstrap capacitor 2110, and other circuit elements, as discussed in more detail below. Some embodiments may also have an external controller (in the example of FIG. 1 ) that provides one or more inputs to the circuit 2100 to regulate the operation of the circuit. Fig.21 Circuit 2100 is for illustrative purposes only, and other variations and configurations are within the scope of the present invention.

[0129] As in Fig.21, in one embodiment, the integrated half-bridge power conversion circuit 2100 may include a low-side circuit disposed on a low-side GaN device 2103, the low-side GaN device 2103 including a low-side transistor 2115 having a low-side control gate 2117. The low-side circuit may further include an integrated low-side transistor driver 2120 having an output 2123 connected to the low-side transistor control gate 2117. In another embodiment, there may be a high-side circuit disposed on a high-side GaN device 2105 including a high-side transistor 2125 having a high-side control gate 2127. The high-side circuit may further include an integrated high-side transistor driver 2130 having an output 2133 connected to the high-side transistor control gate 2127.

[0130] The high-side transistor 2125 can be used to control the power input into the power conversion circuit 2100 and has a voltage source (V+) 2135 (sometimes referred to as a mains voltage) connected to the drain 2137 of the high-side transistor. The high-side transistor 2125 may further have a source 2140 coupled to the drain 2143 of the low-side transistor 2115, thereby forming a switch node (Vsw) 2145. The low-side transistor 2115 may have a source 2147 connected to ground. In one embodiment, the low-side transistor 2115 and the high-side transistor 2125 may be enhancement field effect transistors. In other embodiments, the low-side transistor 2115 and the high-side transistor 2125 may be any other type of device, including but not limited to a GaN-based depletion transistor, a GaN-based depletion transistor connected in series with a silicon-based enhancement field effect transistor, a silicon carbide-based transistor, or a silicon-based transistor, the gate of the depletion transistor being connected to the source of the silicon-based enhancement transistor.

[0131] In some embodiments, the high-side device 2105 and the low-side device 2103 may be made of GaN-based materials. In one embodiment, the GaN-based material may include a layer of GaN on a layer of silicon. In other embodiments, the GaN-based material may include, but is not limited to, a layer of GaN on a layer of silicon carbide, sapphire, or aluminum nitride. In one embodiment, the GaN-based layer may include, but is not limited to, a composite stack of other Group III nitrides such as aluminum nitride and indium nitride and Group III nitride alloys such as AlGaN and InGaN.

[0132] Low side device

[0133] The low-side device 2103 may have multiple circuits for the control and operation of the low-side device and the high-side device 2105. In some embodiments, the low-side device 2103 may include a logic, control and level shifting circuit (low-side control circuit) 2150 that controls the switching of the low-side transistor 2115 and the high-side transistor 2125 together with other functions, as discussed in more detail below. The low-side device 2103 may also include a startup circuit 2155, a bootstrap capacitor charging circuit 2157, and a shielding capacitor 2160, as also discussed in more detail below.

[0134] Reference Fig. 22 , functionally illustrating the circuitry within the low-side control circuit 2150. Figures 23 to 28 Each circuit within the low-side control circuit 2150 is shown in more detail in . In one embodiment, the main function of the low-side control circuit 2150 may be to receive one or more input signals such as PWM signals from a controller and control the operation of the low-side transistor 2115 and the high-side transistor 2125.

[0135] The first level-shift transistor 2203 may be an "on" pulse level-shift transistor, while the second level-shift transistor 2215 may be an "off" pulse level-shift transistor. In one embodiment, a pulse width modulated high side (PWM_HS) signal from a controller (not shown) may be processed by an inverter / buffer 2250 and sent to an on pulse generator 2260 and an off pulse generator 2270. The on pulse generator 2260 may generate a pulse corresponding to a low state to a high state transient of the (PWM_HS) signal, thereby turning on the first level-shift transistor 2203 during the duration of the pulse. The off pulse generator 2270 may similarly generate a pulse corresponding to a high state to a low state transition of the (PWM_HS) signal, thereby turning on the second level-shift transistor 2205 during the duration of the off pulse.

[0136] The first level-shift transistor 2203 and the second level-shift transistor 2205 can each be used as a pull-down transistor in a resistor pull-up inverter circuit. More specifically, turning on can mean that the corresponding level-shift node voltage is pulled low relative to the switch node (Vsw) 2145, and turning off can cause the corresponding level-shift node to adopt the (Vbootstrap) voltage. Because the first level-shift transistor 2203 and the second level-shift transistor 2215 are each "on" only for the duration of the pulse, the power dissipation and stress level on these two devices can be less than Figure 1 The half-bridge circuit 100 described in FIG.

[0137] A first resistor 2207 and a second resistor 2208 may be added in series with the source of the first level-shift transistor 2203 and the second level-shift transistor 2215, respectively, to limit the gate to the source voltage and thus the maximum current through the transistors, respectively. The first resistor 2207 and the second resistor 2208 may be less than Figure 1 The source follower resistor in the half-bridge circuit 100 described in , which can help to perform the pull-down action of the first level-shift transistor 2203 and the second level-shift transistor 2215 faster, thereby reducing the propagation delay to the high-side transistor 2125.

[0138] In other embodiments, the first resistor 2207 and the second resistor 2208 may each be replaced by any form of current sink. One embodiment may connect the source of the first level-shift transistor 2203 and the second level-shift transistor 2205, respectively, to a depletion mode device with a gate-to-source short. One embodiment of a depletion mode transistor formed in high voltage GaN technology may be to replace the enhancement gate stack with one of the high voltage field plate metals stacked on top of the field dielectric layer. The thickness of the field dielectric and the work function of the metal may control the pinch-off voltage of the stack.

[0139] In other embodiments, the first resistor 2207 and the second resistor 2208 can be replaced by current sinks. In one embodiment, the startup circuit 2155 (see Fig.21 ) generates a reference current (Iref). Both the depletion transistor and current sink embodiments can produce significant die area reduction compared to the resistor option (ie, because a small depletion transistor will suffice and Iref is already available).

[0140] The bootstrap transistor drive circuit 2225 can be similar to the above Figure 2 The bootstrap transistor drive circuit 225 described in FIG. The bootstrap transistor drive circuit 2225 can be driven from the low-side drive circuit 2220 (see Fig. 22 ) receives an input and provides a gate drive signal called (BOOTFET_DR) to the bootstrap capacitor charging circuit 2157 (see Fig.21 ) in a bootstrap transistor, as discussed in more detail above.

[0141] Reference Fig.23 , illustrating the first level-shift transistor 2203 together with the pull-up resistor 2303 which may be located in the high-side device 2105. In some embodiments, the first level-shift transistor 2203 may be operated as a pull-down transistor in a resistor pull-up inverter, similar to Figure 3 As discussed above, the pull-up resistor 2303 may be disposed on the high-side device 2105 (see Fig.21). The second level shift transistor 2215 may have a similar configuration. In some embodiments, the first output terminal (LS_NODE) ​​2305 is connected to the switch node (Vsw) 2145 (see Fig.21 ) between the first output terminal 2305 and the ground, wherein the first capacitance is greater than the second capacitance. The first capacitance may be designed so that in response to the switch node (Vsw) 2145 (see Fig.21 ) allows a large portion of the C*dv / dt current to be conducted through the first capacitor to ensure that the voltage at the first output terminal 2305 tracks the voltage at the switch node (Vsw). Shielding capacitor 2160 (see Fig.21 ) can be configured to act as a first capacitor as described above. In other embodiments, shielding capacitor 2160 (see Fig.21 ) can be used to connect the first output terminal 2305 and the switch node (Vsw) 2145 (see Fig.21 ). The shielding capacitor 2160 may also be used to minimize the capacitance between the first output terminal 2305 and the substrate of the semiconductor device. In other embodiments, the shielding capacitor 2160 may be constructed on the low-side GaN device 2103.

[0142] Reference Fig.24 , the inverter / buffer circuit 2250 is described in more detail. In one embodiment, the inverter / buffer circuit 2250 may have a first inverter stage 2405 and a first buffer stage 2410. In other embodiments, the inverter / buffer circuit 2250 may be driven directly by a (PWM_HS) signal from a controller (not shown). The output of the first inverter stage 2405 may be to the turn-on pulse generator 2260 (see Fig. 22 ) of the input signal (PULSE_ON), ​​and the output of the first buffer stage 2410 can be the input signal (PULSE_OFF) to the shutdown pulse generator 2270.

[0143] In some embodiments, the UVLO circuit 2227 (see Fig. 22 ) is sent to a NAND gate placed in the first inverter stage 2405 to generate an optional (LS_UVLO) signal. If (Vcc) or (Vdd_LS) goes below a certain reference voltage (or a portion of a reference voltage), then this circuit can be used to shut down the level shifting operation. In other embodiments, the inverter / buffer circuit 2250 can be a low-side transistor 2115 (see Fig.21) generates a breakdown protection signal (STP_LS1) that can be applied to the low-side transistor gate drive circuit 2120. When the (PWM_HS) signal is high, this can turn off the low-side transistor gate drive circuit 2120 (see Fig.21 ), thereby preventing breakdown.

[0144] Reference Fig.25 , the turn-on pulse generator 2260 is described in more detail. In one embodiment, the turn-on pulse generator 2260 may have a first inverter stage 2505, a first buffer stage 2510, an RC pulse generator 2515, a second inverter stage 2520, a third inverter stage 2525, and a third buffer stage 2530. In another embodiment, the turn-on pulse generator 2260 may have a first inverter stage 2505, a first buffer stage 2510, an RC pulse generator 2515, a second inverter stage 2520, a third inverter stage 2525, and a third buffer stage 2530. Fig. 22 ) can be first inverted and then transformed into an on pulse by the RC pulse generator 2515 and the square wave generator. The result of this operation is transmitted to the first level shift transistor 2203 (see Fig. 22 )’s gate drive signal (LI_DR).

[0145] In other embodiments, the on pulse generator 2260 may include one or more logic functions, such as binary or combinational functions. In one embodiment, the on pulse generator 2260 may have a multi-input NOR gate of the (STP_HS) signal. The (STP_HS) signal may have the same polarity as the (LS_GATE) signal. Therefore, if the (STP_HS) signal is high (corresponding to the LS_GATE signal being high), then the on pulse may not be generated because Fig.25 The first inverter circuit 2505 in will pull low, which will deactivate the pulse generator 2515.

[0146] In other embodiments, the RC pulse generator 2515 may include a clamping diode (not shown). The clamping diode may be added to ensure that the RC pulse generator 2515 operates at a very small duty cycle of the (PWM_LS) signal. In some embodiments, the turn-on pulse generator 2260 may be configured to receive input pulses in the range of 2 nanoseconds to 20 microseconds and transmit pulses of substantially constant duration within the range. In one embodiment, if the voltage across the clamping diode becomes greater than (Vth), the clamping diode may turn on and short out the resistor in the RC pulse generator 2515 (while providing very little capacitor discharge time). This may significantly improve the maximum operating duty cycle of the pulse generator circuit 2260 (relative to the PWM_HS signal).

[0147] Reference Fig.26, the shutdown pulse generator 2270 is described in more detail. In one embodiment, the shutdown pulse generator 2270 may have an RC pulse generator 2603, a first inverter stage 2605, a second inverter stage 2610, and a first buffer stage 2615. In other embodiments, the shutdown pulse generator 2270 may be derived from the inverter / buffer circuit 2250 (see Fig. 22 ) receives an input signal (PULSE_OFF) which can then be transmitted to the RC pulse generator 2603.

[0148] In another embodiment, the pulse from the RC pulse generator 2603 is sent through the first inverter stage 2605, the second inverter stage 2610, and the buffer stage 2615. The pulse may then be sent as the (L2_DR) signal to the second level shift transistor 2215 (see Fig. 22 ). The clamping diode may also be included in the turn-off pulse generator 2270. In some embodiments, the operating principle may be similar to that described above with respect to the turn-on pulse generator 2260 (see Fig.25 ) as discussed above. Such an operating principle ensures that the turn-off pulse generator 2270 is turned off when the high-side transistor 2125 (see Fig.21 ) (i.e., the circuit will operate in a relatively small duty cycle). In some embodiments, the off pulse generator 2270 can be configured to receive an input pulse in the range of 2 nanoseconds to 20 microseconds and transmit a pulse of substantially constant duration in the range. In other embodiments, the off level shift pulse can be shortened by the on input pulse to achieve an off time of less than 50 nanoseconds to turn on the high side transistor 2125.

[0149] In some embodiments, the RC pulse generator 2603 may include a capacitor connected to a resistor divider network. The output from the resistor may be sent to an inverter 2275 (see Fig. 22 ) signal (INV), the inverter 2275 generates a breakdown protection signal (STP_LS2) transmitted to the low-side driver circuit 2220. In other embodiments, the shutdown pulse generator 2270 may include one or more logic functions, such as binary or combinational functions. In one embodiment, similar to the (STP_LS1) signal, the (STP_LS2) signal is sent to the NAND logic circuit within the low-side driver circuit 2220. In some embodiments, these signals can be used to ensure that during the duration of the shutdown pulse signal (PULSE_OFF), the low-side transistor 2115 (see Fig.21) is not turned on (i.e., this is because the high-side transistor 2125 is turned off during the off pulse). In some embodiments, this method can be applied to compensate for the turn-off propagation delay (i.e., the PULSE_OFF signal can achieve breakdown protection), thereby ensuring that the low-side transistor 2115 will only turn on after the gate of the high-side transistor 2125 is completely turned off.

[0150] In other embodiments, a second level shift transistor 2215 may be used to level shift the blanking pulse to the high side device 2105. To accomplish this, a blanking pulse may be sent to the NOR input into the first inverter stage 2605. The blanking pulse may be used to prevent the high side device 2105 from being disconnected due to the switching node Vsw 2145 (see FIG. Fig. 20 ). In some embodiments, the blanking pulse may not be used to filter dv / dt induced or other undesired level shifted output pulses.

[0151] Reference Fig. 27 , the blanking pulse generator 2223 is described in more detail. In one embodiment, the blanking pulse generator 2223 can be a Figure 1 A simpler design is used in the half-bridge circuit 100 described in FIG. 1 because the square wave pulse generator is already part of the turn-off pulse generator 2270. In one embodiment, the (LS_GATE) signal is received from the low-side gate driver circuit 2220 (see FIG. 1 ). Fig. 22 ) is fed as an input to the blanking pulse generator 2223. This signal can be inverted and then sent through the RC pulse generator to produce a positive going pulse. In some embodiments, an inverted signal can be used because the pulse needs to correspond to the falling edge of the (LS_GATE) signal. This output can be used as the blanking pulse input (B_PULSE) to the shutdown pulse generator 2270.

[0152] Reference Fig.28 , the low-side transistor driver circuit 2220 is described in more detail. In one embodiment, the low-side transistor driver circuit 2220 may have a first inverter stage 2805, a first buffer stage 2810, a second inverter stage 2815, a second buffer stage 2820, and a third buffer stage 2825. In some embodiments, two inverter / buffer stages may be used because the input to the gate of the low-side transistor 2115 is synchronized with the (PWM_LS) signal. Therefore, in some embodiments, a (PWM_LS) high state may correspond to a (LS_GATE) high state, and vice versa.

[0153] In other embodiments, the low-side transistor driver circuit 2220 may also include an asymmetric hysteresis using a scheme similar to that described in 120 (see Figure 8) of the transistor pull-down resistor divider. In one embodiment, the low-side transistor driver circuit 2220 includes multiple input NAND gates for (STP_LS1) and (STP_LS2) (breakdown prevention on the low-side transistor 2115) signals. The (STP_LS1) and (STP_LS2) signals can ensure that the low-side transistor driver circuit 2220 (see Fig. 22 ) does not communicate with the low-side transistor 2115 when the high-side transistor 2125 is turned on (see Fig.21 ) communication. This technique can be used to avoid the possibility of breakdown. Other embodiments may include a "NAND" gate for the (LS_UVLO) signal (similar to the above in Fig.28 An embodiment may include a turn-off delay resistor in series with the gate of the final pull-down transistor. This may be used to ensure that the bootstrap transistor is turned off before the low-side transistor 2115 is turned off.

[0154] In other embodiments, the low-side device 2103 (see Fig.21 ) may also include a startup circuit 2155, a bootstrap capacitor charging circuit 2157, a shielding capacitor 2160 and a UVLO circuit 2227, which may be similar to the startup circuit 155, the bootstrap capacitor charging circuit 157, the shielding capacitor 160 and the UVLO circuit 227 discussed above, respectively.

[0155] High side device

[0156] Reference Fig.29 , describes in more detail the high-side logic and control circuit 2153 and how it interacts with the high-side transistor driver 2130. In some embodiments, the high-side logic and control circuit 2153 can be the same as described above in Fig.15 In other embodiments, the high-side logic and control circuit 2153 may operate in a different manner, as discussed in more detail below.

[0157] In one embodiment, the level shift 1 receiver circuit 2910 receives the first level shift transistor 2203 (see Fig. 22) receives the (L_SHIFT1) signal, the first level shift transistor 2203 receives a turn-on pulse upon the low state to high state transition of the (PWM_HS) signal, as discussed above. In response, the level shift 1 receiver circuit 2910 drives the gate of the pull-up transistor 2960 (e.g., in some embodiments, a low voltage enhancement mode GaN transistor). In other embodiments, the pull-up transistor 2960 may then pull up the state storage capacitor 2955 voltage to a value close to (Vdd_HS) with respect to the switch node (Vsw) 2145 voltage. The voltage on the state storage capacitor 2955 may then be transmitted to the high side transistor driver 2130 and to the high side transistor gate 2127 (see Fig.21 ) to turn on the high-side transistor 2125. In some embodiments, the state storage capacitor 2955 can be a latch storage logic circuit configured to change state in response to a first pulse input signal and change state in response to a second pulse input signal. In other embodiments, the state storage capacitor 2955 can be replaced by any type of latch circuit, such as but not limited to an RS flip-flop.

[0158] In further embodiments, during this time, the level shift 2 receiver circuit 2920 may maintain the pull-down transistor 2965 (e.g., in some embodiments, a low voltage enhancement mode GaN transistor) in an off state. This may cut off any discharge path for the state storage capacitor 2955. Thus, in some embodiments, the state storage capacitor 2955 may have a relatively small charging time constant and a relatively large discharging time constant.

[0159] Similarly, the level shift 2 receiver 2920 can receive the second level shift transistor 2215 (see Fig. 22 ) receives the (L_SHIFT2) signal, the second level shift transistor 2215 receives the off pulse at the high state to low state transition of the (PWM_HS) signal, as discussed above. In response, the level shift 2 receiver circuit 2920 drives the gate of the pull-down transistor 2965 (e.g., in some embodiments, a low voltage enhancement mode GaN transistor). In further embodiments, the pull-down transistor 2965 can then pull down (i.e., discharge) the state storage capacitor 2955 voltage to a value close to the switch node (Vsw) 2145, which can thus turn off the high side transistor 2125 through the high side transistor driver 2130.

[0160] Continue to refer Fig.29 , a first shielding capacitor 2970 and a second shielding capacitor 2975 may be connected from the (L_SHIFT1) and (L_SHIFT2) nodes, respectively, to help prevent the switch node (Vsw) 2145 (see Fig.21) during high dv / dt conditions at ). In other embodiments, the (L_SHIFT1) and (L_SHIFT2) nodes are connected to the switch node (Vsw) 2145 (see Fig.21 ) can also be clamped between the switch node (Vsw) 2145 (see Fig.21 ) and the potential difference between the (L_SHIFT1) and (L_SHIFT2) nodes never becomes higher than (Vth). This can be used to generate a high-side transistor 2125 (see Fig.21 )'s relatively fast switching on and off.

[0161] Reference Fig.30 , the level shift 1 receiver 2910 is described in more detail. In one embodiment, the level shift 1 receiver 2910 may include a down level shifter 3005, a first inverter 3010, a second inverter 3015, a first buffer 3020, a third inverter 3025, a second buffer 3030, and a third buffer 3135. In some embodiments, the level shift 1 receiver 2910 shifts (i.e., modulates) the (L_SHIFT1) signal down by a voltage of 3*Vth (e.g., using three enhancement mode transistors, each of which may have a gate to source voltage close to Vth). In other embodiments, fewer or more down shifting transistors may be used.

[0162] In further embodiments, the last source follower transistor may have a three-diode connected transistor clamp across its gate to its source. This configuration may be used in some embodiments because its source voltage may only be as high as (Vdd_HS) (i.e., because its drain is connected to Vdd_HS), while its gate voltage may be as high as V(L_SHIFT1)-2*Vth. Thus, in some embodiments, the maximum gate-to-source voltage on the final source follower transistor may be greater than the maximum rated gate-to-source voltage for the technology.

[0163] In other embodiments, the first inverter 3010 may also have a NOR gate for high-side undervoltage lockout using the (UV_LS1) signal generated by the high-side UVLO circuit 2915. In one embodiment, the level shift 1 receiver 2910 (see Fig.29 ) can be transmitted to the pull-up transistor 2960 (see Fig.29 )'s gate. The voltage of this signal can go from 0 volts in the low state to (Vdd_HS)+(Vdd_HS-Vth) in the high state. This voltage can remain on for the duration of the on pulse.

[0164] Reference Fig.31, the level shift 2 receiver 2920 is described in more detail. In one embodiment, the level shift 2 receiver 2920 may be similar to the level shift 1 receiver 2910 discussed above. In further embodiments, the level shift 2 receiver 2920 may include a blanking pulse generator 3105, a down level shifter 3110, a first inverter 3115, a second inverter 3120, a first buffer 3125, a third inverter 3130, a second buffer 3135, and a third buffer 3140. In one embodiment, the blanking pulse generator 3105 may be used in addition to the 3*Vth down level shifter 3110 and multiple inverter / buffer stages.

[0165] In other embodiments, different configurations may be used. In some embodiments, when the level shift 2 receiver 2920 also serves as the high-side transistor 2125 (see Fig.21 ) turns off and blanks transistor 2940 (see Fig.29 ) drive to obtain better dv / dt immunity. In some embodiments, the blanking pulse generator 3105 can be connected with Fig.17 In one embodiment, the level shift 2 receiver 2920 (see Fig.29 ) can receive the (L_SHIFT2) and (UV_LS2) signals and in response transmit the (PD_FET) signal to the pull-down transistor 2965. In further embodiments, the first inverter 3115 can have a circuit for receiving the high-side UVLO circuit 2915 (see Fig.29 )’s (UV_LS2) signal.

[0166] Reference Fig.32 , the high side UVLO circuit 2915 is described in more detail. In one embodiment, the high side UVLO circuit 2915 may include a downward level shifter 3205 and a resistor pull-up inverter stage 3210. In some embodiments, the high side UVLO circuit 2915 may be configured to shut down the high side transistor 2125 (see Fig.21 ) to prevent circuit failure. In an example embodiment, the high-side UVLO circuit 2915 is designed to engage when (Vboot) decreases to a value less than 4*Vth below the switch node (Vsw) 2145 voltage. In another embodiment, the output of the down level shifter 3205 can be the (UV_LS2) signal transmitted to the second level shift receiver 2920, and the output of the resistor pull-up inverter stage 3210 can be the (UV_LS1) signal transmitted to the first level shift receiver 2910.

[0167] As discussed below, in some embodiments, the high-side UVLO circuit 2915 may be different from the above respectively. Fig.14 and 18 1415 of the high side UVLO circuit of the half bridge circuit 100 discussed in . In one embodiment, the (V bootstrap) signal may be shifted down by 3*Vth and passed to the resistor pull-up inverter stage 3210. In another embodiment, because the level shift 2 receiver circuit 2920 (see Fig.29 ) based on the high-side transistor 2125 (see Fig.21 ) controls the shutdown process, so the 3*Vth down-shifted output applied directly to the "NAND" gate at the input of the level shift 2 receiver circuit 2920 will engage the undervoltage lockout.

[0168] However, in some embodiments, this may also keep the pull-up transistor 2960 (see Fig.29 ) is turned on. In some embodiments, this may cause a conflict. When the level shift 2 receiver circuit 2920 (see Fig.29 ) try to keep the high side transistor 2125 (see Fig.21 ) is turned off, the level shift 1 receiver circuit 2910 may attempt to turn on the high-side transistor. To avoid this, some embodiments may enable the high-side UVLO circuit 2915 (see Fig.29 ) and sends it to the NOR input on the level shift 1 receiver circuit 2910. This ensures that the level shift 1 receiver circuit 2910 does not interfere with the UVLO induced shutdown process.

[0169] Reference Fig.33 , the high-side transistor driver 2130 is described in more detail. In one embodiment, the high-side transistor driver 2130 may include a first inverter 3305, a first buffer 3310, a second inverter 3315, a second buffer 3320, and a third buffer 3325. In some embodiments, the high-side transistor driver 2130 may be a Figure 1 A more basic design of the high-side transistor driver 130 used in the half-bridge circuit 100 described in FIG. 1 is shown in FIG. 1 . In one embodiment, the high-side transistor driver 2130 is fed from the state storage capacitor 2955 (see Fig.29 ) receives the (S_CAP) signal and delivers the corresponding drive (HS_GATE) signal to the high-side transistor 2125 (see Fig.21 ). More specifically, when the (S_CAP) signal is in a high state, the (HS_GATE) signal is in a high state, and vice versa.

[0170] Half-bridge Circuit #2 Operation

[0171] Half-bridge circuit 2100 (see Fig.21 ) are merely examples, and other sequences may be used without departing from the present invention. Fig.21 , 22 and 29.

[0172] In one embodiment, when the (PWM_LS) signal is in a high state, the low-side logic, control and level shift circuit 2150 may send a high signal to the low-side transistor driver 2120, which then transmits the signal to the low-side transistor 2115 to turn it on. This may set the switch node (Vsw) 2145 voltage to near 0 volts. In other embodiments, when the low-side transistor 2115 is turned on, it may provide a path for the bootstrap capacitor 2110 to charge. The charging path may have a parallel combination of a high voltage bootstrap diode and a transistor.

[0173] In some embodiments, the bootstrap transistor driver circuit 2225 can provide a drive signal (BOOTFET_DR) to the bootstrap transistor of the low resistance path for charging the bootstrap capacitor 2110. In one embodiment, the bootstrap diode can ensure that there is a path for charging the bootstrap capacitor 2110 during startup when there is no low-side gate drive signal (LS_GATE). During this time, the (PWM_HS) signal should be in a low state. If the (PWM_HS) signal is accidentally turned on during this time, the (STP_HS) signal generated from the low-side driver circuit 2220 will prevent the high-side transistor 2125 from being turned on. If the (PWM_LS) signal is turned on when the (PWM_HS) signal is turned on, the (STP_LS1) and (STP_LS2) signals generated from the inverter / buffer 2250 and the inverter 2275 will prevent the low-side transistor 2115 from being turned on respectively. Additionally, in some embodiments, the (LS_UVLO) signal may prevent the low side gate 2117 and the high side gate 2127 from turning on when (Vcc) or (Vdd_LS) becomes below a predetermined voltage level.

[0174] Conversely, in some embodiments, when the (PWM_LS) signal is in a low state, the (LS_GATE) signal to the low-side transistor 2115 may also be in a low state. In some embodiments, during the dead time between the (PWM_LS) low signal and the (PWM_HS) high signal transition, the inductive load may force the high-side transistor 2125 or the low-side transistor 2115 to be turned on in the synchronous rectifier mode, depending on the direction of the power flow. If the high-side transistor 2125 is turned on during the dead time (e.g., in boost mode), the switch node (Vsw) 2145 voltage may be increased to be close to (V+) 2135 (i.e., trunk voltage). This dv / dt condition on the switch node (Vsw) 2145 may tend to pull the (L_SHIFT1) node to a low state relative to the switch node (i.e., due to capacitive coupling to ground), which may turn on the high-side transistor driver 2130, thereby causing the non-intended conduction of the high-side transistor 2125. This condition may offset the dead time, thereby causing breakdown.

[0175] In some embodiments, this condition can be prevented by using the blanking pulse generator 2223 to sense the turn-off transient of the low-side transistor 2115 and send a pulse to turn on the second level-shift transistor 2205. This can pull the (L_SHIFT2) signal to a low state, which can then communicate with the level-shift 2 receiver circuit 2920 to generate a blanking pulse that drives the blanking transistor 2940. In one embodiment, the blanking transistor 2940 can act as a pull-up that prevents the (L_SHIFT1) signal from going low with respect to the switch node (Vsw) 2145.

[0176] In further embodiments, after the dead time, when the (PWM_HS) signal transitions from a low state to a high state, the on pulse generator 2260 may generate an on pulse. This may pull the (L_SHIFT1) node voltage down for a brief period of time. In further embodiments, this signal may be inverted by the level shift 1 receiver circuit 2910, and a brief high signal will be sent to the pull-up transistor 2960 that will charge the state storage capacitor 2955 to a high state. This may generate a corresponding high signal at the input of the high-side transistor driver 2130 that will turn on the high-side transistor 2125. The switch node (Vsw) 2145 voltage may remain close to (V+) 2135 (i.e., the mains voltage). The state storage capacitor 2955 voltage may remain in a high state during this time because there is no discharge path.

[0177] In still other embodiments, during the on pulse, the bootstrap capacitor 2110 may be discharged through the first level-shift transistor 2203. However, because the time period is relatively short, the bootstrap capacitor 2110 may not be discharged as much as it would if the first level-shift transistor 2203 was on during the entire duration of the (PWM_HS) signal ( Figure 1 More specifically, in some embodiments, this may allow the switching frequency at which UVLO engages to be higher than that at which Figure 1 The value in the half-bridge circuit 100 is relatively lower.

[0178] In some embodiments, when the (PWM_HS) signal transitions from a high state to a low state, the shutdown pulse generator 2270 may generate a shutdown pulse. This may pull the (L_SHIFT2) node voltage low for a brief period of time. This signal may be inverted by the level shift 2 receiver circuit 2920, and the brief high state signal may be sent to the pull-down transistor 2965 which will discharge the state storage capacitor 2955 to a low state. This will generate a low signal at the input of the high side transistor driver 2130 that will turn off the high side transistor 2125. In other embodiments, the state storage capacitor 2955 voltage may remain in a low state during this time because it does not have a discharge path.

[0179] In one embodiment, because the turn-off process in circuit 2100 does not involve charging the level-shift node capacitor through a high-value pull-up resistor, the turn-off time can be comparable to that in Figure 1 In another embodiment, the high-side transistor 2125 turn-on and turn-off process can be controlled by the turn-on of substantially similar level-shift transistors 2203 and 2205, so the turn-on and turn-off propagation delays can be substantially similar. This can produce no need for Figure 1 Embodiments of both the pull-up trigger circuit and / or the pull-up transistor used in the half-bridge circuit 100.

[0180] ESD Circuit

[0181] Reference Fig.34 In some embodiments, one or more pins (i.e., connections from a semiconductor device within an electronic package to an external terminal on the electronic package) may employ an electrostatic discharge (ESD) clamp circuit to protect the circuit. The following embodiments illustrate ESD clamp circuits that may be used on one or more pins of one or more embodiments disclosed herein, as well as other embodiments that may require ESD protection. In other embodiments, the ESD clamp circuits disclosed herein may be employed on GaN-based devices.

[0182] One embodiment of an electrostatic discharge (ESD) clamp circuit 3400 is illustrated. The ESD clamp circuit 3400 may have a configuration that employs one or more source follower stages 3405 made of enhancement mode transistors. Each source follower stage 3405 may have a gate 3406 connected to a source 3407 of an adjacent source follower stage. Fig.34 In the embodiment illustrated in FIG. 3 , four source follower stages 3405 are employed, however in other embodiments, fewer or more source follower stages may be used. A resistor 3410 is coupled to the source 3407 of the source follower stage 3405 .

[0183] The ESD transistor 3415 is coupled to one or more source follower stages 3405 and can be configured to conduct a current greater than 500 mA when exposed to an overvoltage pulse, as discussed below. A resistor 3410 is disposed between the source 3420 of the ESD transistor 3415 and each source 3407 of the source follower stage 3405. The drain 3408 of the source follower stage 3405 is connected to the drain 3425 of the ESD transistor 3415. The source 3407 of the last source follower stage is coupled to the gate 3430 of the ESD transistor 3415.

[0184] In one embodiment, the turn-on voltage of the ESD clamp circuit 3400 may be set by the total number of source follower stages 3405. However, because the last source follower stage is a transistor with a particular drain 3408 to source 3407 voltage and gate 3406 to source voltage, the current through the last resistor 3410 may be relatively large and may produce a larger gate 3430 to source 3420 voltage across the ESD transistor 3415. This condition may produce a relatively large ESD current capacity and, in some embodiments, may produce improved leakage performance compared to other ESD circuit configurations.

[0185] In further embodiments, the ESD clamp circuit 3400 may have multiple degrees of freedom with respect to transistor size and resistor values. In some embodiments, the ESD clamp circuit 3400 can be made smaller than other ESD circuit configurations. In other embodiments, the performance of the ESD clamp circuit 3400 may be improved by incrementally increasing the size of the source follower stage as the source follower stage 3405 is closer to the ESD transistor 3415. In further embodiments, the resistor 3410 may be replaced, for example, by a depletion transistor, a reference current sink, or a reference current source.

[0186] Reference now Fig.35 , description similar to Fig.343400, however, the ESD clamp circuit 3500 may have resistors in different configurations, as discussed in more detail below. The ESD clamp circuit 3500 may have a configuration that employs one or more source follower stages 3505 made of one or more enhancement mode transistors. Each source follower stage 3505 may have a gate 3506 connected to a source 3507 of an adjacent source follower stage. Fig.35 In the embodiment illustrated in FIG. 1 , four source follower stages 3505 are employed, however in other embodiments, fewer or more source follower stages may be used. Resistors 3510 are coupled between sources 3507 of adjacent source follower stages 3505. ESD transistors 3515 are coupled to source follower stages 3505 through resistors 3510 disposed between sources 3520 of ESD transistors 3515 and sources 3507 of source follower stages 3505. Drains 3508 of source follower stages 3505 may be coupled together and coupled to drains 3525 of ESD transistors 3515.

[0187] Electronic packaging

[0188] Reference Fig.36 and 37 In some embodiments, one or more semiconductor devices may be disposed in one or more electronic packages. A variety of packaging configurations and types of electronic packages are available and are within the scope of the present disclosure. Fig.36 An example of a quad flat no-lead electronic package having two semiconductor devices inside is described.

[0189] Electronic package 3600 may have a package substrate 3610 with one or more die pads 3615 surrounded by one or more terminals 3620. In some embodiments, package substrate 3610 may include a leadframe, while in other embodiments it may include an organic printed circuit board, a ceramic circuit, or another material.

[0190] exist Fig.36, the first device 3620 is mounted to the first die pad 3615 and the second device 3625 is mounted to the second die pad 3627. In another embodiment, one or more of the first device 3620 and the second device 3625 can be mounted on an insulator (not shown) mounted to the package substrate 3610. In one embodiment, the insulator can be a ceramic or other non-conductive material. The first device 3620 and the second device 3625 are electrically coupled to the terminal 3640 by wire bonding 3630 or any other type of electrical interconnect, such as a flip chip bump or column that can be used in a flip chip application. The wire bonding 3630 can extend between the device bonding pad 3635 and the terminal 3640, and in some cases extend to the die pads 3615, 3627, and in other cases extend to the device bonding pad 3635 on the adjacent device.

[0191] Reference Fig.37 , showing an isometric view of electronic package 3600. Terminals 3640 and die attach pads 3615 and 3627 may be disposed on an exterior surface and configured to be attached to a printed circuit board or other device. In further embodiments, terminals 3640 and die attach pads 3615 and 3627 may be accessible only inside electronic package 3600, and other connectors may be disposed outside of the electronic package. More specifically, some embodiments may have internal electrical routing, and there may not be a one-to-one correlation between internal and external connectors.

[0192] In another embodiment, the first device 3620 and the second device 3625 (see Fig.36 ) and the top surface of the package substrate 3610 may be encapsulated by a non-conductive material such as a molding compound. A variety of other electronic packages may be used, such as but not limited to SOIC, DIPS, MCM, etc. In addition, in some embodiments, each device may be in a separate electronic package, while other embodiments may have two or more electronic devices within a single package. Other embodiments may have one or more passive devices within one or more electronic packages.

[0193] Fig.38 FIG. 3 is an illustration of a buck half-bridge power conversion circuit 3800 according to an embodiment of the present invention. The half-bridge power conversion circuit 3800 is connected to a load capacitor 3870 and a load 3880 and may include Figure 1 The corresponding features and aspects of the half-bridge power conversion circuit 100 described in FIG. 1 are similar or identical features and aspects.

[0194] The half-bridge power conversion circuit 3800 includes a control circuit 3810 , a high-side driver 3820 , a high-side current sensing power FET 3830 , a low-side driver 3840 , a low-side current sensing power FET 3850 , and an inductor 3860 .

[0195] Specific operational aspects of the half-bridge power conversion circuit 3800 are described herein. Specific operational aspects of the half-bridge power conversion circuit 3800 are not described because they are known to those skilled in the art. In addition, in some embodiments, the control circuit 3810 causes other elements of the half-bridge power conversion circuit 3800 to operate in a manner different from the specific examples discussed herein. Such other undescribed functionality can be understood by those of ordinary skill in the art from the discussion of the described aspects.

[0196] The control circuit 3810 is configured to generate control signals at nodes HSC and LSC to generate a specific voltage at the output node OUT. In some embodiments, the control circuit 3810 can be programmed with the value of the specific voltage. In addition, in some embodiments, the control circuit 3810 receives a feedback signal (not shown) indicating the actual voltage at the output node OUT, and the control circuit 3810 is configured to modify the control signals at nodes HSC and LSC to reduce the difference between the actual voltage at the output node OUT and the programmed specific voltage.

[0197] The high-side driver 3820 is configured to receive signals at nodes HSC and HDET and generate a gate voltage at node HSG based on the received signals. The gate voltage at node HSG selectively controls the conduction state of the high-side current sensing power FET 3830.

[0198] The high-side current sensing power FET 3830 receives a gate voltage at the node HSG and selectively conducts according to the received gate voltage. When conducting, the high-side current sensing power FET 3830 provides a low resistance current path between the power node V+ and the switch node VSW. When not conducting, the high-side current sensing power FET 3830 presents a high resistance current path between the power node V+ and the switch node VSW, and additionally presents a coupling capacitance between the power node V+ and the switch node VSW.

[0199] The low-side driver 3840 is configured to receive signals at nodes LSC and LDET and generate a gate voltage at node LSG based on the received signals. The gate voltage at node LSG selectively controls the conduction state of the low-side current sensing power FET 3850.

[0200] The low-side current sensing power FET 3850 receives a gate voltage at the node LSG and selectively conducts according to the received gate voltage. When conducting, the low-side current sensing power FET 3850 provides a low resistance current path between the ground node and the switch node VSW. When not conducting, the low-side current sensing power FET 3850 presents a high resistance current path between the ground node and the switch node VSW, and additionally presents a coupling capacitance between the ground node and the switch node VSW.

[0201] The control circuit 3810 is configured to generate control signals at nodes HSC and LSC to cause the high-side current sensing power FET 3830 and the low-side current sensing power FET 3850 to cooperatively provide current to the inductor 3860 so that a programmed specific voltage is generated at the output node OUT.

[0202] Fig.39 Yes Description Fig.38 The waveform diagram of the operation of the half-bridge power conversion circuit 3800 of the invention. The voltage of the control signal at the nodes HSC and LSC, the gate voltage at the nodes HSG and LSG, and the voltage at the switch node VSW are described. In addition, the inductor current IL, the IDS current IDSLFET of the low-side current detection FET 3850, the voltage corresponding to the current IDSLFET of the low-side current detection FET 3850, and the voltage at the node L1 are also described. It should be noted that the horizontal time scale, the vertical voltage or current scale, the signal slope and the signal shape are not accurate descriptions of the actual operation. In fact, it is drawn in order to actually illustrate some aspects and features of the functionality of the half-bridge power conversion circuit 3800.

[0203] During time period T-1, the control signal at node HSC is high, and the control signal at node HSC is high causing the high-side driver 3820 to generate a high gate voltage at node HSG. The high gate voltage at node HSG causes the high-side current sense FET 3830 to conduct.

[0204] During time period T-1, the control signal at node LSC is low, and the control signal at node LSC is low causing low-side driver 3840 to generate a low gate voltage at node LSG. The low gate voltage at node LSG causes low-side current sense FET 3850 to not conduct.

[0205] Because the high-side current sense FET 3830 is conductive and the low-side current sense FET 3850 is non-conductive, the high-side current sense FET 3830 and the low-side current sense FET 3850 collectively cause the voltage at the switch node VSW to be equal to the voltage of the power node V+.

[0206] Also during the time period T-1, because the voltage at the switch node VSW is equal to the substantially fixed voltage of the power node V+, and the voltage at the output node OUT is equal to the substantially fixed output voltage, the current IL through the inductor 3860 increases substantially linearly. In addition, during the time period T-1, the current through the inductor 3860 is supplied by the high-side current detection FET 3830.

[0207] During time period T-1, there is substantially no current IDSLFET through the low side current sense FET 3850.

[0208] During time period T-2, the control signal at node HSC is low, and the control signal at node HSC is low causing the high-side driver 3820 to generate a low gate voltage at node HSG. The low gate voltage at node HSG causes the high-side current sense FET 3830 to not conduct.

[0209] During time period T-2, the control signal at node LSC is low, and the control signal at node LSC is low causing low-side driver 3840 to generate a low gate voltage at node LSG. The low gate voltage at node LSG causes low-side current sense FET 3850 to not conduct.

[0210] In response to the high-side current sense FET 3830 and the low-side current sense FET 3850 not conducting, the current IL in the inductor 3860 causes the voltage at the switch node VSW to decrease until it is clamped at substantially the ground voltage. The current IL in the inductor 3860 is provided by the low-side current sense FET 3850, which is Fig.39 As indicated, during time period T-2, the current IL in inductor 3860 is positive and the current in low-side current sense FET 3850 is negative.

[0211] Using one of the techniques known to those skilled in the art, after the voltage at the switch node VSW reaches or approaches the ground voltage, the control circuit 3810 causes the control signal at the node LSC to go high. Therefore, the low-side driver 3840 causes the gate voltage at the node LSG to go high, and the low-side current sense FET 3850 becomes conductive. Therefore, the voltage at the switch node VSW is equal to or substantially equal to the ground voltage, at which time the current IL in the inductor 3860 continues to decrease toward zero, and the current IDSLFET in the low-side current sense FET 3850 increases toward zero.

[0212] At the beginning of time period T-3, the current IDSLFET in low-side current detection FET 3850 crosses zero or becomes positive. Therefore, the voltage at node LDET becomes positive, and the voltage at node L1 becomes higher. In response to the voltage at node LDET becoming positive, low-side driver 3840 causes the gate voltage at node LSG to become lower. In addition, in response to the voltage at node L1 becoming higher, control circuit 3810 causes the control signal at node LSC to become lower. In certain embodiments, the voltage at node LDET will not cause low-side driver 3840 to drive the gate voltage at node LSG to be low. In such embodiments, in response to the control signal at node LSC because the voltage at node L1 becomes higher and becomes lower, low-side driver 3840 causes the gate voltage at node LSG to become lower.

[0213] During time period T-3, high-side current sense FET 3830 and low-side current sense FET 3850 are not conducting. Therefore, the circuit resonates according to the inductance, capacitance and resistance of the circuit, as is understood by those skilled in the art. Accordingly, the current IL through inductor 3860, the voltage at switch node VSW and the current IDSLFET in low-side current sense FET 3850 exhibit a damped oscillatory response.

[0214] like Fig.39 As shown in , the voltage at node L1 provides an indication of the polarity of the voltage at node LDET, which corresponds to the polarity of the current IDSLFET of the low-side current sense FET 3850. As illustrated, a positive transition in the voltage at node L1 indicates a positive transition in the current IDSLFET, and correspondingly indicates a voltage minimum in the voltage at the switch node VSW. Similarly, a negative transition in the voltage at node L1 indicates a negative transition in the current IDSLFET, and correspondingly indicates a voltage maximum in the voltage at the switch node VSW.

[0215] In response to one of the transitions in the voltage at node LI, control circuit 3810 causes the voltage at node HSC to go high at the beginning of duration T-4.

[0216] In some embodiments, the control circuit 3810 is configured to cause the voltage at the node HSC to become high in response to the Nth transition in the voltage at the node L1. For example, as illustrated, in some embodiments, the control circuit 3810 is configured to cause the voltage at the node HSC to become high in response to the fourth transition in the voltage at the node L1. In such embodiments, the control circuit 3810 may be configured to affect the voltage at the output node OUT of the half-bridge power conversion circuit 3800 by adjusting the duration of the high time of the control signal at the node HSC.

[0217] In some embodiments, the control circuit 3810 is configured to cause the voltage at the node HSC to become high in response to a selected transition in the voltage at the node LI. In such embodiments, the control circuit 3810 may be configured to select a transition so as to affect the voltage at the output node OUT of the half-bridge power conversion circuit 3800.

[0218] In some embodiments, the control circuit 3810 is configured to select a transition corresponding to one of the maximum values ​​in the voltage at the switch node VSW. In an alternative embodiment, the control circuit 3810 is configured to select a transition corresponding to one of the minimum values ​​in the voltage at the switch node VSW.

[0219] In response to the voltage at node HSC going high during duration T-4, high-side driver 3820 causes the voltage at node HSG to go high, causing high-side current sense FET 3830 to become conductive. In response to high-side current sense FET 3830 becoming conductive, the voltage at switch node VSW increases to the voltage of power node V+, and current IL in inductor 3860 increases substantially linearly.

[0220] The functionality of the half-bridge power conversion circuit 3800 during the time period T-4 is equivalent to its functionality during the time period T-1.

[0221] Fig.40 is a schematic illustration of a current sense FET 4000. The current sense FET 4000 may be used, for example, as Fig.38 The high-side current detection FET 3830 and / or the low-side current detection FET 3850 in the half-bridge power conversion circuit 3800.

[0222] The current sense FET 4000 includes a main FET 4010 , a sense FET 4020 , and a sense resistor 4030 .

[0223] The main FET 4010 and the detection FET 4020 conduct or do not conduct depending on the difference between the voltage at the gate G and the source S, wherein the voltage at the gate G is greater than the voltage at the source S by at least a certain threshold causing the main FET 4010 and the detection FET 4020 to conduct, as is understood by those skilled in the art. When conducting, the main FET 4010 provides a low resistance current path between the drain D and the source S. When not conducting, the main FET 4010 provides a high resistance current path between the drain D and the source S, and additionally presents a coupling capacitance between the drain D and the source S. When conducting, the detection FET 4020 provides a low resistance current path between the drain D and the resistor 4030. When not conducting, the detection FET 4020 provides a high resistance current path between the drain D and the resistor 4030, and additionally presents a coupling capacitance between the drain D and the resistor 4030.

[0224] The resistance value of resistor 4030 is low enough so that when both main FET 4010 and sense FET 4020 are conducting, the ratio of the current through main FET 4010 to the current through sense FET 4020 is substantially equal to the ratio of the width divided by the length of main FET 4010 to the width divided by the length of sense FET 4020. In addition, the resistance value of resistor 4030 is high enough so that the current through sense FET 4020 causes the voltage at output node DET to have a sufficient magnitude so that the comparator of low-side driver 3840 produces a valid output signal, as discussed in further detail below.

[0225] In some embodiments, the width of the main FET 4010 divided by the length is about 5, about 10, about 25, about 50, about 100, about 200, about 300, about 400, about 500, about 600, about 700, about 800, about 900, or about 1000 times the width of the detection FET 4020 divided by the length.

[0226] Fig.41 is a layout diagram of an embodiment of a current sense FET 4100. The current sense FET 4100 may have Fig.40 The aspects and features of the current sense FET 4000 described in are similar or identical to aspects and features of the current sense FET 4000 described in .

[0227] The current sense FET 4100 includes a main FET 4110 , a sense FET 4120 , and a sense resistor 4130 .

[0228] The main FET 4110 is formed by layout structures 4110D, 4110FP, 4110G and 4110S, wherein structure 4110D collectively forms the drain of the main FET 4110, structure 4110FP collectively forms the field plate of the main FET 4110, structure 4110G collectively forms the gate of the main FET 4110, and structure 4110S collectively forms the source of the main FET 4110.

[0229] The detection FET 4120 is formed by layout structures labeled 4120D, 4120FP, 4120G and 4120S, where structure 4120D collectively forms the drain of the detection FET 4120, structure 4120FP collectively forms the field plate of the detection FET 4120, structure 4120G collectively forms the gate of the detection FET 4120, and structure 4120S collectively forms the source of the detection FET 4120.

[0230] Resistor 4130 is formed by structure 4130 .

[0231] Layout structures 4110D and 4120D are electrically connected, for example, using contacts and metallization structures known in the art. Similarly, layout structures 4110G and 4120G are also electrically connected, for example, using contacts and metallization structures known in the art. In addition, a first terminal of resistor 4130 is electrically connected to the source of detection FET 4120 (formed by layout structure 4120S) using contacts and metallization structures known in the art, for example. In addition, a second terminal of resistor 4130 is electrically connected to the source of main FET 4110 (formed by layout structure 4110S) using contacts and metallization structures known in the art, for example.

[0232] In some embodiments, the field plate structure 4120FP of the sense FET 4120 is electrically connected to the field plate structure 4110FP of the main FET 4110 using, for example, contacts and metallization structures known in the art. In some embodiments, the field plate structure 4120FP of the sense FET 4120 is electrically connected to the source structure 4120S of the sense FET 4120 using, for example, contacts and metallization structures known in the art.

[0233] Fig.42 FIG. 4 is a schematic diagram of a driver circuit 4200 according to an embodiment. The driver circuit 4200 may be used, for example, as Fig.38 The high-side driver 3820 and / or the low-side driver 3840 of the half-bridge power conversion circuit 3800 described in FIG.

[0234] In the illustrated embodiment, the sense FET 4120 is formed from two separate sections, such as Fig.41 In an alternative embodiment, the detection FET 4120 is formed of a single segment. In some embodiments, the detection FET 4120 is formed of a number of segments greater than two, such as three, four, five or more segments.

[0235] In some embodiments, the detection FET 4120 formed by a single segment is placed in a region at the center of the main FET 4110. Alternatively, in some embodiments, the detection FET 4120 formed by a single segment is placed in a region at the periphery of the main FET 4110.

[0236] In some embodiments, the detection FET 4120 formed by the first and second segments is placed such that the first segment is placed in the area of ​​the center of the first half of the main FET 4110 and the second segment is placed in the area of ​​the center of the second half of the main FET 4110.

[0237] In some embodiments, the detection FET 4120 formed by the first, second, third and fourth segments is placed so that the first segment is placed in the area of ​​the center of the first quadrant of the main FET 4110, the second segment is placed in the area of ​​the center of the second quadrant of the main FET 4110, the third segment is placed in the area of ​​the center of the third quadrant of the main FET 4110, and the fourth segment is placed in the area of ​​the center of the fourth quadrant of the main FET 4110.

[0238] Driver circuit 4200 includes comparator 4210, latch 4220, and output drivers 4230 and 4240. Input signals C and ID generate two output signals to latch 4220 that are buffered by output driver 4230. In addition, the output of comparator 4210 is buffered by output driver 4240.

[0239] Fig.43 Waveform diagrams representing the operation of the driver circuit 4200 are described. Fig.42 and 43 , the input signal C is high causing the latch 4220 to output a high signal. The high output signal of the latch 4220 causes the output driver 4230 to drive the output OUT with a high signal.

[0240] When the input signal ID is less than the ground voltage, the output R of the comparator 4210 is substantially equal to the ground. In addition, when the input signal ID is greater than the ground voltage, the output R of the comparator 4210 is high.

[0241] Accordingly, when the input signal ID changes from less than the ground voltage to greater than the ground voltage, the output R of the comparator 4210 changes from low to high. In response to the high transition of the output R of the comparator 4210, the latch 4220 is reset so that its output changes from high to low. Therefore, the output signal at the output OUT also changes from high to low.

[0242] In some embodiments, the negative input terminal of the comparator 4210 is connected to a voltage other than ground. In such embodiments, the output R of the comparator 4210 transitions in response to the current represented by the input signal ID crossing a value other than zero.

[0243] In an alternative operating mode, the high side current sensing power FET 3830, high side driver 3820 and control circuit 3810 operate cooperatively in a manner that is similar, identical or symmetrical to the functionality of the low side current sensing power FET 3850, low side driver 3840 and control circuit 3810, as described.

[0244] Fig.44FIG. 4 is an illustration of a buck half-bridge power conversion circuit 4400 according to an embodiment of the present invention. The half-bridge power conversion circuit 4400 is connected to a load capacitor 4470 and a load 4480 and may include Figure 1 The corresponding features and aspects of the half-bridge power conversion circuit 100 described in FIG. 1 are similar or identical features and aspects.

[0245] The half-bridge power conversion circuit 4400 includes a control circuit 4410 , a high-side driver 4420 , a high-side current sensing power FET 4430 , a low-side driver 4440 , a low-side current sensing power FET 4450 , and an inductor 4460 .

[0246] The high-side current sensing power FET 4430 and the low-side current sensing power FET 4450 may have the same Fig.38 The high-side current sensing power FET 3830 and the low-side current sensing power FET 3850 of the half-bridge power conversion circuit 3800 have similar or identical features.

[0247] The high-side driver 4420 and the low-side driver 4440 may have Fig.38 The high-side driver 3820 and the low-side driver 3840 of the half-bridge power conversion circuit 3800 have similar or identical features.

[0248] Specific operational aspects of the half-bridge power conversion circuit 4400 are described herein. Specific operational aspects of the half-bridge power conversion circuit 4400 are not described because they are known to those skilled in the art. In addition, in some embodiments, the control circuit 4410 causes other elements of the half-bridge power conversion circuit 4400 to operate in a manner different from the specific examples discussed herein. Such other undescribed functionality can be inferred by one of ordinary skill in the art from the discussion of the described aspects.

[0249] The control circuit 4410 is configured to generate control signals at nodes HSC and LSC to generate a specific voltage at the output node OUT. In some embodiments, the control circuit 4410 can be programmed with the value of the specific voltage. In addition, in some embodiments, the control circuit 4410 receives a feedback signal (not shown) indicating the actual voltage at the output node OUT, and the control circuit 4410 is configured to modify the control signals at nodes HSC and LSC to reduce the difference between the actual voltage at the output node OUT and the programmed specific voltage.

[0250] The high-side driver 4420 is configured to receive signals at nodes HSC and HDET and generate a gate voltage at node HSG based on the received signals. The gate voltage at node HSG selectively controls the conduction state of the high-side current sensing power FET 4430.

[0251] The high-side current sensing power FET 4430 receives a gate voltage at the node HSG and selectively conducts according to the received gate voltage. When conducting, the high-side current sensing power FET 4430 provides a low resistance current path between the output node OUT and the switch node VSW. When not conducting, the high-side current sensing power FET 4430 presents a high resistance current path between the output node OUT and the switch node VSW, and additionally presents a coupling capacitance between the output node OUT and the switch node VSW.

[0252] The low-side driver 4440 is configured to receive signals at nodes LSC and LDET and generate a gate voltage at node LSG based on the received signals. The gate voltage at node LSG selectively controls the conduction state of the low-side current sensing power FET 4450.

[0253] The low-side current sensing power FET 4450 receives a gate voltage at the node LSG and selectively conducts according to the received gate voltage. When conducting, the low-side current sensing power FET 4450 provides a low resistance current path between the ground node and the switch node VSW. When not conducting, the low-side current sensing power FET 4450 presents a high resistance current path between the ground node and the switch node VSW, and additionally presents a coupling capacitance between the ground node and the switch node VSW.

[0254] The control circuit 4410 is configured to generate control signals at nodes HSC and LSC to cause the high-side current sensing power FET 4430 and the low-side current sensing power FET 4450 to cooperatively provide current from the inductor 4460 to the output node OUT, so that a programmed specific voltage is generated at the output node OUT.

[0255] Fig.45 Yes Description Fig.44 Waveform diagram of the operation of the half-bridge power conversion circuit 4400. The voltage of the control signal at the nodes HSC and LSC, the gate voltage at the nodes HSG and LSG, and the voltage at the switch node VSW are illustrated. In addition, the inductor current IL, the IDS current IDSHFET of the high-side current detection FET 4430, the voltage corresponding to the current of the high-side current detection FET 4430, and the voltage at the node HI are also illustrated. It should be noted that the horizontal time scale, the vertical voltage or current scale, the signal slope, and the signal shape are not accurate descriptions of the actual operation. In fact, this drawing is to actually illustrate certain aspects and features of the functionality of the half-bridge power conversion circuit 4400.

[0256] During time period T-1, the control signal at node LSC is high, and the control signal at node LSC is high causing the low-side driver 4440 to generate a high gate voltage at node LSG. The high gate voltage at node LSG causes the low-side current sense FET 4450 to conduct.

[0257] During time period T-1, the control signal at node HSC is low, and the control signal at node HSC is low causing the high-side driver 4420 to generate a low gate voltage at node HSG. The low gate voltage at node HSG causes the high-side current sense FET 4430 to not conduct.

[0258] Because the low-side current sense FET 4450 conducts and the high-side current sense FET 4430 does not conduct, the high-side current sense FET 4430 and the low-side current sense FET 4450 collectively cause the voltage at the switch node VSW to be equal to the ground voltage.

[0259] Also during the time period T-1, because the voltage at the switch node VSW is equal to the substantially fixed ground voltage and the voltage at the output node OUT is equal to the substantially fixed output voltage, the current IL through the inductor 4460 increases substantially linearly. In addition, during the time period T-1, the current through the inductor 4460 is absorbed by the low-side current detection FET 4430.

[0260] During time period T-1, substantially no current IDSHFET flows through the high-side current sense FET 4430.

[0261] During time period T-2, the control signal at node LSC is low, and the control signal at node LSC is low causing the low-side driver 4440 to generate a low gate voltage at node LSG. The low gate voltage at node LSG causes the low-side current sense FET 4450 to not conduct.

[0262] At the beginning of time period T-2, the control signal at node HSC is low, and the control signal at node HSC is low causing the high-side driver 4420 to generate a low gate voltage at node HSG. The low gate voltage at node HSG causes the high-side current sense FET 4430 to not conduct.

[0263] In response to the high-side current sense FET 4430 and the low-side current sense FET 4450 not conducting, the current IL in the inductor 4460 causes the voltage at the switch node VSW to increase until it is substantially clamped at the output voltage at the output OUT. The current IL in the inductor 4460 is conducted from the switch node VSW to the output OUT via the high-side current sense FET 4430, which is Fig.45As indicated, during time period T-2, the current IL in inductor 4460 is positive and the current in high-side current sense FET 4430 is negative.

[0264] Using one of the techniques known to those skilled in the art, after the voltage at the switch node VSW reaches or approaches the voltage at the output OUT, the control circuit 4410 causes the control signal at the node HSC to go high. As a result, the high-side driver 4440 causes the gate voltage at the node HSG to go high, and the high-side current sense FET 4430 becomes conductive. As a result, the voltage at the switch node VSW is equal to or substantially equal to the voltage at the output OUT, at which point the current IL in the inductor 4460 continues to decrease toward zero, and the current IDSHFET in the high-side current sense FET 4430 increases toward zero.

[0265] At the beginning of time period T-3, the current IDSLFET in the high-side current detection FET 4430 crosses zero or becomes positive. Therefore, the voltage at the node HDET becomes positive, and the voltage at the node HI becomes high. In response to the voltage at the node HDET becoming positive, the high-side driver 4420 causes the gate voltage at the node HSG to become low. In addition, in response to the voltage at the node HI becoming high, the control circuit 4410 causes the control signal at the node HSC to become low. In some embodiments, the voltage at the node HDET does not cause the high-side driver 4420 to drive the gate voltage at the node HSG to be low. In such embodiments, in response to the control signal at the node HSC becoming low due to the voltage at the node HI becoming high, the high-side driver 4420 causes the gate voltage at the node HSG to become low.

[0266] During time period T-3, the high-side current sense FET 4430 and the low-side current sense FET 4450 are not conducting. Therefore, the circuit resonates according to the inductance, capacitance and resistance of the circuit, as is understood by those skilled in the art. Accordingly, the current IL through the inductor 4460, the voltage at the switch node VSW and the current IDSHFET in the high-side current sense FET 4430 exhibit a damped oscillatory response.

[0267] like Fig.45 As illustrated in , the voltage at node HI provides an indication of the polarity of the voltage at node HDET, which corresponds to the polarity of the current IDSHFET of the high-side current sense FET 4430. As illustrated, a positive transition in the voltage at node HI indicates a positive transition in the current IDSHFET, and correspondingly indicates a voltage minimum in the voltage at the switching node VSW. Similarly, a negative transition in the voltage at node HI indicates a negative transition in the current IDSHFET, and correspondingly indicates a voltage maximum in the voltage at the switching node VSW.

[0268] In response to one of the transitions in the voltage at node HI, the control circuit 4410 causes the voltage at node LSC to go high at the beginning of duration T-4.

[0269] In some embodiments, the control circuit 4410 is configured to cause the voltage at the node LSC to become high in response to the Nth transition in the voltage at the node HI. For example, as illustrated, in some embodiments, the control circuit 4410 is configured to cause the voltage at the node LSC to become high in response to the fourth transition in the voltage at the node HI. In such embodiments, the control circuit 4410 may be configured to affect the voltage at the output node OUT of the half-bridge power conversion circuit 4400 by adjusting the duration of the high time of the control signal at the node LSC.

[0270] In some embodiments, the control circuit 4410 is configured to cause the voltage at the node LSC to become high in response to a selected transition in the voltage at the node HI. In such embodiments, the control circuit 4410 may be configured to select a transition so as to affect the voltage at the output node OUT of the half-bridge power conversion circuit 4400.

[0271] In some embodiments, the control circuit 4410 is configured to select a transition corresponding to one of the maximum values ​​of the voltage at the switch node VSW. In an alternative embodiment, the control circuit 4410 is configured to select a transition corresponding to one of the minimum values ​​of the voltage at the switch node VSW.

[0272] In response to the voltage at node LSC going high during duration T-4, the low-side driver 4440 causes the voltage at node LSG to go high, causing the low-side current sense FET 4450 to become conductive. In response to the low-side current sense FET 4450 becoming conductive, the voltage at the switch node VSW becomes equal to or substantially equal to the ground voltage, and the current IL in the inductor 4460 increases substantially linearly.

[0273] The functionality of the half-bridge power conversion circuit 4400 during the time period T-4 is equivalent to its functionality during the time period T-1.

[0274] In an alternative operating mode, the high-side current sensing power FET 4430, high-side driver 4420 and control circuit 4410 operate cooperatively in a manner that is similar, identical or symmetrical to the functionality of the low-side current sensing power FET 4450, low-side driver 4440 and control circuit 4410, as described.

[0275] Fig.46 is a schematic illustration of a circuit 4600, which may be used, for example, in Fig.38 Buck half-bridge power conversion circuit 3800 or Fig.44 The invention is used in a switching converter such as the boost half-bridge power conversion circuit 4400 of the embodiment of the present invention, as is known to those skilled in the art. In the embodiment of the circuit 4600, the voltage output at the resistor of the current sense FET 4620 is used as part of the overcurrent protection circuit.

[0276] Circuit 4600 includes a driver 4610 , a current sense FET 4620 , an operational transconductance amplifier 4630 , a resistor 4640 , and a controller 4650 .

[0277] Fig.47 Description Fig.46 A waveform diagram of the operation of the driver circuit 4600.

[0278] refer to Fig.46 and 47 , during time period T-1, controller 4650 causes the signal at node C to be low. Therefore, the gate voltage at node G is low, current sense FET 4620 does not conduct, and the voltages at nodes VI and AVI are also low.

[0279] During time period T-2, in accordance with its converter control scheme, controller 4650 causes the signal at node C to be high. Therefore, the gate voltage at node G is high, current sense FET 4620 becomes conductive, and current flows through both the FET and the resistor of current sense FET 4620. Therefore, the voltage at node V1 increases according to the current flowing through the resistor of current sense FET 4620.

[0280] As the voltage at node VI increases, the current generated by OTA 4630 increases accordingly. In addition, the current generated by OTA 4630 is conducted through resistor 4640, and the voltage at node AVI also increases.

[0281] At the beginning of time period T-3, the voltage at node AVI has increased above the threshold, and controller 4650 causes the signal at node C to go low. Since the signal at node C is low, driver 4610 causes the gate voltage at node G to decrease, causing current sense FET 4620 to become non-conductive. Therefore, current no longer flows through the resistor of current sense FET 4620, and the voltages at nodes VI and AVI drop.

[0282] Accordingly, if Fig.47 As illustrated in FIG. 46 , the current being conducted by current sense FET 4620 is greater than a threshold value and circuit 4600 causes current sense FET 4620 to turn off.

[0283] Fig.48 is a schematic illustration of a circuit 4800, which may be used, for example, in Fig.38Buck half-bridge power conversion circuit 3800 or Fig.44 The invention is used in a switching converter such as the boost half-bridge power conversion circuit 4400 of FIG. 4800 , as is known to those skilled in the art. In an embodiment of the circuit 4800 , the voltage output at the resistor of the current sense FET 4620 is used as part of an overcurrent protection circuit.

[0284] Circuit 4800 includes a driver 4810 , a current sense FET 4820 , an operational transconductance amplifier (OTA) 4830 , a resistor 4840 , a controller 4850 , a latch 4860 , and an AND gate 4870 .

[0285] Fig.49 Description Fig.48 A waveform diagram of the operation of the driver circuit 4800.

[0286] refer to Fig.48 and 49 , during time period T-1, controller 4850 causes the signal at node C2 to be high. Therefore, latch 4860 causes the signal at one of the input nodes OC of AND gate 4870 to be high.

[0287] Additionally, during time period T-1, controller 4850 causes the signal at node C1 to be low. Therefore, the gate voltage at node G is low, current sense FET 4820 is not conducting, and the voltages at nodes VI and AVI are also low.

[0288] During time period T-2, controller 4850 causes the signal at node C2 to be low. Nevertheless, latch 4860 continues to cause the signal at node OC to be high.

[0289] During time period T-3, in accordance with its converter control scheme, controller 4850 causes the signal at node C1 to be high. As a result, the gate voltage at node G is driven high by driver 4810, current sense FET 4820 becomes conductive, and current flows through both the FET and the resistor of current sense FET 4820. As a result, the voltage at node VI increases according to the current flowing through the resistor of current sense FET 4820.

[0290] As the voltage at node VI increases, the current generated by OTA 4830 increases accordingly. In addition, the current generated by OTA 4830 is conducted through resistor 4840, and the voltage at node AVI also increases.

[0291] At the beginning of time period T-4, the voltage at node AVI increases above the threshold, and latch 4860 causes the signal at node OC to go low. Since the signal at node OC is low, driver 4810 causes the gate voltage at node G to drop. In addition, in response to the voltage at node AVI increasing above the threshold, controller 4850 causes the signal at node C1 to go low. Since the signal at node C1 or OC is low, driver 4810 causes the gate voltage at node G to be low, causing current sense FET 4820 to become non-conductive. Therefore, current no longer flows through the resistor of current sense FET 4820, and the voltage at nodes VI and AVI drops.

[0292] During time period T-5, controller 4850 causes the signal at node C2 to be high and latch 4860 causes the signal at node OC to be high, in accordance with its converter control scheme, as described above with reference to period T-1.

[0293] Accordingly, if Fig.49 As illustrated in FIG. 48 , the current being conducted by the current sense FET 4820 is greater than the threshold value, and the circuit 4800 causes the current sense FET 4820 to turn off.

[0294] In the foregoing specification, embodiments of the present invention have been described with reference to many specific details that may vary for different embodiments. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense. The sole and exclusive indication of the scope of the invention and what is intended by the applicant to be the scope of the invention is the literal and equivalent scope of such claims arising from the application in the specific form in which the claim set (including any subsequent amendments) is produced.

Claims

1. A circuit comprising: A power switch system configured to selectively conduct according to one or more gate signals and according to whether a value of a current flowing through the power switch system crosses a threshold, wherein the power switch system comprises: a first switch having a first gate, a first drain, and a first source, wherein the first source has a linear first region aligned with a linear second region; and a second switch having a second gate, a second drain, and a second source, wherein the second source has a linear portion disposed between the first region and the second region, wherein the first gate and the second gate are electrically connected, wherein the first drain and the second drain are electrically connected, and The first switch conducts more current than the second switch, and the second switch is configured to generate a switch signal indicative of current flowing through the first switch. 2 . The circuit of claim 1 , wherein the first region, the second region, and the linear portion are all collinear.

3. The circuit of claim 1 , wherein the first gate comprises a substantially linear first gate region and a substantially linear second gate region, wherein the first gate region is aligned with and spaced apart from the second gate region to define an intermediate region therebetween, and wherein the second gate comprises a second gate portion disposed in the intermediate region. 4 . The circuit of claim 1 , wherein the power switch further comprises a resistor connected between the first source and the second source, and wherein the resistor is configured to generate the switching signal in cooperation with the second switch. 5 . The circuit of claim 4 , wherein the power switch is configured to generate the switching signal at a connection between the resistor and the second source. 6 . The circuit of claim 1 , wherein the power switch further comprises a comparator circuit configured to generate the switching signal in cooperation with the second switch based on whether the current of the second switch is greater than the threshold.

7. The circuit of claim 1 , further comprising a power switch driver, wherein the power switch driver is configured to cause the first switch to become non-conductive in response to the switch signal indicating that the value of the current flowing through the first switch has undergone a first transition from a value less than the threshold to a value greater than the threshold or from a value greater than the threshold to a value less than the threshold after the first switch has become conductive.

8. The circuit of claim 1, wherein the circuit comprises a buck converter.

9. The circuit of claim 1, wherein the circuit comprises a boost converter.

10. The circuit of claim 1, further comprising a power switch driver, wherein the power switch driver is configured to control a conduction state of the first switch in response to an output of a latch having an output state responsive to the switch signal.

11. A method of operating a circuit, comprising: providing one or more gate signals to cause the power switch system to become selectively conductive; as well as The power switch system is rendered non-conductive by a power switch driver in response to a switch signal indicating that a value of a current flowing through the power switch system has exceeded a threshold, wherein the power switch comprises: a first switch having a first gate, a first drain, and a first source, wherein the first source has a linear first region aligned with a linear second region; as well as a second switch having a second gate, a second drain, and a second source, wherein the second source has a linear portion disposed between the linear first region and the linear second region, wherein the first gate and the second gate are electrically connected, wherein the first drain and the second drain are electrically connected, and The first switch conducts more current than the second switch, and the second switch is configured to generate the switching signal. 12 . The method of claim 11 , wherein the linear first region, the linear second region, and the linear portion are all collinear.

13. The method of claim 11, wherein the current is indicated by a voltage signal and wherein the threshold is a non-zero voltage. 14 . The method of claim 11 , wherein the power switch further comprises a resistor connected between the first source and the second source, and wherein the resistor is configured to generate the switching signal in cooperation with the second switch.

15. The method of claim 11, further comprising causing the power switch to become non-conductive by the power switch driver in response to the switch signal indicating that the value of the current flowing through the power switch has undergone a first transition from a value less than the threshold to a value greater than the threshold or from a value greater than the threshold to a value less than the threshold after the power switch has become conductive.

16. The method of claim 11, wherein the circuit comprises a buck converter.

17. The method of claim 11, wherein the first gate comprises a substantially linear first gate region and a substantially linear second gate region, wherein the first gate region is aligned with and spaced apart from the second gate region to define an intermediate region therebetween, and wherein the second gate comprises a second gate portion disposed in the intermediate region.

18. The method of claim 11, further comprising generating the gate signal in response to the output of a latch having an output state responsive to the switch signal by the power switch driver.

19. A resonant circuit comprising: A power switch, the power switch comprising: first and second terminals, and first and second parallel current paths, each of the first and second current paths terminating at each of the first and second terminals, wherein the first and second current paths are configured to selectively conduct according to a gate signal, wherein the second current path is configured to generate a switch signal indicative of a value of current flowing through the first current path, wherein the first current path has a first source having a linear first region aligned with a linear second region, and wherein the second current path has a second source having a linear portion disposed between the linear first region and the linear second region; and A power switch driver is configured to generate the gate signal in response to one or more control signals, wherein the power switch driver is configured to cause the power switch to become conductive in response to the switch signal exceeding a threshold. 20 . The circuit of claim 19 , wherein the power switch further comprises a comparator circuit configured to generate the switch signal based on whether the current of the second current path is greater than the threshold.

21. The circuit of claim 19, wherein the power switch driver is configured to render the power switch non-conductive in response to the switching signal indicating that a value of the current flowing through the power switch has exceeded the threshold after the power switch has become conductive.

22. The circuit of claim 19, wherein the power switch driver is configured to generate the gate signal in response to an output of a latch having an output state responsive to the switch signal and the control signal.

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