A high-speed data transmission VCM baseband signal generation and transmission device

Abstract

The present invention discloses a high-speed data transmission VCM baseband signal generation and transmission device, belonging to the field of communication and data transmission. It includes an interleaving and mapping module, a symbol mapping module, a physical frame generation module, a shaping filter module I, a shaping filter module II, a digital quadrature up-conversion module, a data rate matching module, a data grouping module, a transmission frame generation module, an output data rate matching module I, an output data rate matching module II, an output data rate matching module III, and an output data rate matching module IV, a GTH module I, a GTH module II, a GTH module III, a GTH module IV, an optical-electric converter I, an optical-electric converter II, an optical-electric converter III, and an optical-electric converter IV. The present invention has the characteristics of high implementation reliability, high stability, and low implementation complexity, etc.

Description

Technical Field

[0001] The present invention relates to the field of communication and data transmission, and is particularly suitable for use as a device for generating and transmitting high-speed digital transmission VCM baseband signals in a satellite remote sensing data transmission system. Background Art

[0002] For a traditional high-speed digital transmission VCM signal generating device, after generating and outputting a VCM intermediate frequency modulation signal, the signal is transmitted through a radio frequency cable and accessed to the system through an intermediate frequency switching matrix. During the signal transmission process, signal distortion is likely to occur, resulting in a decline in system performance. The new generation of digital transmission systems adopts the resource pool design concept, which requires the high-speed digital transmission VCM signal generating device to generate and output a VCM baseband signal through an optical signal, and at the same time needs to be interconnected with the system through accessing an optical signal digital switching matrix. During this process, the system also requires that the data transmission delay is controllable and multiple sets of devices can work synchronously. In addition, due to the large amount of data generated and transmitted by the high-speed digital transmission VCM signal generating device, a multi-channel parallel transmission method must be used to complete data transmission. In order to simplify the design of the optical switching digital matrix and improve the flexibility of system interconnection, the underlying GTH binding transmission mode cannot be used during the multi-channel signal transmission process. The above new requirements and new functions are not available in traditional high-speed digital transmission VCM signal generating devices. Summary of the Invention

[0003] The purpose of the present invention is to avoid the deficiencies in the above background art and provide a device for generating and transmitting high-speed digital transmission VCM baseband signals. The present invention also has the characteristics of high reliability, high stability, and low implementation complexity.

[0004] The purpose of the present invention is achieved as follows:

[0005] A device for generating and transmitting high-speed digital transmission VCM baseband signals includes an interleaving and mapping module 1, a symbol mapping module 2, a physical frame generation module 3, a shaping filter module I 5-1, a shaping filter module II 5-2, a digital quadrature up-conversion module 6, a data rate matching module 7, a data grouping module 8, a transmission frame generation module 9, an output data rate matching module I 10-1, an output data rate matching module II 10-2, an output data rate matching module III 10-3, an output data rate matching module IV 10-4, a GTH module I 11-1, a GTH module II 11-2, a GTH module III 11-3, a GTH module IV 11-4, an optical and electrical converter I 12-1, an optical and electrical converter II 12-2, an optical and electrical converter III 12-3, and an optical and electrical converter IV 12-4;

[0006] First, the data interleaving and mapping module 1 receives the input bit data stream to be modulated frame by frame through the CLK zero processing clock, and according to the modulation system indication signal, in the order of the input of the bit data stream, frame by frame, maps the bit data stream according to the corresponding relationship between the current modulation system and the number of mappings between bit data, and completes the data interleaving and mapping through the serial-to-parallel conversion method of queuing in columns in sequence, and transmits the data interleaving and mapping signal to the symbol mapping module 2. The symbol mapping module 2 performs modulation symbol mapping on the received data interleaving and mapping signal through the CLK zero processing clock according to the received modulation system indication signal, generates the I / Q two-way digital baseband signals after symbol mapping, and transmits this signal to the physical frame generation module 3. The physical frame generation module 3 receives the I / Q two-way digital baseband signals output by the symbol mapping module 2 through the CLK zero processing clock, adds a physical frame header with a length of 90 symbol lengths at the frame start position, and at the same time, adds pilot symbols with a length of 36 symbol lengths every 1440 data symbol lengths, and finally generates the I / Q two-way VCM baseband signals, and transmits this signal to the shaping filter module I5-1 and the shaping filter module II5-2 respectively. The shaping filter module I5-1 and the shaping filter module II5-2 select the shaping filter coefficients corresponding to the current shaping coefficient according to the shaping coefficient indication signal, and perform shaping filter processing on the input I / Q two-way VCM baseband signals respectively through the CLK zero processing clock, generate the I / Q two-way VCM baseband signals with 4 times sampling, and transmit this signal to the digital quadrature up-conversion module 6. The digital quadrature up-conversion module 6 performs digital quadrature up-conversion processing on the input I / Q two-way VCM baseband signals through the CLK zero processing clock according to the intermediate frequency setting signal, generates the I / Q two-way VCM baseband signals carrying the intermediate frequency offset, and transmits this signal to the data rate matching module 7. The data rate matching module 7 caches the input I / Q two-way VCM baseband signals through the CLK zero processing clock. When the cache capacity reaches the data output threshold, the data rate matching module 7 outputs a data readable indication signal and transmits this signal to the transmission frame generation module 9. The transmission frame generation module 9 receives the data readable indication signal through the CLK zero processing clock. When the transmission frame generation module 9 receives a valid data readable indication signal, the transmission frame generation module 9 generates and outputs a data read control signal through the CLK one transmission clock. When the data rate matching module 7 receives a valid data read control signal through the CLK one transmission clock, the data rate matching module 7 starts to read the I / Q two-way VCM baseband signals stored in the cache through the CLK one transmission clock, and transmits the read I / Q two-way VCM baseband signals to the data grouping module 8. The data grouping module 8 performs data recombination on the input I / Q two-way VCM baseband signals through the CLK one transmission clock, converts the symbol data of the received I / Q two-way VCM baseband signals into bit data, and generates four-way parallel transmission data through the serial-to-parallel conversion method.And the four-way parallel transmission data generated is transmitted to the transmission frame generation module 9. The transmission frame generation module 9 frames the input 4-way transmission data respectively through the CLK-transmission clock. When framing, every 1388-bit data is used as a valid data block of a transmission frame. Frame header identification, frame tail identification and inter-frame synchronization identification are also added to the transmission frame. After the transmission frame generation module 9 completes the framing process, the four-way transmission frame data generated simultaneously is respectively transmitted to the output data rate matching module I10-1, the output data rate matching module II10-2, the output data rate matching module III10-3 and the output data rate matching module IV10-4. The output data rate matching module I10-1, the output data rate matching module II10-2, the output data rate matching module III10-3 and the output data rate matching module IV10-4 respectively receive and store the transmission frame data input to them through the CLK-transmission clock, and at the rising edge moment of the first 1PPS second pulse signal received after receiving the transmission frame data, they respectively transmit the stored transmission frame data to the GTH module I11-1, the GTH module II11-2, the GTH module III11-3 and the GTH module IV11-4 through the CLK-transmission clock, the CLK-two transmission clock, the CLK-three transmission clock and the CLK-four transmission clock. The GTH module I11-1, the GTH module II11-2, the GTH module III11-3 and the GTH module IV11-4 respectively receive the transmission frame data input to them through the CLK-transmission clock, the CLK-two transmission clock, the CLK-three transmission clock and the CLK-four transmission clock, and generate and output four-way analog electrical signals after processing such as 8B / 10B encoding. The four-way analog electrical signals are respectively processed by the optical-electric converter I12-1, the optical-electric converter II12-2, the optical-electric converter III12-3 and the optical-electric converter IV12-4 to generate four-way optical signals, which are output as the final output signals of this device.

[0007] The present invention has the following advantages compared with the background technology:

[0008] 1. The present invention uses a fully digital method to generate the high-speed data transmission VCM baseband signal. Since the high-speed data transmission VCM baseband signal of this device adopts a digital signal transmission system and uses optical signals for transmission, compared with the traditional high-speed data transmission VCM analog modulation signal, long-distance distortion-free transmission can be achieved, thereby improving the flexibility and adaptability of system use.

[0009] 2. The present invention performs framing processing before data transmission. And to ensure that the backend receiving device completes the receiving and alignment processing of multiple paths of data, an inter-frame synchronization identification is added to the data transmission frame, thereby avoiding the use of the GTH binding mode during the parallel transmission of multiple paths of data, further increasing the flexibility of the interconnection between this device and devices such as optical switching digital matrices, and further simplifying the system design.

[0010] 3. The present invention controls data transmission by using a 1PPS second pulse signal, so that when the backend device receives the transmitted data, it can also control signal reception through the 1PPS second pulse signal, which can eliminate the random transmission delay error caused by the transmission path, ensure that the system data transmission time delay is fixed, and further ensure the synchronization accuracy of the system data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is the principle block diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0012] Referring to Figure 1 , the present invention includes an interleaving mapping module 1, a symbol mapping module 2, a physical frame generation module 3, a shaping filter module I 5-1 and a shaping filter module II 5-2, a digital quadrature up-conversion module 6, a data rate matching module 7, a data grouping module 8, a transmission frame generation module 9, an output data rate matching module I 10-1, an output data rate matching module II 10-2, an output data rate matching module III 10-3, and an output data rate matching module IV 10-4, a GTH module I 11-1, a GTH module II 11-2, a GTH module III 11-3, and a GTH module IV 11-4, an optical-electric converter I 12-1, an optical-electric converter II 12-2, an optical-electric converter III 12-3, and an optical-electric converter IV 12-4.

[0013] It first receives the input bit data stream to be modulated frame by frame through the CLK zero processing clock by the data interleaving mapping module 1, and according to the modulation system indication signal, in the order of the input of the bit data stream, frame by frame, the bit data stream is interleaved and mapped according to the corresponding relationship between the current modulation system and the number of mappings between bit data through the serial-to-parallel conversion method of queuing in columns in sequence, and the data interleaving mapping signal is transmitted to the symbol mapping module 2. The symbol mapping module 2 performs modulation symbol mapping on the received data interleaving mapping signal through the CLK zero processing clock, generates the I / Q two-way digital baseband signals after symbol mapping, and transmits the signals to the physical frame generation module 3. The physical frame generation module 3 receives the I / Q two-way digital baseband signals output by the symbol mapping module 2 through the CLK zero processing clock, adds a physical frame header with a length of 90 symbols at the frame start position, and at the same time, adds pilot symbols with a length of 36 symbols every 1440 data symbol lengths, finally generates the I / Q two-way VCM baseband signals, and transmits the signals to the shaping filter module I5-1 and the shaping filter module II5-2 respectively. The shaping filter module I5-1 and the shaping filter module II5-2 select the shaping filter coefficients corresponding to the current shaping coefficients according to the shaping coefficient indication signal, and perform shaping filtering processing on the input I / Q two-way VCM baseband signals respectively through the CLK zero processing clock, generate the I / Q two-way VCM baseband signals with 4 times sampling, and transmit the signals to the digital quadrature up-conversion module 6. The digital quadrature up-conversion module 6 performs digital quadrature up-conversion processing on the input I / Q two-way VCM baseband signals through the CLK zero processing clock according to the intermediate frequency setting signal, generates the I / Q two-way VCM baseband signals carrying the intermediate frequency offset, and transmits the signals to the data rate matching module 7. The data rate matching module 7 caches the input I / Q two-way VCM baseband signals through the CLK zero processing clock. When the cache capacity reaches the data output threshold, the data rate matching module 7 outputs a data readable indication signal and transmits the signal to the transmission frame generation module 9. The transmission frame generation module 9 receives the data readable indication signal through the CLK zero processing clock. When the transmission frame generation module 9 receives a valid data readable indication signal, the transmission frame generation module 9 generates and outputs a data reading control signal through the CLK one transmission clock. When the data rate matching module 7 receives a valid data reading control signal through the CLK one transmission clock, the data rate matching module 7 starts to read the I / Q two-way VCM baseband signals stored in the cache through the CLK one transmission clock, and transmits the read I / Q two-way VCM baseband signals to the data grouping module 8. The data grouping module 8 performs data recombination on the input I / Q two-way VCM baseband signals through the CLK one transmission clock, converts the symbol data of the received I / Q two-way VCM baseband signals into bit data, and generates four-way parallel transmission data through the serial-to-parallel conversion method.And the generated four-way parallel transmission data is transmitted to the transmission frame generation module 9. The transmission frame generation module 9 frames the input 4-way transmission data respectively through CLK-one transmission clock. When framing, every 1388-bit data is used as a valid data block of a transmission frame. Frame header identification, frame tail identification and inter-frame synchronization identification are also added to the transmission frame. After the transmission frame generation module 9 completes the framing process, the four-way transmission frame data generated simultaneously are respectively transmitted to the output data rate matching module I10-1, the output data rate matching module II10-2, the output data rate matching module III10-3 and the output data rate matching module IV10-4. The output data rate matching module I10-1, the output data rate matching module II10-2, the output data rate matching module III10-3 and the output data rate matching module IV10-4 respectively receive and store the transmission frame data input to them through CLK-one transmission clock, and at the rising edge moment of the first 1PPS second pulse signal received after receiving the transmission frame data, they respectively transmit the stored transmission frame data to the GTH module I11-1, the GTH module II11-2, the GTH module III11-3 and the GTH module IV11-4 through CLK-one transmission clock, CLK-two transmission clock, CLK-three transmission clock and CLK-four transmission clock. The GTH module I11-1, the GTH module II11-2, the GTH module III11-3 and the GTH module IV11-4 respectively receive the transmission frame data input to them through CLK-one transmission clock, CLK-two transmission clock, CLK-three transmission clock and CLK-four transmission clock, and generate and output four-way analog electrical signals after processing such as 8B / 10B encoding. The four-way analog electrical signals are respectively processed by the optical-electric converter I12-1, the optical-electric converter II12-2, the optical-electric converter III12-3 and the optical-electric converter IV12-4 to generate four-way optical signals, which are output as the final output signals of this device. The four-way optical signals output by this device will be transmitted to other devices such as the back-end optical switching digital matrix for use.,

[0014] Using the above principle, this device realizes the purpose of generating and transmitting the high-speed data transmission VCM baseband signal. In the example, the interleaving mapping module 1, the symbol mapping module 2, the physical frame generation module 3, the shaping filter module I5-1 and the shaping filter module II5-2, the digital quadrature up-conversion module 6, the data rate matching module 7, the data grouping module 8, the transmission frame generation module 9, the output data rate matching module I10-1, the output data rate matching module II10-2, the output data rate matching module III10-3, and the output data rate matching module IV10-4, the GTH module I11-1, the GTH module II11-2, the GTH module III11-3 and the GTH module IV11-4 are implemented by using the Virtex7 type FPGA produced by XILINX Company of the United States.

[0015] The brief working principle of the present invention is as follows:

[0016] When a high-speed data transmission VCM baseband signal generating and transmitting device is working, the data interleaving and mapping module 1 receives the input bit data stream to be modulated frame by frame through the CLK zero processing clock, and according to the modulation system indication signal, in the order of the input of the bit data stream, frame by frame, maps the bit data stream according to the corresponding relationship between the current modulation system and the number of mappings between bit data, completes the data interleaving and mapping through the serial-to-parallel conversion method of queuing in columns in sequence, and transmits the data interleaving and mapping signal to the symbol mapping module 2. The symbol mapping module 2 performs modulation symbol mapping on the received data interleaving and mapping signal through the CLK zero processing clock according to the received modulation system indication signal, generates the I / Q two-way digital baseband signal after symbol mapping, and transmits this signal to the physical frame generating module 3. The physical frame generating module 3 receives the I / Q two-way digital baseband signal output by the symbol mapping module 2 through the CLK zero processing clock, adds a physical frame header with a length of 90 symbols at the frame start position, and at the same time, adds pilot symbols with a length of 36 symbols every 1440 data symbol lengths, finally generates the I / Q two-way VCM baseband signal, and transmits this signal to the shaping filter module I5-1 and the shaping filter module II5-2 respectively. The shaping filter module I5-1 and the shaping filter module II5-2 select the shaping filter coefficients corresponding to the current shaping coefficients according to the shaping coefficient indication signal, and perform shaping filtering processing on the input I / Q two-way VCM baseband signal respectively through the CLK zero processing clock, generate the I / Q two-way VCM baseband signal with 4 times sampling, and transmit this signal to the digital quadrature up-conversion module 6. The digital quadrature up-conversion module 6 performs digital quadrature up-conversion processing on the input I / Q two-way VCM baseband signal through the CLK zero processing clock according to the intermediate frequency setting signal, generates the I / Q two-way VCM baseband signal carrying the intermediate frequency offset, and transmits this signal to the data rate matching module 7. The data rate matching module 7 caches the input I / Q two-way VCM baseband signal through the CLK zero processing clock. When the cache capacity reaches the data output threshold, the data rate matching module 7 outputs a data readable indication signal and transmits this signal to the transmission frame generating module 9. The transmission frame generating module 9 receives the data readable indication signal through the CLK zero processing clock. When the transmission frame generating module 9 receives a valid data readable indication signal, the transmission frame generating module 9 generates and outputs a data reading control signal through the CLK one transmission clock. When the data rate matching module 7 receives a valid data reading control signal through the CLK one transmission clock, the data rate matching module 7 starts to read the I / Q two-way VCM baseband signal stored in the cache through the CLK one transmission clock, and transmits the read I / Q two-way VCM baseband signal to the data grouping module 8. The data grouping module 8 performs data recombination on the input I / Q two-way VCM baseband signal through the CLK one transmission clock, converts the symbol data of the received I / Q two-way VCM baseband signal into bit data, and generates four-way parallel transmission data through the serial-to-parallel conversion method.And transmit the generated four-way parallel transmission data to the transmission frame generation module 9. The transmission frame generation module 9 frames the input 4-way transmission data respectively through the CLK-one transmission clock. When framing, every 1388-bit data is used as a valid data block of a transmission frame. Frame header identification, frame tail identification and inter-frame synchronization identification are also added to the transmission frame. After the transmission frame generation module 9 completes the framing process, the four-way transmission frame data generated simultaneously are respectively transmitted to the output data rate matching module I10-1, the output data rate matching module II10-2, the output data rate matching module III10-3 and the output data rate matching module IV10-4. The output data rate matching module I10-1, the output data rate matching module II10-2, the output data rate matching module III10-3 and the output data rate matching module IV10-4 respectively receive and store the input transmission frame data through the CLK-one transmission clock, and at the rising edge moment of the first 1PPS second pulse signal received after receiving the transmission frame data, respectively transmit the stored transmission frame data to the GTH module I11-1, the GTH module II11-2, the GTH module III11-3 and the GTH module IV11-4 through the CLK-one transmission clock, the CLK-two transmission clock, the CLK-three transmission clock and the CLK-four transmission clock. The GTH module I11-1, the GTH module II11-2, the GTH module III11-3 and the GTH module IV11-4 respectively receive the input transmission frame data through the CLK-one transmission clock, the CLK-two transmission clock, the CLK-three transmission clock and the CLK-four transmission clock, and generate and output four-way analog electrical signals after processing such as 8B / 10B encoding. The four-way analog electrical signals are respectively processed by the optical-electric converter I12-1, the optical-electric converter II12-2, the optical-electric converter III12-3 and the optical-electric converter IV12-4 to generate four-way optical signals, which are output as the final output signals of this device. The four-way optical signals output by this device will be transmitted to other devices such as the back-end optical switching digital matrix for use. This device realizes the purpose of generating and transmitting the high-speed data transmission VCM baseband signal by using the above principle.

Claims

1. A high-speed data transmission VCM baseband signal generation and transmission device, characterized in that It includes an interleaving mapping module (1), a symbol mapping module (2), a physical frame generation module (3), a shaping filter module I (5-1), a shaping filter module II (5-2), a digital quadrature upconversion module (6), a data rate matching module (7), a data grouping module (8), a transmission frame generation module (9), an output data rate matching module I (10-1), an output data rate matching module II (10-2), an output data rate matching module III (10-3), an output data rate matching module IV (10-4), a GTH module I (11-1), a GTH module II (11-2), a GTH module III (11-3), a GTH module IV (11-4), an optical-electric converter I (12-1), an optical-electric converter II (12-2), an optical-electric converter III (12-3), and an optical-electric converter IV (12-4); First, the data interleaving and mapping module (1) receives the input bit data stream to be modulated frame by frame through the CLK zero processing clock, and according to the modulation system indication signal, in the order of the input of the bit data stream, maps the bit data stream frame by frame according to the corresponding relationship between the current modulation system and the number of mappings between the bit data. The data interleaving and mapping is completed through the serial-to-parallel conversion method of queuing in columns in sequence, and the data interleaving and mapping signal is transmitted to the symbol mapping module (2). The symbol mapping module (2) performs modulation symbol mapping on the received data interleaving and mapping signal through the CLK zero processing clock according to the received modulation system indication signal, generates the I / Q two-way digital baseband signal after symbol mapping, and transmits this signal to the physical frame generation module (3). The physical frame generation module (3) receives the I / Q two-way digital baseband signal output by the symbol mapping module (2) through the CLK zero processing clock, adds a physical frame header with a length of 90 symbols at the frame start position, and at the same time, adds pilot symbols with a length of 36 symbols every 1440 data symbol lengths, and finally generates the I / Q two-way VCM baseband signal, and transmits this signal to the shaping filter module I (5-1) and the shaping filter module II (5-2) respectively. The shaping filter module I (5-1) and the shaping filter module II (5-2) select the shaping filter coefficients corresponding to the current shaping coefficients according to the shaping coefficient indication signal, and perform shaping filter processing on the input I / Q two-way VCM baseband signal respectively through the CLK zero processing clock, generate the I / Q two-way VCM baseband signal with 4 times sampling, and transmit this signal to the digital quadrature up-conversion module (6). The digital quadrature up-conversion module (6) performs digital quadrature up-conversion processing on the input I / Q two-way VCM baseband signal through the CLK zero processing clock according to the intermediate frequency setting signal, generates the I / Q two-way VCM baseband signal carrying the intermediate frequency offset, and transmits this signal to the data rate matching module (7). The data rate matching module (7) caches the input I / Q two-way VCM baseband signal through the CLK zero processing clock. When the cache capacity reaches the data output threshold, the data rate matching module (7) outputs a data readable indication signal and transmits this signal to the transmission frame generation module (9). The transmission frame generation module (9) receives the data readable indication signal through the CLK zero processing clock. When the transmission frame generation module (9) receives a valid data readable indication signal, the transmission frame generation module (9) generates and outputs a data read control signal through the CLK one transmission clock. When the data rate matching module (7) receives a valid data read control signal through the CLK one transmission clock, the data rate matching module (7) starts to read the I / Q two-way VCM baseband signal stored in the cache through the CLK one transmission clock, and transmits the read I / Q two-way VCM baseband signal to the data packet module (8). The data packet module (8) performs data recombination on the input I / Q two-way VCM baseband signal through the CLK one transmission clock, and converts the symbol data of the received I / Q two-way VCM baseband signal into bit data.Four-way parallel transmission data is generated through the serial-parallel conversion method, and the generated four-way parallel transmission data is transmitted to the transmission frame generation module (9). The transmission frame generation module (9) frames the input 4-way transmission data respectively through the CLK - transmission clock. When framing, every 1388-bit data is used as a valid data block of a transmission frame. Frame header identification, frame tail identification, and frame synchronization identification are also added to the transmission frame. After the transmission frame generation module (9) completes the framing process, the simultaneously generated four-way transmission frame data is respectively transmitted to the output data rate matching module I (10-1), the output data rate matching module II (10-2), the output data rate matching module III (10-3), and the output data rate matching module IV (10-4). The output data rate matching module I (10-1), the output data rate matching module II (10-2), the output data rate matching module III (10-3), and the output data rate matching module IV (10-4) respectively receive and store the input transmission frame data through the CLK - transmission clock, and at the rising edge moment of the first 1PPS second pulse signal received after receiving the transmission frame data, they respectively transmit the stored transmission frame data to the GTH module I (11-1), the GTH module II (11-2), the GTH module III (11-3), and the GTH module IV (11-4) through the CLK - transmission clock, the CLK - two transmission clock, the CLK - three transmission clock, and the CLK - four transmission clock. The GTH module I (11-1), the GTH module II (11-2), the GTH module III (11-3), and the GTH module IV (11-4) respectively receive the input transmission frame data through the CLK - transmission clock, the CLK - two transmission clock, the CLK - three transmission clock, and the CLK - four transmission clock, and generate and output four-way analog electrical signals after processing such as 8B / 10B encoding. The four-way analog electrical signals are respectively processed by the optical-electric converter I (12-1), the optical-electric converter II (12-2), the optical-electric converter III (12-3), and the optical-electric converter IV (12-4) to generate four-way optical signals, which are output as the final output signals of this device.

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