Display substrate, preparation method thereof and display device

Abstract

A display substrate, a manufacturing method thereof, and a display device. The display substrate includes a pixel light-emitting area (PA) and a pixel spacing area (PK); in a plane perpendicular to the display substrate, the display substrate includes a base (10) and a light-emitting structure layer (30) disposed on the base (10), the light-emitting structure layer (30) at least includes an anode (31), a pixel definition layer (32), and at least one spacer (50), the pixel definition layer (32) is provided with a pixel opening (71) in the pixel light-emitting area (PA), the pixel opening (71) exposes the anode (31), the pixel definition layer (32) is provided with a spacing opening (72) in the pixel spacing area (PK), the spacer (50) is disposed in the spacing opening (72), and a normal projection of the spacer (50) on the base (10) is located within a range of a normal projection of the spacing opening (72) on the base (10).

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, display devices using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] A display substrate includes a plurality of pixel light-emitting areas and a plurality of pixel spacing areas located between adjacent pixel light-emitting areas; in a plane perpendicular to the display substrate, the display substrate includes a substrate and a light-emitting structure layer disposed on the substrate, the light-emitting structure layer including at least an anode, a pixel definition layer and at least one spacer pillar, the pixel definition layer having a pixel opening in the pixel light-emitting area, the pixel opening exposing the anode, the pixel definition layer having a spacing opening in the pixel spacing area, the spacer pillar being disposed within the spacing opening, and the orthographic projection of the spacer pillar on the substrate being within the range of the orthographic projection of the spacing opening on the substrate.

[0005] In an exemplary embodiment, a groove is provided between the sidewall of the septum post and the sidewall of the spacer opening.

[0006] In an exemplary embodiment, the lateral distance between the sidewall of the spacer post and the sidewall of the spacer opening gradually increases along a direction away from the substrate, the lateral distance being a dimension in a plane parallel to the display substrate.

[0007] In an exemplary embodiment, at least one anode includes a body portion and at least one protrusion, the pixel opening exposes the body portion of the anode, and the orthographic projection of the groove on the substrate does not overlap with the orthographic projection of the protrusion of the anode on the substrate.

[0008] In an exemplary embodiment, the orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the septum post on the substrate, and the groove is C-shaped and is disposed in the area outside the protrusion.

[0009] In an exemplary embodiment, the protrusion includes at least a first protrusion and a second protrusion. The driving circuit layer is provided with a connection electrode. A first end of the first protrusion is connected to the main body. A second end of the first protrusion is connected to the first end of the connection electrode through a via. A first end of the second protrusion is connected to the second end of the connection electrode through a via. The second end of the second protrusion extends in a direction away from the main body. The orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projection of the septum post on the substrate. The orthographic projection of the connection electrode on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate.

[0010] In an exemplary embodiment, at least one anode includes a body portion and at least one protrusion, the pixel opening exposes the body portion of the anode, the groove is an annular groove surrounding the septum post, the orthographic projection of the groove on the substrate at least partially overlaps with the orthographic projection of the protrusion of the anode on the substrate, forming a connecting overlap area; in the connecting overlap area, the distance between the surface of the groove near the substrate and the substrate is greater than the distance between the surface of the anode away from the substrate and the substrate.

[0011] In an exemplary embodiment, the protrusion has a first width in the connection overlap area and a second width in the area outside the connection overlap area. The first width is smaller than the second width, and the first width and the second width are dimensions along the extension direction of the groove.

[0012] In an exemplary embodiment, the protrusion includes at least a first protrusion, a second protrusion, and a third protrusion. A first end of the first protrusion is connected to the main body. A second end of the first protrusion is connected to the first end of the third protrusion. The second end of the third protrusion extends away from the main body and then connects to the first end of the second protrusion. The second end of the second protrusion extends away from the main body. The orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projection of the spacer post on the substrate. The orthographic projection of the third protrusion on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate. The third protrusion has the first width, and either the first or second protrusion has the second width.

[0013] In an exemplary embodiment, the first width is 0.5 μm to 2 μm, and the second width is 8 μm to 12 μm.

[0014] In an exemplary embodiment, the width of the surface of the groove near the substrate is 0.5 μm to 5.0 μm, and the width is a dimension perpendicular to the extension direction of the groove.

[0015] In an exemplary embodiment, the surface of the protrusion in the connection overlap area has a first roughness, and the surface of the protrusion in the area outside the connection overlap area has a second roughness, wherein the first roughness is greater than the second roughness.

[0016] In an exemplary embodiment, the spacer pillars and the pixel definition layer are made of the same material and are formed synchronously through the same patterning process.

[0017] In an exemplary embodiment, the display substrate further includes a driving circuit layer disposed on the substrate, and the light-emitting structure layer is disposed on the side of the driving circuit layer away from the substrate; the driving circuit layer includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, the plurality of circuit units being aligned on the unit rows and a plurality of sub-pixels being aligned on the unit columns; the light-emitting structure layer includes a plurality of sub-pixels constituting a plurality of pixel rows and a plurality of pixel columns, the plurality of sub-pixels being aligned on the pixel rows and a plurality of sub-pixels being staggered on the pixel columns.

[0018] In an exemplary embodiment, at least one circuit unit includes a pixel driving circuit, which is connected to a first scan signal line, a second scan signal line, and a light emission control line, respectively. The pixel driving circuit includes at least a storage capacitor. In the Mth unit row, the first scan signal line is located on the side of the storage capacitor closer to the (M+1)th unit row, the second scan signal line is located on the side of the storage capacitor away from the (M+1)th unit row, and the light emission control line is located between the storage capacitor and the second scan signal line. At least one sub-pixel includes an anode connected to the pixel driving circuit. The anode in the (2M-1)th pixel row is located on the side of the light emission control line in the Mth unit row away from the (M+1)th unit row, and the anode in the 2Mth pixel row is located on the side of the light emission control line in the Mth unit row closer to the (M+1)th unit row, where 1 ≤ M ≤ K, and K is the row number of the unit row.

[0019] In an exemplary embodiment, the orthographic projection of the anode in the 2M-1 pixel row onto the substrate at least partially overlaps with the orthographic projection of the second scan signal line in the M cell row onto the substrate, and the orthographic projection of the anode in the 2M pixel row onto the substrate at least partially overlaps with the orthographic projection of the storage capacitor onto the substrate.

[0020] In an exemplary embodiment, the orthographic projection of the anode in the 2M-1 pixel row onto the substrate at least partially overlaps with the orthographic projection of the two pixel driving circuits in the M unit row onto the substrate, and the orthographic projection of the anode in the 2M pixel row onto the substrate at least partially overlaps with the orthographic projection of the two pixel driving circuits in the M unit row onto the substrate.

[0021] In an exemplary embodiment, at least one spacer post is located between adjacent anodes, including any one or more of the following: at least one spacer post is located between adjacent anodes in a pixel row, at least one spacer post is located between adjacent anodes in a pixel column, and at least one spacer post is located between an anode in the 2M-1 pixel row and an anode in the 2M pixel row.

[0022] In an exemplary embodiment, the spacer post is rectangular in shape, including a long side and a short side. The spacer post includes at least a first spacer post whose long side extends along the pixel column direction, a second spacer post whose long side extends along the pixel row direction, and a third spacer post whose long side extends along an inclined direction. The inclined direction has a first angle with the pixel column direction, or the inclined direction has a second angle with the pixel row direction. The first angle and the second angle are greater than 0° and less than 90°.

[0023] In an exemplary embodiment, the first spacer post is disposed between adjacent anodes in a pixel row, the second spacer post is disposed between adjacent anodes in a pixel column, and the third spacer post is disposed between the anodes in the 2M-1 pixel row and the anodes in the 2M pixel row.

[0024] In an exemplary embodiment, the orthographic projection of the third septum post on the substrate at least partially overlaps with the orthographic projection of the light-emitting control line on the substrate.

[0025] In an exemplary embodiment, multiple septum pillars constitute multiple rows of septum pillars and multiple columns of septum pillars, with three pixel rows corresponding to four rows of septum pillars.

[0026] A display device includes the aforementioned display substrate.

[0027] A method for fabricating a display substrate, the display substrate comprising a plurality of pixel light-emitting regions and a plurality of pixel spacing regions located between adjacent pixel light-emitting regions; the fabrication method comprising:

[0028] A light-emitting structure layer is formed on a substrate. The light-emitting structure layer includes at least an anode, a pixel definition layer, and at least one spacer pillar. The pixel definition layer has a pixel opening in the pixel light-emitting area, and the pixel opening exposes the anode. The pixel definition layer has a spacing opening in the pixel spacing area, and the spacer pillar is disposed within the spacing opening. The orthographic projection of the spacer pillar on the substrate is located within the range of the orthographic projection of the spacing opening on the substrate.

[0029] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0031] Figure 1 This is a schematic diagram of the structure of an OLED display device;

[0032] Figure 2 This is a schematic cross-sectional view of a display device;

[0033] Figure 3 This is a schematic diagram of a cross-sectional structure of a display substrate;

[0034] Figure 4 This is a schematic diagram of an equivalent circuit for a pixel driving circuit.

[0035] Figure 5 This is a schematic diagram of the planar structure of a driving circuit layer in a display substrate according to an embodiment of the present disclosure;

[0036] Figure 6 This is a schematic diagram of a planar structure of a circuit unit as an exemplary embodiment of the present disclosure;

[0037] Figure 7 This is a schematic diagram of the planar structure of a light-emitting structure layer in a display substrate according to an embodiment of the present disclosure;

[0038] Figure 8a and Figure 8b This is a schematic diagram of the structure of a sub-pixel, which is an exemplary embodiment of the present disclosure;

[0039] Figures 9a to 9c This is a schematic diagram of the structure of another sub-pixel as an exemplary embodiment of the present disclosure;

[0040] Figures 10a to 10c This is a schematic diagram of the structure of another sub-pixel, as an exemplary embodiment of the present disclosure;

[0041] Figures 11a to 11c This is a schematic diagram of the structure of another sub-pixel, as an exemplary embodiment of the present disclosure;

[0042] Figures 12a to 12c This is a schematic diagram of the structure of another sub-pixel, as an exemplary embodiment of the present disclosure;

[0043] Figure 13 This is a schematic diagram showing the formation of the driving structure layer pattern according to an exemplary embodiment of the present disclosure;

[0044] Figure 14a and Figure 14b This is a schematic diagram showing the formation of the anode conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0045] Figure 15a and Figure 15b A schematic diagram showing the septum post pattern formed according to an exemplary embodiment of this disclosure;

[0046] Figure 16 A schematic diagram illustrating an exposure method as an exemplary embodiment of this disclosure;

[0047] Figure 17 This is a schematic diagram illustrating another exposure method of an exemplary embodiment of this disclosure;

[0048] Figure 18a This is a schematic diagram of a pixel definition layer and septum pillar exposure method;

[0049] Figure 18b This is a schematic diagram of a cross-sectional structure of a pixel definition layer and spacer pillars;

[0050] Figure 19 This is a schematic diagram of a display substrate exhibiting light leakage.

[0051] Explanation of reference numerals in the attached figures:

[0052] 10—Substrate; 20—Driver circuit layer; 21—First scan signal line;

[0053] 22—Second scan signal line; 23—Emitting light control line; 24—First electrode plate;

[0054] 25—Connecting electrode; 30—Light-emitting structure layer; 31—Anode;

[0055] 32—Pixel definition layer; 33—Organic light-emitting layer; 34—Cathode;

[0056] 50—September post; 60—Groove; 60-1—First sidewall;

[0057] 60-2—Second sidewall; 60-3—Bottom wall; 61—Connecting overlapping area;

[0058] 71—Pixel opening; 72—Interval opening; 91—Main body;

[0059] 92—Protrusion; 92-1—First protrusion; 92-2—Second protrusion;

[0060] 92-3—Third protrusion; 93—Rough surface area; 100—Halftone mask;

[0061] 101—Unexposed area; 102—Partially exposed area; 103—Fully exposed area.

[0062] 200—Gray mask; 201—Unexposed area; 202—First part of the exposed area;

[0063] 203—Second part of the exposure area; 204—Fully exposed area; 300—Display structure layer;

[0064] 400—Cover glass; 500—Silicone sealant. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0066] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0067] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0068] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0069] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0070] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0071] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0072] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0073] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0074] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0075] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process, and their materials may be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0076] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0077] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0078] Figure 1 This is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting control lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which is connected to the scan signal lines, the light-emitting control lines, and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data driver to the data driver, provide clock signals, scan start signals, etc., of specifications suitable for the scan driver to the scan driver, and provide clock signals, emission stop signals, etc., of specifications suitable for the light-emitting driver to the light-emitting driver. The data driver can use grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. The light-emitting driver can generate transmit signals to be provided to light-emitting control lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from the timing controller. For example, an LED driver can sequentially provide transmit signals with cutoff level pulses to LED control lines E1 to Eo. For example, the LED driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals in the form of cutoff level pulses to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0079] Figure 2 This is a cross-sectional structural diagram of a display device, illustrating an encapsulation method that combines fritter adhesive and cover glass. Figure 2As shown, on a plane perpendicular to the display device, the main structure of the display device may include a substrate 10, a display structural layer 300, a cover glass 400, and glass adhesive 500. The display structural layer 300 is disposed on the rigid substrate 10 and configured to emit light; the display structural layer 300 may be referred to as a display substrate. The cover glass 400 is disposed on the side of the display structural layer 300 away from the substrate 10 and is configured to be encapsulated by glass adhesive 500. The glass adhesive 500 is disposed between the substrate 10 and the cover glass 400 and is fixed to both the substrate 10 and the cover glass 400, forming an accommodating space that seals the display structural layer 300 within this space. In an exemplary embodiment, a plurality of spacer pillars may be provided on the display structural layer 300, and these spacer pillars are configured to support the cover glass together with the glass adhesive.

[0080] Figure 3 This is a schematic cross-sectional view of a display substrate. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include at least a driving circuit layer 20 disposed on the substrate 10 and a light-emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, which are not limited herein.

[0081] In an exemplary embodiment, the substrate 10 may be a rigid substrate. The driving circuit layer 20 may include a plurality of regularly arranged circuit units, each circuit unit may include at least a pixel driving circuit, which is connected to signal lines such as scan signal lines, data signal lines, and light emission control lines. The light emission structure layer 30 may include a plurality of regularly arranged light-emitting devices, each light-emitting device may include at least an anode 31, an organic light-emitting layer 33, and a cathode 34. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light emission control line, and output a corresponding current to the light-emitting device. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0082] In an exemplary embodiment, the pixel driving circuit of the circuit unit may include multiple transistors and a storage capacitor. Figure 3 The example shown uses a pixel driving circuit consisting of a transistor 20A and a storage capacitor 20B. The anode 31 of the light-emitting device is connected to the drain electrode of the transistor 20A through a via. The organic light-emitting layer 33 is connected to the anode 31, and the cathode 34 is connected to the organic light-emitting layer 33. The organic light-emitting layer 33 emits light of the corresponding color under the drive of the anode 31 and the cathode 34.

[0083] In an exemplary embodiment, the light-emitting structure layer 30 may further include a pixel definition layer 32, on which pixel openings are provided, exposing the anode 31 of the light-emitting device to form a light-emitting region. The organic light-emitting layer 33 may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be common layers connected together, and the light-emitting layers of adjacent sub-pixels may have a small amount of overlap or may be isolated.

[0084] In some possible exemplary embodiments, the substrate may be a flexible substrate, and the display substrate may include a thin film encapsulation layer disposed on the side of the light-emitting structure layer away from the substrate. The thin film encapsulation layer may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first encapsulation layer and the third encapsulation layer to ensure that external moisture cannot enter the light-emitting structure layer.

[0085] Figure 4 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Figure 4 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C. The pixel driving circuit may be connected to 7 signal lines (data signal line D, first scan signal line S1, second scan signal line S2, light emission control line E, initial signal line INIT, first power supply line VDD and second power supply line VSS).

[0086] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first terminal of the third transistor T3, the second terminal of the fourth transistor T4, and the second terminal of the fifth transistor T5, respectively. The second node N2 is connected to the second terminal of the first transistor, the first terminal of the second transistor T2, the control terminal of the third transistor T3, and the second terminal of the storage capacitor C, respectively. The third node N3 is connected to the second terminal of the second transistor T2, the second terminal of the third transistor T3, and the first terminal of the sixth transistor T6, respectively.

[0087] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3.

[0088] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3 to initialize the charge of the control electrode of the third transistor T3.

[0089] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a conduction-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to its second electrode.

[0090] The control electrode of the third transistor T3 is connected to the second node N2, meaning the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0091] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, scanning transistor, etc. When a conduction-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0092] The control electrode of the fifth transistor T5 is connected to the light-emitting control line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light-emitting control line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device. The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the light-emitting control line E, the fifth transistor T5 and the sixth transistor T6 cause the light-emitting device to emit light by forming a driving current path between the first power supply line VDD and the second power supply line VSS.

[0093] The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0094] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal. The first scan signal line S1 is the scan signal line in the pixel driving circuit of this display row, and the second scan signal line S2 is the scan signal line in the pixel driving circuit of the previous display row. That is, for the nth display row, the first scan signal line S1 is S(n), and the second scan signal line S2 is S(n-1). The second scan signal line S2 of this display row and the first scan signal line S1 in the pixel driving circuit of the previous display row are the same signal line, which can reduce the signal lines of the display panel and realize a narrow bezel of the display panel.

[0095] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0096] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0097] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emission control line E, and the initial signal line INIT can extend in the horizontal direction, while the second power line VSS, the first power line VDD, and the data signal line D can extend in the vertical direction.

[0098] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0099] In an exemplary embodiment, taking all seven transistors as P-type transistors as an example, the operation of the pixel driving circuit may include:

[0100] In the first stage A1, also known as the reset stage, the signal on the second scan signal line S2 is low, while the signals on the first scan signal line S1 and the light-emitting control line E are high. The low signal on the second scan signal line S2 turns on the first transistor T1, and the initial signal line INIT is supplied to the second node N2 to initialize (reset) the storage capacitor C, clearing its existing charge. The low signal on the second scan signal line S2 turns on the seventh transistor T7, and the initial voltage of the initial signal line INIT is supplied to the first electrode of the OLED to initialize (reset) it, clearing its internal pre-stored voltage and completing the initialization. The high signals on the first scan signal line S1 and the light-emitting control line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7; during this stage, the OLED does not emit light.

[0101] The second stage, A2, also known as the data writing stage or threshold compensation stage, involves a low-level signal on the first scan signal line S1, while the signals on the second scan signal line S2 and the light-emitting control line E are high-level signals. The data signal line D outputs a data voltage. During this stage, the second terminal of the storage capacitor C is low, causing the third transistor T3 to conduct. The low-level signal on the first scan signal line S1 turns on the second transistor T2 and the fourth transistor T4. The conduction of the second transistor T2 and the fourth transistor T4 allows the data voltage output from the data signal line D to be supplied to the second node N2 via the first node N1, the conducting third transistor T3, the third node N3, and the conducting second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is then charged into the storage capacitor C. The voltage at the second terminal of the storage capacitor C (second node N2) is Vd - |Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. The high-level signal on the second scan signal line S2 turns off the first transistor T1 and the seventh transistor T7. The signal on the light-emitting control line E is a high-level signal, which disconnects the fifth transistor T5 and the sixth transistor T6.

[0102] The third stage, A3, is called the light-emitting stage. During this stage, the light-emitting control line E is at a low level, while the first scan signal line S1 and the second scan signal line S2 are at a high level. The low level of the light-emitting control line E turns on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output from the first power line VDD then provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, driving the OLED to emit light.

[0103] During the pixel driving circuit operation, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and its first electrode. Since the voltage at the second node N2 is Vdata - |Vth|, the driving current of the third transistor T3 is:

[0104] I = K * (Vgs - Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd)] 2

[0105] Where I is the driving current flowing through the third transistor T3, which is the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0106] Figure 5 This is a schematic diagram of a planar structure of a driving circuit layer in a display substrate, as an exemplary embodiment of this disclosure. Figure 5 As shown, in an exemplary embodiment, on a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units QD, and at least one circuit unit QD may include a pixel driving circuit, which is configured to output a corresponding current to the connected light-emitting device, so that the light-emitting device emits light of a corresponding brightness.

[0107] In an exemplary embodiment, multiple circuit units QD can form multiple cell rows and multiple cell columns. Multiple circuit units QD arranged sequentially along the horizontal direction can be called a cell row, and multiple circuit units QD arranged sequentially along the vertical direction can be called a cell column. Multiple cell rows and multiple cell columns constitute an array of arranged circuit units. In an exemplary embodiment, the driving circuit layer can include K cell rows, where K is a positive integer greater than 1.

[0108] In an exemplary embodiment, multiple circuit units QD can be arranged sequentially in the cell row direction according to an alignment method, and multiple circuit units QD can be arranged sequentially in the cell column direction according to an alignment method to form a layout with horizontal and vertical alignment.

[0109] Figure 6 This is a schematic diagram of a planar structure of a circuit unit, illustrating the structure of pixel driving circuits in 3 unit rows and 7 unit columns, as an exemplary embodiment of this disclosure. Figure 6 As shown, at least one circuit unit may include a pixel driving circuit, which may be connected to multiple signal lines. In an exemplary embodiment, the multiple signal lines may include at least a first scan signal line 21, a second scan signal line 22, and a light emission control line 23 extending in a horizontal direction. The pixel driving circuit may include at least a storage capacitor C and seven transistors (first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, and seventh transistor T7). The storage capacitor C includes at least a first electrode plate 24.

[0110] In an exemplary embodiment, in a plane perpendicular to the substrate, at least one circuit unit may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, and a third conductive layer stacked on the substrate. The semiconductor layer may include at least the active layers of the first transistors T1 to the seventh transistor T7. The first conductive layer may include at least the gate electrode of the first transistors T1 to the seventh transistor T7 and the first plate of the storage capacitor C. The second conductive layer may include at least the second plate of the storage capacitor C and an initial signal line. The third conductive layer may include at least a data signal line, a first power supply line, and the first and second electrodes of the first transistors T1 to the seventh transistor T7. To clearly illustrate the location of each transistor... Figure 7 Only a portion of the structure of the semiconductor layer and the first conductive layer is shown.

[0111] In an exemplary embodiment, the semiconductor layer of each circuit unit may include at least the first active layer of the first transistor T1 to the seventh active layer of the seventh transistor T7, and the first active layer to the seventh active layer are interconnected as an integral structure. The second active layer of the circuit unit in the Mth unit row of each unit column is interconnected with the first active layer of the circuit unit in the M+1th unit row. That is, the semiconductor layers of adjacent circuit units in each unit column are interconnected as an integral structure, 1≤M≤K, where K is the row number of the unit row.

[0112] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region of the first active layer may serve as the first region of the seventh active layer and is configured to be connected to an initial signal line. The second region of the first active layer may simultaneously serve as the first region of the second active layer; the first region of the third active layer may simultaneously serve as the second region of both the fourth and fifth active layers; the second region of the third active layer may simultaneously serve as the second region of both the second and sixth active layers; and the second region of the sixth active layer may serve as the second region of the seventh active layer. The first region of the fourth active layer may be configured separately to be connected to a data signal line. The first region of the fifth active layer may be configured separately to be connected to a first power supply line.

[0113] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, and the light emission control line 23 can be disposed in the first conductive layer, and can be a line shape extending horizontally along the main body. The storage capacitor C can be located between the first scan signal line 21 and the light emission control line 23. In the Mth cell row, the first scan signal line 21 can be located on the side of the storage capacitor C closer to the (M+1)th cell row, the second scan signal line 22 can be located on the side of the storage capacitor C away from the (M+1)th cell row, and the light emission control line 23 can be located between the storage capacitor C and the second scan signal line 22.

[0114] In this disclosure, "near" and "far" are described from the perspective of orthographic projections onto the substrate. For example, the orthographic projection of A onto the substrate is abbreviated as A projection, the orthographic projection of B onto the substrate is abbreviated as B projection, and the orthographic projection of D onto the substrate is abbreviated as D projection. "A is located on the side of D that is closer to B" means that the A projection is located on the side of the D projection that is closer to the B projection.

[0115] In an exemplary embodiment, the first plate 24 of the storage capacitor C can serve as the gate electrode of the third transistor (driving transistor) T3; the region where the first scan signal line 21 overlaps with the second active layer and the fourth active layer can serve as the gate electrode of the second transistor T2 and the gate electrode of the fourth transistor T4, respectively; the region where the second scan signal line 22 overlaps with the first active layer and the seventh active layer can serve as the gate electrode of the first transistor T1 and the gate electrode of the seventh transistor T7, respectively; and the region where the light emission control line 23 overlaps with the fifth active layer and the sixth active layer can serve as the gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6, respectively.

[0116] In an exemplary embodiment, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 of the pixel driving circuit in the Mth cell row can be located on the side of the storage capacitor C away from the M+1th cell row, and the second transistor T2 and the fourth transistor T4 can be located on the side of the storage capacitor C close to the M+1th cell row.

[0117] In an exemplary embodiment, the fourth transistor T4 and the fifth transistor T5 of the pixel driving circuit in the Nth unit column can be located on the side of the storage capacitor C closer to the N+1th unit column, and the second transistor T2 and the sixth transistor T6 can be located on the side of the storage capacitor C away from the N+1th unit column, where N is a positive integer greater than or equal to 1.

[0118] The pixel driving circuits in each circuit row have the same shape and are aligned. The pixel driving circuits in the Mth unit row have the same shape and are aligned with the pixel driving circuits in the M+1th pixel row.

[0119] Figure 7 This is a schematic diagram of a planar structure of a light-emitting layer in a display substrate, as an exemplary embodiment of this disclosure. Figure 7As shown, in an exemplary embodiment, on a plane parallel to the display substrate, the light-emitting structure layer may include a plurality of pixel units P arranged in a matrix. At least one of the plurality of pixel units P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the three sub-pixels may include a light-emitting device. The light-emitting devices of the three sub-pixels are respectively connected to a pixel driving circuit in a corresponding circuit unit. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0120] In an exemplary embodiment, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a blue (B) sub-pixel that emits blue light, and the third sub-pixel P3 may be a green (G) sub-pixel that emits green light. The shapes of the three sub-pixels may be triangles, rectangles, rhombuses, pentagons, or hexagons, etc., and are not limited herein.

[0121] In an exemplary embodiment, multiple sub-pixels can form multiple pixel rows and multiple pixel columns. Multiple sub-pixels arranged sequentially along a horizontal direction can be called a pixel row, and multiple sub-pixels arranged sequentially along a vertical direction can be called a pixel column. Multiple pixel rows and multiple pixel columns constitute an array of pixels. In an exemplary embodiment, the light-emitting structure layer can include 2K pixel rows, where K is the number of cell rows in the driving circuit layer.

[0122] In an exemplary embodiment, in the pixel row direction, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 can be arranged sequentially in an aligned manner, while in the pixel column direction, they can be arranged sequentially in a staggered manner, forming a triangular layout of sub-pixels. For example, the first sub-pixel P1 in an odd-numbered row can be located between adjacent second sub-pixels P2 and third sub-pixels P3 in an even-numbered row, or the first sub-pixel P1 in an even-numbered row can be located between adjacent second sub-pixels P2 and third sub-pixels P3 in an odd-numbered row. Similarly, the second sub-pixel P2 in an odd-numbered row can be located between adjacent first sub-pixels P1 and third sub-pixels P3 in an even-numbered row, or the second sub-pixel P2 in an even-numbered row can be located between adjacent first sub-pixels P1 and third sub-pixels P3 in an odd-numbered row. For example, the third sub-pixel P3 in an odd-numbered row can be located between the first sub-pixel P1 and the second sub-pixel P2 in an even-numbered row, or the third sub-pixel P3 in an even-numbered row can be located between the first sub-pixel P1 and the second sub-pixel P2 in an odd-numbered row.

[0123] In an exemplary embodiment, multiple pixel units P can be arranged in a triangular layout to form pixel units.

[0124] The circuit unit mentioned in this disclosure refers to a region divided according to the driving circuit layer, and each circuit unit includes a pixel driving circuit. The sub-pixel mentioned in this disclosure refers to a region divided according to the light-emitting structure layer, and each sub-pixel includes a light-emitting device. In exemplary embodiments, the positions of the sub-pixel and the circuit unit may correspond, or the positions of the sub-pixel and the circuit unit may not correspond.

[0125] In an exemplary embodiment, each sub-pixel may include a light-emitting region and a non-light-emitting region. In this disclosure, the light-emitting region of each sub-pixel is referred to as the pixel light-emitting region, and the non-light-emitting region of each sub-pixel is referred to as the pixel spacing region. In an exemplary embodiment, a pixel opening is provided on the pixel definition layer of each sub-pixel, exposing the anode, so that the organic light-emitting layer is connected to the anode through the pixel opening. Since the organic light-emitting layer emits light from the pixel opening region defined by the pixel definition layer, the pixel opening region is the pixel light-emitting region, and the region outside the pixel opening is the pixel spacing region, which is located on the periphery of the pixel light-emitting region. For example, the pixel opening region in the first sub-pixel and the second sub-pixel is the pixel light-emitting region, and the region between the pixel light-emitting region of the first sub-pixel and the pixel light-emitting region of the second sub-pixel is the pixel spacing region. Thus, the display substrate may include a plurality of periodically arranged pixel light-emitting regions and a plurality of pixel spacing regions located between adjacent pixel light-emitting regions.

[0126] In an exemplary embodiment, the light-emitting structure layer may include a light-emitting device, a pixel definition layer, and at least one photo spacer (PS). The light-emitting device may include an anode, an organic light-emitting layer, and a cathode. The at least one photo spacer may be disposed in the pixel spacing region. In an exemplary embodiment, for an encapsulation method combining fritter adhesive and cover glass, the photo spacer is configured to support the cover glass.

[0127] This disclosure provides an exemplary embodiment of a display substrate. In an exemplary embodiment, the display substrate may include a plurality of pixel light-emitting areas and a plurality of pixel spacing areas located between adjacent pixel light-emitting areas in a plane parallel to the display substrate. In a plane perpendicular to the display substrate, the display substrate may include a substrate, a driving circuit layer disposed on the substrate, and a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate. The light-emitting structure layer includes at least an anode, a pixel definition layer, and at least one spacer pillar. The pixel definition layer has a pixel opening in the pixel light-emitting area, the pixel opening exposing the anode. The pixel definition layer has a spacing opening in the pixel spacing area, and the spacer pillar is disposed within the spacing opening. The orthographic projection of the spacer pillar onto the substrate is within the range of the orthographic projection of the spacing opening onto the substrate.

[0128] In an exemplary embodiment, a groove is provided between the sidewall of the septum post and the sidewall of the spacer opening.

[0129] In an exemplary embodiment, the lateral distance between the sidewall of the spacer post and the sidewall of the spacer opening gradually increases along a direction away from the substrate, the lateral distance being a dimension in a plane parallel to the display substrate.

[0130] In an exemplary embodiment, the spacer pillars and the pixel definition layer are made of the same material and are formed synchronously through the same patterning process.

[0131] In one exemplary embodiment, at least one anode includes a body portion and a protrusion portion, the pixel opening exposes the body portion of the anode, and the orthographic projection of the groove on the substrate does not overlap with the orthographic projection of the protrusion of the anode on the substrate.

[0132] In another exemplary embodiment, at least one anode includes a body portion and a protrusion portion, the pixel opening exposes the body portion of the anode, the groove is an annular groove surrounding the septum post, the orthographic projection of the groove on the substrate at least partially overlaps with the orthographic projection of the protrusion of the anode on the substrate, forming a connecting overlap area; in the connecting overlap area, the distance between the surface of the groove near the substrate and the substrate is greater than the distance between the surface of the anode away from the substrate and the substrate.

[0133] In another exemplary embodiment, the protrusion has a first width in the connection overlap area and a second width in the area outside the connection overlap area, the first width being smaller than the second width, and the first width and the second width being dimensions along the extension direction of the groove.

[0134] In another exemplary embodiment, the surface of the protrusion in the connecting overlap area has a first roughness, and the surface of the protrusion in the area outside the connecting overlap area has a second roughness, wherein the first roughness is greater than the second roughness.

[0135] In an exemplary embodiment, the driving circuit layer may include a plurality of circuit units constituting a plurality of cell rows and a plurality of cell columns, wherein the plurality of circuit units are aligned on the cell rows and a plurality of sub-pixels are aligned on the cell columns; the light-emitting structure layer includes a plurality of sub-pixels constituting a plurality of pixel rows and a plurality of pixel columns, wherein the plurality of sub-pixels are aligned on the pixel rows and a plurality of sub-pixels are staggered on the pixel columns.

[0136] In an exemplary embodiment, at least one circuit unit includes a pixel driving circuit, which is connected to a first scan signal line, a second scan signal line, and a light emission control line, respectively. The pixel driving circuit includes at least a storage capacitor. In the Mth unit row, the first scan signal line is located on the side of the storage capacitor closer to the (M+1)th unit row, the second scan signal line is located on the side of the storage capacitor away from the (M+1)th unit row, and the light emission control line is located between the storage capacitor and the second scan signal line. At least one sub-pixel includes an anode connected to the pixel driving circuit. The anode in the (2M-1)th pixel row is located on the side of the light emission control line in the Mth unit row away from the (M+1)th unit row, and the anode in the 2Mth pixel row is located on the side of the light emission control line in the Mth unit row closer to the (M+1)th unit row, where 1 ≤ M ≤ K, and K is the row number of the unit row.

[0137] In an exemplary embodiment, the orthographic projection of the anode in the 2M-1 pixel row onto the substrate at least partially overlaps with the orthographic projection of the second scan signal line in the M cell row onto the substrate, and the orthographic projection of the anode in the 2M pixel row onto the substrate at least partially overlaps with the orthographic projection of the storage capacitor onto the substrate.

[0138] In an exemplary embodiment, the orthographic projection of the anode in the 2M-1 pixel row onto the substrate at least partially overlaps with the orthographic projection of the two pixel driving circuits in the M unit row onto the substrate, and the orthographic projection of the anode in the 2M pixel row onto the substrate at least partially overlaps with the orthographic projection of the two pixel driving circuits in the M unit row onto the substrate.

[0139] In an exemplary embodiment, at least one spacer post is located between adjacent anodes in a pixel row, or at least one spacer post is located between adjacent anodes in a pixel column.

[0140] In an exemplary embodiment, at least one septum post is located between the anode in the 2M-1 pixel row and the anode in the 2M pixel row.

[0141] In an exemplary embodiment, the orthographic projection of the spacer pillar located between the anode in the 2M-1 pixel row and the anode in the 2M pixel row onto the substrate at least partially overlaps with the orthographic projection of the light-emitting control line in the M cell row onto the substrate.

[0142] Figure 8a This is a schematic diagram of a planar structure of a sub-pixel, illustrating an anode, a pixel opening, and a spacer pillar, as an exemplary embodiment of this disclosure. Figure 8b for Figure 8a A sectional view along the AA direction. (e.g.) Figure 8a and Figure 8bAs shown, on a plane parallel to the display substrate, the display substrate may include at least a plurality of pixel light-emitting areas PA and a pixel spacing area PK located between adjacent pixel light-emitting areas PA.

[0143] In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 20 disposed on a substrate 10 and a light-emitting structure layer 30 disposed on the side of the driving circuit layer 20 away from the substrate. The light-emitting structure layer 30 may include at least an anode 31, a pixel definition layer 32, and at least one spacer pillar 50. The anode 31 may be disposed on the side of the driving circuit layer 20 away from the substrate 10, and the pixel definition layer 32 may be disposed on the side of the anode 31 away from the substrate 10. The pixel definition layer 32 may have a pixel opening 71 and a spacing opening 72. The pixel opening 71 exposes the surface of the anode 31 and forms a pixel light-emitting area PA and a pixel spacing area PK located between adjacent pixel light-emitting areas PA. The spacing opening 72 may be disposed in the pixel spacing area PK, and the spacer pillar 50 is disposed within the spacing opening 72. The orthographic projection of the spacer pillar 50 on the substrate is within the range of the orthographic projection of the spacing opening 72 on the substrate.

[0144] In an exemplary embodiment, the area of ​​the orthographic projection of the spacer post 50 onto the substrate is smaller than the area of ​​the orthographic projection of the spacer opening 72 onto the substrate, and a groove 60 is formed between the spacer post 50 and the spacer opening 72. The groove 60 formed between the spacer post 50 and the spacer opening 72 means that a gap is formed between the outer sidewall of the spacer post 50 and the inner sidewall of the spacer opening 72. The first sidewall 60-1 of the gap is the outer sidewall of the spacer post 50, and the second sidewall 60-2 of the gap is the inner sidewall of the spacer opening 72. The bottom wall 60-3 of the gap connects the first sidewall 60-1 and the second sidewall 60-2, respectively. The distance between the surface of the bottom wall 60-3 and the substrate is not only smaller than the distance between the surface of the spacer post 50 away from the substrate and the substrate, but also smaller than the distance between the surface of the pixel definition layer 32 away from the substrate and the substrate.

[0145] In an exemplary embodiment, on a plane perpendicular to the display substrate, along a direction away from the substrate 10, the lateral distance between the outer sidewall (first sidewall 60-1) of the spacer post 50 and the inner sidewall (second sidewall 60-2) of the spacer opening 72 gradually increases, and the lateral distance is a dimension parallel to the substrate plane.

[0146] In an exemplary embodiment, the width B of the surface of the groove 60 near the substrate can be approximately 1 μm to 2 μm, the surface of the groove 60 near the substrate can be a bottom wall 60-3, and the width B can be a dimension perpendicular to the extension direction of the groove. For example, the width B can be approximately 1.0 μm, or approximately 1.5 μm.

[0147] In an exemplary embodiment, the distance between the surface of the septum post 50 away from the substrate and the substrate is greater than the distance between the surface of the pixel definition layer 32 away from the substrate and the substrate.

[0148] In an exemplary embodiment, in a plane parallel to the substrate, the shape of the pixel opening 71 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse; the shape of the spacing opening 72 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse; and the shape of the spacer post 50 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse.

[0149] In an exemplary embodiment, in a plane perpendicular to the substrate, the cross-sectional shape of the pixel opening 71 can be an inverted trapezoid or a quasi-inverted trapezoid, and the sidewalls of the inverted trapezoid or quasi-inverted trapezoid can be straight, broken, or curved.

[0150] In an exemplary embodiment, in a plane perpendicular to the base, the cross-sectional shape of the spaced openings 72 can be an inverted trapezoid or a quasi-inverted trapezoid, and the sidewalls of the inverted trapezoid or quasi-inverted trapezoid can be straight, broken, or curved.

[0151] In an exemplary embodiment, the cross-sectional shape of the septum post 50 in a plane perpendicular to the base can be a regular trapezoid or a trapezoidal shape, and the sidewalls of the regular trapezoid or trapezoidal shape can be straight, broken, or curved. For example, the cross-sectional shape of the septum post 50 can be a circular crown shape or a semi-circular shape.

[0152] In an exemplary embodiment, the shape, size, and position of the spacer post 50 can be designed to position the spacer opening 72 and the spacer post 50 in the pixel spacing region PK as far away from the anode 31 as possible, so that the orthographic projection of the spacer opening 72 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate, or the orthographic projection of the spacer post 50 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate, or the orthographic projection of the groove 60 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate.

[0153] In an exemplary embodiment, at least one anode 31 may include a main body 91 and at least one protrusion 92. The shape of the main body 91 may include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle and ellipse. The shape of the protrusion 92 may be strip-shaped. The first end of the protrusion 92 is connected to the main body 91, and the second end of the protrusion 92 extends away from the main body 91.

[0154] In an exemplary embodiment, the position of the pixel opening 71 corresponds to the position of the main body portion 91 of the anode 31. That the pixel opening 71 exposes the surface of the anode 31 means that the pixel opening 71 exposes the surface of the main body portion 91 of the anode 31.

[0155] In an exemplary embodiment, that the orthographic projection of the spacer opening 72 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate means that the orthographic projection of the spacer opening 72 on the substrate does not overlap with the orthographic projection of the protruding portion 92 of the anode 31 on the substrate. That the orthographic projection of the spacer column 50 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate means that the orthographic projection of the spacer column 50 on the substrate does not overlap with the orthographic projection of the protruding portion 92 of the anode 31 on the substrate. That the orthographic projection of the groove 60 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate means that the orthographic projection of the groove 60 on the substrate does not overlap with the orthographic projection of the protruding portion 92 of the anode 31 on the substrate.

[0156] In an exemplary embodiment, the driving circuit layer 20 may include a plurality of circuit units. At least one circuit unit may include a pixel driving circuit, and the pixel driving circuit may be connected to a plurality of signal lines. In an exemplary embodiment, the plurality of signal lines may at least include a first scanning signal line 21, a second scanning signal line 22, and a light emission control line 23 extending along the horizontal direction. The pixel driving circuit may at least include a storage capacitor and a plurality of transistors. The storage capacitor may at least include a first electrode plate 24, and the plurality of transistors may at least include a third transistor as a driving transistor. The first electrode plate 24 may serve as the gate electrode of the third transistor.

[0157] In an exemplary embodiment, the anode 31 may include a first anode 31A for red sub-pixels, a second anode 31B for blue sub-pixels, and a third anode 31C for green sub-pixels. The first anode 31A, the second anode 31B, and the third anode 31C may each include a main body portion and at least one protruding portion. The shapes of the main body portions of the first anode 31A, the second anode 31B, and the third anode 31C may be different, and the connection positions and shapes of the protruding portions of the first anode 31A, the second anode 31B, and the third anode 31C may be different.

[0158] In an exemplary embodiment, since the circuit units of the driving circuit layer 20 are arranged in alignment and the sub-pixels of the light-emitting circuit layer 30 are arranged in a "pin" shape, the positions and shapes of the circuit units do not correspond to the positions and shapes of the sub-pixels. That is, the position and shape of the pixel driving circuit do not correspond to the position and shape of the connected anode. Two pixel rows of the light-emitting circuit layer 30 correspond to one unit row of the driving circuit layer 20.

[0159] In an exemplary embodiment, in the 2M-1 pixel row, the main body portions of the first anode 31A, the second anode 31B, and the third anode 31C can be located on the side of the M-th unit row away from the M+1 unit row of the light emission control line 23. In the 2M pixel row, the main body portions of the first anode 31A, the second anode 31B, and the third anode 31C can be located on the side of the M-th unit row closer to the M+1 unit row of the light emission control line 23.

[0160] In an exemplary embodiment, the orthographic projections of the main body of the first anode 31A, the main body of the second anode 31B, and the main body of the third anode 31C in the 2M-1 pixel row onto the substrate at least partially overlap with the orthographic projection of the second scan signal line 22 in the M unit row onto the substrate.

[0161] In an exemplary embodiment, the orthographic projections of the main body portion of the first anode 31A, the main body portion of the second anode 31B, and the main body portion of the third anode 31C in the 2M pixel row onto the substrate at least partially overlap with the orthographic projection of the first electrode plate 24 in the M unit row onto the substrate.

[0162] In an exemplary embodiment, the width of the main body portion of the first anode 31A, the main body portion of the second anode 31B, and the main body portion of the third anode 31C can be greater than the width of a circuit unit, and the width is the dimension in the horizontal direction.

[0163] In an exemplary embodiment, the orthographic projection of the anode in the 2M-1 pixel row onto the substrate at least partially overlaps with the orthographic projection of the two pixel driving circuits in the M unit row onto the substrate, and the orthographic projection of the anode in the 2M pixel row onto the substrate at least partially overlaps with the orthographic projection of the two pixel driving circuits in the M unit row onto the substrate.

[0164] In an exemplary embodiment, in the 2M-1 pixel row, the orthographic projection of the main body of the first anode 31A onto the substrate at least partially overlaps not only with the orthographic projection of the pixel driving circuit of the Nth unit column onto the substrate, but also at least partially overlaps with the orthographic projection of the pixel driving circuit of the N+1th unit column onto the substrate. In the 2M pixel row, the orthographic projection of the main body of the second anode 31B onto the substrate at least partially overlaps not only with the orthographic projection of the pixel driving circuit of the Nth unit column onto the substrate, but also at least partially overlaps with the orthographic projection of the pixel driving circuit of the N-1th unit column onto the substrate. The orthographic projection of the main body of the third anode 31C onto the substrate at least partially overlaps not only with the orthographic projection of the pixel driving circuit of the N+1th unit column onto the substrate, but also at least partially overlaps with the orthographic projection of the pixel driving circuit of the N+2th unit column onto the substrate.

[0165] In an exemplary embodiment, the spacer post 50 can be rectangular in shape, and the corners of the rectangle can be chamfered, including two long sides and two short sides that are arranged opposite each other.

[0166] In an exemplary embodiment, the spacer post 50 may include at least a first spacer post 50A with its long side extending along the pixel column direction, a second spacer post 50B with its long side extending along the pixel row direction, and a third spacer post 50C with its long side extending along the inclined direction. The inclined direction has a first angle with the pixel column direction, or the inclined direction has a second angle with the pixel row direction. The first angle and the second angle are greater than 0° and less than 90°.

[0167] In an exemplary embodiment, at least one septum post 50 may be disposed between adjacent anodes 31 such that the orthographic projection of the spacer opening 72 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate, or the orthographic projection of the septum post 50 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate, or the orthographic projection of the groove 60 on the substrate does not overlap with the orthographic projection of the anode 31 on the substrate.

[0168] In an exemplary embodiment, at least one spacer post 50 disposed between adjacent anodes 31 may include any one or more of the following: a first spacer post 50A may be disposed between adjacent anodes 31 in a pixel row, a second spacer post 50B may be disposed between adjacent anodes 31 in a pixel column, and a third spacer post 50C may be disposed between the anodes in the 2M-1 pixel row and the anodes in the 2M pixel row, wherein the anodes in the 2M-1 pixel row and the anodes in the 2M pixel row are adjacent.

[0169] In an exemplary embodiment, the orthographic projection of the third septum post 50C onto the substrate at least partially overlaps with the orthographic projection of the light-emitting control line onto the substrate.

[0170] In an exemplary embodiment, multiple septum columns 50 can form multiple rows of septum columns and multiple columns of septum columns. Multiple septum columns 50 arranged sequentially along the horizontal direction can be referred to as a row of septum columns, and multiple septum columns 50 arranged sequentially along the vertical direction can be referred to as a column of septum columns. Multiple rows of septum columns and multiple columns of septum columns constitute a regularly arranged array of septum columns.

[0171] In an exemplary embodiment, the number of septum pillars in at least one pixel row is greater than the number of anodes. For example, the 2M pixel row includes not only a plurality of first septum pillars 50A, but also a plurality of third septum pillars 50C.

[0172] In an exemplary embodiment, three pixel rows correspond to four spacer pillar rows, meaning that four spacer pillar rows are provided in the area where the three pixel rows are located. For example, in the area where the 2M-2 pixel row, the 2M-1 pixel row, and the 2M pixel row are located, there are two spacer pillar rows including multiple first spacer pillars 50A, one spacer pillar row including multiple second spacer pillars 50B, and one spacer pillar row including multiple third spacer pillars 50C.

[0173] Figure 9a This is a schematic diagram of another planar structure of a sub-pixel, illustrating another structure of the anode, pixel opening, and spacer pillar, as an exemplary embodiment of this disclosure. Figure 9b for Figure 9a A schematic diagram of a planar structure of one anode. Figure 9c for Figure 9a A sectional view along the AA direction. (e.g.) Figures 9a to 9c As shown, a pixel opening 71 can be provided on the pixel definition layer 32 of the pixel light-emitting area. The pixel definition layer within the pixel opening 71 is removed, exposing the surface of the anode 31. At least one spacing opening 72 can be provided on the pixel definition layer 32 of the pixel spacing area. A spacer post 50 is disposed within the spacing opening 72. The orthographic projection of the spacer post 50 on the substrate can be located within the range of the orthographic projection of the spacing opening 72 on the substrate. A ring-shaped groove 60 is formed between the spacer post 50 and the spacing opening 72, surrounding the entire spacer post 50.

[0174] In an exemplary embodiment, the width B of the surface of the groove 60 near the substrate can be approximately 1 μm to 2 μm, and the width B can be a dimension perpendicular to the extension direction of the groove. For example, the width B can be approximately 1.0 μm, or approximately 1.5 μm.

[0175] In an exemplary embodiment, the anode 31 can be disposed on the side of the driving circuit layer 20 away from the substrate. At least one anode 31 can include a main body 91 and at least one protrusion 92. The shape of the main body 91 can include any one or more of the following: triangle, rectangle, pentagon, hexagon, circle, and ellipse. The shape of the protrusion 92 can be strip-shaped. A first end of the protrusion 92 is connected to the main body 91, and a second end of the protrusion 92 extends away from the main body 91 into the pixel spacing region PK. In one exemplary embodiment, the protrusion 92 is configured to connect to the pixel driving circuit of the driving circuit layer 20. In another exemplary embodiment, the protrusion 92 can be configured to block a corresponding transistor to prevent light from affecting the electrical performance of the transistor. In yet another exemplary embodiment, the protrusion 92 can be configured to form a corresponding parasitic capacitance.

[0176] In an exemplary embodiment, the orthographic projection of the spacer opening 72 on the substrate at least partially overlaps with the orthographic projection of the protrusion 92 of the anode 31 on the substrate, and the orthographic projection of the spacer post 50 on the substrate at least partially overlaps with the orthographic projection of the protrusion 92 of the anode 31 on the substrate.

[0177] In an exemplary embodiment, the orthographic projection of the groove 60 on the substrate and the orthographic projection of the protrusion 92 of the anode 31 on the substrate at least partially overlap, forming a connecting overlap area 61.

[0178] In an exemplary embodiment, in the region where the overlapping area 61 is located, the distance between the surface of the bottom wall 60-3 of the groove 60 and the substrate is greater than the distance between the surface of the protrusion 92 of the anode 31 on the side away from the substrate and the substrate, that is, the bottom wall 60-3 of the groove 60 covers the surface of the protrusion 92.

[0179] In an exemplary embodiment, in the region where the overlapping area 61 is located, the protrusion 92 may have a first width L1, and in the region outside the overlapping area 61, the protrusion 92 may have a second width L2. The first width L1 may be smaller than the second width L2, and the first width L1 and the second width L2 may be dimensions extending along the direction of the annular groove 60.

[0180] In an exemplary embodiment, at least one strip-shaped protrusion 92 may include a first protrusion 92-1, a second protrusion 92-2, and a third protrusion 92-3. The first end of the first protrusion 92-1 is connected to the main body 91. The second end of the first protrusion 92-1 extends away from the main body 91 and connects to the first end of the third protrusion 92-3. The second end of the third protrusion 92-3 extends away from the main body 91 and connects to the first end of the second protrusion 92-2. The second end of the second protrusion 92-2 extends away from the main body 91.

[0181] In an exemplary embodiment, the orthographic projection of the second protrusion 92-2 on the substrate at least partially overlaps with the orthographic projection of the spacer post 50 on the substrate. The orthographic projections of the first protrusion 92-1 and the second protrusion 92-2 on the substrate do not overlap with the orthographic projection of the groove 60 on the substrate. The orthographic projection of the third protrusion 92-3 on the substrate at least partially overlaps with the orthographic projection of the groove 60 on the substrate. The third protrusion 92-3 has a first width L1, and the first protrusion 92-1 or the second protrusion 92-2 has a second width L2. Thus, the width of the protrusion in the connecting overlapping area 61 is less than the width of the protrusion in the area outside the connecting overlapping area 61.

[0182] In an exemplary embodiment, the first width L1 may be approximately 1 / 4 to 1 / 20 of the second width L2.

[0183] In an exemplary embodiment, the first width L1 can be approximately 0.5 μm to 2 μm. For example, the first width L1 can be approximately 1 μm.

[0184] In an exemplary embodiment, the second width L2 can be approximately 8 μm to 12 μm. For example, the second width L2 can be approximately 10 μm.

[0185] In other exemplary embodiments, the width of the first protrusion 92-1 may be the same as the width of the third protrusion 92-3, or the width of the second protrusion 92-2 may be the same as the width of the third protrusion 92-3, or the widths of the first protrusion 92-1 and the second protrusion 92-2 may both be the same as the width of the third protrusion 92-3, that is, the protrusion 92 is a structure with an equal width having a first width L1, which is not limited in this disclosure.

[0186] In an exemplary embodiment, in the 2M-1 pixel row, the main body of the plurality of anodes 31 may be located on the side of the light emission control line 23 in the M unit row away from the M+1 unit row. In the 2M pixel row, the main body of the plurality of anodes 31 may be located on the side of the light emission control line 23 in the M unit row closer to the M+1 unit row.

[0187] In an exemplary embodiment, the orthographic projection of the main body of the plurality of anodes 31 in the 2M-1 pixel row onto the substrate at least partially overlaps with the orthographic projection of the second scan signal line 22 in the M unit row onto the substrate.

[0188] In an exemplary embodiment, the orthographic projection of the main body of the plurality of anodes 31 in the 2M pixel row onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate 24 in the M unit row onto the substrate.

[0189] In an exemplary embodiment, the width of the main body of at least one anode 31 may be greater than the width of a circuit unit. In the 2M-1 pixel row, the orthographic projection of the main body of at least one anode 31 on the substrate at least partially overlaps with the orthographic projection of the pixel driving circuits of the two unit columns on the substrate.

[0190] In an exemplary embodiment, at least one spacer post 50 may be disposed between adjacent anodes 31, including any one or more of the following: spacer posts 50 may be disposed between adjacent anodes 31 in a pixel row, or spacer posts 50 may be disposed between adjacent anodes 31 in a pixel column.

[0191] Figure 10a This is a schematic diagram of another sub-pixel planar structure according to an exemplary embodiment of the present disclosure, illustrating another positional relationship between the anode, pixel opening, and spacer pillar. Figure 10b for Figure 10a A schematic diagram of a planar structure of one anode. Figure 10c for Figure 10a A cross-sectional view along the AA direction. The structure of the pixel definition layer and the spacer pillar in this exemplary embodiment is substantially the same as that in the previous embodiment, except that the orthographic projection of the spacer pillar 50 on the substrate at least partially overlaps with the orthographic projection of the protrusion 92 of the anode 31 on the substrate, but the orthographic projection of the groove 60 on the substrate does not overlap with the orthographic projection of the protrusion 92 of the anode 31 on the substrate.

[0192] like Figures 10a to 10c As shown, in an exemplary embodiment, the protrusion 92 may include a first protrusion 92-1 and a second protrusion 92-2 spaced apart. The first end of the first protrusion 92-1 is connected to the main body 91, and the second end of the first protrusion 92-1 extends away from the main body 91. The first end of the second protrusion 92-2 is located on the side of the first protrusion 92-1 away from the main body 91, and the second end of the second protrusion 92-2 extends away from the main body 91. The orthographic projection of the second protrusion 92-2 on the substrate at least partially overlaps with the orthographic projection of the spacer post 50 on the substrate, while the orthographic projections of the first protrusion 92-1 and the second protrusion 92-2 on the substrate do not overlap with the orthographic projection of the groove 60 on the substrate.

[0193] In an exemplary embodiment, a connection electrode 25 is provided in the driving circuit layer 20, and the orthographic projection of the connection electrode 25 on the substrate at least partially overlaps with the orthographic projection of the groove 60 on the substrate. The second end of the first protrusion 92-1 is connected to the first end of the connection electrode 25 through a via, and the first end of the second protrusion 92-2 is connected to the second end of the connection electrode 25 through a via. In this way, not only is the mutual connection of the first protrusion 92-1 and the second protrusion 92-2 through the connection electrode 25 achieved, but also the orthographic projection of the protrusion 92 on the substrate does not overlap with the orthographic projection of the groove 60 on the substrate.

[0194] Figure 11a This is a schematic diagram of another sub-pixel planar structure according to an exemplary embodiment of the present disclosure, illustrating another positional relationship between the anode, pixel opening, and spacer pillar. Figure 11b for Figure 11a A schematic diagram of a planar structure of one anode. Figure 11c for Figure 11a A cross-sectional view along the AA direction. The structure of the pixel definition layer and the spacer pillar in this exemplary embodiment is basically the same as that in the previous embodiment, except that the groove 60 formed between the spacer pillar 50 and the spacer opening 72 does not surround the entire spacer pillar 50, and no groove 60 is provided between the spacer pillar 50 and the pixel definition layer 32 in the area where the protrusion 92 of the anode 31 is located.

[0195] like Figures 11a to 11cAs shown, in an exemplary embodiment, the protrusion 92 can be a strip of equal width. The first end of the protrusion 92 is connected to the main body 91, and the second end of the protrusion 92 extends in a direction away from the main body 91 to the area where the septum post 50 is located, such that the orthographic projection of the protrusion 92 of the anode 31 on the substrate at least partially overlaps with the orthographic projection of the septum post 50 on the substrate.

[0196] In an exemplary embodiment, the groove 60 may be C-shaped, surrounding the spacer post 50 and located outside the area of ​​the protrusion 92. In the area outside the protrusion 92, the groove 60 formed between the spacer post 50 and the spacing opening 72 is not formed between the spacer post 50 and the pixel definition layer 32 within the area of ​​the protrusion 92. Therefore, the orthographic projection of the protrusion 92 on the substrate and the orthographic projection of the groove 60 on the substrate do not overlap.

[0197] In one exemplary embodiment, the protrusion 92 can be a conventional structure with a second width, which can be approximately 8 μm to 12 μm.

[0198] In another exemplary embodiment, the width of the protrusion 92 may be an integrally narrowed structure with a first width, and the width of the protrusion 92 may be approximately 0.5 μm to 2 μm.

[0199] Figure 12a This is a schematic diagram of another sub-pixel planar structure according to an exemplary embodiment of the present disclosure, illustrating another positional relationship between the anode, pixel opening, and spacer pillar. Figure 12b for Figure 12a A schematic diagram of the planar structure of the central anode. Figure 12c for Figure 12a A cross-sectional view along the AA direction. The structure of the pixel definition layer and the septum pillar in this exemplary embodiment is basically the same as that in the previous embodiment, except that a ring-shaped groove 60 is formed between the septum pillar 50 and the spacer opening 72, surrounding the entire septum pillar 50. The orthographic projection of the groove 60 on the substrate and the orthographic projection of the protrusion 92 of the anode 31 on the substrate at least partially overlap, forming a connecting overlap area 61. The protrusion 92 in the area where the connecting overlap area 61 is located has a rougher surface.

[0200] like Figures 12a to 12c As shown, in an exemplary embodiment, the protrusion 92 can be a strip of equal width. The first end of the protrusion 92 is connected to the main body 91, and the second end of the protrusion 92 extends in a direction away from the main body 91 to the area where the septum post 50 is located, such that the orthographic projection of the protrusion 92 of the anode 31 on the substrate at least partially overlaps with the orthographic projection of the septum post 50 on the substrate.

[0201] In an exemplary embodiment, the protrusion 92 includes at least one rough surface region 93, which can be formed by ion bombardment of the surface of the protrusion 92. The surface of the region where the rough surface region 93 is located has a first roughness, and the surface of the region outside the rough surface region 93 has a second roughness. The first roughness can be greater than the second roughness.

[0202] In an exemplary embodiment, the orthographic projection of the rough surface region 93 on the substrate at least partially overlaps with the orthographic projection of the groove 60 on the substrate.

[0203] In one exemplary embodiment, the protrusion 92 can be a conventional structure with a second width, which can be approximately 8 μm to 12 μm.

[0204] In another exemplary embodiment, the width of the protrusion 92 may be an integrally narrowed structure with a first width, and the width of the protrusion 92 may be approximately 0.5 μm to 2 μm.

[0205] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0206] In an exemplary embodiment, taking three sub-pixels of a display substrate as an example, the fabrication process of the display substrate may include the following operations.

[0207] (1) Forming a driving circuit layer pattern. In an exemplary embodiment, forming a driving circuit layer pattern may include:

[0208] A first insulating film and a semiconductor film are sequentially deposited on a substrate. The semiconductor film is patterned using a patterning process to form a first insulating layer covering the entire substrate, and a semiconductor layer pattern disposed on the first insulating layer. The semiconductor layer pattern includes at least an active layer located in each sub-pixel.

[0209] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned using a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first metal layer pattern disposed on the second insulating layer. The first metal layer pattern includes at least a gate electrode and a first electrode plate located in each sub-pixel.

[0210] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer covering the first metal layer, and a second metal layer pattern disposed on the third insulating layer. The second metal layer pattern includes at least a second electrode plate located in each sub-pixel, and the orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first electrode plate on the substrate.

[0211] Subsequently, a fourth insulating film is deposited, and a pattern of the fourth insulating layer covering the second metal layer is formed by a patterning process. Multiple first vias are formed on the fourth insulating layer. The fourth, third, and second insulating layers within the first vias are etched away, exposing the two ends of the active layer.

[0212] Subsequently, a third metal thin film is deposited and patterned using a patterning process to form a third metal layer pattern on the fourth insulating layer. The third metal layer pattern includes at least a first pole and a second level located in each sub-pixel. The first pole and the second level are respectively connected to the active layer through a first via.

[0213] Subsequently, a planarization film is coated and patterned using a patterning process to form a planarization layer covering the third metal layer. A second via is formed on the planarization layer, and the planarization film inside the second via is etched away to expose the second level in each sub-pixel.

[0214] At this point, the pattern of the driving circuit layer 20 is complete on the substrate 10, as follows: Figure 13 As shown. In an exemplary embodiment, the driving circuit layer 20 for each sub-pixel may include a plurality of transistors and storage capacitors constituting the pixel driving circuit. Figure 13The example shown uses a pixel driving circuit comprising a transistor 20A and a storage capacitor 20B. In an exemplary embodiment, transistor 20A may include an active layer, a gate electrode, a first electrode, and a second electrode, and storage capacitor 20B may include a first electrode plate and a second electrode plate.

[0215] In exemplary embodiments, the substrate can be a rigid substrate, which can be made of materials such as glass or quartz. In some possible embodiments, the substrate can be a flexible substrate, or it can be a silicon wafer. The flexible substrate can be made of materials such as polyimide (PI) or polyethylene terephthalate (PET). The flexible substrate can be a single-layer structure, or it can be a laminated structure composed of inorganic material layers and flexible material layers. This disclosure does not limit the scope of the invention.

[0216] In an exemplary embodiment, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, used to improve the substrate's resistance to water and oxygen. The second and third insulating layers are called gate insulating (GI) layers, and the fourth insulating layer is called an interlayer insulating (ILD) layer. The planarization layer can be made of organic materials, such as resin. The first, second, and third metal layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The semiconductor layer can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0217] In an exemplary embodiment, the driving circuit layer 20 may also include structures such as power lines, connecting electrodes, and a fifth insulating layer (PVX), which are not limited herein.

[0218] (2) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, patterning the anode conductive film using a patterning process to form an anode conductive layer pattern, wherein the anode conductive layer pattern includes at least an anode 31 located in each sub-pixel, and the anode 31 is connected to the second stage of the transistor through a second via, such as... Figure 14a and Figure 14bAs shown, Figure 14b for Figure 14a A plan view of region C in the middle.

[0219] In an exemplary embodiment, the anode conductive layer can be made of a metallic material or a transparent conductive material. The metallic material can include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals. The transparent conductive material can include indium tin oxide (ITO) or indium zinc oxide (IZO). In an exemplary embodiment, the anode conductive layer can be a single-layer structure or a multi-layer composite structure, such as ITO / Al / ITO.

[0220] In an exemplary embodiment, at least one anode 31 may include an interconnected main body 91 and at least one protrusion 92. The shape of the main body 91 may include any one or more of the following: triangular, rectangular, rhomboid, pentagonal, and hexagonal. The protrusion 92 may be strip-shaped. A first end of the protrusion 92 is connected to the main body 91, and a second end of the protrusion 92 extends away from the main body 91. The protrusion 92 may be configured to connect to the second stage of the transistor 20A in the pixel driving circuit through a second via. In one exemplary embodiment, the protrusion 92 may be configured to block the corresponding transistor to prevent light from affecting the electrical performance of the transistor. In another exemplary embodiment, the protrusion 92 may be configured to form a corresponding parasitic capacitance.

[0221] In an exemplary embodiment, the strip-shaped protrusion 92 may include a first protrusion 92-1, a second protrusion 92-2, and a third protrusion 92-3. The first end of the first protrusion 92-1 is connected to the main body 91. The second end of the first protrusion 92-1 extends away from the main body 91 and connects to the first end of the third protrusion 92-3. The second end of the third protrusion 92-3 extends away from the main body 91 and connects to the first end of the second protrusion 92-2. The second end of the second protrusion 92-2 extends away from the main body 91.

[0222] In an exemplary embodiment, the third protrusion 92-3 has a first width L1, and the first protrusion 92-1 or the second protrusion 92-2 has a second width L2. The first width L1 may be smaller than the second width L2.

[0223] In an exemplary embodiment, the first width L1 may be approximately 1 / 4 to 1 / 20 of the second width L2.

[0224] In an exemplary embodiment, the first width L1 can be approximately 0.5 μm to 2 μm, and the second width L2 can be approximately 8 μm to 12 μm. For example, the first width L1 can be approximately 1 μm, and the second width L2 can be approximately 10 μm.

[0225] In an exemplary embodiment, the position of the third protrusion 92-3 corresponds to the position of the subsequently formed groove, that is, the orthographic projection of the third protrusion 92-3 on the substrate and the orthographic projection of the subsequently formed groove on the substrate at least partially overlap. The third protrusion 92-3 is configured to reduce the reflection of the protrusion on the exposed light and weaken the exposure degree of the pixel definition film in the area where the groove is located.

[0226] (3) Forming the pixel definition layer and spacer pillar pattern. In an exemplary embodiment, forming the pixel definition layer and spacer pillar pattern may include: coating a pixel definition film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition film using a halftone mask patterning process to form the pixel definition layer 32 and spacer pillar 50 pattern, such as... Figure 15a and Figure 15b As shown, Figure 15b for Figure 15a A plan view of region C in the middle.

[0227] In an exemplary embodiment, the pixel definition layer 32 pattern may include a plurality of pixel openings 71 and spacer openings 72 located between adjacent pixel openings 71. The entire thickness of the pixel definition layer within the pixel openings 71 is removed, exposing the surface of the anode 31. A portion of the pixel definition layer within the spacer openings 72 located between adjacent pixel openings 71 is removed, leaving a portion of the pixel definition layer intact.

[0228] In an exemplary embodiment, the septum post 50 is disposed within the spacer opening 72, and the orthographic projection of the septum post 50 on the substrate can be located within the range of the orthographic projection of the spacer opening 72 on the substrate. A ring-shaped groove 60 is formed between the septum post 50 and the sidewall of the spacer opening 72, surrounding the septum post 50.

[0229] In an exemplary embodiment, the height of the septum post 50 is greater than the height of the pixel definition layer 32, that is, the distance between the surface of the septum post 50 away from the substrate and the substrate is greater than the distance between the surface of the pixel definition layer 32 away from the substrate and the substrate.

[0230] In an exemplary embodiment, the orthographic projection of the groove 60 on the substrate at least partially overlaps with the orthographic projection of the third protrusion 92-3 on the substrate, forming a connecting overlapping area, while the orthographic projections of the first protrusion 92-1 and the second protrusion 92-2 on the substrate do not overlap with the orthographic projection of the groove 60 on the substrate.

[0231] In an exemplary embodiment, in the region where the overlapping area is located, the distance between the surface of the bottom wall of the groove 60 and the substrate is greater than the distance between the surface of the third protrusion 92-3 on the side away from the substrate and the substrate. The bottom wall of the groove 60 covers the third protrusion 92-3, that is, the third protrusion 92-3 is not exposed in the groove 60.

[0232] In an exemplary embodiment, the width of the groove 60 can be approximately 1 μm to 2 μm, and the width can be a dimension perpendicular to the extension direction of the groove. For example, the width of the groove 60 can be approximately 1.0 μm, or the width of the groove 60 can be approximately 1.5 μm.

[0233] Figure 16 This is a schematic diagram illustrating an exposure method as an exemplary embodiment of this disclosure. Figure 16 As shown, in an exemplary embodiment, the halftone mask 100 used for exposure may include at least an unexposed area 101, a partially exposed area 102, and a fully exposed area 103. This exposure method can be referred to as HPDL Mask exposure. The unexposed area 101 does not transmit exposure light, thus preventing the corresponding pixel definition film from being exposed. The partially exposed area 102 transmits some exposure light, exposing a portion of the thickness of the corresponding pixel definition film. The fully exposed area 103 transmits all exposure light, completely exposing the corresponding pixel definition film.

[0234] In an exemplary embodiment, the unexposed area 101 corresponds to the area where the spacer post 50 is located, the partially exposed area 102 corresponds to the area where the pixel definition layer 32 is located, and the fully exposed area 103 corresponds to the area where the pixel opening 71 and the groove 60 are located.

[0235] In an exemplary embodiment, after the pixel definition film corresponding to the unexposed area 101 is developed and cured, the entire thickness of the pixel definition film is retained to form the septum post 50 pattern.

[0236] In an exemplary embodiment, after the pixel definition film corresponding to the partial exposure area 102 is developed and cured, a portion of the pixel definition film thickness is retained to form a pixel definition layer 32 pattern.

[0237] In an exemplary embodiment, the pixel definition film corresponding to the fully exposed area 103 may include a strong exposure area and a weak exposure area. For the area where the orthographic projection of the fully exposed area 103 onto the substrate overlaps with the orthographic projection of the main body 91 in the anode 31 onto the substrate, the reflection of the exposed light by the main body 91 intensifies the exposure in this area, thus making it a strong exposure area. After development and curing, the pixel definition film in this area is completely removed, forming a pixel opening 71 pattern, which exposes the surface of the main body 91. For the area where the orthographic projection of the fully exposed area 103 onto the substrate overlaps with the orthographic projection of the third protrusion 92-3 in the anode 31 onto the substrate, the width of the third protrusion 92-3 is small, resulting in less reflection of the exposed light. Therefore, this area is a weak exposure area. After development and curing, this area retains a portion of the pixel definition film thickness, and the bottom wall of the formed groove 60 covers the third protrusion 92-3, meaning the third protrusion 92-3 is not exposed within the groove 60.

[0238] Figure 17 This is a schematic diagram illustrating another exposure method of an exemplary embodiment of this disclosure. For example... Figure 17 As shown, the grayscale mask 200 used for exposure may include at least a non-exposed area 201, a first partially exposed area 102, a second partially exposed area 203, and a fully exposed area 204. The non-exposed area 201 does not transmit exposure light, thus preventing the corresponding pixel definition film from being exposed. The first partially exposed area 202 transmits approximately half of the exposure light, exposing approximately half the thickness of the corresponding pixel definition film. The second partially exposed area 203 transmits approximately three-quarters of the exposure light, exposing approximately three-quarters of the thickness of the corresponding pixel definition film. The fully exposed area 204 transmits all the exposure light, fully exposing the corresponding pixel definition film.

[0239] In an exemplary embodiment, the unexposed area 201 may correspond to the area where the septum post 50 is located, forming a septum post 50 pattern. The first partially exposed area 202 may correspond to the area where the pixel definition layer 32 is located, forming a pixel definition layer 32 pattern. The second partially exposed area 203 may correspond to the area where the groove 60 is located, forming a groove 60 pattern, the bottom wall of the groove 60 covering the third protrusion 92-3. The fully exposed area 204 may correspond to the area where the pixel opening 71 is located, forming a pixel opening 71 pattern, the pixel opening 71 exposing the surface of the anode body portion.

[0240] In an exemplary embodiment, by setting four exposure areas on a gray-toned mask, the thickness of the bottom wall of the groove can be ensured, so that even if the width of the protrusion is wide, the bottom wall of the groove can cover the protrusion of the anode.

[0241] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acrylic or polyethylene terephthalate, etc., and this disclosure does not limit it.

[0242] Subsequent fabrication processes may include forming an organic light-emitting layer and a cathode pattern, as well as forming an encapsulation structure, which will not be elaborated here.

[0243] In one type of display substrate, the pixel definition layer and spacer pillars are formed separately through two patterning processes. First, the pixel definition layer is formed through a patterning process, and then the spacer pillars are formed on the pixel definition layer through a second patterning process. In order to shorten the process time and reduce the number of masks, in another type of display substrate, the pixel definition layer and spacer pillars are formed simultaneously through a single patterning process using a halftone mask. Figure 18a This is a schematic diagram of a pixel definition layer and septum pillar exposure method in the prior art. Figure 18b This is a cross-sectional schematic diagram of a pixel definition layer and spacer pillars in the prior art. The halftone mask 100 used for exposure includes a non-exposed area 101, a partially exposed area 102, and a fully exposed area 103. The non-exposed area 101 corresponds to the area where the spacer pillars 50 are located, the partially exposed area 102 corresponds to the area where the pixel definition layer 32 is located, and the fully exposed area 103 corresponds to the area where the pixel opening 71 is located. The inventors of this application have discovered that due to the fluidity of the pixel definition film, the pixel definition layer and spacer pillars have no clear boundary after curing, resulting in poor morphology and a low overall height. The low height of the spacer pillars not only leads to poor support but also causes defects such as Newton's rings.

[0244] The display substrate provided by the exemplary embodiments of this disclosure, by adjusting the position of the fully exposed area in the halftone mask, forms a groove around the spacer pillar. The groove can prevent the flow of the pixel definition film in the subsequent baking process. Combined with process exposure control, the cured pixel definition layer and spacer pillar are clearly defined, have good morphology, and have a high overall height. The height of the spacer pillar meets the requirements, which not only improves the support effect, but also avoids defects such as Newton's rings, thereby improving product quality and display quality.

[0245] Figure 19 This is a schematic diagram illustrating a light leakage problem in a display substrate. In an exemplary embodiment, Figure 19 The intermediate anode can be adopted Figure 11bAs shown in the structure, the anode 31 may include a main body 91 and a protrusion 92, the strip-shaped protrusion 92 being designed with a uniform width. The orthographic projection of the groove 60 onto the substrate and the orthographic projection of the protrusion 92 in the anode 31 onto the substrate form a connecting overlap area. The inventors of this application have discovered that because the protrusion 92 in the connecting overlap area is wider, the reflection of exposure light by the protrusion 92 intensifies the exposure level of the connecting overlap area. The higher exposure level of the pixel definition film in the connecting overlap area leads to the complete removal of the pixel definition film, exposing the surface of the protrusion 92. Since the subsequently formed organic light-emitting layer is connected to the protrusion 92, light leakage occurs due to light emitted from the connecting overlap area.

[0246] The exemplary embodiment of this disclosure provides a display substrate in which the shape and position of the spacer pillars are designed so that the orthographic projection of the groove on the substrate does not overlap with the orthographic projection of the anode protrusion on the substrate, effectively avoiding the exposure of the protrusion surface and effectively avoiding light leakage problems.

[0247] The alternative display substrate provided in the exemplary embodiments of this disclosure, when the orthographic projection of the groove on the substrate overlaps with the orthographic projection of the anode protrusion on the substrate, by specifically designing the anode protrusion, reduces the width of part of the protrusion, reduces the area of ​​the overlapping region, reduces the reflection of the protrusion on the exposure light, effectively weakens the exposure degree of the pixel definition film in the overlapping region, ensures that the bottom wall of the groove can cover the protrusion, avoids light emitted from the overlapping region, eliminates the light leakage problem, and improves the display quality.

[0248] In another display substrate provided by the exemplary embodiments of this disclosure, when the orthographic projection of the groove on the substrate overlaps with the orthographic projection of the anode protrusion on the substrate, the protrusion of the anode is isolated by designing a separation, and the isolated protrusion is connected by a connection electrode provided in the driving circuit layer, so that the orthographic projection of the groove on the substrate and the orthographic projection of the anode protrusion on the substrate do not overlap, effectively avoiding the situation of exposing the surface of the protrusion and effectively avoiding the problem of light leakage.

[0249] In another display substrate provided by the exemplary embodiments of this disclosure, when the orthographic projection of the spacer pillar on the substrate overlaps with the orthographic projection of the anode protrusion on the substrate, the groove is removed in the overlapping area. That is, the groove is formed in the area other than the protrusion, while no groove is formed in the area where the protrusion is located. This ensures that the orthographic projection of the groove on the substrate does not overlap with the orthographic projection of the anode protrusion on the substrate, effectively avoiding the situation where the surface of the protrusion is exposed, and effectively avoiding the problem of light leakage.

[0250] In another display substrate provided by the exemplary embodiments of this disclosure, when the orthographic projection of the groove on the substrate overlaps with the orthographic projection of the anode protrusion on the substrate, the surface of the protrusion is roughened to form diffuse reflection, which can effectively reduce the exposure of the pixel definition film in the overlapping area. This ensures that the bottom wall of the groove can cover the protrusion, avoids light emanating from the overlapping area, eliminates light leakage, and improves display quality.

[0251] As can be seen from the above description of the display substrate structure and fabrication process, this disclosure ensures the height and morphology of the spacer pillars by forming grooves around them, which not only improves the support effect but also avoids defects such as Newton's rings. This disclosure effectively avoids light leakage problems and improves display quality by preventing the grooves from overlapping with the anode protrusions, reducing the overlap area, or weakening the exposure of the pixel-defining film connecting the overlapping areas. The fabrication method of this disclosure requires minimal process modifications, has high compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0252] This disclosure also provides a method for fabricating a display substrate. In an exemplary embodiment, the display substrate includes a plurality of pixel light-emitting regions and a plurality of pixel spacing regions located between adjacent pixel light-emitting regions; the fabrication method may include:

[0253] A light-emitting structure layer is formed on a substrate. The light-emitting structure layer includes at least an anode, a pixel definition layer, and at least one spacer pillar. The pixel definition layer has a pixel opening in the pixel light-emitting area, and the pixel opening exposes the anode. The pixel definition layer has a spacing opening in the pixel spacing area, and the spacer pillar is disposed within the spacing opening. The orthographic projection of the spacer pillar on the substrate is located within the range of the orthographic projection of the spacing opening on the substrate.

[0254] This disclosure also provides a display device, including the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, navigator, in-vehicle display, smartwatch, or smart bracelet.

[0255] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope of this disclosure; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate comprising a plurality of pixel light-emitting regions and a plurality of pixel spacing regions located between adjacent pixel light-emitting regions; in a plane perpendicular to the display substrate, the display substrate includes a substrate and a light-emitting structure layer disposed on the substrate, the light-emitting structure layer including at least an anode, a pixel definition layer and at least one spacer pillar, the pixel definition layer having a pixel opening in the pixel light-emitting region, the pixel opening exposing the anode, the pixel definition layer having a spacing opening in the pixel spacing region, the spacer pillar being disposed within the spacing opening, a groove being provided between the sidewall of the spacer pillar and the sidewall of the spacing opening; a portion of the pixel definition layer thickness within the spacing opening is removed, the distance between the surface of the region where the groove is located in the spacing opening and the substrate is less than the distance between the surface of the pixel definition layer and the substrate on the side away from the substrate, and the orthographic projection of the spacer pillar on the substrate is within the range of the orthographic projection of the spacing opening on the substrate.

2. The display substrate according to claim 1, wherein, Along a direction away from the substrate, the lateral distance between the sidewall of the septum post and the sidewall of the spacer opening gradually increases, and the lateral distance is a dimension in a plane parallel to the display substrate.

3. The display substrate according to claim 1, wherein, At least one anode includes a body portion and at least one protrusion, the pixel opening exposes the body portion of the anode, and the orthographic projection of the groove on the substrate does not overlap with the orthographic projection of the protrusion of the anode on the substrate.

4. The display substrate according to claim 3, wherein, The display substrate further includes a driving circuit layer disposed on the substrate. The protrusion includes at least a first protrusion and a second protrusion. The driving circuit layer is provided with a connection electrode. A first end of the first protrusion is connected to the main body. A second end of the first protrusion is connected to the first end of the connection electrode through a via. A first end of the second protrusion is connected to the second end of the connection electrode through a via. The second end of the second protrusion extends in a direction away from the main body. The orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projection of the spacer post on the substrate. The orthographic projection of the connection electrode on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate.

5. The display substrate according to claim 3, wherein, The orthographic projection of the protrusion on the substrate at least partially overlaps with the orthographic projection of the septum post on the substrate, and the groove is C-shaped and is located in the area outside the protrusion.

6. The display substrate according to claim 1, wherein, At least one anode includes a main body and at least one protrusion, the pixel opening exposes the main body of the anode, the groove is an annular groove surrounding the septum post, the orthographic projection of the groove on the substrate at least partially overlaps with the orthographic projection of the protrusion of the anode on the substrate, forming a connecting overlap area; in the connecting overlap area, the distance between the surface of the groove near the substrate and the substrate is greater than the distance between the surface of the anode away from the substrate and the substrate.

7. The display substrate according to claim 6, wherein, In the overlapping area, the protrusion has a first width, and in the area outside the overlapping area, the protrusion has a second width. The first width is smaller than the second width, and the first width and the second width are dimensions along the extension direction of the groove.

8. The display substrate according to claim 7, wherein, The protrusion includes at least a first protrusion, a second protrusion, and a third protrusion. A first end of the first protrusion is connected to the main body. A second end of the first protrusion is connected to the first end of the third protrusion. The second end of the third protrusion extends away from the main body and then connects to the first end of the second protrusion. The second end of the second protrusion extends away from the main body. The orthographic projection of the second protrusion on the substrate at least partially overlaps with the orthographic projection of the spacer post on the substrate. The orthographic projection of the third protrusion on the substrate at least partially overlaps with the orthographic projection of the groove on the substrate. The third protrusion has the first width, and either the first or second protrusion has the second width.

9. The display substrate according to claim 7, wherein, The first width is 0.5 μm to 2 μm, and the second width is 8 μm to 12 μm.

10. The display substrate according to claim 6, wherein, The width of the surface of the groove near the substrate is 0.5 μm to 5.0 μm, and the width is the dimension perpendicular to the extension direction of the groove.

11. The display substrate according to claim 6, wherein, The surface of the protrusion in the overlapping region has a first roughness, and the surface of the protrusion in the region outside the overlapping region has a second roughness, wherein the first roughness is greater than the second roughness.

12. The display substrate according to claim 1, wherein, The spacer pillars and the pixel definition layer are made of the same material and are formed synchronously through the same patterning process.

13. The display substrate according to any one of claims 1 to 12, wherein, The display substrate further includes a driving circuit layer disposed on the substrate, and the light-emitting structure layer is disposed on the side of the driving circuit layer away from the substrate; the driving circuit layer includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, the plurality of circuit units being aligned on the unit rows and the plurality of circuit units being aligned on the unit columns; the light-emitting structure layer includes a plurality of sub-pixels constituting a plurality of pixel rows and a plurality of pixel columns, the plurality of sub-pixels being aligned on the pixel rows and the plurality of sub-pixels being staggered on the pixel columns.

14. The display substrate according to claim 13, wherein, At least one circuit unit includes a pixel driving circuit, which is connected to a first scan signal line, a second scan signal line, and a light emission control line, respectively. The pixel driving circuit includes at least a storage capacitor. In the Mth unit row, the first scan signal line is located on the side of the storage capacitor closer to the (M+1)th unit row, the second scan signal line is located on the side of the storage capacitor away from the (M+1)th unit row, and the light emission control line is located between the storage capacitor and the second scan signal line. At least one sub-pixel includes an anode connected to the pixel driving circuit. In the 2M-1th pixel row, the anode is located on the side of the light emission control line in the Mth unit row away from the (M+1)th unit row, and the anode in the 2Mth pixel row is located on the side of the light emission control line in the Mth unit row closer to the (M+1)th unit row, where 1 ≤ M ≤ K, and K is the row number of the unit row.

15. The display substrate according to claim 14, wherein, The orthographic projection of the anode in the 2M-1 pixel row onto the substrate at least partially overlaps with the orthographic projection of the second scan signal line in the M-th cell row onto the substrate, and the orthographic projection of the anode in the 2M pixel row onto the substrate at least partially overlaps with the orthographic projection of the storage capacitor onto the substrate.

16. The display substrate according to claim 14, wherein, The orthographic projection of the anode in the 2M-1 pixel row onto the substrate at least partially overlaps with the orthographic projection of the two pixel driving circuits in the M unit row onto the substrate.

17. The display substrate according to claim 14, wherein, At least one spacer post is located between adjacent anodes, including any one or more of the following: at least one spacer post is located between adjacent anodes in a pixel row, at least one spacer post is located between adjacent anodes in a pixel column, and at least one spacer post is located between an anode in the 2M-1 pixel row and an anode in the 2M pixel row.

18. The display substrate according to claim 14, wherein, The spacer post is rectangular in shape, including a long side and a short side. The spacer post includes at least a first spacer post whose long side extends along the pixel column direction, a second spacer post whose long side extends along the pixel row direction, and a third spacer post whose long side extends along an inclined direction. The inclined direction has a first angle with the pixel column direction, or the inclined direction has a second angle with the pixel row direction. The first angle and the second angle are greater than 0° and less than 90°.

19. The display substrate according to claim 18, wherein, The first spacer post is disposed between adjacent anodes in a pixel row, the second spacer post is disposed between adjacent anodes in a pixel column, and the third spacer post is disposed between the anodes in the 2M-1 pixel row and the anodes in the 2M pixel row.

20. The display substrate according to claim 18, wherein, The orthographic projection of the third septum column on the substrate at least partially overlaps with the orthographic projection of the light-emitting control line on the substrate.

21. The display substrate according to claim 13, wherein, Multiple septum bars form multiple rows of septum bars and multiple columns of septum bars, with three pixel rows corresponding to four rows of septum bars.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

23. A method for fabricating a display substrate, the display substrate comprising a plurality of pixel light-emitting regions and a plurality of pixel spacing regions located between adjacent pixel light-emitting regions; the fabrication method comprising: A light-emitting structure layer is formed on a substrate. The light-emitting structure layer includes at least an anode, a pixel definition layer, and at least one spacer pillar. The pixel definition layer has a pixel opening in the pixel light-emitting area, which exposes the anode. The pixel definition layer also has a spacing opening in the pixel spacing area. The spacer pillar is disposed within the spacing opening, and a groove is formed between the sidewall of the spacer pillar and the sidewall of the spacing opening. A portion of the pixel definition layer within the spacing opening is removed. The distance between the surface of the region where the groove is located in the spacing opening and the substrate is less than the distance between the surface of the pixel definition layer and the substrate. The orthographic projection of the spacer pillar on the substrate is within the range of the orthographic projection of the spacing opening on the substrate.

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