Display panel and display device

Abstract

The present application discloses a display panel and a display device, wherein the display panel includes a display area and a non-display area surrounding at least part of the display area, and the display panel includes: a substrate; a gate driving circuit and an electrostatic discharge protection circuit, which are arranged on one side of the substrate and located in the non-display area; the gate driving circuit includes a plurality of gate driving units; the electrostatic discharge protection circuit includes a plurality of electrostatic discharge protection units, and the arrangement tracks of the orthographic projections of the plurality of gate driving units on the substrate overlap with the arrangement tracks of the orthographic projections of the plurality of electrostatic release protection units on the substrate at least in part, and the arrangement tracks of the orthographic projections of the plurality of gate driving units on the substrate and the arrangement tracks of the orthographic projections of the plurality of electrostatic release protection units on the substrate extend along the extension direction of the side of the display area. The present application can avoid the electrostatic discharge protection circuit from occupying the layout space of the non-display area extra, thereby effectively compressing the space and meeting the requirement of a narrow frame of the display panel.

Description

Technical Field

[0001] The present application relates to the technical field of display equipment, and in particular to a display panel and a display device. Background Art

[0002] Display devices in various fields such as smart watches and vehicle dashboards have attracted widespread attention. The display panels of such display devices usually have a circular structure, and both the circular display area (AA area) and the non-display area (non-AA area) are configured in a circular shape.

[0003] The current electrostatic discharge protection circuit needs to occupy a large wiring space, resulting in an increase in the size of the non-display area, which cannot meet the requirement of a narrow frame of the display panel. Summary of the invention

[0004] The main technical problem solved by the present application is to provide a display panel and a display device, which can solve the problem that the electrostatic discharge protection circuit occupies a large wiring space.

[0005] In order to solve the above-mentioned technical problems, the first technical solution adopted in the present application is to provide a display panel, which includes a display area and a non-display area surrounding at least part of the display area, and the display panel includes: a substrate; a gate driving circuit and an electrostatic release protection circuit, which are arranged on one side of the substrate and located in the non-display area; the gate driving circuit includes a plurality of gate driving units; the electrostatic release protection circuit includes a plurality of electrostatic release protection units, and the arrangement trajectory of the orthographic projections of the plurality of gate driving units on the substrate at least partially overlaps with the arrangement trajectory of the orthographic projections of the plurality of electrostatic release protection units on the substrate, and the arrangement trajectory of the orthographic projections of the plurality of gate driving units on the substrate and the arrangement trajectory of the orthographic projections of the plurality of electrostatic release protection units on the substrate extend along the extension direction of the side of the display area.

[0006] Among them, at least part of the electrostatic release protection units and at least part of the gate driving units are arranged along the extension direction of the side of the display area; or, the gate driving circuit is arranged on the side of the electrostatic release protection circuit close to the substrate; or, the electrostatic release protection circuit is arranged on the side of the gate driving circuit close to the substrate; optionally, the display area includes an arc-shaped edge; optionally, in the extension direction of the arc-shaped edge, at least one electrostatic release protection unit is arranged in the gap between adjacent gate driving units; or, at least one gate driving unit is arranged in the gap between adjacent electrostatic release protection units.

[0007] Among them, the electrostatic release protection circuit includes multiple protection unit groups arranged along the extension direction of the arc edge, the protection unit group includes at least one electrostatic release protection unit, the number of electrostatic release protection units in different protection unit groups is the same or different, and at least one gate drive unit is arranged between any two adjacent protection unit groups.

[0008] Among them, the non-display area includes a first voltage signal line and a second voltage signal line, the display area includes a data line, and the non-display area also includes a fan-out line for electrically connecting the data line and the driving chip; the electrostatic release protection unit includes a first switch unit and a second switch unit, one end of the first switch unit is electrically connected to the fan-out line, and the other end of the first switch unit is electrically connected to the first voltage signal line, one end of the second switch unit is electrically connected to the fan-out line, and the other end of the second switch unit is electrically connected to the second voltage signal line; optionally, the number of fan-out lines is multiple, and multiple electrostatic release protection units are electrically connected to multiple fan-out lines accordingly; optionally, the first switch unit includes a first transistor and a second transistor, the source and gate of the first transistor are respectively connected to the first voltage signal line, the drain of the first transistor is connected to the source and gate of the second transistor, and the drain of the second transistor is connected to the fan-out line; the second switch unit includes a third transistor and a fourth transistor, the source and gate of the third transistor are connected to the fan-out line, the drain of the third transistor is connected to the source and gate of the fourth transistor, and the drain of the fourth transistor is connected to the second voltage signal line.

[0009] The electrostatic discharge protection circuit and the gate driving circuit share the first voltage signal line and / or the second voltage signal line.

[0010] Among them, the electrostatic release protection circuit and the gate drive circuit include transistors, the active layer and the gate layer of the transistor of the electrostatic release protection circuit are arranged on the side of the first voltage signal line or the second voltage signal line close to the substrate; the active layer and the gate layer of the transistor of the gate drive circuit are arranged on the side of the first voltage signal line or the second voltage signal line close to the substrate.

[0011] Among them, the first voltage signal line and the second voltage signal line are arranged in the same layer; optionally, the first voltage signal line and / or the second voltage signal line are arranged in the same layer as the data line; optionally, the fan-out line is located on the side of the data line close to or away from the substrate.

[0012] Wherein, the non-display area includes a binding area, and the arc-shaped edge is recessed toward the binding area; optionally, the display area is circular or elliptical.

[0013] In order to solve the above technical problem, the second technical solution adopted in the present application is to provide a display device, which includes the above display panel.

[0014] In order to solve the above technical problems, the third technical solution adopted in the present application is to provide a display panel, which includes a display area and a non-display area surrounding at least part of the display area, and the display panel includes: a substrate; a first functional circuit and a second functional circuit, which are arranged on one side of the substrate and located in the non-display area; the first functional circuit includes a plurality of first functional units, and the second circuit includes a plurality of second functional units, and the arrangement trajectory of the orthographic projections of the plurality of first functional units on the substrate at least partially overlaps with the arrangement trajectory of the orthographic projections of the plurality of second functional units on the substrate, and the arrangement trajectory of the orthographic projections of the plurality of first functional units on the substrate and the arrangement trajectory of the orthographic projections of the plurality of second functional units on the substrate extend along the extension direction of the side of the display area.

[0015] The beneficial effect of the present application is as follows: the present application provides a display panel and a display device, by making the arrangement trajectory of the orthographic projections of multiple gate driving units on the substrate at least partially overlap with the arrangement trajectory of the orthographic projections of multiple electrostatic release protection units on the substrate, and the arrangement trajectory of the orthographic projections of multiple gate driving units on the substrate and the arrangement trajectory of the orthographic projections of multiple electrostatic release protection units on the substrate extend along the extension direction of the side of the display area, the layout space of the electrostatic release protection circuit can be optimized, and the electrostatic release protection circuit is prevented from occupying additional layout space of the non-display area, thereby effectively compressing the space, and then reducing the size of the non-display area, meeting the requirement of a narrow frame of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0017] Figure 1 It is a schematic structural diagram of an embodiment of a display panel of the present application;

[0018] Figure 2 yes Figure 1 Schematic diagram of the enlarged structure of area A in the middle;

[0019] Figure 3 yes Figure 1 A schematic diagram of the structure of the electrostatic discharge protection circuit and the gate drive circuit;

[0020] Figure 4 yes Figure 3 Equivalent circuit diagram of the electrostatic discharge protection unit. DETAILED DESCRIPTION

[0021] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0022] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0023] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0024] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0025] In the related art, the left and right side frame areas of the non-display area are provided with gate drive units (GIP) arranged along the extension direction of the AA area curve, and the lower frame area of ​​the non-display area is provided with an electrostatic discharge (ESD) protection circuit, which includes a plurality of electrostatic discharge protection units, which are arranged along the extension direction of the AA area curve, and respectively connect the data line (data line) and the fan-out line (source) of the AA area to perform electrostatic protection on the data line. However, the electrostatic discharge protection circuit in the above-mentioned setting method needs to occupy a large wiring space, resulting in an increase in the size of the non-display area, which cannot meet the requirements of a narrow frame of the display panel.

[0026] Based on the above situation, the present application provides a display panel and a display device, which can solve the problem that the electrostatic discharge protection circuit occupies a large wiring space.

[0027] The display panel provided in the present application includes a display area and a non-display area surrounding at least part of the display area, and the display panel includes: a substrate; a gate driving circuit and an electrostatic release protection circuit, which are arranged on one side of the substrate and located in the non-display area; the gate driving circuit includes a plurality of gate driving units; the electrostatic release protection circuit includes a plurality of electrostatic release protection units, and the arrangement trajectory of the orthographic projections of the plurality of gate driving units on the substrate at least partially overlaps with the arrangement trajectory of the orthographic projections of the plurality of electrostatic release protection units on the substrate, and the arrangement trajectory of the orthographic projections of the plurality of gate driving units on the substrate and the arrangement trajectory of the orthographic projections of the plurality of electrostatic release protection units on the substrate extend along the extension direction of the side of the display area. By making the arrangement trajectory of the orthographic projections of the multiple gate driving units on the substrate at least partially overlap with the arrangement trajectory of the orthographic projections of the multiple electrostatic release protection units on the substrate, and the arrangement trajectory of the orthographic projections of the multiple gate driving units on the substrate and the arrangement trajectory of the orthographic projections of the multiple electrostatic release protection units on the substrate extend along the extension direction of the side of the display area, the layout space of the electrostatic release protection circuit can be optimized, and the electrostatic release protection circuit is prevented from occupying additional layout space of the non-display area, thereby effectively compressing the space, thereby reducing the size of the non-display area, and meeting the requirement of a narrow frame of the display panel.

[0028] To illustrate the specific structure of the display panel of this application, please refer to Figure 1 and Figure 2 , Figure 1 is a schematic structural diagram of an embodiment of a display panel of the present application, Figure 2 yes Figure 1 Schematic diagram of the enlarged structure of area A in the middle.

[0029] In this embodiment, the display panel 100 includes a display area 1 and a non-display area 2 surrounding at least a portion of the display area 1. The display panel 100 includes a substrate (not shown) and a gate driving circuit 10 and an electrostatic discharge protection circuit 20 disposed on one side of the substrate and located in the non-display area 2. The gate driving circuit 10 includes a plurality of gate driving units 11. The electrostatic discharge protection circuit 20 includes a plurality of electrostatic discharge protection units 21. The arrangement trajectory of the orthographic projections of the plurality of gate driving units 11 on the substrate and the arrangement trajectory of the orthographic projections of the plurality of electrostatic discharge protection units 21 on the substrate at least partially overlap, and the arrangement trajectory of the orthographic projections of the plurality of gate driving units 11 on the substrate and the arrangement trajectory of the orthographic projections of the plurality of electrostatic discharge protection units 21 on the substrate extend along the extension direction of the side edge of the display area 1.

[0030] In some specific embodiments, at least part of the electrostatic discharge protection unit 21 and at least part of the gate driving unit 11 are arranged along the extension direction of the side of the display area 1. In other specific embodiments, the gate driving circuit 11 is arranged on the side of the electrostatic discharge protection circuit 21 close to the substrate. In some other specific embodiments, the electrostatic discharge protection circuit 21 is arranged on the side of the gate driving circuit 11 close to the substrate.

[0031] It can be understood that by making the arrangement trajectories of the positive projections of at least part of the electrostatic discharge protection unit 21 and at least part of the gate driving unit 11 on the substrate at least partially overlap, the layout space of the electrostatic protection circuit 20 on the side can be reduced by stacking, thereby avoiding increasing the border spacing on the side where the gate driving circuit 10 is located, thereby achieving a narrow border effect.

[0032] In some embodiments, the display area 1 includes an arc-shaped edge. Wherein, the non-display area 2 includes a binding area, and the arc-shaped edge is concave toward the binding area. In some embodiments, the display area 1 is circular or elliptical, which is not limited in the present application.

[0033] The display area 1 includes pixel units arranged in an array, a plurality of scan lines arranged in parallel, and a plurality of data lines arranged in parallel, wherein the data lines are arranged perpendicular to the scan lines. The scan lines extend along the row direction of the pixel unit array and are arranged in the column direction of the pixel units. The data lines extend along the column direction of the pixel unit array and are arranged in the row direction of the pixel units. Each column of pixel units corresponds to a data line, and the scan signal output by the scan line controls the conduction and cutoff of the switch element in the pixel driving circuit. The data line controls the pixel display by writing a data signal to the pixel driving circuit, and the scan line and the data line jointly drive the pixel unit. The non-display area 2 also includes a driver chip for transmitting signals to the plurality of data lines in the display area 1. Specifically, the non-display area 2 also includes a fan-out line 30 for electrically connecting the data line and the driver chip.

[0034] In this embodiment, the plurality of gate driving units 11 are used to transmit signals to the plurality of scanning lines in the display area 1 .

[0035] In some implementations, a metal wiring area is provided between the gate driving circuit 10 and the display area 1 , and the metal wiring area is used to connect the gate driving unit 11 and the scan lines in the display area 1 .

[0036] In this embodiment, multiple electrostatic discharge protection units 21 are connected one-to-one with multiple data lines in the display area 1 to achieve the purpose of releasing static electricity and prevent the data lines from being damaged by static electricity. The number of the above-mentioned fan-out lines 30 is also multiple, and the multiple electrostatic discharge protection units 21 are electrically connected to the multiple fan-out lines 30 accordingly.

[0037] For the electrostatic discharge protection units 21 and gate driving units 11 arranged along the extension direction of the arc edge, at least one electrostatic discharge protection unit 21 is arranged at the gap between adjacent gate driving units 11, or at least one gate driving unit 11 is arranged at the gap between adjacent electrostatic discharge protection units 21.

[0038] In some specific embodiments, the electrostatic release protection circuit 20 includes multiple protection unit groups arranged along the extension direction of the arc edge, the protection unit group includes at least one electrostatic release protection unit 21, the number of electrostatic release protection units 21 in different protection unit groups is the same or different, and at least one gate drive unit is provided between any two adjacent protection unit groups.

[0039] In a specific implementation, the protection unit group includes only one electrostatic discharge protection unit 21 , that is, the electrostatic discharge protection unit 21 and the gate driving unit 11 are alternately arranged.

[0040] In another specific embodiment, the protection unit group includes two electrostatic discharge protection units 21 , that is, the gate driving unit 11 is arranged between every two electrostatic discharge protection units 21 .

[0041] Furthermore, the arrangement density of the electrostatic release protection units 21 is related to the arrangement density of the data lines in the display area 1. If the data lines corresponding to a certain arc section of the display area 1 are arranged more densely, the arrangement of the corresponding electrostatic release protection units 21 is also densely arranged, and only one to two gate driving units 11 may be spaced apart between every two adjacent electrostatic release protection units 21; if the data lines corresponding to a certain arc section of the display area 1 are arranged more sparsely, the arrangement of the corresponding electrostatic release protection units 21 is also sparsely arranged, and three to four or more gate driving units 11 may be spaced apart between every two adjacent electrostatic release protection units 21.

[0042] In some embodiments, the display panel 100 further includes a plurality of first fan-out lines 31 and a plurality of second fan-out lines 32. The plurality of first fan-out lines 31 are located on a side of the gate drive circuit 10 away from the display area 1, and the plurality of second fan-out lines 32 are located in the gap between adjacent gate drive units 11, and the orthographic projection on the substrate overlaps with the orthographic projection of the electrostatic discharge protection unit 21. The plurality of second fan-out lines 32 are used to connect the plurality of data lines in the display area 1 to the plurality of first fan-out lines 31 one by one. The correspondingly connected one of the first fan-out lines 31 and one of the second fan-out lines 32 constitute the above-mentioned fan-out line 30.

[0043] In the related art, multiple electrostatic discharge protection units in a circular display panel are arranged along the curved extension direction of the circular display area and are set on the side of the gate driving circuit close to the circular display area, which increases the frame spacing on the side where the gate driving circuit is located, resulting in an increase in the size of the non-display area.

[0044] Different from the related art, this embodiment optimizes the layout space of the electrostatic release protection circuit 20 by extending the arrangement trajectory of the orthographic projections of multiple gate driving units 11 on the substrate and the arrangement trajectory of the orthographic projections of multiple electrostatic release protection units 21 on the substrate along the extension direction of the side of the display area 1, thereby avoiding the electrostatic release protection circuit 20 from occupying additional layout space of the non-display area 2, thereby effectively compressing the space and then reducing the size of the non-display area 2, thereby achieving a narrow frame effect.

[0045] In the present embodiment, the non-display area 2 includes a first voltage signal line and a second voltage signal line, the electrostatic release protection unit 20 includes a first switch unit and a second switch unit, one end of the first switch unit is electrically connected to the fan-out line 30, and the other end of the first switch unit is electrically connected to the first voltage signal line, one end of the second switch unit is electrically connected to the fan-out line 30, and the other end of the second switch unit is electrically connected to the second voltage signal line.

[0046] In some embodiments, the first switch unit includes a first transistor and a second transistor, the source and gate of the first transistor are respectively connected to the first voltage signal line, the drain of the first transistor is connected to the source and gate of the second transistor, and the drain of the second transistor is connected to the fan-out line 30; the second switch unit includes a third transistor and a fourth transistor, the source and gate of the third transistor are connected to the fan-out line 30, the drain of the third transistor is connected to the source and gate of the fourth transistor, and the drain of the fourth transistor is connected to the second voltage signal line.

[0047] In some implementations, to further optimize the electrostatic discharge protection circuit 20 , the electrostatic discharge protection circuit 20 and the gate driving circuit 10 share a first voltage signal line and a second voltage signal line.

[0048] Specifically, see Figure 3 and Figure 4 , Figure 3 yes Figure 1 The schematic diagram of the structure of the electrostatic discharge protection circuit and the gate drive circuit. Figure 4 yes Figure 3 Equivalent circuit diagram of the electrostatic discharge protection unit.

[0049] In this embodiment, the multiple electrostatic discharge protection units 21 in the electrostatic discharge protection circuit 20 and the multiple gate driving units 11 in the gate driving circuit 10 are coupled between the first voltage signal line and the second voltage signal line. The first voltage signal line is a high-level voltage signal line (VGH), which is the on-voltage of the thin film transistor (TFT), and the second voltage signal line is a low-level voltage signal line (VGL), which is the off-voltage of the TFT. The VGH voltage is higher than the VGL voltage.

[0050] In this embodiment, the electrostatic discharge protection unit 21 includes a first switch unit and a second switch unit. Figure 4 As shown, the first switch unit includes a first transistor T1 and a second transistor T2, the source and gate of the first transistor T1 are respectively connected to VGH, the drain of the first transistor T1 is connected to the source and gate of the second transistor T2, and the drain of the second transistor T2 is connected to the fan-out line source. The second switch unit includes a third transistor T3 and a fourth transistor T4, the source and gate of the third transistor T3 are connected to the fan-out line source, the drain of the third transistor T3 is connected to the source and gate of the fourth transistor T4, and the drain of the fourth transistor T4 is connected to VGL.

[0051] Among them, the working principle of the electrostatic discharge protection unit 21 is as follows: when there is static charge on the source line, if the voltage of the static charge is higher than the VGH voltage, the first transistor T1 and the second transistor T2 are turned on, and the static charge is conducted away through VGH; if the voltage of the static charge is lower than the VGL voltage, the third transistor T3 and the fourth transistor T4 are turned on, and the static charge is conducted away through VGL, thereby eliminating the adverse effects of the static charge on the circuit.

[0052] In the related art, the electrostatic discharge protection circuit and the gate driving circuit usually have different high-level voltage signal lines and low-level voltage signal lines, and the high-level voltage signal lines and the low-level voltage signal lines usually occupy a larger wiring space, making it impossible to further reduce the border.

[0053] Different from the related art, this embodiment can reduce the space occupied by the electrostatic discharge protection circuit 20 in the routing area by setting the electrostatic discharge protection circuit 20 and the gate drive circuit 10 to share the first voltage signal line and the second voltage signal line, thereby further meeting the requirement of a narrow frame of the display panel 100.

[0054] In this embodiment, the electrostatic discharge protection circuit 20 and the gate drive circuit 10 include transistors, and the active layer and the gate layer of the transistor of the electrostatic discharge protection circuit 20 are arranged on the side of the first voltage signal line or the second voltage signal line close to the substrate. The active layer and the gate layer of the transistor of the gate drive circuit 10 are arranged on the side of the first voltage signal line or the second voltage signal line close to the substrate. Among them, the first voltage signal line and the second voltage signal line are arranged in the same layer. In some embodiments, the first voltage signal line and / or the second voltage signal line are arranged in the same layer as the data line. In some embodiments, the fan-out line 30 is located on the side of the data line close to or away from the substrate.

[0055] In some specific embodiments, the display panel 100 includes a substrate, a first metal layer M1 disposed on a surface of one side of the substrate, a first insulating layer covering the first metal layer M1, a second metal layer M2 disposed on the first insulating layer, a second insulating layer covering the second metal layer M2, and a third metal layer M3 disposed on the second insulating layer. The first voltage signal line and the second voltage signal line are disposed on the third metal layer M3, and the first fan-out line 31, the second fan-out line 32, and the metal routing area are disposed on the first metal layer M1 or the second metal layer M2.

[0056] Among them, the third metal layer M3 has a lower surface resistivity than the first metal layer M1 and the second metal layer M2, and is mainly used to set the routing with higher impedance requirements, such as the routing of the total signal, the cathode routing, and the VGH routing and VGL routing in the GIP circuit. The first metal layer M1 and the second metal layer M2 are mainly used to set the routing with lower impedance requirements, such as the data line and the routing used to connect to the display area pixels in the GIP (the above-mentioned metal routing area). Specifically, the routings set on the same metal film layer will not cross to avoid routing short circuits.

[0057] Please continue reading Figure 1 In this embodiment, the display panel 100 further includes a packaging area 40 , which is disposed at the outer peripheral edge of the non-display area 2 to protect the display panel 100 .

[0058] The packaging area 40 is disposed at the outermost side of the non-display area 2 to isolate water vapor and oxygen to prevent water vapor and oxygen from adversely affecting the circuit and wiring structure in the display panel 100 , thereby ensuring the normal operation of the display panel 100 .

[0059] Among them, the packaging method adopted by the display panel 100 is glass powder (Frit) packaging, that is, glass powder slurry is formed on the periphery of the screen body by coating or screen printing process, and then the solid glass powder is laser sintered to make it melt and then solidify, so as to seal the cover plate and the substrate, and then achieve the effect of isolating water and oxygen.

[0060] In actual production, the inventors of the present application found that by arranging at least part of the electrostatic discharge protection unit and at least part of the gate drive unit along the extension direction of the arc edge, and making the electrostatic discharge protection circuit and the gate drive circuit share the first voltage signal line and the second voltage signal line, the border of the display panel can be reduced by 50μm, thereby meeting the demand for a narrow border.

[0061] Correspondingly, the present application provides a display device, comprising any one of the above-mentioned display panels.

[0062] Different from the prior art, the present application optimizes the layout space of the electrostatic release protection circuit by making the arrangement tracks of the orthographic projections of multiple gate driving units on the substrate overlap with the arrangement tracks of the orthographic projections of multiple electrostatic release protection units on the substrate at least partially, and the arrangement tracks of the orthographic projections of multiple gate driving units on the substrate and the arrangement tracks of the orthographic projections of multiple electrostatic release protection units on the substrate extend along the extension direction of the side of the display area, thereby avoiding the electrostatic release protection circuit from occupying the layout space of the non-display area, thereby effectively compressing the space, and then reducing the size of the non-display area, meeting the requirements of the narrow frame of the display panel. Furthermore, the electrostatic release protection circuit and the gate driving circuit share the first voltage signal line and the second voltage signal line, which can reduce the wiring space occupied by the first voltage signal line and the second voltage signal line, thereby further reducing the frame.

[0063] Correspondingly, the present application provides a display panel, which includes a display area and a non-display area surrounding at least part of the display area, and the display panel includes: a substrate; a first functional circuit and a second functional circuit, which are arranged on one side of the substrate and located in the non-display area; the first functional circuit includes a plurality of first functional units, and the second circuit includes a plurality of second functional units, and the arrangement trajectory of the orthographic projections of the plurality of first functional units on the substrate at least partially overlaps with the arrangement trajectory of the orthographic projections of the plurality of second functional units on the substrate, and the arrangement trajectory of the orthographic projections of the plurality of first functional units on the substrate and the arrangement trajectory of the orthographic projections of the plurality of second functional units on the substrate extend along the extension direction of the side of the display area.

[0064] The first functional circuit may be a gate driving circuit, and the second driving circuit may be an electrostatic discharge protection circuit. In other embodiments, the first functional circuit and the second functional circuit may also be other circuits, which are not limited in the present application.

[0065] Different from the prior art, the present application optimizes the layout space of the second functional circuit by making the arrangement trajectory of the orthographic projections of multiple first functional units on the substrate at least partially overlap with the arrangement trajectory of the orthographic projections of multiple second functional units on the substrate, and the arrangement trajectory of the orthographic projections of multiple first functional units on the substrate and the arrangement trajectory of the orthographic projections of multiple second functional units on the substrate extend along the extension direction of the side of the display area, thereby avoiding at least part of the first functional units and at least part of the second functional units being arranged along the extension direction of the arc edge to occupy additional layout space of the non-display area, thereby effectively compressing the space, and then reducing the size of the non-display area, meeting the requirement of a narrow bezel of the display panel.

[0066] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel includes a display area and a non-display area surrounding at least a portion of the display area, the display area includes an arc-shaped edge, and the display panel includes: substrate; A gate driving circuit and an electrostatic discharge protection circuit are arranged on one side of the substrate and located in the non-display area; The gate driving circuit includes a plurality of gate driving units; The electrostatic discharge protection circuit includes a plurality of electrostatic discharge protection units, the arrangement trajectory of the orthographic projections of the plurality of gate driving units on the substrate at least partially overlaps with the arrangement trajectory of the orthographic projections of the plurality of electrostatic discharge protection units on the substrate, and the arrangement trajectory of the orthographic projections of the plurality of gate driving units on the substrate and the arrangement trajectory of the orthographic projections of the plurality of electrostatic discharge protection units on the substrate extend along the extension direction of the side of the display area.

2. The display panel according to claim 1, characterized in that: At least part of the electrostatic release protection unit and at least part of the gate drive unit are arranged along the extension direction of the side of the display area; or, the gate drive circuit is arranged on a side of the electrostatic release protection circuit close to the substrate; or, the electrostatic release protection circuit is arranged on a side of the gate drive circuit close to the substrate.

3. The display panel according to claim 2, characterized in that: In the extending direction of the arc-shaped edge, at least one of the electrostatic release protection units is arranged at a gap between adjacent gate driving units; or at least one of the gate driving units is arranged at a gap between adjacent electrostatic release protection units.

4. The display panel according to claim 3, characterized in that: The electrostatic release protection circuit includes a plurality of protection unit groups arranged along the extension direction of the arc edge, the protection unit group includes at least one electrostatic release protection unit, the number of the electrostatic release protection units in different protection unit groups is the same or different, and at least one gate drive unit is provided between any two adjacent protection unit groups.

5. The display panel according to claim 1, characterized in that: The non-display area includes a first voltage signal line and a second voltage signal line, the display area includes a data line, and the non-display area also includes a fan-out line for electrically connecting the data line and a driving chip; The electrostatic discharge protection unit includes a first switch unit and a second switch unit, one end of the first switch unit is electrically connected to the fan-out line, and the other end of the first switch unit is electrically connected to the first voltage signal line, one end of the second switch unit is electrically connected to the fan-out line, and the other end of the second switch unit is electrically connected to the second voltage signal line.

6. The display panel according to claim 5, characterized in that: The number of the fan-out lines is multiple, and the multiple electrostatic discharge protection units are electrically connected to the multiple fan-out lines accordingly.

7. The display panel according to claim 5, characterized in that: The first switch unit includes a first transistor and a second transistor, the source and gate of the first transistor are respectively connected to the first voltage signal line, the drain of the first transistor is connected to the source and gate of the second transistor, and the drain of the second transistor is connected to the fan-out line; the second switch unit includes a third transistor and a fourth transistor, the source and gate of the third transistor are connected to the fan-out line, the drain of the third transistor is connected to the source and gate of the fourth transistor, and the drain of the fourth transistor is connected to the second voltage signal line.

8. The display panel according to claim 1, characterized in that: The electrostatic discharge protection circuit and the gate driving circuit share a first voltage signal line and / or a second voltage signal line.

9. The display panel according to any one of claims 5 to 8, characterized in that: The electrostatic discharge protection circuit and the gate driving circuit include transistors, and the active layer and the gate layer of the transistor of the electrostatic discharge protection circuit are arranged on a side of the first voltage signal line or the second voltage signal line close to the substrate; The active layer and the gate layer of the transistor of the gate driving circuit are arranged on a side of the first voltage signal line or the second voltage signal line close to the substrate.

10. The display panel according to claim 5, characterized in that: The first voltage signal line and the second voltage signal line are arranged in the same layer.

11. The display panel according to claim 10, characterized in that: The first voltage signal line and / or the second voltage signal line are arranged in the same layer as the data line.

12. The display panel according to claim 10, characterized in that: The fan-out line is located at a side of the data line close to or far away from the substrate.

13. The display panel according to claim 2, characterized in that: The non-display area includes a binding area, and the arc-shaped edge is recessed toward the binding area.

14. The display panel according to claim 13, characterized in that: The display area is circular or elliptical.

15. A display device, characterized in that: A display panel comprising any one of claims 1-14.

16. A display panel, characterized in that: The display panel includes a display area and a non-display area surrounding at least a portion of the display area, the display area includes an arc-shaped edge, and the display panel includes: substrate; A first functional circuit and a second functional circuit are arranged on one side of the substrate and located in the non-display area; wherein the first functional circuit is a gate driving circuit, and the second functional circuit is an electrostatic discharge protection circuit; The first functional circuit includes a plurality of first functional units, and the second functional circuit includes a plurality of second functional units. The arrangement trajectory of the orthographic projections of the plurality of first functional units on the substrate at least partially overlaps with the arrangement trajectory of the orthographic projections of the plurality of second functional units on the substrate, and the arrangement trajectory of the orthographic projections of the plurality of first functional units on the substrate and the arrangement trajectory of the orthographic projections of the plurality of second functional units on the substrate extend along the extension direction of the side of the display area.

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