A novel thermally tunable laser chip and its fabrication method

Abstract

This invention discloses a novel thermally tunable laser chip and its fabrication method. The chip includes a substrate and multiple functional layers sequentially grown on the substrate. Specifically, the laser's ridge waveguide is located along its light-emitting axis. First thermal insulation grooves are formed in the channels on both sides of the ridge waveguide, penetrating all functional layers and connecting to the substrate. At least one functional layer below the ridge waveguide is hollowed out to form a void thermal insulation region. This void thermal insulation region is formed by etching at least one pair of second thermal insulation grooves on both sides of the ridge waveguide, followed by etching through at least one functional layer between the pair of second thermal insulation grooves. Furthermore, the two sides of the void thermal insulation region are adjacent to the first thermal insulation grooves. This invention avoids heat loss within the chip, improving the chip's thermal insulation effect and thermal tuning efficiency.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor laser chip technology, and more specifically, relates to a novel thermally tunable laser chip and its fabrication method. Background Technology

[0002] Tunable semiconductor lasers, as lasers whose output wavelength can be continuously changed within a certain range, are key components of dense wavelength division multiplexing systems and future all-optical networks. Their advantages will become increasingly prominent as the demand for transmission speed and capacity in network systems continues to rise. The unique advantages of tunable lasers in terms of tuning range and narrow linewidth have attracted numerous researchers to study their structure, aiming to adjust parameters such as temperature and current within the laser cavity to emit different wavelengths.

[0003] In tunable semiconductor lasers, the temperature inside the optical cavity is mainly adjusted by resistors. However, in the existing technology, the temperature insulation effect of semiconductor lasers is poor, and the heat generated by the resistors is easily spread to the outside, resulting in low utilization of the heat of the resistors. The temperature inside the optical cavity cannot reach the expected temperature, thus affecting the thermal tuning efficiency of the chip.

[0004] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0005] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a novel thermally tunable laser chip with a novel structure. Its purpose is to increase the thermal insulation space of the chip while ensuring the chip's support stability, so as to improve the chip's thermal insulation effect and thus improve the chip's thermal tuning efficiency. This solves the technical problem that existing tunable semiconductor laser chips cannot provide sufficient thermal insulation space while ensuring chip support stability, resulting in poor thermal insulation effect and low thermal tuning efficiency.

[0006] To achieve the above objectives, according to one aspect of the present invention, a novel thermally tunable laser chip is provided, comprising a substrate 1 and a plurality of functional layers 2 sequentially grown on the substrate 1, specifically:

[0007] The ridge waveguide of the laser is located on the axial direction of its light output. A first heat-insulating groove 3 is provided in the channel on both sides of the ridge waveguide, penetrating all functional layers 2 and connecting to the substrate 1. At least one functional layer 2 below the ridge waveguide is hollowed out to form a hollow heat-insulating region 4.

[0008] The hollow heat insulation region 4 is formed by etching at least one pair of second heat insulation grooves 5 on both sides of the spine, and then corroding through at least one functional layer 2 between the pair of second heat insulation grooves 5; and the two sides of the hollow heat insulation region 4 are adjacent to the first heat insulation groove 3.

[0009] Preferably, the second heat-insulating groove 5 is a portion of the channel located on both sides of the spine in the ridge waveguide, which is further etched in the direction towards the substrate 1; and the second heat-insulating groove 5 is arranged parallel to the first heat-insulating groove 3, with multiple functional layers on the suspended and void heat-insulating regions 4 spaced between them.

[0010] Preferably, a support and corrosion-resistant structure 6 with both corrosion-resistant and support functions is grown on the inner wall of the first heat-insulating groove 3. The two sides of the hollow heat-insulating area 4 are adjacent to the first heat-insulating groove 3, and the support and corrosion-resistant structure 6 is separated from the two.

[0011] Preferably, the supporting corrosion-resistant structure 6 consists of a first layer of sputtered metal Ti and Pt, with the outermost layer being the layer adjacent to the first heat-insulating groove 3, and the second layer being an oxide film deposited by CVD.

[0012] Preferably, when multiple pairs of the second heat-insulating grooves 5 are included, wherein the distance between each pair of second heat-insulating grooves 5 extending along the laser axial direction and the adjacent pair of second heat-insulating grooves 5 is exactly the same as the length of a grating region, then the multiple spacing distances formed by the multiple pairs of second heat-insulating grooves 5 form a periodic structure consistent with the periodic grating region; wherein, the spacing distance between each pair of second heat-insulating grooves 5 extending along the laser axial direction and the adjacent pair of second heat-insulating grooves 5 retains the corresponding functional layers etched away in the second heat-insulating grooves.

[0013] Preferably, the plurality of functional layers 2 sequentially grown on the substrate 1 include at least one of the following: lower cladding layer 21, overhead layer 22, lower etch stop layer 23, lower sacrificial layer 24, upper etch stop layer 25, upper sacrificial layer 26, active layer 27, and waveguide layer 28.

[0014] Preferably, it also includes two parts: resistor 7 and electrode 8. Each resistor 7 is sputtered on the ridge waveguide of the laser above the dielectric layer, and each resistor 7 is connected to a set of electrodes.

[0015] According to another aspect of the present invention, a method for fabricating a novel thermally tunable laser chip is also provided, wherein a layered growth substrate 1 is pre-set, and the method includes:

[0016] A ridge waveguide structure is etched on the layered substrate 1, wherein the channel of the ridge waveguide structure is etched down to the active layer 27;

[0017] The locations of the corresponding first heat-insulating groove 3 and second heat-insulating groove 5 are drawn by photolithography, and the first heat-insulating groove 3 and second heat-insulating groove 5 are obtained by etching and / or wet etching; wherein, the first heat-insulating groove 3 is hollowed out to the substrate 1, and the second heat-insulating groove 5 is hollowed out to the lower etching stop layer 23.

[0018] A corrosion-resistant support structure 6 is grown on the inner wall of the first heat-insulating groove 3;

[0019] The lower sacrificial layer 24, the lower corrosion stop layer 23, and the overhead layer 22 below the ridge waveguide structure are corroded and hollowed out to obtain a hollow heat insulation region 4. The surface of the hollow heat insulation region 4 is in communication with the second heat insulation groove 5, and the two sides of the second heat insulation groove 5 abut against the supporting corrosion-resistant structure 6.

[0020] Preferably, etching the ridge waveguide structure on the layered substrate 1 specifically includes:

[0021] A corresponding ridge waveguide pattern is defined on the surface of the layered substrate 1 by photolithography, and etching is performed on the semiconductor chip based on the defined ridge waveguide pattern, with an etching depth exceeding the waveguide layer 28.

[0022] An acidic etching solution is used to etch the chip waveguide layer 28 to form grooves on the left and right sides of the semiconductor chip waveguide, which extend along the direction close to the substrate 1.

[0023] Preferably, the step of etching away the lower sacrificial layer 24, lower etch stop layer 23, and overhead layer 22 beneath the ridge waveguide structure using wet etching specifically includes:

[0024] The lower corrosion stop layer 23 of the InGaAsP material was etched for a preset time using an H2SO4-based solution, and the lower sacrificial layer 24 and the support layer 22 of the InP material were etched and hollowed out using a hydrochloric acid-based solution.

[0025] Overall, the above-mentioned technical solutions conceived by the present invention have the following beneficial effects compared with the prior art: The present invention, by setting a support corrosion-resistant structure to provide support for the chip, also sets multiple hole structures on the support corrosion-resistant structure, thereby ensuring the support stability of the chip, increasing the heat insulation space of the first heat insulation groove, avoiding heat loss inside the chip, improving the chip's temperature insulation effect, and thus improving the chip's thermal tuning efficiency. Attached Figure Description

[0026] Figure 1 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0027] Figure 2 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0029] Figure 4 This is a top view of a novel thermally tunable laser chip provided in an embodiment of the present invention.

[0030] Figure 5 This is a cross-sectional view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0031] Figure 6 This is one of the embodiments provided by the present invention. Figure 1 This is a schematic diagram of the structure of a layered substrate grown in a novel thermally tunable laser chip.

[0032] Figure 7 This is a planar top view of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0033] Figure 8 This is a schematic flowchart of a novel thermally tunable laser chip fabrication method provided in an embodiment of the present invention;

[0034] Figure 9 This is a schematic flowchart of a novel thermally tunable laser chip fabrication method provided in an embodiment of the present invention;

[0035] Figure 10 This is a partial top view of a chip during the fabrication process of a novel thermally tunable laser chip according to an embodiment of the present invention.

[0036] Figure 11 This is a partial top view schematic diagram of a novel thermally tunable laser chip provided in an embodiment of the present invention;

[0037] Figure 12 This is a schematic flowchart of a novel thermally tunable laser chip fabrication method provided in an embodiment of the present invention;

[0038] Figure 13 This is a cross-sectional view of the chip during the fabrication process of a novel thermally tunable laser chip according to an embodiment of the present invention.

[0039] Figure 14 This is a cross-sectional view of the chip during the fabrication process of a novel thermally tunable laser chip according to an embodiment of the present invention.

[0040] Figure 15 This is a cross-sectional view of the chip during the fabrication process of a novel thermally tunable laser chip according to an embodiment of the present invention.

[0041] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein:

[0042] 1. Substrate; 2. Functional layer; 21. Lower cladding layer; 22. Overhead layer; 23. Lower etch stop layer; 24. Lower sacrificial layer; 25. Upper etch stop layer; 26. Upper sacrificial layer; 27. Active layer; 28. Waveguide layer; 3. First thermal insulation groove; 4. Void thermal insulation area; 5. Second thermal insulation groove; 6. Supporting corrosion-resistant structure; 7. Resistor; 8. Electrode; 9. Spine; 10. Grooves on both sides of the spine. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0044] Example 1:

[0045] Embodiment 1 of the present invention provides a novel thermally tunable laser chip, comprising a substrate 1 and multiple functional layers 2 sequentially grown on the substrate 1, such as... Figure 1 As shown, specifically: the ridge waveguide of the laser is located on its light-emitting axis, and a first heat-insulating groove 3 is provided in the channels on both sides of the ridge waveguide, penetrating all functional layers 2 and connecting to the substrate 1, and at least one functional layer 2 below the ridge waveguide is hollowed out to form a hollow heat-insulating region 4.

[0046] The hollow heat insulation region 4 is formed by etching at least one pair of second heat insulation grooves 5 on both sides of the spine, and then corroding through at least one functional layer 2 between the pair of second heat insulation grooves 5; and the two sides of the hollow heat insulation region 4 are adjacent to the first heat insulation groove 3.

[0047] The implicit information is that when hollowing out at least one or more functional layers 2 below the ridge waveguide, it is necessary not to damage the structure of the ridge waveguide itself and to form a cavity. Under this condition, at least one functional layer 2 must be retained below the ridge waveguide to ensure that the structure of the ridge waveguide remains unchanged and that a cavity is formed rather than a groove.

[0048] Each functional layer 2 is tightly connected and fixed to the inner wall of the chip. The inner wall of the chip can be the inner wall around the chip or the upper inner wall of the chip, specifically the inner wall of the chip that is bonded or fixed to the retained functional layer 2. This allows the ridge waveguide to be suspended and supported by the retained functional layer 2 when the space under the ridge waveguide is hollowed out.

[0049] Research and testing revealed that the heat generated by the chip during normal operation is mainly exchanged with the outside air through the substrate 1 material. In this embodiment, a hollow heat insulation area 4 is set below the ridge waveguide to prevent heat from being transferred from below to the substrate 1. Furthermore, a first heat insulation groove 3 is set on both sides of the ridge waveguide to prevent heat from being transferred to the edge of the chip. This prevents heat from being transferred from the edge of the chip to the substrate 1 and then leaking out from the substrate 1, thus avoiding heat loss from inside the chip, improving the chip's heat insulation effect, and thereby improving the chip's thermal tuning efficiency.

[0050] To further reduce heat diffusion from below to substrate 1, in conjunction with the above embodiments, the following preferred implementation methods also exist, such as... Figure 2 As shown, specifically, it includes: in a portion of the area between the spine of the ridge waveguide and the first heat insulation groove 3, one or more second heat insulation grooves 5 are provided that connect to the cavity heat insulation area 4.

[0051] The second heat insulation groove 5 is a portion of the channel located on both sides of the spine in the ridge waveguide, which is further etched in the direction of the substrate 1; and the second heat insulation groove 5 is arranged parallel to the first heat insulation groove 3, with multiple functional layers suspended and voided on the heat insulation region 4 between them.

[0052] Since there are first heat-insulating grooves 3 respectively in the channels on both sides of the ridge waveguide, there are two regions between the spine and the first heat-insulating grooves 3. At least one second heat-insulating groove 5 can be provided in each region, or at least one second heat-insulating groove 5 can be provided in only one region.

[0053] When a second heat-insulating groove 5 is provided in each region, the distance between the second heat-insulating grooves 5 located on both sides of the spine is determined by an expert based on the width of the spine and the thickness of the functional layer 2.

[0054] Furthermore, the second heat-insulating grooves 5 located on the same side of the spine also need to be spaced at a corresponding distance, such as... Figure 4 As shown, the second heat-insulating grooves 5 located on the same side of the spine are spaced by a first preset distance d1. This first preset distance d1 is determined by comprehensively considering the width of the spine, the thickness of the functional layer 2, and the length L of a single second heat-insulating groove 5 in the light-emitting axis. Generally, the wider the spine, the smaller the overall thickness of the functional layer 2, and the smaller the length L of a single second heat-insulating groove 5 in the light-emitting axis, the smaller the first preset distance d1 can be set; conversely, the first preset distance d1 needs to be increased. In this embodiment of the invention, as... Figure 4 As shown, the ridge waveguide structure is intuitively represented as a spine 9 located in the middle and channels 10 located on both sides of the spine.

[0055] This preferred embodiment further increases the heat insulation space by providing a second heat insulation groove 5, thereby reducing heat loss and improving the thermal tuning efficiency of the chip.

[0056] In the above embodiments, the support of the ridge waveguide is mainly achieved by connecting the functional layer 2 to the inner wall of the chip. However, the presence of the hollow heat insulation area 4 and the second heat insulation groove 5 reduces the functional layer 2 used for support or decreases the connection tightness between some areas of the functional layer 2, which may weaken the support effect. To address this problem, the following preferred embodiments exist, such as... Figure 5 As shown, specifically, it includes: a support and corrosion-resistant structure 6 with both corrosion-resistant and support functions is grown on the inner wall of the first heat-insulating groove 3; the functional layer 2 retained below the ridge waveguide is attached to the outer wall of the support and corrosion-resistant structure 6, providing suspended support for the ridge waveguide. The two sides of the hollow heat-insulating area 4 are adjacent to the first heat-insulating groove 3, and the support and corrosion-resistant structure 6 separates them.

[0057] This invention also provides a preferred implementation, wherein the supporting corrosion-resistant structure 6 comprises, from the outermost layer adjacent to the first heat-insulating groove 3 to the innermost layer, a first layer of sputtered metal Ti and Pt (e.g., thicknesses of 80 nm and 90 nm, respectively), and a second layer of oxide film deposited by CVD (e.g., thickness of 800 nm). The supporting corrosion-resistant structure 6 can be one or more combinations, or a single dielectric layer; the metal thin film primarily protects against corrosion of the subsequent corrosion-stopping layer, while the thicker dielectric layer provides support to ultimately form the heat-insulating structure.

[0058] The supporting corrosion-resistant structure 6 can be configured as one or more layers. The reserved functional layer 2 specifically refers to the functional layer 2 that is retained but not removed when one or more functional layers 2 below the ridge waveguide are hollowed out, and that is in contact with the outer wall of the first groove.

[0059] In this preferred embodiment, the supporting corrosion-resistant structure 6 disposed on the inner wall of the first heat-insulating groove 3 not only enhances the heat insulation effect and improves the thermal tuning efficiency of the chip, but also provides corresponding support to the ridge waveguide through the multiple functional layers 2 connected to the outer wall of the supporting corrosion-resistant structure 6. This achieves double support for the ridge waveguide, enhancing the stability of the ridge waveguide structure and preventing the chip structure from collapsing due to external forces. Furthermore, by integrating heat insulation and support, this embodiment reduces the chip space required when separately setting up the heat insulation structure and support frame. Moreover, by placing it on the inner wall of the first heat-insulating groove 3, it reduces the difficulty of the manufacturing process and makes reasonable use of existing space without the need for additional space, reducing the space occupied by the chip and providing a basis for the miniaturization of the chip.

[0060] In the above embodiments, a method of suspending the ridge waveguide by fixing the functional layer to the inner wall of the chip was pointed out. In this preferred embodiment, a method of suspending the ridge waveguide by supporting the corrosion-resistant structure is proposed. In practice, depending on the chip design requirements and the material, density and other factors of each functional layer, only one method can be selected for support or both methods can be used together to enhance the structural stability of the chip.

[0061] At the location of the second heat-insulating groove 5, because the second heat-insulating groove 5 is created, the spine and the supporting corrosion-resistant structure 6 are not directly connected. However, the spine and the supporting corrosion-resistant structure 6 are connected through the functional layer 2 between the two second heat-insulating grooves 5. The spine at the location of the second heat-insulating groove 5 and the interval between the second heat-insulating grooves 5 are connected. Therefore, the spine at the location of the second heat-insulating groove 5 can be supported through the interval between the second heat-insulating grooves 5. The specific manifestation of the location of the second heat-insulating groove 5 is as follows: Figure 4 The second heat insulation groove 5 and its upper and lower parts are shown.

[0062] In conjunction with the embodiments of the present invention, when fabricating multiple second heat-insulating grooves 5, there is a preferred implementation method for their distribution, such as... Figure 3 As shown, when multiple pairs of the second heat-insulating grooves 5 are included, the distance between each pair of second heat-insulating grooves 5 extending along the laser axial direction and the adjacent pair of second heat-insulating grooves 5 is exactly the same as the length of a grating region. Thus, the multiple intervals formed by the multiple pairs of second heat-insulating grooves 5 constitute a periodic structure consistent with the periodic grating region. Furthermore, the intervals between each pair of second heat-insulating grooves 5 extending along the laser axial direction and the adjacent pair of second heat-insulating grooves 5 retain the corresponding functional layers etched away in the second heat-insulating grooves. The advantage of this approach is that, while fully utilizing the heat-insulating structure characteristics proposed in this invention, the heat dissipation effect of the corresponding grating region can be relatively inherited and preserved, improving the stability of the grating region's operation.

[0063] A preferred implementation of the supporting corrosion-resistant structure 6 includes having multiple porous structures. The fabrication of this porous structure will be detailed in the fabrication method of Embodiment 3 of this invention, and will not be elaborated upon here. This structure is designed to reduce the heat dissipation characteristics of the supporting corrosion-resistant structure 6 itself, which acts as a barrier against the sidewalls of the hollow heat-insulating region 4, thereby further maximizing the heat insulation effect of the first heat-insulating groove 3 (i.e., utilizing the fact that the air inside it has lower heat dissipation characteristics compared to the substrate and functional layer).

[0064] As a preferred implementation method, such as Figure 4As shown, the second heat-insulating groove 5 and the first heat-insulating groove 3 located on the same side of the ridge waveguide are spaced by a second preset distance d2. This second preset distance d2 is to increase the connection area between the functional layer 2 and the support frame, preventing the functional layer 2 connected to the support frame below the ridge waveguide from being unable to support the entire ridge waveguide structure, thus avoiding chip structure collapse. Similarly, the second preset distance d2 is determined by comprehensively considering the width of the spine, the thickness of the functional layer 2, the support strength of the functional layer 2, the width of a single second heat-insulating groove 5, and the width of the first heat-insulating groove 3.

[0065] The rationale for this preferred approach is that, since the spine portion between the second heat-insulating groove 5 is still connected to the support frame via the functional layer 2, even if there is no distance between the second heat-insulating groove 5 and the first heat-insulating groove 3, provided the material of the functional layer 2 and the support corrosion-resistant structure 6 are sufficiently strong, the spine can still be effectively supported through the connection between the area between the second heat-insulating groove 5 and the support corrosion-resistant structure 6, as well as through the connection between the functional layer 2 and the inner wall of the chip. However, with a preset second distance d2, the connection area between the functional layer 2 and the support corrosion-resistant structure 6 can be increased, thereby enhancing the support strength and preventing chip collapse.

[0066] In a preferred embodiment, a dielectric layer and / or metal oxide are deposited on the inner walls of the second heat-insulating groove 5 and the hollow heat-insulating region 4, so that the heat dissipated from the substrate 1 is greatly reduced when the chip exchanges heat with the outside air through the substrate 1, thereby further improving the thermal tuning efficiency of the chip.

[0067] like Figure 6 As shown, the plurality of functional layers 2 grown sequentially on the substrate 1 include at least one of the following: lower cladding layer 21, overhead layer 22, lower etch stop layer 23, lower sacrificial layer 24, upper etch stop layer 25, upper sacrificial layer 26, active layer 27, and waveguide layer 28.

[0068] The active layer 27 and waveguide layer 28 can be one or more of the following: laser layer structure, detector layer structure, modulator layer structure, and passive waveguide layer 28. In actual implementation, these various functional layers 2 are usually designed in combination to meet the different requirements of thermally tunable laser chips. The laser layer structure and modulator layer structure are generally the most practically significant in terms of performance. Other functional layers 2 are designed according to the support requirements, thermal insulation requirements, and fabrication process of the ridge waveguide. The designed parameters include, but are not limited to, the material, thickness, and arrangement of the functional layers 2.

[0069] In this embodiment of the invention, a more practical complex structure diagram is also provided, such as... Figure 7As shown, it also includes two parts: resistor 7 and electrode 8. Each resistor 7 is sputtered on the ridge waveguide of the laser above the dielectric layer, and each resistor 7 is connected to a set of electrodes.

[0070] In this embodiment, the second heat-insulating groove 5, the first heat-insulating groove 3, and the hollow heat-insulating region 4, etc., can be applied to areas of the thermally tunable laser chip, including but not limited to the front grating region, the phase region, and the rear grating region. This embodiment can be applied to specific regions individually, or it can be used in combination for multiple regions.

[0071] Taking the second heat-insulating groove 5, the first heat-insulating groove 3, and the hollow heat-insulating region 4 applied to the front grating area of ​​the thermally tuned laser chip in this embodiment as an example, wherein, from Figure 7 The cross-sectional view obtained at position 1b indicated by the dashed line is as follows: Figure 1 The second heat insulation groove 5 is not provided, so that Figure 7 The cross-sectional view obtained at position 2b indicated by the dashed line is as follows: Figure 2 The diagram shows a second heat insulation groove 5.

[0072] In the embodiments of the present invention, the limiting descriptions such as "first" and "second" do not refer to a specific order. They are merely used to separate the corresponding limited objects from the same category and to facilitate the description of two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.

[0073] In the embodiments of this invention, expressions such as "A and / or B" actually mean that the implementation can be implemented with A as an object, or with B as an object, or with a combination of A and B. A and B can also be replaced with specific subject name objects according to the needs of the specific description scenario.

[0074] Example 2:

[0075] Based on the method described in Embodiment 1, this invention provides an embodiment that combines specific application scenarios and uses technical descriptions within those scenarios to illustrate the implementation process of the invention's features in those scenarios.

[0076] like Figure 7 The image shown is a planar top view of a novel semiconductor laser chip structure. In a typical example of a thermally tunable laser chip, it includes, for example... Figure 7 The SOA area, front grating area, gain area, phase area, rear grating area, and COA area are shown.

[0077] This embodiment uses an application area including a front grating area, a rear grating area, and a phase area as an example to demonstrate the detailed structure and function, specifically including: Figure 6As shown, a lower cladding layer 21 made of InGaAs material, an overhead layer 22 made of InP material, a lower etch stop layer 23 made of InGaAsP material, a lower sacrificial layer 24 made of InP material, an upper etch stop layer 25 made of InGaAsP material, an upper sacrificial layer 26 made of InP material, an active layer 27 made of InGaAsP material, and a waveguide layer 28 made of InGaAsP material are sequentially grown on the substrate 1.

[0078] A ridge waveguide structure is provided in the front grating region, phase region, and rear grating region. A laser is placed above the spine of the ridge waveguide structure. First heat-insulating grooves 3 are respectively provided in the channels on both sides of the ridge waveguide. The first heat-insulating grooves 3 are directly connected to the substrate 1. The hollow area of ​​the first heat-insulating groove 3 forms an air heat insulation layer, preventing heat from diffusing through the sides of the ridge waveguide to the chip edge and from the edge to the substrate 1. This prevents the heat generated by the resistor 7 from dissipating through heat exchange between the substrate 1 and the outside, allowing the heat generated by the resistor 7 to act more continuously inside the chip, thereby improving the thermal tuning efficiency of the chip. Furthermore, a supporting corrosion-resistant structure 6 is provided on the inner wall of the first heat-insulating groove 3 to further prevent heat from dissipating from the substrate 1, improving the thermal tuning efficiency of the chip.

[0079] The corrosion-resistant support structure 6 can be constructed by setting multiple small circular holes inside a high-strength support material, and vertical support columns within these holes. This reduces the self-weight of the corrosion-resistant support structure 6 while reinforcing the sacrificed support strength through the support columns. A dielectric layer or metal oxide is applied to the outer wall of the support material to achieve thermal insulation. The corrosion-resistant support structure 6 is connected and fixed to the substrate 1.

[0080] Furthermore, by hollowing out the overhead layer 22, the lower corrosion-stopping layer 23, and the lower sacrificial layer 24 below the ridge waveguide, and by connecting the other functional layers 2 of the ridge waveguide to the outer wall of the support corrosion-resistant structure 6 of the first heat-insulating groove 3 located on both sides of the ridge waveguide, the ridge waveguide can be suspended.

[0081] A second heat-insulating groove 5 is provided in the area between the spine of the waveguide and the first heat-insulating groove 3, connecting to the hollow heat-insulating area 4. The second heat-insulating grooves 5 are arranged at intervals, that is, one second heat-insulating groove 5 is provided on each side of the spine at a first preset distance. This allows the spine of the waveguide to connect with the supporting corrosion-resistant structure 6 through the functional layer 2 reserved between the second heat-insulating grooves 5, and to connect with the inner wall of the chip through the functional layer 2, thereby obtaining support and preventing the chip structure from collapsing. The first preset distance is determined by those skilled in the art based on a comprehensive analysis of the width of the spine, the thickness of each functional layer 2, and the length of a single second heat-insulating groove 5 in the light-emitting axis. The desired effect of this design is to achieve heat insulation space while ensuring effective support for the waveguide structure.

[0082] The second heat insulation groove 5 and the first heat insulation groove 3 also maintain a second preset distance. Specifically, the second heat insulation groove 5 located on the same side of the spine and the first heat insulation groove 3 maintain a second preset distance, so that the part of the functional layer 2 reserved on both sides of the second heat insulation groove 5 is used to connect with the support corrosion-resistant structure 6, increasing the connection area with the support corrosion-resistant structure 6 and providing stronger support for the spine waveguide structure.

[0083] The second heat insulation groove 5 and the hollow heat insulation area 4 form a second heat insulation space, which prevents heat from spreading from the substrate 1 to the outside and further improves the thermal tuning efficiency of the chip.

[0084] In the embodiments of the present invention, the limiting descriptions such as "first" and "second" do not refer to a specific order. They are merely used to separate the corresponding limited objects from the same category and to facilitate the description of two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.

[0085] Example 3:

[0086] This invention provides a novel method for fabricating a thermally tunable laser chip, which can be used to fabricate the novel thermally tunable laser chips described in Embodiments 1 and 2. It should be noted that this invention focuses on the method process output related to substantially differentiating features; other processes, such as electrode fabrication, are not within the scope of this invention and are conventional prior art, therefore they will not be described in detail later in this invention. In this invention embodiment, as... Figure 8 As shown, a pre-formed layered substrate 1 is used for the growth of a ridge waveguide structure, the method including: in step 201, etching a ridge waveguide structure on the layered substrate 1, wherein the channel of the ridge waveguide structure is etched down to the active layer 27; the formed structure is as follows. Figure 14 As shown.

[0087] In step 202, the locations of the corresponding first heat-insulating groove 3 and second heat-insulating groove 5 are drawn by photolithography, and the first heat-insulating groove 3 and second heat-insulating groove 5 are obtained by etching and / or wet etching. A support corrosion-resistant structure 6 is provided on the inner wall of the first heat-insulating groove 3; wherein, the first heat-insulating groove 3 is hollowed out to the substrate 1, and the second heat-insulating groove 5 is hollowed out to the lower etching stop layer 23; the formed structure is as follows. Figure 15 As shown.

[0088] In step 203, the lower sacrificial layer 24, lower corrosion stop layer 23, and overhead layer 22 beneath the ridge waveguide structure are corroded and hollowed out using wet etching to obtain a void insulation region 4. The surface of the void insulation region 4 is in communication with the second insulation groove 5, and the two sides of the second insulation groove 5 abut against the supporting corrosion-resistant structure 6. The resulting structure is as follows: Figure 13 As shown.

[0089] In this embodiment of the invention, steps 201-203 are merely one sequential form of the method process presented in this embodiment. In optional solutions, for example, the order of steps 202 and 203 in this embodiment can be interchanged. More importantly, in subsequent embodiments of the invention, the refinement of specific steps in steps 201-203, without the need for creative labor by those skilled in the art, and the adjustment of the execution order should also be reasonably considered to fall within the protection scope of this invention.

[0090] Because the lower sacrificial layer 24, lower corrosion stop layer 23, and overhead layer 22 below the ridge waveguide are hollowed out, the ridge waveguide needs to be suspended and supported by the corrosion-resistant support structure 6 in order to maintain the normal structure of the ridge waveguide. Therefore, if the hollow heat insulation area 4 is made before the first heat insulation groove 3 is made and the corrosion-resistant support structure 6 is set, the ridge waveguide structure may sink. In this case, after the first heat insulation groove 3 is made, the other functional layers 2 of the ridge waveguide can be fixed to the outer wall of the corrosion-resistant support structure 6 by bonding or other means, so that it is suspended. When the hollow heat insulation area 4 is made by wet etching, the etching liquid needs to be in contact with the lower sacrificial layer 24, lower corrosion stop layer 23, and overhead layer 22. In the sequence of the method process shown in this embodiment, the etching liquid can be poured through the second heat insulation groove 5. If the hollow heat insulation area 4 is made before the second heat insulation groove 5 is made, it can be achieved by drilling a hole at the location of the second heat insulation groove 5 or by other means.

[0091] In this embodiment, since the thermal tuning efficiency of the material is largely unaffected by the material bandgap, a material with a higher bandgap can be used as the passive waveguide region for wavelength tuning in the chip design. This further reduces the absorption loss of the passive waveguide region material, lowers the chip threshold, and reduces the laser linewidth. Simultaneously, the waveguide layer 28 is thermally isolated from the substrate 1 by air. With a given chip thermal power, both the thermal tuning efficiency and the tuning response speed are significantly improved.

[0092] In this embodiment of the invention, a scenario for implementing a laser is provided, such as... Figure 6 As shown, the layered substrate 1 specifically includes: a lower cladding layer 21, a suspended layer 22, a lower etch stop layer 23, a lower sacrificial layer 24, an upper etch stop layer 25, an upper sacrificial layer 26, an active layer 27, and a waveguide layer 28, all made of multi-element materials, grown sequentially on the substrate 1. The present invention also provides materials suitable for some functional layers, specifically including: the lower cladding layer 21 is made of InGaAs, the suspended layer 22 is made of InP, the lower etch stop layer 23 is made of InGaAsP, the lower sacrificial layer 24 is made of InP, the upper etch stop layer 25 is made of InGaAsP, the upper sacrificial layer 26 is made of InP, and the active layer 27 is made of InGaAsP.

[0093] The processing technology used for each functional layer 2 is determined by the processing requirements and materials of each functional layer 2. Next, taking the materials of each functional layer 2 given in this embodiment as examples, the process of generating the corresponding ridge waveguide structure and generating the first heat-insulating groove 3, the second heat-insulating groove 5, and the void heat-insulating region 4 will be described one by one.

[0094] The etching of the ridge waveguide structure on the layered substrate 1 specifically includes: defining the corresponding ridge waveguide pattern on the surface of the layered substrate 1 by photolithography, and etching on the semiconductor chip based on the defined ridge waveguide pattern, with the etching depth exceeding the waveguide layer 28.

[0095] An acidic etching solution is used to etch the chip waveguide layer 28 to form grooves on the left and right sides of the semiconductor chip waveguide, which extend along the direction close to the substrate 1.

[0096] The process of obtaining the first heat-insulating groove 3 and the second heat-insulating groove 5 by etching and / or wet etching specifically includes: protecting the area outside the first heat-insulating groove 3 and the second heat-insulating groove 5 by depositing a dielectric layer; hollowing out the active layer 27 and the upper etched layer by etching; and hollowing out the upper sacrificial layer 26 and the lower sacrificial layer 24 by etching with an acidic solution.

[0097] When processing the second heat-insulating groove 5, appropriate acid-resistant materials are used to limit the corrosion liquid from vertically downward corrosion and prevent it from drilling to both sides.

[0098] The process of etching away the lower sacrificial layer 24, lower etch stop layer 23, and overhead layer 22 beneath the ridge waveguide structure using wet etching specifically includes: etching the lower etch stop layer 23 with an H2SO4-based solution for a preset time, and etching away the lower sacrificial layer 24 and overhead layer 22 with a hydrochloric acid-based solution. The preset time is determined based on actual testing, and its effect is to complete the removal of the corresponding lower etch stop layer 23. One optional formulation of the H2SO4-based solution is H2O2 and H2SO4. Another optional formulation of the hydrochloric acid-based solution is HCl and H3PO4, with a 1:3 ratio of HCl to H3PO4. When etching the lower sacrificial layer 24 and overhead layer 22, the presence of a first heat-insulating groove 3 and a supporting corrosion-resistant structure 6 on the inner wall of the first groove allows the etching range to be limited by the surface of the supporting corrosion-resistant structure 6. This eliminates the need for a preset etching time, achieving the etching effect on the lower sacrificial layer 24 and overhead layer 22 while protecting the surrounding area from corrosion.

[0099] In the embodiments of the present invention, the limiting descriptions such as "first" and "second" do not refer to a specific order. They are merely used to separate the corresponding limited objects from the same category and to facilitate the description of two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.

[0100] In the embodiments of this invention, expressions such as "A and / or B" actually mean that the implementation can be implemented with A as an object, or with B as an object, or with a combination of A and B. A and B can also be replaced with specific subject name objects according to the needs of the specific description scenario.

[0101] In Example 1, it was proposed that the supporting corrosion-resistant structure 6 be fabricated with multiple holes. The actual stage of its fabrication method involves completing the process described above. Figure 5 The fabrication of the supporting corrosion-resistant structure 6 and the hollow heat-insulating area 4 shown is as follows: Figure 9 As shown, the method includes: in step 301, photoresist is filled into the first heat insulation groove 3, and the corresponding photoresist covers the surface of the support corrosion-resistant structure 6 and fills the first heat insulation groove 3.

[0102] In step 302, photoresist is filled into the first heat insulation groove 3, and photolithography is performed at a predetermined interval and at a first depth along the laser optical axis to form a row of periodically arranged photolithographic patterns that expose the surface of the supporting corrosion-resistant structure 6 between the first heat insulation groove 3 and the hollow heat insulation area 4.

[0103] The first pattern can be square, semi-circular, triangular, etc. The wider side of the first pattern fits against the side of the first heat-insulating groove 3 closest to the spine. Furthermore, the side of the first pattern facing away from the spine is located in the middle region of the first heat-insulating groove 3. This results in a row of periodically arranged photolithographic patterns after the photolithography pattern is removed, exposing the surface of the corrosion-resistant structure 6 supporting the first heat-insulating groove 3 and the hollow heat-insulating region 4. For example... Figure 10 As shown, preferably, the position of the corresponding first pattern is exactly offset from the position of the second heat insulation groove 5, thereby making full use of the residual functional material layer between two adjacent pairs of second heat insulation grooves 5 to compensate for the weakening of the support effect caused by the multiple hole structure.

[0104] In step 303, an etching solution is injected into the first heat-insulating groove 3 after the above-mentioned photolithographic pattern has been fabricated. After etching for a preset time to form the support and corrosion-resistant structure 6 on the side of the first pattern facing the first heat-insulating groove 3 near the spine, the photoresist is removed to form the plurality of hole structures. The formed group structure is as follows: Figure 11 As shown.

[0105] Example 4:

[0106] This invention will describe the method implemented in embodiment 4 of the invention in actual practice from a relatively complete processing technology process, after elaborating on the relevant technical details.

[0107] like Figure 7 The image shown is a planar top view of a novel semiconductor laser chip structure. In a typical example of a thermally tunable laser chip, it includes, for example... Figure 7 The SOA region, front grating region, gain region, phase region, rear grating region, COA region, etc., shown are included, but are not limited to, the front grating region, phase region, and rear grating region shown in the figure, and those suitable for forming the second heat insulation groove 5, the first heat insulation groove 3, and the hollow heat insulation region 4 described in Embodiment 1 of the present invention. Furthermore, depending on the different structures of each region, the size of the individual second heat insulation groove 5, the size of the first heat insulation groove 3, the spacing between the second heat insulation grooves 5, and the spacing between the second heat insulation groove 5 and the first heat insulation groove 3 can be adjusted appropriately according to actual conditions. For example... Figure 7As shown, the heating part mainly includes two parts: resistor 7 and resistor electrode 8. Each resistor 7 is formed by sputtering above the dielectric layer, and each resistor 7 is connected to a set of resistor electrodes 8. This structure mainly reflects the basic principle of realizing the energization and heating mechanism of the present invention.

[0108] Depend on Figure 6 As can be seen, the chip is formed by stacking multiple materials on substrate 1, namely, a lower cladding layer 21, an overhead layer 22, a lower etch stop layer 23, a lower sacrificial layer 24, an upper etch stop layer 25, an upper sacrificial layer 26, an active layer 27, and a waveguide layer 28. The specific structure of the functional layer 2 depends on the actual scenario and can be one or more of the following: a laser layer structure, a detector layer structure, a modulator layer structure, or a passive waveguide layer structure.

[0109] In actual manufacturing, the heat generated by the chip during normal operation is mainly exchanged with the outside air through the substrate 1. The upper sacrificial layer 26 is composed of InP, and the active layer 27 is composed of InGaAsP. By growing multiple functional layers on top of the substrate, the gap between the resistor 7 and the substrate 1 is greatly increased, reducing the diffusion of heat generated by the resistor 7 to the substrate 1, thereby improving the thermal tuning efficiency of the chip.

[0110] The corresponding steps in Example 4 can be represented by the following detailed steps, such as... Figure 12 As shown, specifically, in step 401, a layered substrate is grown.

[0111] In step 402, a first dielectric layer is deposited, and a ridge waveguide structure A is fabricated by photolithography and etching, as shown in the figure. Figure 13 The markings show the grooves on both sides of the spine of the ridge waveguide.

[0112] In step 403, a second dielectric layer is deposited, and a second thermal insulation groove B is fabricated by photolithography, etching, and wet etching. The second thermal insulation groove B is as follows: Figure 13 As indicated.

[0113] In step 404, a third dielectric layer is deposited, and a first thermal insulation groove D is fabricated by photolithography, etching, and wet etching. The first thermal insulation groove D is as follows: Figure 13 As indicated.

[0114] In step 405, a dielectric layer, a resistor, and an electrode are deposited.

[0115] In step 406, a hollow heat insulation region C is created by corroding through the bottom of the second heat insulation groove 5, as shown in the figure. Figure 13 As indicated.

[0116] The layered substrate 1 described in step 401 specifically includes: growing a lower cladding layer 21 of InGaAs material, an overhead layer 22 of InP material, a lower etch stop layer 23 of InGaAsP material, a lower sacrificial layer 24 of InP material, an upper etch stop layer 25 of InGaAsP material, an upper sacrificial layer 26 of InP material, an active layer 27 of InGaAsP material, and a waveguide layer 28 of InGaAsP material on the InP substrate 1 in sequence.

[0117] As described in step 402, a first dielectric layer is deposited, and a ridge waveguide structure A is fabricated using photolithography and etching. Specifically, this includes: depositing a first dielectric layer to protect the portion outside the ridge waveguide structure A from etching or wet etching; defining the corresponding ridge waveguide A pattern on the chip surface using photolithography; performing RIE etching on the semiconductor chip based on the defined ridge waveguide A pattern, with the etching depth exceeding the waveguide layer 28, which is composed of InGaAsP material; alternatively, a hydrochloric acid solution (HCl:H3PO4=1:3) can be used to etch the waveguide layer 28, thereby forming trenches extending along the direction close to the substrate 1 on both sides of the semiconductor chip waveguide. After fabricating the ridge waveguide structure A pattern, the first dielectric layer can be removed by reactive ion etching and / or wet etching using an acidic etchant. After fabrication, the structure appears as shown below. Figure 14 The aforementioned structure.

[0118] As described in step 403, a second dielectric layer is deposited, and a second thermal insulation groove B is fabricated through photolithography, etching, and wet etching. Specifically, this includes: depositing a second dielectric layer to protect the area outside the structure of the second thermal insulation groove B, and using photolithography to define the position and size of the second thermal insulation groove B; then, under the protection of the second dielectric layer, performing RIE etching on the active layer 27 until reaching the upper sacrificial layer 26; then using a hydrochloric acid solution (HCl:H3PO4=1:3) to etch the upper sacrificial layer 26; then performing RIE etching on the upper etching stop layer 25 until reaching the lower sacrificial layer 24; continuing to use a hydrochloric acid solution (HCl:H3PO4=1:3) to etch the lower sacrificial layer 24 until reaching the overhead layer 22; and using InGaAsP material to restrict the etching solution from etching the InP material vertically downwards without drilling to the sides. Thus, the fabrication of the second thermal insulation groove B is completed.

[0119] As described in step 404, a third dielectric layer is deposited, and a first heat-insulating groove D is fabricated using photolithography, etching, and wet etching. Specifically, this includes: depositing a third dielectric layer; locating the position of the first heat-insulating groove D using photolithography; and, based on the material characteristics of each functional layer 2, selecting RIE etching, hydrochloric acid solution, or H2SO4 solution to etch the corresponding functional layer 2 until the substrate 1 is reached. A supporting corrosion-resistant structure 6 is then fixed to the inner wall of the first heat-insulating groove D using methods such as bonding. The supporting corrosion-resistant structure 6 can be a groove with small circular holes inside, each containing a supporting pillar, and completely fitted to the inner wall of the first heat-insulating groove D. Dielectric layers and / or metal oxides are deposited on the inner and outer layers of the integrally formed groove to achieve its heat-insulating effect. The resulting second heat-insulating groove 5 and first heat-insulating groove 3 exhibit the following characteristics: Figure 15 The structure shown.

[0120] The deposition of dielectric layer, resistor 7 and electrode as described in step 405 specifically includes: strictly controlling the deposition of resistor 7 and electrode materials by re-depositing dielectric layer and photolithography to ensure the original intention of resistance value and power application during chip design.

[0121] As described in step 406, the dielectric layer deposited on the electrode by the aforementioned process is removed by reactive ion etching and / or wet etching with an acidic etchant to ensure the normal power-carrying structure of the chip. Subsequently, the cavity thermal insulation region C is fabricated using photolithography. An acidic solution (H2O2 and H2SO4) is used to etch the lower etch stop layer InGaAsP material for a predetermined time. Then, a hydrochloric acid solution (HCl:H3PO4=1:3) is used to etch the lower sacrificial layer 24 and the void layer 22, hollowing out the lower sacrificial layer 24, the lower etch stop layer 23, and the void layer 22 below the ridge waveguide structure. A dielectric layer and / or metal oxide are deposited inside the first thermal insulation groove 3D and the hollowed-out thermal insulation region by sputtering or CVD to form a thermal insulation layer, further preventing heat transfer to the substrate.

[0122] Thus, by fixing the other functional layers 2 below the ridge waveguide structure to the supporting corrosion-resistant structure 6, the supporting corrosion-resistant structure 6 suspends and supports the ridge waveguide structure, thereby forming a suspended thermal insulation structure with cantilever support. After fabrication, it presents as follows: Figure 13 The hollowed-out structure C is shown.

[0123] The preset time is determined by those skilled in the art based on experience and analysis of the material properties of the lower corrosion stop layer 23, or by obtaining the relationship between material density, thickness, and corrosion rate through detailed testing experiments, thereby determining the time required for complete corrosion of the lower corrosion stop layer 23 as the preset time. The upper cross-section of the ridge waveguide structure A, the second heat insulation groove B, the void heat insulation region C, and the first heat insulation groove D, fabricated by photolithography, can be square, circular, or other shapes, depending on the actual situation, and is not specifically limited here.

[0124] In the embodiments of the present invention, the limiting descriptions such as "first" and "second" do not refer to a specific order. They are merely used to separate the corresponding limited objects from the same category and to facilitate the description of two or more different objects in the same category. They should not be interpreted as having a further limiting meaning.

[0125] In the embodiments of this invention, expressions such as "A and / or B" actually mean that the implementation can be implemented with A as an object, or with B as an object, or with a combination of A and B. A and B can also be replaced with specific subject name objects according to the needs of the specific description scenario.

[0126] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A novel thermally tunable laser chip, characterized in that, It includes a substrate (1) and multiple functional layers (2) grown sequentially on the substrate (1). The ridge waveguide of the laser is located on the axial direction of its light output. A first heat-insulating groove (3) is provided in the channel on both sides of the ridge waveguide, and at least one pair of second heat-insulating grooves (5) are etched on both sides of the ridge. The first heat-insulating groove (3) is formed by etching at least one functional layer (2). The inner wall of the first heat insulation groove (3) is grown with a support and corrosion-resistant structure (6) that has both corrosion-resistant and support functions. The supporting corrosion-resistant structure (6) has multiple hole structures, which are connected to the first heat insulation groove (3) to increase the heat insulation space of the first heat insulation groove (3); At least one functional layer (2) below the ridge waveguide is hollowed out to form a hollow heat insulation area (4). The two sides of the hollow heat insulation area (4) are adjacent to the first heat insulation groove (3), and the two are separated by the support corrosion-resistant structure (6). The plurality of hole structures are arranged on the support corrosion-resistant structure (6) between the first heat insulation groove (3) and the hollow heat insulation area (4).

2. The novel thermally tunable laser chip as described in claim 1, characterized in that, When multiple pairs of the second heat-insulating grooves (5) are included; The multiple hole structures are arranged at a preset interval along the laser optical axis, and the positions of the corresponding hole structures are offset from the positions of the second heat insulation grooves (5) so as to make up for the weakening of the support caused by the hole structures by using the functional layer material remaining between the two adjacent pairs of second heat insulation grooves (5).

3. The thermally tunable laser chip with the novel structure as described in claim 1 or 2, characterized in that, When multiple pairs of the second heat-insulating grooves (5) are included, the distance between each pair of the second heat-insulating grooves (5) extending along the laser axial direction and the adjacent pair of the second heat-insulating grooves (5) is exactly the same as the length of a grating region. Then, the multiple intervals formed by the multiple pairs of the second heat-insulating grooves (5) form a periodic structure consistent with the periodic grating region. In the interval between each pair of the second heat-insulating grooves (5) extending along the laser axial direction and the adjacent pair of the second heat-insulating grooves (5), the corresponding functional layers that were etched away in the second heat-insulating grooves are retained.

4. The novel thermally tunable laser chip as described in claim 1, characterized in that, The hollow heat insulation area (4) is formed by etching at least one pair of second heat insulation grooves (5) on both sides of the spine and then corroding through at least one functional layer (2) between the pair of second heat insulation grooves (5).

5. The thermally tunable laser chip with the novel structure as described in claim 4, characterized in that, The second heat insulation groove (5) is a portion of the channel located on both sides of the spine in the ridge waveguide, which is further etched in the direction towards the substrate (1); and the second heat insulation groove (5) is arranged parallel to the first heat insulation groove (3), with multiple functional layers suspended on the cavity heat insulation area (4) between them.

6. The novel thermally tunable laser chip according to claim 1, characterized in that, The supporting corrosion-resistant structure (6) consists of a layer adjacent to the first heat insulation groove (3) as the outermost layer, and the innermost layer includes a first layer of sputtered metal Ti and Pt, and a second layer of oxide film deposited by CVD.

7. The novel thermally tunable laser chip as described in claim 1, characterized in that, The plurality of functional layers (2) grown sequentially on the substrate (1) include at least one of the following: lower cladding layer (21), overhead layer (22), lower etch stop layer (23), lower sacrificial layer (24), upper etch stop layer (25), upper sacrificial layer (26), active layer (27), and waveguide layer (28).

8. The novel thermally tunable laser chip according to claim 1, characterized in that, It also includes two parts: resistors (7) and electrodes (8). Each resistor (7) is sputtered on the ridge waveguide of the laser above the dielectric layer, and each resistor (7) is connected to a set of electrodes.

9. A method for fabricating a thermally tunable laser chip with a novel structure as described in any one of claims 1-8, characterized in that, A method comprising pre-growing multiple functional layers (2) on a substrate (1) includes: A ridge waveguide structure is etched on the plurality of functional layers (2), wherein the channel of the ridge waveguide structure is etched to the active layer (27). The positions of the corresponding first heat insulation groove (3) and second heat insulation groove (5) are drawn by photolithography, and the first heat insulation groove (3) and second heat insulation groove (5) are obtained by etching and / or wet etching. A support corrosion-resistant structure (6) is grown on the inner wall of the first heat insulation groove (3); Photoresist is filled into the first heat insulation groove (3), and photolithography is performed at a predetermined interval according to the first pattern to a first depth along the laser optical axis to form a row of periodically arranged photolithographic patterns that expose the surface of the support corrosion-resistant structure (6) between the first heat insulation groove (3) and the cavity heat insulation area (4). Etching solution is injected into the first heat-insulating groove (3) with the above-mentioned photolithographic pattern, and etching is performed for a preset time. After etching multiple hole structures that are connected to the first heat-insulating groove (3) into the support corrosion-resistant structure (6), the photoresist in the first heat-insulating groove (3) is removed.

10. The method for fabricating a thermally tunable laser chip with the novel structure as described in claim 9, characterized in that, The position of the first pattern is offset from the position of the second heat insulation groove (5), so that the position of the multiple hole structures formed after corrosion is offset from the position of the second heat insulation groove (5).

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