Pixel circuit, display device, and display driving method

Abstract

The present application relates to a kind of pixel circuit capable of improving image display effect, display device and display driving method.The pixel circuit includes: first storage unit, with bit line connection, obtain odd frame image data from bit line and save;Second storage unit, with bit line connection, obtain even frame image data from bit line and save, odd frame image data and even frame image data are cyclically alternately written from bit line to pixel circuit;Output unit is respectively connected with first storage unit, second storage unit, when first storage unit has odd frame image data, output unit controls odd frame image data is output to the pixel electrode of pixel circuit, even frame image data and odd frame image data are alternately output to the pixel electrode;Second storage unit obtains even frame image data from bit line and save when odd frame image data is output to the pixel electrode of pixel circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a pixel circuit, a display device and a display driving method. BACKGROUND

[0002] Liquid Crystal On Silicon (LCOS) is a kind of reflective small size matrix liquid crystal display device.

[0003] The driving scheme of LCOS is to display the driving voltage of each row of pixels in turn for writing a frame of image, and to turn off the light source after the driving voltage of all pixels in a frame of image is written, so as to avoid the influence on the overall display effect when different frames of image are displayed at the same time.

[0004] However, the turning off of the light source will affect the display effect of the image. SUMMARY

[0005] Therefore, it is necessary to provide a pixel circuit, a display device and a display driving method capable of improving the display effect of the image.

[0006] In a first aspect, a pixel circuit is provided, which comprises:

[0007] a first storage unit connected with a bit line, and configured to obtain and save odd frame image data from the bit line;

[0008] a second storage unit connected with the bit line, and configured to obtain and save even frame image data from the bit line, wherein the odd frame image data and the even frame image data are alternately written from the bit line to the pixel circuit;

[0009] an output unit connected with the first storage unit and the second storage unit respectively, and configured to control the odd frame image data to be output to a pixel electrode of the pixel circuit when the first storage unit saves the odd frame image data, and to alternately output the even frame image data and the odd frame image data to the pixel electrode.

[0010] The second storage unit is configured to obtain and save the even frame image data from the bit line when the odd frame image data is output to the pixel electrode.

[0011] In a second aspect, a display device is provided, which comprises a plurality of bit lines and a plurality of pixel circuits provided in the first aspect; the plurality of pixel circuits are arranged into a plurality of rows along a first direction and a plurality of columns along a second direction, and the first direction and the second direction intersect; the plurality of bit lines correspond to the plurality of columns of pixel circuits one by one, and each bit line is connected with each pixel circuit in the corresponding column respectively.

[0012] In a third aspect, a display driving method is provided, which is applied to the pixel circuit provided in the first aspect, and the control method comprises:

[0013] When odd frame image data is written on the bit line, the first storage unit is controlled to obtain the odd frame image data from the bit line and save the odd frame image data;

[0014] When the first storage unit saves the odd frame image data, the odd frame image data is output to the pixel electrode; and

[0015] When the odd frame image data is output to the pixel electrode, the second storage unit is controlled to obtain even frame image data written on the bit line from the bit line and save the even frame image data;

[0016] The odd frame image data and the even frame image data are cyclically and alternately written from the bit line and alternately output to the pixel electrode.

[0017] The pixel circuit, the display device and the display driving method described above, the first storage unit obtains odd frame image data from the bit line and saves the odd frame image data, the second storage unit obtains even frame image data from the bit line and saves the even frame image data, the output unit controls the odd frame image data to be output to the pixel electrode of the pixel circuit when the first storage unit saves the odd frame image data, and the second storage unit obtains even frame image data from the bit line and saves the even frame image data when the odd frame image data is output to the pixel electrode, so that the output of the odd frame image data from the first storage unit to the pixel electrode is synchronized with the saving of the even frame image data on the bit line in the second storage unit, and thus the even frame image data can be output from the second storage unit to the pixel electrode after the odd frame image data is output from the first storage unit to the pixel electrode, and the even frame image can be displayed immediately after the odd frame image is displayed by lighting the pixel light source, and the power supply does not need to be turned off between the display of different frame images. Moreover, the odd frame image data and the even frame image data are cyclically and alternately written from the bit line to the pixel circuit and alternately output to the pixel electrode, and the simultaneous display of different frame images can also be avoided. Therefore, the application can reduce the interval time between different frame images, improve the refresh speed and overall brightness of the image, and further improve the display effect of the image. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0019] Figure 1A structural block diagram of a display device provided for an embodiment;

[0020] Figure 2 A structural schematic diagram of a pixel circuit provided for an embodiment;

[0021] Figure 3 For Figure 1 A specific circuit diagram of the first storage unit and the second storage unit in the embodiment;

[0022] Figure 4 For Figure 1 A specific circuit diagram of the output unit in the embodiment;

[0023] Figure 5 A graph of the relationship between the transmission ratio and the applied voltage;

[0024] Figure 6 A flow chart of a display driving method provided for an embodiment;

[0025] Figure 7 A timing chart of each signal line provided for an embodiment.

[0026] Explanation of reference numerals:

[0027] 1000 - display device, 100 - pixel unit, 200 - scan line, 300 - data line, 400 - pixel circuit;

[0028] 10 - first storage unit, 20 - second storage unit, 30 - output unit. DETAILED DESCRIPTION

[0029] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The embodiments of the present application are given in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0031] It can be understood that the terms "first", "second", and the like used herein can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the other element. For example, without departing from the scope of the present application, a first resistor can be referred to as a second resistor, and similarly, a second resistor can be referred to as a first resistor. The first resistor and the second resistor are both resistors, but they are not the same resistor.

[0032] It can be understood that, in the following embodiments, “connection” should be understood as “electrical connection”, “communication connection” and the like if the circuits, modules, units and the like connected with each other have transmission of electrical signals or data.

[0033] As used herein, the singular forms “a”, “an” and “the” include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms “comprises”, “comprising”, “includes” and / or “including”, or the like, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

[0034] Referring to Figure 1 , a structural schematic diagram of a display device 1000 in an embodiment of the present application is shown. The display device 1000 includes a plurality of pixel units 100, a plurality of scan lines 200 and a plurality of data lines 300. The plurality of scan lines 200 and the plurality of data lines 300 cross to define the plurality of pixel units 100, and each pixel unit 100 includes a pixel circuit 400. The pixel units 100 in the same row are connected to the same scan line 200, and the pixel units 100 in the same column are connected to the same data line 300. According to the row scan signals output in sequence on each scan line 200, the data on each data line 300 is written into each row of pixel units 100 in sequence for display. After the data is written into each row of pixel units 100, the display of one frame of image is completed. At this time, if the next frame of image data is directly written into each row of pixel units 100 in sequence for display, because the pixel units 100 in different rows are written with data in different sequences, the pixel units 100 in the front row display the current frame of image, and the pixel units 100 in the rear row display the previous frame of image, i.e., two frames of images are displayed on the display device 1000 at the same time, thereby affecting the overall display effect.

[0035] For the LCoS display device, in order to avoid the display device 1000 from displaying different frames of images at the same time, in the related art, after each row of pixel units 100 is written with the current frame of image data for display, the light source of the LCoS display device is first turned off, and then the next frame of image data is written into each row of pixel units 100 in sequence while the light source is turned off, and then the light source is turned on for display, thereby avoiding the display of two frames of images at the same time. However, the turning off of the light source occupies a certain time, which affects the display effect of the image, such as the display brightness of the image.

[0036] To solve the above problems, the embodiment of the present application provides a pixel circuit, a display device and a display driving method. The first storage unit and the second storage unit of the pixel circuit alternately obtain image data from the bit line and save, and alternately output the saved image data to the pixel electrode through the output unit, so that the odd frame image data is output from the first storage unit to the pixel electrode, and the even frame image data is saved in the second storage unit synchronously. Therefore, after the odd frame image data is output from the first storage unit to the pixel electrode, the even frame image data can be output from the second storage unit to the pixel electrode, and the pixel light source can display the even frame image immediately after displaying the odd frame image, without turning off the power supply between displaying different frame images. Therefore, the present application can reduce the interval time between different frame images, improve the refresh speed and overall brightness of the image, and further improve the display effect of the image.

[0037] Referring to Figure 2 , which is a structural block diagram of a pixel circuit 400 provided by an embodiment of the present application. The pixel circuit 400 includes a first storage unit 10, a second storage unit 20 and an output unit 30. The first storage unit 10 is connected with a bit line (BL) to obtain and save odd frame image data from the bit line. The second storage unit 20 is connected with the bit line to obtain and save even frame image data from the bit line. When displaying an image, the display device 1000 sequentially loads different frame image data from the bit line. In the embodiment of the present application, the odd frame image data and the even frame image data are alternately written from the bit line to the pixel circuit 400, wherein one odd frame image data and one even frame image data are two frame image data sequentially displayed by the display device 1000. The output unit 30 is connected with the first storage unit 10 and the second storage unit 20 respectively. When the first storage unit 10 saves the odd frame image data, the output unit 30 controls the odd frame image data to be output to the pixel electrode of the pixel circuit, and the even frame image data and the odd frame image data are alternately output to the pixel electrode. When the odd frame image data is output to the pixel electrode, the second storage unit 20 obtains and saves the even frame image data from the bit line.

[0038] The bit line is a data line, and the odd frame image data and the even frame image data are alternately written on the bit line. In the embodiment of the present application, the time period of writing the odd frame image data on the bit line is defined as the first stage, and the time period of writing the even frame image data on the bit line is defined as the second stage. In this way, the first stage and the second stage appear alternately, that is, the second stage appears after the first stage, the first stage appears after the second stage, and the first stage, the second stage, the first stage and the second stage appear in turn. In other embodiments, the time period of writing the even frame image data on the bit line is defined as the second stage, and the time period of writing the odd frame image data on the bit line is defined as the first stage.

[0039] Specifically, in the first stage, odd frame image data is written on the bit line, and the first storage unit 10 acquires the odd frame image data from the bit line and saves it. In the second stage, even frame image data is written on the bit line, and the second storage unit 20 acquires the even frame image data from the bit line and saves it. When the first storage unit 10 has saved the image data, the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode (not shown in the figure) of the pixel circuit 400, and when the pixel electrode acquires the image data, the light source of the pixel is lit. When the second storage unit 20 has saved the even frame image data, the output unit 30 outputs the even frame image data in the second storage unit 20 to the pixel electrode. In the embodiment of the present application, when the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode of the pixel circuit 400, the second stage can be entered at the same time, and the second storage unit 20 is controlled to acquire and save the even frame image data from the bit line. That is, in the first first stage, the first storage unit 10 acquires and saves the odd frame image data from the bit line; in the first second stage, the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode of the pixel circuit 400, and at the same time, the second storage unit 20 acquires and saves the even frame image data from the bit line. In the next first stage, the first storage unit 10 acquires and saves the odd frame image data from the bit line.

[0040] In other embodiments, when the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode, the second stage is not entered synchronously, but after the odd frame image data in the first storage unit 10 is output to the pixel electrode, the second stage is entered, and the second storage unit 20 is controlled to acquire and save the even frame image data from the bit line.

[0041] In other embodiments, in the first stage, even frame image data is written on the bit line, and the second storage unit 20 obtains the even frame image data from the bit line and saves it. In the second stage, odd frame image data is written on the bit line, and the first storage unit 10 obtains the odd frame image data from the bit line and saves it. When the first storage unit 10 saves the image data, the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode (not shown in the figure) of the pixel circuit 400, and when the pixel electrode obtains the image data, the light source of the pixel is lit. When the second storage unit 20 saves the even frame image data, the output unit 30 outputs the even frame image data in the second storage unit 20 to the pixel electrode. In the embodiments of the present application, when the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode of the pixel circuit 400, the first stage can be entered at the same time, and the second storage unit 20 is controlled to obtain and save the even frame image data from the bit line. That is, in the first second stage, the first storage unit 10 obtains and saves the odd frame image data from the bit line; in the second first stage, the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode of the pixel circuit 400, and at the same time, the second storage unit 20 obtains and saves the even frame image data from the bit line. In the next second stage, the first storage unit 10 obtains and saves the odd frame image data from the bit line.

[0042] The pixel circuit described above comprises a first storage unit, a second storage unit and an output unit, the first storage unit obtains and saves odd frame image data from a bit line, the second storage unit obtains and saves even frame image data from the bit line, and the output unit controls the odd frame image data to be output to a pixel electrode of the pixel circuit when the first storage unit saves the odd frame image data, and the second storage unit obtains and saves even frame image data from the bit line when the odd frame image data is output to the pixel electrode, so that the output of the odd frame image data from the first storage unit to the pixel electrode is synchronized with the saving of the even frame image data from the bit line in the second storage unit. Therefore, after the odd frame image data is output from the first storage unit to the pixel electrode, the even frame image data can be output from the second storage unit to the pixel electrode, and the even frame image can be displayed immediately after the odd frame image is displayed, without the need to turn off the power supply between the display of different frame images. Moreover, the odd frame image data and the even frame image data are written from the bit line to the pixel circuit alternately and output to the pixel electrode alternately, so that the simultaneous display of different frame images can also be avoided. Therefore, the present application can reduce the interval time between different frame images, improve the refresh speed and overall brightness of the image, and further improve the display effect of the image.

[0043] In addition, the entire pixel circuit can be integrated together, without the need to separately provide a control part outside, which is conducive to reducing the overall occupied area and reducing the control difficulty.

[0044] In some embodiments, the output unit 30 also controls the output of the even frame image data to the pixel electrode when the second storage unit 20 stores the even frame image data. The first storage unit 10 acquires the next odd frame image data written by the bit line and stores the odd frame image data from the bit line when the odd frame image data is output to the pixel electrode.

[0045] Specifically, in the first stage, the odd frame image data is written on the bit line, and the first storage unit 10 acquires the odd frame image data from the bit line and stores the odd frame image data. In the second stage, the even frame image data is written on the bit line, and the second storage unit 20 acquires the even frame image data from the bit line and stores the even frame image data. When the first storage unit 10 stores the image data, the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode (not shown in the figure) of the pixel circuit 400, and when the pixel electrode acquires the image data, the light source of the pixel can be lit. When the second storage unit 20 stores the even frame image data, the output unit 30 outputs the even frame image data in the second storage unit 20 to the pixel electrode. In the embodiments of the present application, when the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode of the pixel circuit 400, the second stage can be entered at the same time, and the second storage unit 20 is controlled to acquire and store the even frame image data from the bit line; when the output unit 30 outputs the even frame image data in the second storage unit 20 to the pixel electrode of the pixel circuit 400, the first stage can be entered at the same time, and the first storage unit 10 is controlled to acquire and store the odd frame image data from the bit line. That is, in the first first stage, the first storage unit 10 acquires and stores the odd frame image data from the bit line; in the first second stage, the output unit 30 outputs the odd frame image data in the first storage unit 10 to the pixel electrode of the pixel circuit 400, and at the same time, the second storage unit 20 acquires and stores the even frame image data from the bit line. In the next first stage, the output unit 30 outputs the even frame image data in the second storage unit 20 to the pixel electrode of the pixel circuit 400, and at the same time, the first storage unit 10 acquires and stores the odd frame image data from the bit line. In other embodiments, the time period in which the even frame image data is written on the bit line is defined as the first stage, and the time period in which the odd frame image data is written on the bit line is defined as the second stage. In the first stage, the even frame image data is written on the bit line, and the second storage unit 20 acquires the even frame image data from the bit line and stores the even frame image data; in the second stage, the odd frame image data is written on the bit line, and the first storage unit 10 acquires the odd frame image data from the bit line and stores the odd frame image data. In the first first stage, the output unit 30 controls the second storage unit 20 to acquire the even frame image data from the bit line, and in the first second stage, the output unit 30 controls the first storage unit 10 to acquire the odd frame image data from the bit line.

[0046] In the first first stage, when the first storage unit 10 stores odd frame image data, the output unit 30 controls the second storage unit 20 to acquire even frame image data from the bit line and outputs the odd frame image data stored in the first storage unit 10 to the pixel electrode; when the first storage unit 10 does not store odd frame image data, the output unit 30 only controls the second storage unit 20 to acquire even frame image data from the bit line. Similarly, in the first second stage, when the second storage unit 20 stores even frame image data, the output unit 30 controls the first storage unit 10 to acquire odd frame image data from the bit line and outputs the even frame image data stored in the second storage unit 20 to the pixel electrode; when the second storage unit 20 does not store even frame image data, the output unit 30 only controls the first storage unit 10 to acquire odd frame image data from the bit line.

[0047] In another first stage, even frame image data is written in the bit line, the second storage unit 20 acquires even frame image data from the bit line and stores it, while the output unit 30 outputs the odd frame image data stored in the first storage unit 10 to the pixel electrode to light up the pixel light source. In another second stage, odd frame image data is written in the bit line, the first storage unit 10 acquires odd frame image data from the bit line and stores it, while the output unit 30 outputs the even frame image data in the second storage unit 20 to the pixel electrode to light up the pixel light source. The cycle continues.

[0048] In the above embodiment, the output unit also controls the output of even frame image data to the pixel electrode when the second storage unit stores even frame image data, and the first storage unit acquires the next odd frame image data written in the bit line from the bit line and stores it when the even frame image data is output to the pixel electrode, so that the output of even frame image data to the pixel electrode is synchronized with the storage of odd frame image data in the bit line in the first storage unit. Thus, after the output of even frame image data from the second storage unit to the pixel electrode, odd frame image data can be output from the first storage unit to the pixel electrode, and the display of odd frame image data can be immediately displayed after the display of even frame image data, so that the display of odd frame image and even frame image is alternated, and the power supply can be turned off between the display of any two adjacent frames of image, which can minimize the interval time between different frames of image, effectively improve the refresh speed and overall brightness of the image, and further improve the display effect of the image.

[0049] Referring to Figure 3, as shown in a specific circuit diagram of the pixel circuit 400. In some embodiments, the bit line includes a first bit line BLB, and the first storage unit 10 and the second storage unit 20 each include a first switch tube T1, a second switch tube T2, and a third switch tube T3. The on-off condition of the first switch tube T1 is opposite to that of the second switch tube T2. The control end of the third switch tube T3 of the first storage unit 10 is connected to the first word line WL0 of the pixel circuit, and the control end of the third switch tube T3 of the second storage unit 20 is connected to the second word line WL1 of the pixel circuit. The first end of the third switch tube T3 is connected to the first bit line BLB, and the second end of the third switch tube T3 is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2. The first end of the first switch tube T1 and the first end of the second switch tube T2 are connected to the output unit 30, and the second end of the first switch tube T1 is connected to a first working voltage, and the second end of the second switch tube T2 is connected to a second working voltage.

[0050] The first word line WL0 and the second word line WL1 are scanning lines.

[0051] Exemplarily, the first switch tube T1 is a P-type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), the second switch tube T2 is an N-type MOSFET, and the third switch tube T3 is an N-type MOSFET.

[0052] The first working voltage is a power supply voltage (i.e., a high level), and the second working voltage is a ground voltage (i.e., a low level).

[0053] In the present embodiment, the first word line WL0 is connected to a high level in the first stage and to a low level in the second stage, and the second word line WL1 is connected to a low level in the first stage and to a high level in the second stage. In other embodiments, the first word line WL0 is connected to a low level in the first stage and to a high level in the second stage, and the second word line WL1 is connected to a high level in the first stage and to a low level in the second stage. That is, only one of the first word line WL0 and the second word line WL1 is connected to a high level and the other is connected to a low level in the same stage.

[0054] Specifically, in the first stage, when the first word line WL0 is accessed to high level, the control end of the third switch tube T3 of the first storage unit 10 is high level. Since the third switch tube T3 is N type MOSFET, the first end and the second end of the third switch tube T3 of the first storage unit 10 are connected, i.e. the first bit line BLB is connected with the control end of the first switch tube T1 of the first storage unit 10 and the control end of the second switch tube T2 of the first storage unit 10. At the same time, the second word line WL1 is accessed to low level, the control end of the third switch tube T3 of the second storage unit 20 is low level. Since the third switch tube T3 is N type MOSFET, the first end and the second end of the third switch tube T3 of the second storage unit 20 are disconnected, i.e. the first bit line BLB is disconnected with the control end of the first switch tube T1 of the second storage unit 20 and the control end of the second switch tube T2 of the second storage unit 20.

[0055] If the first bit line BLB is accessed to high level, the control end of the first switch tube T1 of the first storage unit 10 and the control end of the second switch tube T2 of the first storage unit 10 are high level. Since the first switch tube T1 is P type MOSFET and the second switch tube T2 is N type MOSFET, the first end and the second end of the first switch tube T1 of the first storage unit 10 are disconnected, and the first end and the second end of the second switch tube T2 of the first storage unit 10 are connected. Since the first end of the first switch tube T1 is connected with the first end of the second switch tube T2 and the second end of the second switch tube T2 is accessed to the second working voltage, the first end of the first switch tube T1 of the first storage unit 10 and the first end of the second switch tube T2 of the first storage unit 10 are accessed to the second working voltage, i.e. low level, which is opposite to the voltage accessed by the first bit line BLB.

[0056] If the first bit line BLB is accessed to low level, the control end of the first switch tube T1 of the first storage unit 10 and the control end of the second switch tube T2 of the first storage unit 10 are low level. Since the first switch tube T1 is P type MOSFET and the second switch tube T2 is N type MOSFET, the first end and the second end of the first switch tube T1 of the first storage unit 10 are connected, and the first end and the second end of the second switch tube T2 of the first storage unit 10 are disconnected. Since the first end of the first switch tube T1 is connected with the first end of the second switch tube T2 and the second end of the first switch tube T1 is accessed to the first working voltage, the first end of the first switch tube T1 of the first storage unit 10 and the first end of the second switch tube T2 of the first storage unit 10 are accessed to the first working voltage, i.e. high level, which is opposite to the voltage accessed by the first bit line BLB.

[0057] No matter whether the first bit line BLB is connected to high level or low level, the first end of the first switch tube Tl of the first storage unit 10 and the first end of the second switch tube T2 of the first storage unit 10 are connected to the opposite voltage of the first bit line BLB, so that the first storage unit 10 obtains the data on the bit line and saves it.

[0058] In the second stage, when the first word line WL0 is connected to low level, the control end of the third switch tube T3 of the first storage unit 10 is low level. Since the third switch tube T3 is N-type MOSFET, the first end and the second end of the third switch tube T3 of the first storage unit 10 are disconnected, i.e. the first bit line BLB is disconnected from the control end of the first switch tube Tl of the first storage unit 10 and the control end of the second switch tube T2 of the first storage unit 10. At the same time, the second word line WL1 is connected to high level, and the control end of the third switch tube T3 of the second storage unit 20 is high level. Since the third switch tube T3 is N-type MOSFET, the first end and the second end of the third switch tube T3 of the second storage unit 20 are connected, i.e. the first bit line BLB is connected to the control end of the first switch tube Tl of the second storage unit 20 and the control end of the second switch tube T2 of the second storage unit 20.

[0059] If the first bit line BLB is connected to high level, the control end of the first switch tube Tl of the second storage unit 20 and the control end of the second switch tube T2 of the second storage unit 20 are high level. Since the first switch tube Tl is P-type MOSFET and the second switch tube T2 is N-type MOSFET, the first end and the second end of the first switch tube Tl of the second storage unit 20 are disconnected, and the first end and the second end of the second switch tube T2 of the second storage unit 20 are connected. Since the first end of the first switch tube Tl is connected to the first end of the second switch tube T2, and the second end of the second switch tube T2 is connected to the second working voltage, the first end of the first switch tube Tl of the second storage unit 20 and the first end of the second switch tube T2 of the second storage unit 20 are connected to the second working voltage, i.e. low level, which is opposite to the first bit line BLB.

[0060] If the first bit line BLB is connected to a low level, then the control terminals of the first switching transistor T1 and the second switching transistor T2 of the second storage unit 20 are at a low level. Since the first switching transistor T1 is a P-type MOSFET and the second switching transistor T2 is an N-type MOSFET, the first and second terminals of the first switching transistor T1 of the second storage unit 20 are connected, while the first and second terminals of the second switching transistor T2 of the second storage unit 20 are disconnected. Furthermore, since the first terminal of the first switching transistor T1 is connected to the first terminal of the second switching transistor T2, and the second terminal of the first switching transistor T1 is connected to the first operating voltage, the first terminals of the first switching transistor T1 and the first terminal of the second switching transistor T2 of the second storage unit 20 are connected to the first operating voltage, i.e., a high level, which is opposite to the first bit line BLB.

[0061] Regardless of whether the first bit line BLB is connected to a high level or a low level, the voltages connected to the first terminal of the first switch transistor T1 of the second storage unit 20 and the first terminal of the second switch transistor T2 of the second storage unit 20 are opposite to those connected to the first bit line BLB, thereby enabling the second storage unit 20 to acquire and save data on the bit line.

[0062] like Figure 3 As shown, exemplarily, the bit line also includes a second bit line BL, the data on the second bit line BL being opposite to the data on the first bit line BLB at the same time. The first storage unit 10 and the second storage unit 20 also include a fourth switch transistor T4, a fifth switch transistor T5, and a sixth switch transistor T6, respectively, the on / off conditions of the fifth switch transistor T5 being opposite to those of the sixth switch transistor T6. The control terminal of the fourth switch transistor T4 in the first storage unit 10 is connected to the first word line WL0, and the control terminal of the fourth switch transistor T4 in the second storage unit 20 is connected to the second word line WL1. The first end of the fourth switch transistor T4 is connected to the second bit line BL, and the second end of the fourth switch transistor T4 is connected to the first end of the first switch transistor T1, the first end of the second switch transistor T2, the control terminal of the fifth switch transistor T5, and the control terminal of the sixth switch transistor T6. The first ends of the fifth switch transistor T5 and the sixth switch transistor T6 are connected to the control terminals of the first switch transistor T1 and the second switch transistor T2, respectively. The second end of the fifth switch transistor T5 is connected to a first operating voltage, and the second end of the sixth switch transistor T6 is connected to a second operating voltage.

[0063] For example, the fourth switch T4 is an N-type MOSFET, the fifth switch T5 is a P-type MOSFET, and the sixth switch T6 is an N-type MOSFET.

[0064] Specifically, in the first stage, when the first word line WL0 is accessed to high level, the control end of the fourth switch tube T4 of the first storage unit 10 is high level. Since the fourth switch tube T4 is N-type MOSFET, the first end and the second end of the fourth switch tube T4 of the first storage unit 10 are connected, that is, the second bit line BL is connected with the control end of the fifth switch tube T5 of the first storage unit 10 and the control end of the sixth switch tube T6 of the first storage unit 10. At the same time, the second word line WL1 is accessed to low level, and the control end of the fourth switch tube T4 of the second storage unit 20 is low level. Since the fourth switch tube T4 is N-type MOSFET, the first end and the second end of the fourth switch tube T4 of the second storage unit 20 are disconnected, that is, the second bit line BL is disconnected with the control end of the fifth switch tube T5 of the second storage unit 20 and the control end of the sixth switch tube T6 of the second storage unit 20.

[0065] If the first bit line BLB is accessed to high level and the second bit line BL is accessed to low level, the control end of the first switch tube T1 of the first storage unit 10 and the control end of the second switch tube T2 of the first storage unit 10 are high level, and the control end of the fifth switch tube T5 of the first storage unit 10 and the control end of the sixth switch tube T6 of the first storage unit 10 are low level. Since the first switch tube T1 is P-type MOSFET, the second switch tube T2 is N-type MOSFET, the fifth switch tube T5 is P-type MOSFET, and the sixth switch tube T6 is N-type MOSFET, the first end and the second end of the first switch tube T1 of the first storage unit 10 are disconnected, the first end and the second end of the second switch tube T2 of the first storage unit 10 are connected, the first end and the second end of the fifth switch tube T5 of the first storage unit 10 are connected, and the first end and the second end of the sixth switch tube T6 of the first storage unit 10 are disconnected. Since the first end of the first switch tube T1 is connected with the first end of the second switch tube T2, and the second end of the second switch tube T2 is accessed to the second working voltage, the first end of the first switch tube T1 of the first storage unit 10 and the first end of the second switch tube T2 of the first storage unit 10 are accessed to the second working voltage (i.e. low voltage, same as the second bit line BL); since the first end of the fifth switch tube T5 is connected with the first end of the sixth switch tube T6, and the second end of the fifth switch tube T5 is accessed to the first working voltage, the first end of the fifth switch tube T5 of the first storage unit 10 and the first end of the sixth switch tube T6 of the first storage unit 10 are accessed to the first working voltage (i.e. high voltage, same as the first bit line BLB), so as to realize that the first storage unit 10 acquires data on the bit line and saves.

[0066] If the first bit line BLB is connected to low voltage and the second bit line BL is connected to high voltage, the control end of the first switch tube T1 of the first storage unit 10 and the control end of the second switch tube T2 of the first storage unit 10 are connected to low voltage, and the control end of the fifth switch tube T5 of the first storage unit 10 and the control end of the sixth switch tube T6 of the first storage unit 10 are connected to high voltage. Since the first switch tube T1 is a P-type MOSFET, the second switch tube T2 is an N-type MOSFET, the fifth switch tube T5 is a P-type MOSFET, and the sixth switch tube T6 is an N-type MOSFET, the first end and the second end of the first switch tube T1 of the first storage unit 10 are connected, the first end and the second end of the second switch tube T2 of the first storage unit 10 are disconnected, the first end and the second end of the fifth switch tube T5 of the first storage unit 10 are disconnected, and the first end and the second end of the sixth switch tube T6 of the first storage unit 10 are connected. Since the first end of the first switch tube T1 is connected to the first end of the second switch tube T2, and the second end of the first switch tube T1 is connected to the first working voltage, the first end of the first switch tube T1 of the first storage unit 10 and the first end of the second switch tube T2 of the first storage unit 10 are connected to the first working voltage (i.e. high voltage, same as the second bit line BL). Since the first end of the fifth switch tube T5 is connected to the first end of the sixth switch tube T6, and the second end of the sixth switch tube T6 is connected to the second working voltage, the first end of the fifth switch tube T5 of the first storage unit 10 and the first end of the sixth switch tube T6 of the first storage unit 10 are connected to the second working voltage (i.e. low voltage, same as the first bit line BLB), so that the first storage unit 10 obtains the data on the bit line and stores it.

[0067] In the second stage, when the first word line WL0 is connected to low voltage, the control end of the fourth switch tube T4 of the first storage unit 10 is connected to low voltage. Since the fourth switch tube T4 is an N-type MOSFET, the first end and the second end of the fourth switch tube T4 of the first storage unit 10 are disconnected, i.e. the second bit line BL is disconnected from the control end of the fifth switch tube T5 of the first storage unit 10 and the control end of the sixth switch tube T6 of the first storage unit 10. At the same time, the second word line WL1 is connected to high voltage, and the control end of the fourth switch tube T4 of the second storage unit 20 is connected to high voltage. Since the fourth switch tube T4 is an N-type MOSFET, the first end and the second end of the fourth switch tube T4 of the second storage unit 20 are connected, i.e. the second bit line BL is connected to the control end of the fifth switch tube T5 of the second storage unit 20 and the control end of the sixth switch tube T6 of the second storage unit 20.

[0068] If the first bit line BLB is connected to high level and the second bit line BL is connected to low level, the control end of the first switch tube T1 of the second storage unit 20 and the control end of the second switch tube T2 of the second storage unit 20 are high level, and the control end of the fifth switch tube T5 of the second storage unit 20 and the control end of the sixth switch tube T6 of the second storage unit 20 are low level. Since the first switch tube T1 is a P-type MOSFET, the second switch tube T2 is an N-type MOSFET, the fifth switch tube T5 is a P-type MOSFET, and the sixth switch tube T6 is an N-type MOSFET, the first end and the second end of the first switch tube T1 of the second storage unit 20 are disconnected, the first end and the second end of the second switch tube T2 of the second storage unit 20 are connected, the first end and the second end of the fifth switch tube T5 of the second storage unit 20 are connected, and the first end and the second end of the sixth switch tube T6 of the second storage unit 20 are disconnected. Since the first end of the first switch tube T1 is connected to the first end of the second switch tube T2, and the second end of the second switch tube T2 is connected to the second working voltage, the first end of the first switch tube T1 of the second storage unit 20 and the first end of the second switch tube T2 of the second storage unit 20 are connected to the second working voltage (i.e. low voltage, same as the second bit line BL); since the first end of the fifth switch tube T5 is connected to the first end of the sixth switch tube T6, and the second end of the fifth switch tube T5 is connected to the first working voltage, the first end of the fifth switch tube T5 of the second storage unit 20 and the first end of the sixth switch tube T6 of the second storage unit 20 are connected to the first working voltage (i.e. high voltage, same as the first bit line BLB), so as to realize that the second storage unit 20 obtains the data on the bit line and saves it.

[0069] If the first bit line BLB is connected to low voltage and the second bit line BL is connected to high voltage, the control end of the first switch T1 of the second storage unit 20 and the control end of the second switch T2 of the second storage unit 20 are connected to low voltage, and the control end of the fifth switch T5 of the second storage unit 20 and the control end of the sixth switch T6 of the second storage unit 20 are connected to high voltage. Since the first switch T1 is a P-type MOSFET, the second switch T2 is an N-type MOSFET, the fifth switch T5 is a P-type MOSFET, and the sixth switch T6 is an N-type MOSFET, the first end and the second end of the first switch T1 of the second storage unit 20 are connected, the first end and the second end of the second switch T2 of the second storage unit 20 are disconnected, the first end and the second end of the fifth switch T5 of the second storage unit 20 are disconnected, and the first end and the second end of the sixth switch T6 of the second storage unit 20 are connected. Since the first end of the first switch T1 is connected to the first end of the second switch T2, and the second end of the first switch T1 is connected to the first working voltage, the first end of the first switch T1 of the second storage unit 20 and the first end of the second switch T2 of the second storage unit 20 are connected to the first working voltage (i.e. high voltage, same as the second bit line BL). Since the first end of the fifth switch T5 is connected to the first end of the sixth switch T6, and the second end of the sixth switch T6 is connected to the second working voltage, the first end of the fifth switch T5 of the second storage unit 20 and the first end of the sixth switch T6 of the second storage unit 20 are connected to the second working voltage (i.e. low voltage, same as the first bit line BLB), thereby realizing that the first storage unit 10 acquires data on the bit line and saves it.

[0070] In the embodiment, the first switch T1 and the second switch T2 form an inverter, the fifth switch T5 and the sixth switch T6 form another inverter, and the two inverters form a mutual locking structure, thereby realizing the saving of data.

[0071] Please refer to Figure 4 , which is a specific circuit diagram of the transmission control unit 30 in some embodiments of the application. In some embodiments, the output unit 30 includes the seventh switch T7 and the eighth switch T8 with opposite on-off conditions, the control end of the seventh switch T7 and the control end of the eighth switch T8 are connected to the first enable signal line EN, the first end of the seventh switch T7 is connected to the first storage unit 10, the first end of the eighth switch T8 is connected to the second storage unit 20, and the second end of the seventh switch T7 and the second end of the eighth switch T8 are connected to the pixel electrode.

[0072] For example, the seventh switch T7 is an N-type MOSFET, and the eighth switch T8 is a P-type MOSFET.

[0073] The first enable signal line EN is connected to low in the first stage and connected to high in the second stage, and the second enable signal line ENB is connected to high in the first stage and connected to low in the second stage.

[0074] Specifically, in the first stage, the first enable signal line EN is connected to low, and the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are connected to low. Since the seventh switch tube T7 is an N-type MOSFET and the eighth switch tube T8 is a P-type MOSFET, the first end and the second end of the seventh switch tube T7 are disconnected, and the first end and the second end of the eighth switch tube T8 are connected, that is, the first storage unit 10 is disconnected with the pixel electrode, and the second storage unit 20 is connected with the pixel electrode, so as to realize that the output unit 30 outputs the data in the second storage unit 20 to the pixel electrode.

[0075] In the second stage, the first enable signal line EN is connected to high, and the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are connected to high. Since the seventh switch tube T7 is an N-type MOSFET and the eighth switch tube T8 is a P-type MOSFET, the first end and the second end of the seventh switch tube T7 are connected, and the first end and the second end of the eighth switch tube T8 are disconnected, that is, the first storage unit 10 is connected with the pixel electrode, and the second storage unit 20 is disconnected with the pixel electrode, so as to realize that the output unit 30 outputs the data in the first storage unit 10 to the pixel electrode.

[0076] As shown in the figure, Figure 4 Exemplarily, the output unit 30 further includes a ninth switch tube T9 and a tenth switch tube T10, the on-off condition of the ninth switch tube T9 is opposite to that of the seventh switch tube T7, and the on-off condition of the tenth switch tube T10 is opposite to that of the eighth switch tube T8. The control end of the ninth switch tube T9 and the control end of the tenth switch tube T10 are connected with the second enable signal line ENB, and the signal on the second enable signal line ENB is opposite to that on the first enable signal line EN at the same time. The first end of the ninth switch tube T9 is connected with the first storage unit 10 and the first end of the seventh switch tube T7, and the first end of the tenth switch tube T10 is connected with the second storage unit 20 and the first end of the eighth switch tube T8. The second end of the ninth switch tube T9 and the second end of the tenth switch tube T10 are connected with the pixel electrode, the second end of the seventh switch tube T7 and the second end of the eighth switch tube T8.

[0077] Exemplarily, the ninth switch tube T9 is a P-type MOSFET, and the tenth switch tube T10 is an N-type MOSFET.

[0078] Specifically, in the first stage, the first enable signal line EN is connected to low, the second enable signal line ENB is connected to high, the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are low, and the control end of the ninth switch tube T9 and the control end of the tenth switch tube T10 are high. Since the seventh switch tube T7 is an N-type MOSFET, the eighth switch tube T8 is a P-type MOSFET, the ninth switch tube T9 is a P-type MOSFET, and the tenth switch tube T10 is an N-type MOSFET, the first end and the second end of the seventh switch tube T7 are disconnected, the first end and the second end of the eighth switch tube T8 are connected, the first end and the second end of the ninth switch tube T9 are disconnected, and the first end and the second end of the tenth switch tube T10 are connected, that is, the first storage unit 10 is disconnected with the pixel electrode, and the second storage unit 20 is connected with the pixel electrode, so as to realize that the output unit 30 outputs the data in the second storage unit 20 to the pixel electrode.

[0079] In the second stage, the first enable signal line EN is connected to high, the second enable signal line ENB is connected to low, the control end of the seventh switch tube T7 and the control end of the eighth switch tube T8 are high, and the control end of the ninth switch tube T9 and the control end of the tenth switch tube T10 are low. Since the seventh switch tube T7 is an N-type MOSFET, the eighth switch tube T8 is a P-type MOSFET, the ninth switch tube T9 is a P-type MOSFET, and the tenth switch tube T10 is an N-type MOSFET, the first end and the second end of the seventh switch tube T7 are connected, the first end and the second end of the eighth switch tube T8 are disconnected, the first end and the second end of the ninth switch tube T9 are connected, and the first end and the second end of the tenth switch tube T10 are disconnected, that is, the first storage unit 10 is connected with the pixel electrode, and the second storage unit 20 is disconnected with the pixel electrode, so as to realize that the output unit 30 outputs the data in the first storage unit 10 to the pixel electrode.

[0080] In the embodiment, the seventh switch tube T7 and the ninth switch tube T9 form a transmission gate, the eighth switch tube T8 and the tenth switch tube T10 form another transmission gate, the on-resistance of the transmission gate is approximately a constant, and both digital signals and analog signals can be transmitted.

[0081] In some embodiments, the first switch tube T1, the second switch tube T2, the third switch tube T3, the fourth switch tube T4, the fifth switch tube T5, the sixth switch tube T6, the seventh switch tube T7, the eighth switch tube T8, the ninth switch tube T9, and the tenth switch tube T10 are 3.3V devices, which can ensure that a sufficient liquid crystal driving voltage V is output, so that the LCOS can be normally displayed.

[0082] Referring to Figure 5 , a graph of the transmission ratio and the applied voltage in some embodiments of the present application is shown. Compared with the devices using 5V, the devices using 3.3V can meet the requirements of the LCOS display, and the transmission ratio is higher than that of the devices using 5V.Figure 5 The requirement of the liquid crystal voltage transmission curve shown can also reduce the device size, improve the device reaction speed, reduce the device energy consumption, and improve the brightness while taking into account the volume and power consumption.

[0083] Based on the same inventive concept, one embodiment of the present application provides a display device (not shown in the figure) comprising a plurality of bit lines and a plurality of pixel circuits provided by the above-mentioned embodiments. The plurality of pixel circuits are arranged into a plurality of rows along a first direction and a plurality of columns along a second direction, and the first direction and the second direction intersect. The plurality of bit lines correspond one-to-one to the plurality of columns of pixel circuits, and each bit line is connected to each pixel circuit in the corresponding column.

[0084] In some embodiments, each bit line comprises a first bit line and a second bit line, and the data on the second bit line is opposite to the data on the first bit line at the same time.

[0085] In some embodiments, the display device further comprises a plurality of first word lines and a plurality of second word lines, the plurality of first word lines and the plurality of second word lines correspond one-to-one to the plurality of rows of pixel circuits, each first word line is connected to the first storage unit in each pixel circuit in the corresponding row, and each second word line is connected to the second storage unit in each pixel circuit in the corresponding row.

[0086] In some embodiments, the display device further comprises a first enable signal line and a second enable signal line, the first enable signal line is connected to the output unit in each pixel circuit, and the second enable signal line is connected to the output unit in each pixel circuit.

[0087] Referring to Figure 6 , a flowchart of a display driving method in some embodiments of the present application is shown. Based on the same inventive concept, one embodiment of the present application provides a display driving method, comprising the following steps:

[0088] In step S602, when odd frame image data is written on the bit line, the first storage unit is controlled to obtain the odd frame image data from the bit line and save it.

[0089] In step S604, when the odd frame image data is saved on the bit line, the odd frame image data is output to the pixel electrode.

[0090] In step S606, when the odd frame image data is output to the pixel electrode, the second storage unit is controlled to obtain even frame image data written on the bit line from the bit line and save it.

[0091] Among them, the odd frame image data and the even frame image data are written from the bit line in a cyclic and alternating manner and are output to the pixel electrode alternately.

[0092] In some embodiments, the method further comprises: outputting the even frame image data to the pixel electrode when the second storage unit stores the even frame image data; and controlling the first storage unit to obtain the next odd frame image data written by the bit line and store the next odd frame image data when the even frame image data is output to the pixel electrode.

[0093] Referring to Figure 7 , which is a timing diagram of the signal lines in some embodiments of the present application. Specifically, in the first stage, first, the first word line WL0 is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 in the first storage unit 10 in the first row of pixel circuits, the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the first storage unit 10 in the first row of pixel circuits, so as to realize that the first storage unit 10 in the first row of pixel circuits obtains the data on the bit line and stores the data.

[0094] Then, the first word line WL2 is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 in the first storage unit 10 in the second row of pixel circuits, the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the first storage unit 10 in the second row of pixel circuits, so as to realize that the first storage unit 10 in the second row of pixel circuits obtains the data on the bit line and stores the data.

[0095] Then, the first word line WL2i is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 in the first storage unit 10 in the i+1 row of pixel circuits, the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the first storage unit 10 in the i+1 row of pixel circuits, so as to realize that the first storage unit 10 in the i+1 row of pixel circuits obtains the data on the bit line and stores the data.

[0096] Finally, the first word line WL2n is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 in the first storage unit 10 in the n+1 row of pixel circuits, the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the first storage unit 10 in the n+1 row of pixel circuits, so as to realize that the first storage unit 10 in the n+1 row of pixel circuits obtains the data on the bit line and stores the data.

[0097] At the same time, the second word line WL1 is connected to low level, the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the second storage unit 20 in the first row of pixel circuits, and the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 in the second storage unit 20 in the first row of pixel circuits.

[0098] The second word line WL3 is connected to low level, the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the second row of pixel circuits, and the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the second row of pixel circuits.

[0099] The second word line WL2n+1 is connected to low level, the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the n+1 row of pixel circuits, and the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the i+1 row of pixel circuits.

[0100] The second word line WL2n+1 is connected to low level, the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the n+1 row of pixel circuits, and the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the n+1 row of pixel circuits.

[0101] In addition, the first enable signal line EN is connected to low level, the first storage unit 10 of each pixel circuit is disconnected from the pixel electrode, and the second storage unit 20 of each pixel circuit is in communication with the pixel electrode, so that the output unit 30 outputs the data in the second storage unit 20 of each pixel circuit to the pixel electrode to light up the pixel light source to display the first frame image.

[0102] In the second stage, first, the second word line WL1 is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 of the second storage unit 20 in the first row of pixel circuits, and the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the first row of pixel circuits, so that the second storage unit 20 in the first row of pixel circuits acquires data on the bit line and saves it.

[0103] Then, the second word line WL3 is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 of the second storage unit 20 in the second row of pixel circuits, and the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the second row of pixel circuits, so that the second storage unit 20 in the second row of pixel circuits acquires data on the bit line and saves it.

[0104] Then the first sub-line WL2n+1 is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 of the second storage unit 20 in the n+1th row pixel circuit, and the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the n+1th row pixel circuit, so that the second storage unit 20 in the n+1th row pixel circuit obtains the data on the bit line and saves it.

[0105] Finally, the first sub-line WL2n+1 is connected to high level, the first bit line BLB is connected to the control end of the first switch tube T1 and the control end of the second switch tube T2 of the second storage unit 20 in the n+1th row pixel circuit, and the second bit line BL is connected to the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the second storage unit 20 in the n+1th row pixel circuit, so that the second storage unit 20 in the n+1th row pixel circuit obtains the data on the bit line and saves it.

[0106] At the same time, the second word line WL0 is connected to low level, the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the first storage unit 10 in the first row pixel circuit, and the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the first storage unit 10 in the first row pixel circuit.

[0107] The second word line WL2 is connected to low level, the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the first storage unit 10 in the second row pixel circuit, and the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the first storage unit 10 in the second row pixel circuit.

[0108] The second word line WL2n+1 is connected to low level, the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the first storage unit 10 in the n+1th row pixel circuit, and the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the first storage unit 10 in the n+1th row pixel circuit.

[0109] The second word line WL2n+1 is connected to low level, the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the first storage unit 10 in the n+1th row pixel circuit, and the second bit line BL is disconnected from the control end of the fifth switch tube T5 and the control end of the sixth switch tube T6 of the first storage unit 10 in the n+1th row pixel circuit.

[0110] In addition, the first enable signal line EN is connected to high level, the first storage unit 10 of each pixel circuit is connected to the pixel electrode, the second storage unit 20 of each pixel circuit is disconnected from the pixel electrode, so that the output unit 30 outputs the data in the first storage unit 10 of each pixel circuit to the pixel electrode to light up the pixel light source to display the second frame image.

[0111] The third frame image and the fourth frame image are displayed in sequence according to the above-mentioned manner. In this way, until the last frame image.

[0112] In actual application, after the power is turned on, the first storage unit 10 and the second storage unit 20 in each pixel circuit are written to low level, i.e. 0.

[0113] In the description of the present specification, the description referring to the terms "some embodiments", "other embodiments", "ideal embodiments" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above-mentioned terms does not necessarily refer to the same embodiment or example.

[0114] Each technical feature of the above-mentioned embodiments can be combined arbitrarily, and in order to make the description simple, each technical feature in the above-mentioned embodiments is not described all possible combinations, however, as long as the combination of these technical features does not exist contradictory, it should be considered as the scope of the present specification.

[0115] The above-mentioned embodiments only express several implementation manners of the present application, the description is more specific and detailed, but it should not be understood as the limitation of the patent scope of the present application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A pixel circuit, characterized in that, The pixel circuit includes: The first storage unit is connected to the bit line and acquires and saves odd-numbered frame image data from the bit line in the first stage. The second storage unit is connected to the bit line. In the second stage, it acquires and saves even-numbered frame image data from the bit line. The odd-numbered frame image data and the even-numbered frame image data are cyclically and alternately written from the bit line to the pixel circuit. The time period during which the odd-numbered frame image data is written to the bit line is the first stage, and the time period during which the even-numbered frame image data is written to the bit line is defined as the second stage. The first stage and the second stage alternate. An output unit is connected to the first storage unit and the second storage unit respectively. When the first storage unit stores odd-numbered frame image data, the output unit controls the output of the odd-numbered frame image data to the pixel electrode of the pixel circuit. The even-numbered frame image data and the odd-numbered frame image data are alternately output to the pixel electrode. When the output unit outputs the odd-numbered frame image data from the first storage unit to the pixel electrode, the second storage unit simultaneously enters the second stage to obtain and save the even-numbered frame image data from the bit line; or, when the output unit outputs the odd-numbered frame image data from the first storage unit to the pixel electrode, the second storage unit does not enter the second stage synchronously, but enters the second stage after the odd-numbered frame image data from the first storage unit is output to the pixel electrode, to obtain and save the even-numbered frame image data from the bit line.

2. The pixel circuit according to claim 1, characterized in that, When the output unit still stores an even number of frame image data in the second storage unit, it controls the output of the even number of frame image data to the pixel electrode. When the first storage unit outputs the even-numbered frame image data to the pixel electrode, it obtains and saves the next odd-numbered frame image data written by the bit line.

3. The pixel circuit according to claim 1, characterized in that, The bit line includes a first bit line; the first memory unit and the second memory unit each include a first switch transistor, a second switch transistor, and a third switch transistor, the on / off conditions of the first switch transistor are opposite to those of the second switch transistor; the control terminal of the third switch transistor of the first memory unit is connected to the first word line, and the control terminal of the third switch transistor of the second memory unit is connected to the second word line; the first end of the third switch transistor is connected to the first bit line, and the second end of the third switch transistor is connected to the control terminals of the first switch transistor and the second switch transistor; the first end of the first switch transistor and the first end of the second switch transistor are connected to the output unit, the second end of the first switch transistor is connected to a first operating voltage, and the second end of the second switch transistor is connected to a second operating voltage.

4. The pixel circuit according to claim 3, characterized in that, The bit line further includes a second bit line, the data on the second bit line being opposite to the data on the first bit line at the same time; the first storage unit and the second storage unit respectively further include a fourth switch, a fifth switch, and a sixth switch, the on / off condition of the fifth switch being opposite to the on / off condition of the sixth switch; the control terminal of the fourth switch of the first storage unit is connected to the first word line, and the control terminal of the fourth switch of the second storage unit is connected to the second word line; the first end of the fourth switch is connected to the second bit line, and the second end of the fourth switch is connected to the first end of the first switch, the first end of the second switch, the control terminal of the fifth switch, and the control terminal of the sixth switch; the first end of the fifth switch and the first end of the sixth switch are connected to the control terminals of the first switch and the second switch, the second end of the fifth switch is connected to the first operating voltage, and the second end of the sixth switch is connected to the second operating voltage.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that, The output unit includes a seventh switch and an eighth switch with opposite on / off conditions. The control terminals of the seventh switch and the eighth switch are connected to a first enable signal line. The first terminal of the seventh switch is connected to the first storage unit, the first terminal of the eighth switch is connected to the second storage unit, and the second terminals of the seventh switch and the eighth switch are connected to the pixel electrode.

6. The pixel circuit according to claim 5, characterized in that, The output unit further includes a ninth switch and a tenth switch. The on / off condition of the ninth switch is opposite to that of the seventh switch, and the on / off condition of the tenth switch is opposite to that of the eighth switch. The control terminals of the ninth and tenth switches are connected to a second enable signal line, and the signal on the second enable signal line is opposite to the signal on the first enable signal line at the same time. The first terminal of the ninth switch is connected to the first memory unit and the first terminal of the seventh switch, and the first terminal of the tenth switch is connected to the second memory unit and the first terminal of the eighth switch. The second terminals of the ninth and tenth switches are connected to the pixel electrode, the second terminal of the seventh switch, and the second terminal of the eighth switch.

7. A display device, characterized in that, The display device includes multiple bit lines and multiple pixel circuits as described in any one of claims 1 to 6; the multiple pixel circuits are arranged in multiple rows along a first direction and in multiple columns along a second direction, the first direction and the second direction intersect; the multiple bit lines correspond one-to-one with the multiple columns of pixel circuits, and each bit line is connected to each pixel circuit in the corresponding column.

8. The display device according to claim 7, characterized in that, The display device further includes multiple first word lines and multiple second word lines, each of the multiple first word lines and the multiple second word lines corresponding one-to-one with multiple rows of pixel circuits. Each first word line is connected to a first storage unit in each pixel circuit of the corresponding row, and each second word line is connected to a second storage unit in each pixel circuit of the corresponding row.

9. A display driving method, characterized in that, Applied to the pixel circuit as described in any one of claims 1 to 6, the method comprises: When an odd number of frame image data is written to the bit line, the first storage unit is controlled to retrieve the odd number of frame image data from the bit line and save it. When the first storage unit stores the odd-numbered frame image data, the odd-numbered frame image data is output to the pixel electrode; and When the odd-numbered frame image data is output to the pixel electrode, the second storage unit is controlled to obtain and save the even-numbered frame image data written on the bit line. The odd-numbered frame image data and the even-numbered frame image data are cyclically and alternately written from the bit line and alternately output to the pixel electrode.

10. The display driving method according to claim 9, characterized in that, The method further includes: When the second storage unit stores an even number of frame image data, the even number of frame image data is output to the pixel electrode; and When outputting the even-numbered frame image data to the pixel electrode, the first storage unit is controlled to obtain the next odd-numbered frame image data written by the bit line from the bit line and save it.

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