Chip carrier

Abstract

The present invention discloses a chip carrier tray, belonging to the field of chip technology. The chip carrier tray includes a main plate; a receiving groove, provided on the main plate, for placing an epitaxial high-class chip in the receiving groove, the inner sidewall of the receiving groove being a sloped surface; a placement platform, convexly provided at the bottom of the receiving groove; and a pin placement space, concavely provided at the bottom of the receiving groove, wherein the depth of the pin placement space is greater than the downward extension depth of the pins of the epitaxial high-class chip. The chip carrier tray of the present invention can prevent the placement position of the epitaxial high-class chip from being offset and the pins from being damaged.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a chip carrier tray. Background Art

[0002] At present, chip carriers are generally designed for chips without epitaxial pins. There are no carriers designed for chips with standing and epitaxial pins. When using carriers that are not designed for epitaxial standing chips to circulate chips, it will cause varying degrees of damage to the pins of the product, reducing the chip appearance yield and easily causing core solder joints, which will have a certain impact on the company's benefits.

[0003] The following problems exist during the transportation of high-end chips on the carrier tray at the epitaxial station:

[0004] (1) The existing carrier tray does not provide effective protection for transporting high-class chips to the epitaxial station;

[0005] (2) The existing carrier plate size design cannot stably ensure that the chip will not produce a large range of displacement in the carrier plate;

[0006] (3) The existing carrier plate design makes it impossible for chip users to correctly pick up and place products, resulting in poor soldering on the upper board.

[0007] Therefore, there is an urgent need to provide a chip carrier to solve the above problems. Summary of the Invention

[0008] The object of the present invention is to provide a chip carrier to prevent the placement position of high-end chips of epitaxial stations from being offset and to prevent pins from being damaged.

[0009] To achieve the above objectives, the following technical solutions are provided:

[0010] Chip carrier, including:

[0011] Main plate;

[0012] A receiving groove is provided on the main plate, wherein the receiving groove is used to place the epitaxial high-class chip, and the inner side wall of the receiving groove is a slope surface;

[0013] A placement platform is protruded from the bottom of the accommodating groove;

[0014] The pin placement space is recessed in the bottom of the accommodating groove, and the depth of the pin placement space is greater than the downward extending depth of the pins of the epitaxial high-type chip.

[0015] As an optional solution for the chip carrier, two pin placement spaces are provided in each of the accommodating grooves, and the two pin placement spaces are located at opposite ends of the placement platform.

[0016] As an optional solution for the chip carrier, a first limiting portion is protruded from the inner side wall of the accommodating groove, and the X edge of the plastic package of the epitaxial high chip is stopped at the first limiting portion.

[0017] As an optional solution for the chip carrier, four first limiting portions are circumferentially spaced apart and arranged on the inner side wall of the accommodating groove.

[0018] As an optional solution for the chip carrier, the two opposite ends of the placement platform are provided with second limiting parts, and the Y edge of the plastic package of the epitaxial high chip is stopped at the second limiting part.

[0019] As an optional solution for the chip carrier disk, the main disk includes a vacuum adsorption area and a non-vacuum adsorption area, and the vacuum adsorption area and the non-vacuum adsorption area are both provided with a plurality of the accommodating grooves in an array.

[0020] As an optional solution for the chip carrier disk, the non-vacuum adsorption area of ​​the main disk is provided with an exhaust hole, and the exhaust hole is communicated with the accommodating groove.

[0021] As an optional solution for the chip carrier plate, the exhaust hole is opened through the placement platform.

[0022] As an optional solution for the chip carrier plate, the main plate is made of polyphenylene ether.

[0023] As an optional solution for the chip carrier disk, a reinforcing rib is protruded from the main body disk, and the reinforcing rib is located between the outer side walls of two adjacent accommodating grooves.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The chip carrier provided by the present invention is provided with a receiving groove for placing epitaxial station high-class chips on the main plate. Since the inner side surface of the receiving groove is a sloped surface, the groove area of ​​the receiving groove gradually increases in the direction away from the bottom of the groove, which not only allows the epitaxial station high-class chips to be quickly and accurately confined to the bottom of the receiving groove along the sloped surface, preventing the placement position of the epitaxial station high-class chips from shifting, but also facilitates the placement of epitaxial station high-class chips of different sizes, thereby expanding the scope of application of the chip carrier; wherein a placement platform and a pin placement space are provided at the bottom of the receiving groove, the plastic package of the epitaxial station high-class chip is in contact with the placement platform, and the pins of the epitaxial station high-class chip are placed in the pin placement space, and since the depth of the pin placement space is greater than the depth of the downward extension of the pins of the epitaxial station high-class chip, the pins of the epitaxial station high-class chip are prevented from being damaged. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in describing the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the contents of the embodiments of the present invention and these drawings without any creative work.

[0027] Figure 1 A top view of a high-class chip at an epitaxial station in an embodiment of the present invention;

[0028] Figure 2 This is a left view of the epitaxial station high-class chip in an embodiment of the present invention;

[0029] Figure 3 A top view of a chip carrier tray according to an embodiment of the present invention;

[0030] Figure 4 for Figure 3 A partial enlarged view of point A in the middle.

[0031] Reference numerals:

[0032] 100, epitaxial high-end chip; 101, plastic package; 1011, X edge; 1012, Y edge; 102, pin;

[0033] 1. Main plate; 2. Accommodation groove; 3. Reinforcement ribs;

[0034] 11. Vacuum adsorption area; 12. Exhaust hole;

[0035] 21. Slope surface; 22. Placement platform; 23. Pin placement space; 24. First limit portion; 25. Second limit portion. DETAILED DESCRIPTION

[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0037] In the description of the present invention, it should be noted that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when in use. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0038] In the description of the present invention, it should be noted that, unless otherwise specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0039] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0040] In order to prevent the placement position of the epitaxial high-end chip from being offset and to prevent the pins from being damaged, this embodiment provides a chip carrier. Figures 1 to 4 The specific contents of this embodiment are described in detail.

[0041] Specifically, if Figure 1 and Figure 2 As shown, the epitaxial high-end chip 100 in this embodiment includes a plastic package 101 and pins 102. Pins 102 are provided at opposite ends of the plastic package 101, and the pins 102 are in a Z shape. Figure 1 As shown, the right-angled sides of the plastic package body 101 are respectively an X edge 1011 and a Y edge 1012 .

[0042] like Figure 2 Combine Figure 3As shown, the chip carrier includes a main plate 1, a receiving slot 2, a placement platform 22, and a pin placement space 23. The receiving slot 2 is provided on the main plate 1 and is used to place the epitaxial high-class chip 100. The inner sidewall of the receiving slot 2 is a sloped surface 21. The placement platform 22 is convexly disposed at the bottom of the receiving slot 2. The pin placement space 23 is recessed at the bottom of the receiving slot 2, and the depth of the pin placement space 23 is greater than the downward extension depth of the pins 102 of the epitaxial high-class chip 100.

[0043] In short, the chip carrier provided by the present invention is provided with a receiving groove 2 for placing the epitaxial station high-class chip 100 on the main plate 1. Since the inner side surface of the receiving groove 2 is a slope surface 21, the groove area of ​​the receiving groove 2 gradually increases in the direction away from the groove bottom, which not only allows the epitaxial station high-class chip 100 to be quickly and accurately confined to the groove bottom of the receiving groove 2 along the slope surface 21, preventing the epitaxial station high-class chip 100 from being offset, but also facilitates the placement of epitaxial station high-class chips 100 of different sizes. 00, which expands the application range of the chip carrier; a placement platform 22 and a pin placement space 23 are provided at the bottom of the accommodating groove 2, the plastic package 101 of the epitaxial station high-class chip 100 is in contact with the placement platform 22, and the pins 102 of the epitaxial station high-class chip 100 are placed in the pin placement space 23, and because the depth of the pin placement space 23 is greater than the depth of the pins 102 of the epitaxial station high-class chip 100 extending downward, the pins 102 of the epitaxial station high-class chip 100 are prevented from being damaged.

[0044] Specifically, if Figure 4 As shown, in this embodiment, each accommodating groove 2 is provided with two pin placement spaces 23, and the two pin placement spaces 23 are located at opposite ends of the placement platform 22. For example, in this embodiment, the plastic package 101 in the middle of the epitaxial high-class chip 100 is located on the placement platform 22, and the pins 102 at both ends of the epitaxial high-class chip 100 are in a suspended state, effectively protecting the pins 102 at both ends of the epitaxial high-class chip 100 and preventing the pins 102 from being damaged.

[0045] Furthermore, if Figure 4 As shown, the inner sidewall of the receiving groove 2 is provided with a first stopper 24, and the X-edge 1011 of the plastic package 101 of the epitaxial high-type chip 100 is stopped by the first stopper 24. By adding the first stopper 24 to the inner sidewall of the receiving groove 2, the X-edge 1011 of the plastic package 101 abuts against the first stopper 24, and the first stopper 24 limits the movement of the chip along the X direction, thereby limiting the position of the epitaxial high-type chip 100 in the receiving groove 2.

[0046] Specifically, in this embodiment, four first limiting portions 24 are circumferentially spaced apart on the inner sidewall of the receiving groove 2. Two first limiting portions 24 are provided on each of the inner sidewalls on both sides of the receiving groove 2. The four first limiting portions 24 are located at the four corners of the plastic package 101 of the epitaxial high-class chip 100 to ensure that the plastic package 101 is stably stored in the receiving groove 2 and to prevent the pins 102 from contacting the carrier plate.

[0047] Furthermore, if Figure 4 As shown, second stoppers 25 are provided at opposite ends of the placement platform 22. The Y-edge 1012 of the plastic package 101 of the epitaxial high chip 100 is stopped by the second stoppers 25. The addition of the second stoppers 25 limits the movement of the chip along the Y direction, ensuring that the plastic package 101 is securely stored in the receiving groove 2 and preventing contact between the pins 102 and the carrier plate.

[0048] For example, Figure 3 As shown, in this embodiment, the main plate 1 includes a vacuum adsorption area 11 and a non-vacuum adsorption area. The vacuum adsorption area 11 is located in the center of the main plate 1, and the non-vacuum adsorption area is located on the periphery of the vacuum adsorption area 11. Multiple accommodating slots 2 are arranged in an array in the vacuum adsorption area 11 and the non-vacuum adsorption area. The multiple accommodating slots 2 are provided on the main plate 1 for transporting multiple chips at a time, thereby improving transportation efficiency. When the chip carrier needs to be transported, the suction nozzle on the mechanical equipment is attracted to the vacuum adsorption area 11 of the main plate 1.

[0049] Furthermore, in order to ensure accurate positioning, calibration points and reference holes are provided on the main plate 1 to facilitate matching with automated machine positioning.

[0050] In some application scenarios, such as Figure 3 Combine Figure 4 As shown, the non-vacuum adsorption area of ​​the main plate 1 is provided with an exhaust hole 12, which is connected to the receiving groove 2. When the epitaxial high-type chip 100 is placed in the receiving groove 2, the exhaust hole 12 facilitates the discharge of air from the receiving groove 2, ensuring that the chip slides quickly into the receiving groove 2 and preventing it from getting stuck due to the presence of air.

[0051] In this embodiment, the exhaust hole 12 is opened through the placement platform 22 in the non-vacuum area of ​​the main plate 1. Since the thickness near the placement platform 22 is large, the exhaust hole 12 is opened on the placement platform 22 to reduce the impact of the opening on the structural strength of the main plate 1.

[0052] For example, the main plate 1 is made of polyphenylene ether (PPE). PPE is a high-strength engineering plastic known as poly-2,6-dimethyl-1,4-phenylene ether (PPO or PPE), also known as polyphenylene oxide or polyphenylene ether. PPE exhibits excellent mechanical strength, stress relaxation resistance, creep resistance, and dimensional stability.

[0053] Furthermore, if Figure 4 As shown, the main plate 1 is provided with a convex reinforcement rib 3, which is located between the outer side walls of two adjacent accommodating grooves 2. By adding the reinforcement rib 3 to the main plate 1, the overall structural strength of the main plate 1 is improved, so that more chips can be placed on the main plate 1, and the number of chips that can be transported at one time is increased.

[0054] In summary, the carrier plate in this embodiment: 1. Structural design: The carrier plate design structure ensures the smooth placement of the chip while adding multiple chip positioning designs to reduce the contact of the pin 102 with the carrier plate, and at the same time reduce the displacement of the chip in the carrier plate; 2. The carrier plate meets the use of machine equipment. The machine can place the chip with pin 102 directly into the carrier plate. When the subsequent mechanical equipment absorbs it, it can more accurately absorb the center of the chip to prevent offset and reduce the machine alarm rate. 3. Receptacle 2 is where the entire chip pin 102 is placed. The outer frame of recess 2 is designed to be larger than the product size to prevent the product from getting stuck with the positioning frame during placement, causing damage to the appearance. The sloped surface 21 is a chamfered outer frame, allowing the chip to smoothly enter the accurate position. The first limiting portion 24 positions the X edge 1011 of the chip's plastic package 101 to avoid contact with the chip pins 102 during positioning, reducing damage to the pins 102. The second limiting portion 25 positions the Y edge 1012 of the chip's plastic package 101 to eliminate contact between the pins 102 and the outer frame, reducing damage to the pins 102. The lower edge of the plastic package 101 is placed on the placement platform 22, and the chip's pins 102 are placed in the pin placement space 23. The specially designed depth of the pin placement space 23 is greater than the height from the lower surface of the plastic package 101 to the bottom surface of the pins 102, so that the pins 102 are not subjected to force, reducing damage to the pins 102. Ultimately, by positioning the chip's plastic package 101, precise positioning is achieved and damage to the pins 102 is avoided.

[0055] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A chip carrier, characterized in that: include: Main plate (1); A receiving groove (2) is provided on the main plate (1), the receiving groove (2) being used for placing an epitaxial high-class chip (100), and the inner side wall of the receiving groove (2) is a slope surface (21); A placement platform (22) is protruding from the bottom of the accommodating groove (2); A pin placement space (23) is recessed in the bottom of the accommodating groove (2), and the depth of the pin placement space (23) is greater than the downward extension depth of the pins (102) of the epitaxial high-class chip (100). Two pin placement spaces (23) are provided in each accommodating groove (2), and the two pin placement spaces (23) are located at opposite ends of the placement platform (22).

2. The chip carrier according to claim 1, wherein: A first limiting portion (24) is convexly provided on the inner side wall of the accommodating groove (2), and an X edge (1011) of the plastic package (101) of the epitaxial high-class chip (100) is stopped at the first limiting portion (24).

3. The chip carrier according to claim 2, wherein: The four first limiting portions (24) are circumferentially spaced apart and arranged on the inner side wall of the accommodating groove (2).

4. The chip carrier according to claim 2, wherein: The placement platform (22) is provided with second limiting portions (25) at opposite ends thereof, and the Y edge (1012) of the plastic package (101) of the epitaxial high-class chip (100) is stopped at the second limiting portion (25).

5. The chip carrier according to any one of claims 1 to 4, characterized in that: The main body disk (1) comprises a vacuum adsorption area (11) and a non-vacuum adsorption area, and both the vacuum adsorption area (11) and the non-vacuum adsorption area are provided with a plurality of the accommodating grooves (2) in an array.

6. The chip carrier according to claim 5, characterized in that: The non-vacuum adsorption area of ​​the main body disk (1) is provided with an exhaust hole (12), and the exhaust hole (12) is communicated with the accommodating groove (2).

7. The chip carrier according to claim 6, wherein: The exhaust hole (12) is opened through the placement platform (22).

8. The chip carrier according to claim 5, wherein: The main body plate (1) is made of polyphenylene ether material.

9. The chip carrier according to claim 5, wherein: A reinforcing rib (3) is convexly provided on the main body plate (1), and the reinforcing rib (3) is located between the outer side walls of two adjacent accommodating grooves (2).

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