Chip, preparation method thereof, and terminal

Abstract

The application provides a chip and a preparation method thereof and a terminal, relates to the technical field of semiconductors, and can improve the lodging phenomenon of each film layer and make the performance of P-type transistors and N-type transistors more matched. The preparation method of the chip comprises the following steps: forming a laminated arrangement of a sacrificial layer and a channel layer, the channel layer being located between adjacent sacrificial layers; the material of a first channel layer of an N-type transistor is the same as that of a second channel layer of a P-type transistor; removing part of the sacrificial layer located in a channel region; forming a cap layer on the side of the channel layer facing and / or facing away from the substrate, the cap layer being located in the channel region; the cap layer forms a split energy band at the interface between the cap layer and the channel layer, so as to confine electrons in the cap layer when the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value, and to confine holes in the cap layer when the electron mobility of the first channel layer is greater than a third preset value and the hole mobility of the second channel layer is less than a fourth preset value.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip, its fabrication method, and a terminal. Background Technology

[0002] As chip technology nodes continue to shrink, the application of gate-all-around field-effect transistors (GAAFETs) with novel device structures is essential to further achieve performance, power, area, cost, and time-to-market (PPACt) goals. To further reduce the area of ​​standard cells, vertically stacked complementary field-effect transistors (CFETs) have become an important development target. Currently, lateral-gate all-around (L-GAA) devices have high compatibility with the already mass-produced fin field-effect transistors (FinFETs) and are the primary target for the next stage of mass production.

[0003] However, in existing gate-around device fabrication techniques, there is a performance mismatch between P-type and N-type transistors. For example, if silicon (Si) is selected as the channel material for both P-type and N-type transistors, the performance of P-type transistors is weaker than that of N-type transistors due to their lower hole mobility. This leads to increased leakage current and power consumption in circuits containing both P-type and N-type transistors, as well as propagation delay issues. Summary of the Invention

[0004] This application provides a chip and its fabrication method and terminal, which can improve the performance of P-type transistors and N-type transistors by improving the collapse phenomenon of each film layer caused by etching and cleaning processes.

[0005] In a first aspect, this application provides a method for fabricating a chip, the chip including N-type transistors and P-type transistors. The method for fabricating N-type transistors and P-type transistors includes: forming a sacrificial layer and a channel layer stacked on a substrate, the channel layer being located between adjacent sacrificial layers; the channel layer including a first channel layer for N-type transistors and a second channel layer for P-type transistors, the material of the first channel layer being the same as the material of the second channel layer; removing a portion of the sacrificial layer located in the channel region; forming a capping layer on the side of the channel layer facing and / or away from the substrate, the capping layer being located in the channel region; the thickness of the capping layer being less than the thickness of the sacrificial layer along the direction from the substrate to the channel layer; the capping layer forming a split energy band at its interface with the channel layer, so as to confine electrons in the capping layer when the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value, and to confine holes in the capping layer when the electron mobility of the first channel layer is greater than a third preset value and the hole mobility of the second channel layer is less than a fourth preset value.

[0006] In this application, by using the same material for the first channel layer and the second channel layer, the first and second channel layers can be formed simultaneously using the same semiconductor process. Compared to solutions where the materials for the first and second channel layers are different, this application simplifies the chip fabrication process, reduces the number of photomasks required, and thus saves on chip fabrication costs. Furthermore, it eliminates the need for separate etching of sacrificial layers or other structures to protect the first or second channel layer, reducing the number of etching and cleaning cycles, mitigating the collapse phenomenon in the films of N-type and P-type transistors caused by etching and cleaning processes, improving chip yield, and reducing costs.

[0007] Furthermore, to improve the performance of P-type transistors without compromising the performance of N-type transistors, a material capable of forming a split energy band at the interface with the channel layer can be selected as the capping layer material. When the N-type transistor is turned on, a two-dimensional electron gas is formed, confining electrons within the capping layer. This makes the capping layer and the channel layer together part of the channel, improving the electron mobility of the N-type transistor and thus enhancing its performance. This better matches the performance of P-type and N-type transistors.

[0008] Alternatively, to improve the performance of N-type transistors without reducing the performance of P-type transistors, a material capable of forming a split energy band at the interface with the channel layer can be selected as the capping layer material. When the P-type transistor is turned on, a two-dimensional electron gas of holes is formed, confining the holes within the capping layer of the P-type transistor. This makes the capping layer and the channel layer together part of the channel, improving the electron mobility of the P-type transistor and thus enhancing its performance, making the performance of the P-type transistor more closely matched with that of the N-type transistor.

[0009] In some possible implementations, based on the performance differences between different types of N-type and P-type transistors, as well as the material differences in the channel layer, the first preset value can be equal to the third preset value, and the second preset value can be equal to the fourth preset value. For example, the first preset value is 200cm. 2 / V·s, the second preset value is 110cm 2 At / V·s, because the electron mobility of the first channel layer is too small, the N-type transistor needs to add a capping layer to confine electrons in the capping layer, thereby improving the electron mobility of the N-type transistor and thus improving the performance of the N-type transistor.

[0010] In some possible implementations, after forming a sacrificial layer and a channel layer stacked on the substrate, and before removing the portion of the sacrificial layer located in the channel region, the fabrication methods for N-type and P-type transistors further include: removing the portion of the sacrificial layer other than the channel region using the same photolithography process; recessing the sacrificial layer relative to the channel layer along the channel length direction; and filling a first spacer layer along the channel length direction at the recessed position of the sacrificial layer relative to the channel layer. The dielectric constant of the material of the first spacer layer is lower than the dielectric constant of the materials of the channel layer, gate, source, and drain. Since the first spacer layer is disposed between the gate to be formed and the source and drain, the parasitic capacitance between the gate to be formed and the source and drain can be reduced by using a material with a lower dielectric constant as the material of the first spacer layer.

[0011] In some possible implementations, after forming a sacrificial layer and a channel layer stacked on a substrate, and before removing the portion of the sacrificial layer other than the channel region using the same photolithography process, the fabrication method of N-type and P-type transistors further includes: forming a dummy gate and a second spacer layer; the second spacer layer is disposed on opposite sides of the dummy gate along the channel length direction. After filling the first spacer layer at a position where the sacrificial layer is recessed relative to the channel layer, and before forming a capping layer on the side of the channel layer facing and / or away from the substrate, the fabrication method of N-type and P-type transistors further includes: removing the dummy gate. After forming the capping layer on the side of the channel layer facing and / or away from the substrate, the fabrication method of N-type and P-type transistors further includes: cleaning the exposed surface in the capping layer; and sequentially forming a gate dielectric layer and a gate on the exposed surface side of the capping layer.

[0012] For N-type and / or P-type transistors that retain a capping layer after cleaning, the capping layer can be used to reduce the interface states at the channel layer and gate dielectric layer interface, improve the interface, and address the problem that the gate voltage cannot be fully used to control the conduction of N-type and / or P-type transistors. Furthermore, in some possible implementations, the materials of the channel layer (e.g., germanium-silicon) and the gate dielectric layer (e.g., hafnium oxide) can result in a high number of interface states at the channel layer and gate dielectric layer interface. This application can utilize an existing capping layer disposed between the channel layer and gate dielectric layer to reduce dangling bonds at the channel layer and gate dielectric layer interface, decrease the interface state density, and improve the interface quality between the channel layer and gate dielectric layer.

[0013] During the cleaning process of the exposed surface of the capping layer, the thickness of the capping layer may be affected and thinned. This application aims to ensure that, even when the performance of the N-type transistor is weaker than that of the P-type transistor, the N-type transistor still includes a capping layer after cleaning; the P-type transistor may or may not include a capping layer, i.e., the thickness of the capping layer is 0. (The last sentence is a repetition of the previous one and can be omitted.)

[0014] When both the N-type and P-type transistors include a capping layer, if the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value, the thickness of the portion of the capping layer located in the P-type transistor is less than the thickness of the portion of the capping layer located in the N-type transistor. If the electron mobility of the first channel layer is greater than a third preset value and the hole mobility of the second channel layer is less than a fourth preset value, the thickness of the portion of the capping layer located in the P-type transistor is greater than the thickness of the portion of the capping layer located in the N-type transistor.

[0015] In some possible implementations, the lattice constant of the capping layer material is greater than that of the first channel layer material, and the capping layer 19 generates compressive strain on the first channel layer to improve the carrier mobility of the N-type transistor; and / or, the lattice constant of the capping layer material is less than that of the second channel layer material, and the capping layer 19 generates tensile strain on the second channel layer to improve the carrier mobility of the P-type transistor.

[0016] In some possible implementations, the channel layer is multi-layered along the direction from the substrate to the sacrificial layer. For example, N-type transistors and P-type transistors are CFETs.

[0017] Secondly, this application provides a chip including a substrate and an N-type transistor and a P-type transistor disposed on the substrate. The N-type transistor includes a first channel layer and a capping layer, and the P-type transistor includes a second channel layer; the first channel layer and the second channel layer are made of the same material. The capping layer is located in the channel region of the N-type transistor and is disposed on the side of the channel layer facing and / or away from the substrate; along the direction from the substrate to the first channel layer, the thickness of the capping layer is less than the distance between the substrate and the first channel layer. The capping layer forms a split energy band at its interface with the channel layer to confine electrons in the capping layer when the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value.

[0018] In this application, by using the same material for the first channel layer and the second channel layer, the first and second channel layers can be formed simultaneously using the same semiconductor process. Compared to solutions where the materials for the first and second channel layers are different, this application simplifies the chip fabrication process, reduces the number of photomasks required, and thus saves on chip fabrication costs. Furthermore, it eliminates the need for separate etching of sacrificial layers or other structures to protect the first or second channel layer, reducing the number of etching and cleaning cycles, mitigating the collapse phenomenon in the films of N-type and P-type transistors caused by etching and cleaning processes, improving chip yield, and reducing costs.

[0019] Furthermore, to improve the performance of P-type transistors without compromising the performance of N-type transistors, a material capable of forming a split energy band at the interface with the channel layer can be selected as the capping layer material. When the N-type transistor is turned on, a two-dimensional electron gas is formed, confining electrons within the capping layer. This makes the capping layer and the channel layer together part of the channel, improving the electron mobility of the N-type transistor and thus enhancing its performance. This better matches the performance of P-type and N-type transistors.

[0020] In some possible implementations, based on the performance differences between different types of N-type and P-type transistors, as well as the material differences in the channel layer, the first preset value can be equal to the third preset value, and the second preset value can be equal to the fourth preset value. For example, the first preset value is 200cm. 2 / V·s, the second preset value is 110cm 2 At / V·s, because the electron mobility of the first channel layer is too small, the N-type transistor needs to add a capping layer to confine electrons in the capping layer, thereby improving the electron mobility of the N-type transistor and thus improving the performance of the N-type transistor.

[0021] In some possible implementations, the P-type transistor also includes a capping layer located in the channel region of the P-type transistor. The thickness of the portion of the capping layer within the P-type transistor is less than the thickness of the portion of the capping layer within the N-type transistor.

[0022] For N-type and / or P-type transistors that still retain a capping layer, the capping layer can be used to reduce the interface states at the interface between the channel layer and the gate dielectric layer, improving the interface and addressing the problem that the gate voltage cannot be fully used to control the conduction of N-type and / or P-type transistors. Furthermore, in some possible implementations, the materials of the channel layer (e.g., germanium-silicon) and the gate dielectric layer (e.g., hafnium oxide) can result in a high number of interface states at the interface between the channel layer and the gate dielectric layer. This application can utilize an existing capping layer disposed between the channel layer and the gate dielectric layer to reduce dangling bonds at the interface, decrease the interface state density, and improve the interface quality between the channel layer and the gate dielectric layer.

[0023] In some possible implementations, both the first and second channel layers are multilayered along the direction from the substrate to the sacrificial layer, and the thickness of the capping layer is less than the distance between adjacent first channel layers and the distance between adjacent second channel layers. For example, N-type transistors and P-type transistors are CFETs.

[0024] Thirdly, this application provides a chip including a substrate and an N-type transistor and a P-type transistor disposed on the substrate. The N-type transistor includes a first channel layer, and the P-type transistor includes a second channel layer and a capping layer; the first channel layer and the second channel layer are made of the same material. The capping layer is located in the channel region of the P-type transistor and is disposed on the side of the channel layer facing and / or away from the substrate; along the direction from the substrate to the second channel layer, the thickness of the capping layer is less than the distance between the substrate and the second channel layer. The capping layer forms a split energy band at its interface with the channel layer to confine holes in the capping layer when the electron mobility of the first channel layer is greater than a third preset value and the hole mobility of the second channel layer is less than a fourth preset value.

[0025] In this application, by using the same material for the first channel layer and the second channel layer, the first and second channel layers can be formed simultaneously using the same semiconductor process. Compared to solutions where the materials for the first and second channel layers are different, this application simplifies the chip fabrication process, reduces the number of photomasks required, and thus saves on chip fabrication costs. Furthermore, it eliminates the need for separate etching of sacrificial layers or other structures to protect the first or second channel layer, reducing the number of etching and cleaning cycles, mitigating the collapse phenomenon in the films of N-type and P-type transistors caused by etching and cleaning processes, improving chip yield, and reducing costs.

[0026] Furthermore, to improve the performance of N-type transistors without reducing the performance of P-type transistors, a material capable of forming a split energy band at the interface with the channel layer can be selected as the capping layer material. When the P-type transistor is turned on, a two-dimensional electron gas of holes is formed, confining the holes within the capping layer of the P-type transistor. This makes the capping layer and the channel layer together part of the channel, improving the electron mobility of the P-type transistor and thus enhancing its performance, making the performance of the P-type transistor more closely matched with that of the N-type transistor.

[0027] In some possible implementations, the N-type transistor also includes a capping layer located in the channel region of the N-type transistor. The thickness of the portion of the capping layer within the N-type transistor is less than the thickness of the portion of the capping layer within the P-type transistor.

[0028] For N-type and / or P-type transistors that still retain a capping layer, the capping layer can be used to reduce the interface states at the interface between the channel layer and the gate dielectric layer, improving the interface and addressing the problem that the gate voltage cannot be fully used to control the conduction of N-type and / or P-type transistors. Furthermore, in some possible implementations, the materials of the channel layer (e.g., germanium-silicon) and the gate dielectric layer (e.g., hafnium oxide) can result in a high number of interface states at the interface between the channel layer and the gate dielectric layer. This application can utilize an existing capping layer disposed between the channel layer and the gate dielectric layer to reduce dangling bonds at the interface, decrease the interface state density, and improve the interface quality between the channel layer and the gate dielectric layer.

[0029] In some possible implementations, both the first and second channel layers are multilayered along the direction from the substrate to the sacrificial layer, and the thickness of the capping layer is less than the distance between adjacent first channel layers and the distance between adjacent second channel layers. For example, N-type transistors and P-type transistors are CFETs.

[0030] Fourthly, this application provides a terminal, which includes a circuit board and the chip described in the second or third aspect, the chip being disposed on the circuit board.

[0031] The fourth aspect and any implementation thereof correspond to the second aspect, any implementation thereof, the third aspect, and any implementation thereof, respectively. The technical effects of the fourth aspect and any implementation thereof can be found in the technical effects of the second aspect, any implementation thereof, the third aspect, and any implementation thereof, as described above; they will not be repeated here. Attached Figure Description

[0032] Figure 1This is a connection diagram of the various structures in the terminal provided in the embodiments of this application;

[0033] Figure 2 A top view of the chip provided in an embodiment of this application;

[0034] Figure 3 A circuit diagram including a transistor is provided for an embodiment of this application;

[0035] Figure 4 The fabrication flowcharts of N-type and P-type transistors provided in the embodiments of this application are shown.

[0036] Figure 5a This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0037] Figure 5b This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0038] Figure 5c This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0039] Figure 5d This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0040] Figure 5e This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0041] Figure 5f This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0042] Figure 5g This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0043] Figure 5h This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0044] Figure 5i for Figure 5h A sectional view along the A1-A2 direction;

[0045] Figure 5j for Figure 5h A sectional view along the B1-B2 direction;

[0046] Figure 5k This application provides a diagram illustrating the fabrication process of the channel layer and sacrificial layer in an embodiment of the invention.

[0047] Figure 6a This is a diagram illustrating the fabrication process of the shallow trench isolation layer provided in an embodiment of this application.

[0048] Figure 6bfor Figure 6a A sectional view along the A1-A2 direction;

[0049] Figure 7a This is a process diagram illustrating the fabrication of the dummy gate provided in an embodiment of this application;

[0050] Figure 7b A diagram illustrating the fabrication process of the second spacer layer provided in an embodiment of this application;

[0051] Figure 8a A diagram illustrating the fabrication process of the source and drain electrodes provided in the embodiments of this application;

[0052] Figure 8b A process diagram illustrating the selective removal of the sacrificial layer and the channel layer provided in this application embodiment;

[0053] Figure 9 A process diagram illustrating the selective removal of the sacrificial layer provided in an embodiment of this application;

[0054] Figure 10 A diagram illustrating the fabrication process of the first spacer layer provided in an embodiment of this application;

[0055] Figure 11a A diagram illustrating the fabrication process of the source and drain electrodes provided in the embodiments of this application;

[0056] Figure 11b A diagram illustrating the fabrication process of the source and drain electrodes provided in the embodiments of this application;

[0057] Figure 11c This is a process diagram illustrating the fabrication of the interlayer dielectric provided in the embodiments of this application;

[0058] Figure 12 A process diagram for removing the dummy gate and sacrificial layer provided in an embodiment of this application;

[0059] Figure 13a This is a diagram illustrating the preparation process of the capping layer provided in an embodiment of this application;

[0060] Figure 13b This is a diagram illustrating the preparation process of the capping layer provided in an embodiment of this application;

[0061] Figure 13c The graph showing the relationship between electron mobility and germanium composition is provided for embodiments of this application.

[0062] Figure 13d A graph showing the relationship between hole mobility and germanium composition provided in an embodiment of this application;

[0063] Figure 14 A distribution map of electrons and holes provided for embodiments of this application;

[0064] Figure 15aThis application provides a schematic diagram of the structure of an N-type transistor and a P-type transistor according to embodiments of the present application;

[0065] Figure 15b This is a schematic diagram of another N-type transistor and a P-type transistor provided in the embodiments of this application.

[0066] Figure label:

[0067] 1-Chip; 10-Substrate; 111-First film layer; 121-Second film layer; 13-Shallow trench isolation layer; 14-Dummy gate; 15-Second spacer layer; 16-First spacer layer; 17-Source; 18-Drain; 19-Capping layer; 20-Interlayer dielectric layer; 31-First mask layer; 311-First mask pattern; 32-Photoresist; 321-Photoresist pattern; 33-Second mask layer; 331-Second mask pattern. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0069] The terms "first," "second," etc., used in the specification, embodiments, claims, and drawings of this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or order. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "Installation," "connection," "linking," etc., should be interpreted broadly, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, an indirect connection through an intermediate medium, or a connection within two elements. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, including a series of steps or units. A method, system, product, or device is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices. Terms such as “up,” “down,” “left,” and “right” are used only in relation to the orientation of the components in the accompanying drawings. These directional terms are relative concepts used for relative description and clarification, and they can change accordingly depending on the orientation of the components in the accompanying drawings.

[0070] This application provides a terminal, which can also be a mobile phone, computer, tablet computer, personal digital assistant (PDA), smart wearable device, smart home device, or other device including a chip. This application does not limit the application to this type of device. For ease of explanation, a mobile phone is used as an example below.

[0071] like Figure 1 As shown, a mobile phone may include a circuit board, a display screen, a battery, a camera, etc. The circuit board may integrate a processor, internal memory, charging circuitry, etc. Of course, a mobile phone may also include other components, and the circuit board may integrate other circuit structures; this application does not limit this.

[0072] A processor may include one or more processing units, such as an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, memory, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural network processing unit (NPU). Different processing units may be independent devices or integrated into one or more processors.

[0073] A GPU is a microprocessor for image processing, connected to the display and application processor. The GPU performs mathematical and geometric calculations and is used for graphics rendering. This allows the phone to achieve its display functions through the GPU, display, and application processor.

[0074] A mobile phone's charging circuit includes a power management circuit and a charging management circuit. The power management circuit connects the battery, the charging management circuit, and the processor. The charging management circuit receives charging input from the charger to charge the battery. While charging the battery, the charging management circuit can also supply power to the phone through the power management circuit. The power management circuit receives input from the battery and / or the charging management module to supply power to the processor, internal memory, display, camera, etc.

[0075] Mobile phones can also achieve shooting functions through cameras, GPUs, displays, and application processors.

[0076] The internal memory in a mobile phone can be used to store executable program code, which includes instructions. The processor executes the instructions stored in the internal memory to perform various functions and data processing of the mobile phone.

[0077] The processor, internal memory, charging circuit, etc., integrated on the circuit board mentioned above each include one or more chips. Chips can be coupled to the circuit board via pins. Chips can also be coupled to external circuits via the circuit board; for example, a chip can be coupled to a power supply circuit via the circuit board, which can then provide DC voltage to the chip to power it. Alternatively, with multiple chips, some of the chips can be coupled together via traces on the circuit board to collaboratively achieve specific functions.

[0078] like Figure 2As shown, chip 1 contains multiple transistors 101, which may include N-type transistors and P-type transistors. The N-type and P-type transistors can be transistors of any structure; for example, they can be CFETs, complementary metal-oxide-semiconductor (CMOS), FinFETs, etc. When fabricating N-type and P-type transistors on the same chip, if the material of the channel layer of the N-type transistor is the same as the material of the channel layer of the P-type transistor, the channel layers of both N-type and P-type transistors can be formed simultaneously using semiconductor processes.

[0079] However, when the same material is used as the channel layer material for both N-type and P-type transistors, if the hole mobility and electron mobility of the material are different, it will lead to a performance mismatch between the N-type and P-type transistors.

[0080] For example, the channel layer material of both N-type and P-type transistors includes silicon, which has a higher electron mobility than hole mobility. As a result, the performance of P-type transistors is weaker than that of N-type transistors.

[0081] For example, the channel layer material of both N-type and P-type transistors includes germanium (Ge), which has a higher hole mobility than electron mobility. As a result, the performance of N-type transistors is weaker than that of P-type transistors.

[0082] like Figure 3 As shown, those skilled in the art should know that in CMOS and CFET structures, when N-type and P-type transistors are connected in series and their gates are electrically connected, either the N-type transistor is on and the P-type transistor is off, or the P-type transistor is on and the N-type transistor is off. However, because the hole mobility in the channel layer of the P-type transistor is relatively weak, or the electron mobility in the channel layer of the N-type transistor is relatively weak, both the N-type and P-type transistors may be on simultaneously. This results in resistance in the branches containing the N-type and P-type transistors, leading to leakage current and increased chip power consumption.

[0083] Furthermore, when the hole mobility in the channel layer of a P-type transistor is weak, or the electron mobility in the channel layer of an N-type transistor is weak, the charging and discharging speeds of the P-type and N-type transistors are mismatched, the transistor switching speed decreases, and a transmission delay problem occurs.

[0084] Based on this, related technologies propose that materials with higher hole mobility can be selected as the channel layer material for P-type transistors, and materials with higher electron mobility can be selected as the channel layer material for N-type transistors.

[0085] However, if the channel layer materials of N-type and P-type transistors are different, it is necessary to separately lithographically etch sacrificial layers in the regions where the N-type and P-type transistors are located, based on the materials of their channel layers. On the one hand, this increases the fabrication process for N-type and P-type transistors, which is not conducive to saving fabrication costs; on the other hand, because the sacrificial layers in the regions where the N-type and P-type transistors are lithographically etched separately, the number of etching operations during the fabrication process increases. Since the dimensions of each film layer in N-type and P-type transistors are very small, especially under the condition of gradually shrinking technology nodes, the film layer dimensions may shrink to the nanometer scale. Multiple etching operations, as well as the cleaning process after etching, increase the probability of film layer collapse, reduce chip yield, and increase costs.

[0086] Furthermore, related technologies propose that, when the channel layer materials of N-type and P-type transistors are the same, if the hole mobility of the channel layer material is weak, then to balance the performance of N-type and P-type transistors, one N-type transistor may correspond to multiple P-type transistors; conversely, if the electron mobility of the channel layer material is weak, then to balance the performance of N-type and P-type transistors, one P-type transistor may correspond to multiple N-type transistors. However, while such technologies balance the performance of N-type and P-type transistors, they significantly increase the number of transistors in the chip, which is detrimental to the trend of chip miniaturization.

[0087] Based on the above, this application provides a method for fabricating a chip, the chip including N-type transistors and P-type transistors. This method reduces etching and cleaning processes without increasing the number of transistors, prevents flip-flop issues in the transistor layers, and improves chip yield. Simultaneously, it allows for a better performance match between N-type and P-type transistors.

[0088] The fabrication process of N-type and P-type transistors will be described in detail below with reference to the accompanying drawings.

[0089] This application provides a method for fabricating N-type transistors and P-type transistors, such as... Figure 4 As shown, this can be achieved through the following steps:

[0090] S110, a sacrificial layer and a channel layer are formed on a substrate, with the channel layer located between adjacent sacrificial layers. The channel layer includes a first channel layer for N-type transistors and a second channel layer for P-type transistors, with the first channel layer being made of the same material as the second channel layer.

[0091] Specifically, Figures 5a-5k Taking the simultaneous formation of four channel layers as an example, the fabrication process of the sacrificial layer and the channel layer is shown. Figure 5aAs shown, a first film layer 111, a second film layer 121, a first mask layer 31, and a photoresist 32 can be sequentially formed on the substrate 10. Figure 5b As shown, photoresist 32 is exposed and developed to obtain photoresist pattern 321. (As shown...) Figure 5c and Figure 5d As shown, under the protection of the photoresist pattern 321, the first mask layer 31 is etched to obtain the first mask pattern 311. During the etching of the first mask layer 31, the photoresist pattern 321 can also be completely etched. Then, as... Figure 5e As shown, a second mask layer 33 is formed on the side of the first mask pattern 311 facing away from the substrate 10. Figure 5f As shown, dry etching is used to etch the second mask layer 33 to obtain a second mask pattern 331. Along the distance direction between adjacent first mask patterns 311, the second mask pattern 331 is located on opposite sides of each first mask pattern 311, and adjacent second mask patterns 331 are disconnected. Figure 5g As shown, the first mask pattern 311 is removed. Figures 5h-5k As shown, under the protection of the second mask pattern 331, the second film layer 121 is used to obtain the channel layer 12, and the first film layer 111 is etched to obtain the sacrificial layer 11.

[0092] Of course, other processes can also be used to form the sacrificial layer 11 and the channel layer 12, and this application embodiment does not limit this.

[0093] Next, a third film layer can be formed on the side of the trench layer 12 away from the substrate 10. The material of the third film layer may include an oxide material. In some possible implementations, the third film layer 131 may also be subjected to chemical mechanical polishing (CMP), and the second mask pattern 331 may serve as a CMP stop layer.

[0094] like Figure 6a and Figure 6b As shown, the third film layer can also be etched back to remove the portion of the third film layer located on the side of the trench layer 12 facing away from the substrate 10, to obtain a shallow trench isolation (STI) layer 13, exposing the trench layer 12 and the sacrificial layer 11. The shallow trench isolation layer 13 is located between adjacent trench layers 12. When removing the portion of the third film layer located on the side of the trench layer 12 facing away from the substrate 10, the second mask pattern 331 can also be used to protect the sacrificial layer 11 and the trench layer 12. During the etching of the portion of the third film layer located on the side of the trench layer 12 facing away from the substrate 10, the second mask pattern 331 can also be completely etched.

[0095] In some possible implementations, the sacrificial layer 11 and the channel layer 12 prepared using the above-described process and the second mask pattern 331 have the same pattern. In other possible implementations, the patterns of the sacrificial layer 11 and the channel layer 12 may also be different, as long as the pattern of the sacrificial layer 11 does not affect subsequent steps (e.g., forming the shallow trench isolation layer 13).

[0096] In some possible implementations, this application does not limit the specific material of the channel layer 12, as long as the materials of the first channel layer and the second channel layer are the same. Since the materials of the first and second channel layers are the same, on the one hand, the first and second channel layers can be formed simultaneously through the same semiconductor process. Compared to schemes where the materials of the first and second channel layers are different, this application simplifies the chip fabrication process, reduces the number of masks required during chip fabrication, and thus saves chip fabrication costs. On the other hand, it eliminates the need for separate etching of sacrificial layers 11 and other structures to protect the first or second channel layers, reducing the number of etching and cleaning cycles, improving the collapse phenomenon of each film layer in N-type and P-type transistors due to etching and cleaning processes, increasing chip yield, and reducing costs.

[0097] In some possible ways of implementation, such as Figure 5k As shown, for different types of transistors, the channel layer 12 can be a single layer or multiple layers along the direction from the substrate 10 to the sacrificial layer 11. Regardless of whether the channel layer 12 is a single layer or multiple layers, each channel layer 12 is located between adjacent sacrificial layers 11.

[0098] S120, such as Figures 7a-7b As shown, a dummy gate 14 and a second spacer layer 15 are formed. Along the channel length direction, the second spacer layer 15 is disposed on opposite sides of the dummy gate 14.

[0099] It should be noted here that those skilled in the art should know that for N-type and P-type transistors, the channel length direction refers to the direction from the source to the drain of the N-type and P-type transistors.

[0100] In some possible implementations, the gate typically comprises a metallic material, which is highly temperature-sensitive, while the front-end process involves multiple high-temperature processes. Therefore, a dummy gate 14 made of non-metallic material can be formed first. On the one hand, this prevents high temperatures from affecting the gate's performance; on the other hand, forming the dummy gate 14 at the location of the gate to be formed first prevents other film layers from forming at that location and affecting the gate's pattern and position.

[0101] In some possible implementations, the material of the dummy gate 14 is not limited, as long as the material of the dummy gate 14 does not affect the performance of other films in the front-end process during its formation. For example, the material of the dummy gate 14 may include amorphous silicon (a-Si).

[0102] In some possible implementations, the material of the second spacer layer 15 is not limited, as long as the second spacer layer 15 can serve as an insulator between the gate 11 to be formed and the source and drain to be formed.

[0103] Considering that the dummy gate 14 still needs to be removed, in order to prevent damage to the second spacer layer 15 due to the removal of the dummy gate 14, the material of the second spacer layer 15 and the material of the dummy gate 14 can optionally have a large etching selectivity ratio.

[0104] In some possible ways of implementation, such as Figure 8a and Figure 8b As shown, after step S120 and before step S130, the method for fabricating N-type transistors and P-type transistors further includes: performing a first selective etching on the sacrificial layer 11 and the channel layer 12, wherein the edges of the sacrificial layer 11 and the channel layer 12 retained after etching can be flush with the edges of the second spacer layer 15.

[0105] S130, such as Figure 9 As shown, the same photolithography process is used to remove the portion of the sacrificial layer 11 except for the channel region.

[0106] It should be noted here that the channel region refers to the portion of the channel layer 12 that overlaps with the orthographic projection of the gate to be formed on the substrate 10 and is located between the source and the drain to be formed.

[0107] In this embodiment, since the material of the first channel layer is the same as that of the second channel layer, when selectively removing the portion of the sacrificial layer 11 other than the channel region, a single photolithography process can be used to remove the portion of the sacrificial layer 11 of both the N-type and P-type transistors other than the channel region. This reduces the number of etching and cleaning operations on the chip, improves the problem of flipping in each film layer of the N-type and P-type transistors, increases chip yield, and reduces costs.

[0108] In some possible implementations, regardless of whether the number of channel layers 12 is one or more, all portions of the sacrificial layers 11 other than the channel regions are selectively removed.

[0109] In some possible implementations, based on the materials of the sacrificial layer 11 and the channel layer 12, embodiments of this application can perform dry etching or wet selective removal of the sacrificial layer 11. For example, the material of the sacrificial layer 11 may include silicon, and the material of the channel layer 12 may include germanium. Since alkaline solutions have a high selectivity for germanium, wet etching of the sacrificial layer 11 can be performed using an alkaline solution, introducing fewer surface state defects. Alternatively, dry etching of the sacrificial layer 11 can be performed using hydrogen along the direction from the source to the drain to be formed, and also along the direction from the drain to the source.

[0110] S140, such as Figure 10 As shown, along the length of the channel, the first spacer layer 16 is filled at the location where the sacrificial layer 11 is removed in step S130. Alternatively, along the length of the channel, the sacrificial layer 11 is recessed relative to the channel layer 12, and the first spacer layer is disposed at the location where the sacrificial layer 11 is recessed relative to the channel layer 12.

[0111] In some possible implementations, the location of the first spacer layer 16 is related to the location of the cap layer described below. Along the length of the channel, the first spacer layer 16 is located on opposite sides of the cap layer. The locations of the cap layer and the first spacer layer 16 are described in detail below.

[0112] In some possible implementations, the material of the first spacer layer 16 is not limited, as long as the material of the first spacer layer 16 is an insulating material.

[0113] Optionally, the dielectric constant of the material of the first spacer layer 16 can be less than the dielectric constant of the material of the channel layer 12. Furthermore, the dielectric constant of the material of the first spacer layer 16 can also be less than the dielectric constant of the materials of the gate, source, and drain to be formed. Since the first spacer layer 16 is disposed between the gate to be formed and the source and drain, the parasitic capacitance between the gate to be formed and the source and drain can be reduced by using a material with a smaller dielectric constant as the material of the first spacer layer 16.

[0114] For example, the material of the first spacer layer 16 may include at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxide (SiO2), and silicon carbon nitride (SiOCN).

[0115] In some possible implementations, corresponding to step S130, a first spacer layer 16 is filled at the location where the sacrificial layer 11 is selectively removed. That is, if the channel layer 12 is a single layer, the first spacer layer 16 is filled between the substrate 10 and the channel layer 12, and on the side of the channel layer 12 facing away from the substrate 10. If the channel layer 12 is a multilayer layer, the first spacer layer 16 is filled between the substrate 10 and the channel layer 12, between adjacent channel layers 12, and on the side of the channel layer 12 facing away from the substrate 10.

[0116] In some possible ways of implementation, such as Figure 11a and Figure 11b As shown, after step S140 and before step S150, the fabrication method of the N-type transistor and the P-type transistor may further include: forming a source 17 and a drain 18. Along the channel length direction, the source 17 and the drain 18 are respectively disposed on opposite sides of the channel layer 11.

[0117] Subsequently, the fabrication method of N-type and P-type transistors may further include: forming an inter-level dielectric (ILD) 20 on the substrate 10, wherein the inter-level dielectric 20 may cover the source 17, drain 18, second spacer layer 15, and shallow trench isolation layer 13, exposing the dummy gate. In this way, when removing the dummy gate 14 and sacrificial layer 11 in step S150, the source 17, drain 18, second spacer layer 15, and shallow trench isolation layer 13 can be avoided from being affected.

[0118] S150, such as Figure 12 As shown, the portion of the dummy gate 14 and the sacrificial layer 11 located in the channel region is removed. At this point, the sacrificial layer 11 is completely removed.

[0119] It should be noted here that the portion of the sacrificial layer 11 located in the channel region refers to the portion of the channel layer 12 that overlaps with the orthographic projection of the gate to be formed on the substrate 10 and is located between the source 12 to be formed and the drain 13 to be formed.

[0120] In some possible implementations, the portion of the sacrificial layer 11 removed may exactly coincide with the channel region; or, a portion of the removed portion of the sacrificial layer 11 may coincide with the channel region while another portion may not; or, all the removed portions of the sacrificial layer 11 may coincide with the channel region, but the area of ​​its orthographic projection onto the substrate 10 is smaller than the area of ​​the channel region. The portion of the sacrificial layer 11 selectively removed in step S130 refers to the portion of the sacrificial layer 11 other than the portion removed in step S150.

[0121] It should be noted here that the orthogonal projection of the removed portion of the sacrificial layer 11 onto the substrate 10 refers to the projection of the sacrificial layer 11 onto the substrate 10 perpendicularly along the direction from the sacrificial layer 11 to the substrate 10.

[0122] In some possible implementations, the method of removing the portion of the sacrificial layer 11 located in the channel region can be the same as the method of selectively etching the sacrificial layer 11 in the aforementioned step S130, and will not be repeated here. It should be noted that if hydrogen is used to perform dry etching on the portion of the sacrificial layer located in the channel region, the etching direction can be along the direction from the channel layer 12 to the substrate 10.

[0123] S160, such as Figure 13a and Figure 13b As shown, a capping layer 19 is formed on the side of the channel layer 12 facing and / or away from the substrate 10, and the capping layer 19 is located in the channel region. That is, the region where the capping layer 19 is located is the region where the sacrificial layer 11 removed in step S150 is located. Along the length direction of the channel, the channel layer 12 protrudes from the capping layer 19, and the first spacer layer 16 is located on opposite sides of the capping layer 19. Along the direction from the substrate 10 to the channel layer 12, the thickness of the capping layer 19 is less than the thickness of the sacrificial layer 11. The capping layer 19 forms a split energy band at its interface with the channel layer 12, so as to confine electrons in the capping layer 19 when the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value, and to confine holes in the capping layer 19 when the electron mobility of the first channel layer is greater than a third preset value and the hole mobility of the second channel layer is less than a fourth preset value.

[0124] In some possible implementations, based on the performance differences between different types of N-type and P-type transistors, as well as the material differences of the channel layer 12, the first preset value may be the same as or different from the third preset value; the second preset value may be the same as or different from the fourth preset value.

[0125] For example, the electron mobility of the first channel layer 12 is less than a first preset value of 200 cm⁻¹. 2 At / V·s, because the electron mobility of the first channel layer 12 is too small, the N-type transistor needs to add a capping layer 19 to confine electrons in the capping layer 19, thereby improving the electron mobility of the N-type transistor and thus improving the performance of the N-type transistor.

[0126] The hole mobility of the second channel layer 12 is greater than the second preset value of 110cm. 2 At / V·s, the hole mobility of the channel layer 12 of the P-tube is significantly improved, eliminating the need for the introduction of the capping layer 19.

[0127] In some possible implementations, the variations in electron and hole mobility of the channel layer 12 are related to the composition of certain elements in the material of the channel layer 12. For example... Figure 13c and Figure 13d As shown, the material of the channel layer 12 includes germanium silicon (Si). x Ge 1-x Taking a silicon-based transistor as an example, the electron mobility of the channel layer 12 can be related to the germanium content in the channel layer 12. Compared to a channel layer 12 containing only silicon, as the germanium content in the silicon-germanium transistor increases, the electron mobility of the channel layer 12 gradually decreases, while the hole mobility gradually increases, thereby improving the performance of the P-type transistor and reducing the performance of the N-type transistor. Where 0 < x < 1.

[0128] For example, when the germanium content in germanium-silicon is 0.4%, the electron mobility of channel layer 12 is relatively low, at the first preset value of 200 cm⁻¹. 2 For N-channel transistors, a silicon capping layer 19 needs to be introduced. In this case, the hole mobility of the channel layer 12 is greater than 110 cm⁻¹. 2 / V·s, P-type transistors do not require a capping layer 19.

[0129] like Figure 14 As shown, taking an example where the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value, the performance of the N-type transistor is weaker than that of the P-type transistor. For example, the material of the channel layer 12 includes germanium. In order to improve the performance of the P-type transistor without reducing the performance of the N-type transistor, a material that can form a split energy band at the interface with the channel layer 12 can be selected as the material of the capping layer 19. When the N-type transistor is turned on, a two-dimensional electron gas is formed, which confines the electrons in the capping layer 19 of the N-type transistor, improves the electron mobility of the N-type transistor, thereby improving the performance of the N-type transistor and making the performance of the P-type transistor more matched with that of the N-type transistor.

[0130] Similarly, if the electron mobility of the first channel layer is greater than a third preset value, and the hole mobility of the second channel layer is less than a fourth preset value, the performance of the P-type transistor is weaker than that of the N-type transistor. To improve the performance of the N-type transistor without reducing the performance of the P-type transistor, a material capable of forming a split energy band at the interface with the channel layer 12 can be selected as the material for the capping layer 19. When the P-type transistor is turned on, a two-dimensional electron gas of holes is formed, confining the holes within the capping layer 19 of the P-type transistor. This allows the capping layer 19 and the channel layer 12 to function together as part of the channel, increasing the hole mobility of the P-type transistor and thus improving its performance, making the performance of the P-type transistor more closely matched with that of the N-type transistor.

[0131] Furthermore, the electron mobility of N-type transistors or the hole mobility of P-type transistors can be improved by changing the materials of the substrate 10 and the channel layer 12. For example, when the electron mobility of the first channel layer is less than a first preset value, and the hole mobility of the second channel layer is greater than a second preset value, and the performance of the N-type transistor is weaker than that of the P-type transistor, the substrate 10 is a relaxed germanium-based substrate, and a strained silicon channel layer is grown on the relaxed germanium-based substrate. This introduces tensile stress into the silicon channel layer, causing the conduction band of the silicon channel layer to split, removing the sixfold degeneracy, and becoming a twofold degeneracy light electron effective mass band. This places the silicon conduction band below the germanium conduction band, thereby improving the effective electron mobility of the N-type transistor. Experiments have shown that the effective electron mobility of the N-type transistor can be increased by more than two times.

[0132] In some possible implementations, the material of the capping layer 19 is not limited, as long as it can form a split energy band at the interface with the channel layer 12 when the performance of the N-type transistor is weaker than that of the P-type transistor, forming a two-dimensional electron gas when the N-type transistor is turned on, confining electrons in the capping layer 19 of the N-type transistor; and when the performance of the P-type transistor is weaker than that of the N-type transistor, forming a split energy band at the interface with the channel layer 12, forming a two-dimensional electron gas of holes when the P-type transistor is turned on, confining holes in the capping layer 19 of the P-type transistor. For example, the material of the capping layer 19 may include III-V group materials or two-dimensional materials, etc.

[0133] In some possible implementations, the thickness of the capping layer 19 is less than the thickness of the sacrificial layer 11, that is, the capping layer 19 fails to completely fill the void area between the channel layer 12 and the substrate 10 (or between the channel layer 12 and the substrate 10, and between adjacent channel layers) in the direction from the substrate 10 to the channel layer 12.

[0134] In some possible implementations, where the electron mobility of the first channel layer is less than a first preset value, the hole mobility of the second channel layer is greater than a second preset value, and the performance of the N-type transistor is weaker than that of the P-type transistor, the thickness of the portion of the capping layer 19 formed in step S160 located in the P-type transistor can be less than the thickness of the portion of the capping layer 19 located in the N-type transistor. For example, the thickness of the portion of the capping layer 19 formed in step S160 located in the N-type transistor is 3 nm, and the thickness of the portion of the capping layer 19 formed in step S160 located in the P-type transistor is 1 nm.

[0135] When the electron mobility of the first channel layer is greater than a third preset value, and the hole mobility of the second channel layer is less than a fourth preset value, and the performance of the P-type transistor is weaker than that of the N-type transistor, the thickness of the portion of the capping layer 19 formed in step S160 located in the P-type transistor can be greater than the thickness of the portion of the capping layer 19 located in the N-type transistor. For example, the thickness of the portion of the capping layer 19 formed in step S160 located in the P-type transistor is 3 nm, and the thickness of the portion of the capping layer 19 formed in step S160 located in the N-type transistor is 1 nm.

[0136] After step S160 and before step S170, the fabrication methods for N-type and P-type transistors may further include cleaning the exposed surfaces in the capping layer 19. During the cleaning process, the thickness of the capping layer 19 may be affected and thinned. In this application embodiment, it should be ensured that even when the performance of the N-type transistor is weaker than that of the P-type transistor, the N-type transistor still includes the capping layer 19 after cleaning; the P-type transistor may or may not include the capping layer 19, that is, the thickness of the capping layer is 0 (…). Figure 15a To ensure that the performance of the P-type transistor is weaker than that of the N-type transistor, the P-type transistor still includes the capping layer 19 after cleaning; the N-type transistor may or may not include the capping layer 19, that is, the thickness of the capping layer is 0. Figure 15b ).

[0137] In some possible ways of implementation, such as Figure 13b As shown, for substrate 10 materials that are easy to form films on, such as silicon, capping layer 19 can also be disposed on the surface of substrate 10 facing the channel layer 12.

[0138] In addition, the capping layer 19 can also introduce stress at its interface with the channel layer 12 to improve the carrier mobility of N-type transistors and P-type transistors.

[0139] For example, for an N-type transistor, the lattice constant of the material of the capping layer 19 can be greater than that of the material of the first channel layer. The capping layer 19 can be used to generate compressive strain on the first channel layer, thereby improving the carrier mobility of the N-type transistor.

[0140] For example, for a P-type transistor, the lattice constant of the material of the capping layer 19 can be smaller than that of the material of the second channel layer. The capping layer 19 can be used to generate tensile strain on the second channel layer to improve the carrier mobility of the P-type transistor.

[0141] Since the thickness of the capping layer 19 is less than the thickness of the sacrificial layer 11, the surface of the capping layer 19 facing or away from the substrate 10 is exposed before step S170. Therefore, in step S170, a gate dielectric layer and a gate can be sequentially formed on the exposed surface side of the capping layer, and a plurality of gates can be used to control the channel layer 12.

[0142] For N-type and / or P-type transistors that retain the capping layer 19 after cleaning, the capping layer 19 can also be used to reduce the interface states at the interface between the channel layer 12 and the gate dielectric layer, improving the interface and addressing the problem that the gate voltage cannot be fully used to control the conduction of the N-type and / or P-type transistors. Furthermore, in some possible implementations, the materials of the channel layer 12 (e.g., germanium-silicon) and the gate dielectric layer (e.g., hafnium oxide) can result in a high number of interface states at the interface between the channel layer 12 and the gate dielectric layer. This application can utilize the existing capping layer 19 disposed between the channel layer 12 and the gate dielectric layer to reduce dangling bonds at the interface between the channel layer 12 and the gate dielectric layer, thereby reducing the interface state density and improving the interface quality between the channel layer 12 and the gate dielectric layer.

[0143] In another embodiment, this application also provides a chip that can be fabricated using the foregoing embodiments. For example... Figure 15a As shown, in cases where the performance of an N-type transistor is weaker than that of a P-type transistor, the N-type transistor includes a first channel layer and a capping layer 19, while the P-type transistor includes a second channel layer; the first and second channel layers are made of the same material. The capping layer 19 is located in the channel region of the N-type transistor and is disposed on the side of the channel layer 12 facing and / or away from the substrate 10; along the direction from the substrate 10 to the first channel layer, the thickness of the capping layer 19 is less than the distance between the substrate 10 and the first channel layer. The capping layer 19 forms a split energy band at its interface with the channel layer 12 to confine electrons in the capping layer 19 when the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value.

[0144] In some possible implementations, the N-type and P-type transistors prepared by the foregoing embodiments may further include a source 17, a drain 18, a gate dielectric layer, and a gate. For details regarding the positions of the source 17, drain 18, gate dielectric layer, and gate, please refer to the foregoing embodiments; further details will not be repeated here.

[0145] In some possible implementation methods, specific values ​​for the first and second preset values ​​can be set based on actual needs. For example, the electron mobility of the first channel layer 12 is less than the first preset value of 200 cm⁻¹. 2 At / V·s, because the electron mobility of the first channel layer 12 is too small, the N-type transistor needs to add a capping layer 19 to confine electrons in the capping layer 19, thereby improving the electron mobility of the N-type transistor and thus improving the performance of the N-type transistor.

[0146] The hole mobility of the second channel layer 12 is greater than the second preset value of 110cm. 2 At / V·s, the hole mobility of the channel layer 12 of the P-tube is significantly improved, eliminating the need for the introduction of the capping layer 19.

[0147] In some possible implementations, the variations in electron and hole mobility of the channel layer 12 are related to the composition of certain elements in the material of the channel layer 12. For example... Figure 13c and Figure 13d As shown, the material of the channel layer 12 includes germanium silicon (Si). x Ge 1-x Taking a silicon-based transistor as an example, the electron mobility of the channel layer 12 can be related to the germanium content in the channel layer 12. Compared to a channel layer 12 containing only silicon, as the germanium content in the silicon-germanium transistor increases, the electron mobility of the channel layer 12 gradually decreases, while the hole mobility gradually increases, thereby improving the performance of the P-type transistor and reducing the performance of the N-type transistor. Where 0 < x < 1.

[0148] For example, when the germanium content in germanium-silicon is 0.4%, the electron mobility of channel layer 12 is relatively low, at the first preset value of 200 cm⁻¹. 2 For N-channel transistors, a silicon capping layer 19 needs to be introduced. In this case, the hole mobility of the channel layer 12 is greater than 110 cm⁻¹. 2 / V·s, P-type transistors do not require a capping layer 19.

[0149] Building upon this, for N-type and P-type transistors including the capping layer 19, the capping layer 19 can also be used to reduce the interface states at the interface between the channel layer 12 and the gate dielectric layer to be formed, improving the interface and addressing the problem that the gate voltage cannot be fully used to control the conduction of the N-type and P-type transistors. Furthermore, in some possible implementations, the materials of the channel layer 12 (e.g., germanium-silicon) and the gate dielectric layer (e.g., hafnium oxide) can result in a high number of interface states at the interface between the channel layer 12 and the gate dielectric layer. This application can utilize the existing capping layer 19 disposed between the channel layer 12 and the gate dielectric layer to reduce dangling bonds at the interface between the channel layer 12 and the gate dielectric layer, thereby reducing the interface state density and improving the interface quality between the channel layer 12 and the gate dielectric layer.

[0150] In some possible ways of implementation, such as Figure 13a As shown, the P-type transistor also includes a capping layer 19, which is located in the channel region of the P-type transistor. The thickness of the portion of the capping layer 19 located in the P-type transistor is less than the thickness of the portion of the capping layer 19 located in the N-type transistor. For example, the thickness of the portion of the capping layer 19 located in the N-type transistor is 3 nm, and the thickness of the portion of the capping layer 19 located in the P-type transistor is 1 nm.

[0151] In some possible implementations, both the first and second channel layers are multilayered along the direction from the substrate 10 to the sacrificial layer 11. The thickness of the capping layer 19 can also be less than the distance between adjacent first channel layers and the distance between adjacent second channel layers. Furthermore, the N-type and P-type transistors may include a first spacer layer 16, which is disposed between adjacent first channel layers and adjacent second channel layers to provide support.

[0152] Based on this, the dielectric constant of the material of the first spacer layer 16 can be lower than that of the materials of the first channel layer, the second channel layer, the source 17, the drain 18, and the gate. Since the first spacer layer 16 is disposed between the gate to be formed and the source and drain, the parasitic capacitance between the gate to be formed and the source and drain can be reduced by using a material with a smaller dielectric constant as the material of the first spacer layer 16.

[0153] Furthermore, the other explanations and beneficial effects of the embodiments of this application are the same as those of the aforementioned chip fabrication method, and will not be repeated here.

[0154] In yet another embodiment, this application also provides a chip that can be fabricated using the foregoing embodiments. For example... Figure 15b As shown, when the performance of a P-type transistor is weaker than that of an N-type transistor, the N-type transistor includes a first channel layer, and the P-type transistor includes a second channel layer and a capping layer 19; the first channel layer and the second channel layer are made of the same material. The capping layer 19 is located in the channel region of the P-type transistor and is disposed on the side of the channel layer 12 facing and / or away from the substrate 10; along the direction from the substrate 10 to the second channel layer, the thickness of the capping layer 19 is less than the distance between the substrate 10 and the second channel layer. The capping layer 19 forms a split energy band at its interface with the channel layer 12 to confine holes in the capping layer 19 when the electron mobility of the first channel layer is greater than a third preset value and the hole mobility of the second channel layer is less than a fourth preset value.

[0155] In some possible implementations, the N-type and P-type transistors prepared by the foregoing embodiments may further include a source 17, a drain 18, a gate dielectric layer, and a gate. For details regarding the positions of the source 17, drain 18, gate dielectric layer, and gate, please refer to the foregoing embodiments; further details will not be repeated here.

[0156] In some possible implementations, based on the performance differences between different types of N-type and P-type transistors, as well as the material differences of the channel layer 12, the first preset value may be the same as or different from the third preset value; the second preset value may be the same as or different from the fourth preset value.

[0157] To improve the performance of N-type transistors without degrading the performance of P-type transistors, a material capable of forming a split energy band at the interface with the channel layer 12 can be selected as the material for the capping layer 19. When the P-type transistor is turned on, a two-dimensional electron gas of holes is formed, confining the holes within the capping layer 19. This allows the capping layer 19 and the channel layer 12 to function together as part of the channel, improving the electron mobility of the P-type transistor and thus enhancing its performance, making the performance of the P-type transistor more closely matched with that of the N-type transistor.

[0158] Building upon this, for N-type and P-type transistors including the capping layer 19, the capping layer 19 can also be used to reduce the interface states at the interface between the channel layer 12 and the gate dielectric layer to be formed, improving the interface and addressing the problem that the gate voltage cannot be fully used to control the conduction of the N-type and P-type transistors. Furthermore, in some possible implementations, the materials of the channel layer 12 (e.g., germanium-silicon) and the gate dielectric layer (e.g., hafnium oxide) can result in a high number of interface states at the interface between the channel layer 12 and the gate dielectric layer. This application can utilize the existing capping layer 19 disposed between the channel layer 12 and the gate dielectric layer to reduce dangling bonds at the interface between the channel layer 12 and the gate dielectric layer, thereby reducing the interface state density and improving the interface quality between the channel layer 12 and the gate dielectric layer.

[0159] In some possible ways of implementation, such as Figure 13a As shown, the N-type transistor also includes a capping layer 19, which is located in the channel region of the N-type transistor. The thickness of the portion of the capping layer 19 located in the N-type transistor is less than the thickness of the portion of the capping layer 19 located in the P-type transistor. For example, the thickness of the portion of the capping layer 19 located in the P-type transistor is 3 nm, and the thickness of the portion of the capping layer 19 located in the N-type transistor is 1 nm.

[0160] In some possible implementations, both the first and second channel layers are multilayered along the direction from the substrate 10 to the sacrificial layer 11. The thickness of the capping layer 19 can also be less than the distance between adjacent first channel layers and the distance between adjacent second channel layers. Furthermore, the N-type and P-type transistors may include a first spacer layer 16, which is disposed between adjacent first channel layers and adjacent second channel layers to provide support.

[0161] Based on this, the dielectric constant of the material of the first spacer layer 16 can be lower than that of the materials of the first channel layer, the second channel layer, the source 17, the drain 18, and the gate. Since the first spacer layer 16 is disposed between the gate to be formed and the source and drain, the parasitic capacitance between the gate to be formed and the source and drain can be reduced by using a material with a smaller dielectric constant as the material of the first spacer layer 16.

[0162] Furthermore, the other explanations and beneficial effects of the embodiments of this application are the same as those of the aforementioned chip fabrication method, and will not be repeated here.

[0163] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for fabricating a chip, characterized in that, The chip includes N-type transistors and P-type transistors, and the method for fabricating the N-type transistors and the P-type transistors includes: A sacrificial layer and a channel layer are stacked on a substrate, the channel layer being located between adjacent sacrificial layers; the channel layer includes a first channel layer for N-type transistors and a second channel layer for P-type transistors, the material of the first channel layer being the same as the material of the second channel layer; Remove the portion of the sacrificial layer located in the channel region; A capping layer is formed on the side of the channel layer facing and / or away from the substrate, the capping layer being located in the channel region; the thickness of the capping layer is less than the thickness of the sacrificial layer along the direction from the substrate to the channel layer; the capping layer forms a split energy band at its interface with the channel layer, so as to confine electrons in the capping layer when the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value, and to confine holes in the capping layer when the electron mobility of the first channel layer is greater than a third preset value and the hole mobility of the second channel layer is less than a fourth preset value.

2. The chip fabrication method according to claim 1, characterized in that, The first preset value is equal to the third preset value, and the second preset value is equal to the fourth preset value.

3. The method for fabricating a chip according to claim 1 or 2, characterized in that, The first preset value is 200cm 2 / V·s, the second preset value is 110cm 2 / V·s.

4. The method for fabricating a chip according to claim 1 or 2, characterized in that, After forming the sacrificial layer and the channel layer stacked on the substrate, and before removing the portion of the sacrificial layer located in the channel region, the fabrication method of the N-type transistor and the P-type transistor further includes: Using the same photolithography process, the portion of the sacrificial layer other than the channel region is removed; along the length of the channel, the sacrificial layer is recessed relative to the channel layer; Along the length of the channel, a first spacer layer is filled at a position where the sacrificial layer is recessed relative to the channel layer.

5. The method for fabricating a chip according to claim 4, characterized in that, The dielectric constant of the material of the first spacer layer is less than the dielectric constant of the material of the channel layer.

6. The method for fabricating a chip according to claim 4, characterized in that, After forming the sacrificial layer and the channel layer stacked on the substrate, and before removing the portion of the sacrificial layer other than the channel region using the same photolithography process, the fabrication method of the N-type transistor and the P-type transistor further includes: A dummy gate and a second spacer layer are formed; along the length of the channel, the second spacer layer is disposed on opposite sides of the dummy gate; After filling the first spacer layer at the location where the sacrificial layer is recessed relative to the channel layer, and before forming a capping layer on the side of the channel layer facing and / or away from the substrate, the fabrication method of the N-type transistor and the P-type transistor further includes: Remove the dummy gate; After forming a capping layer on the side of the channel layer facing and / or away from the substrate, the method for fabricating the N-type transistor and the P-type transistor further includes: Clean the exposed surfaces in the cap layer; A gate dielectric layer and a gate are sequentially formed on the exposed surface side of the cap layer.

7. The method for fabricating a chip according to claim 1 or 2, characterized in that, The electron mobility of the first channel layer is less than the first preset value, the hole mobility of the second channel layer is greater than the second preset value, and the thickness of the portion of the capping layer located in the P-type transistor is less than the thickness of the portion of the capping layer located in the N-type transistor.

8. The method for fabricating a chip according to claim 4, characterized in that, The thickness of the portion of the capping layer located in the P-type transistor is 0.

9. The method for fabricating a chip according to claim 1 or 2, characterized in that, The electron mobility of the first channel layer is greater than the third preset value, the hole mobility of the second channel layer is less than the fourth preset value, and the thickness of the portion of the capping layer located in the P-type transistor is greater than the thickness of the portion of the capping layer located in the N-type transistor.

10. The method for fabricating a chip according to claim 9, characterized in that, The thickness of the portion of the capping layer located in the N-type transistor is 0.

11. The method for fabricating a chip according to claim 1 or 2, characterized in that, The lattice constant of the material of the capping layer is greater than the lattice constant of the material of the first channel layer; and / or, The lattice constant of the material of the capping layer is less than the lattice constant of the material of the second channel layer.

12. The method for fabricating a chip according to claim 1 or 2, characterized in that, The channel layer is multilayered along the direction from the substrate to the sacrificial layer.

13. A chip, characterized in that, Includes a substrate, and N-type transistors and P-type transistors disposed on the substrate; The N-type transistor includes a first channel layer and a capping layer, and the P-type transistor includes a second channel layer; the first channel layer and the second channel layer are made of the same material; The capping layer is located in the channel region of the N-type transistor and is disposed on the side of the channel layer facing and / or away from the substrate; Along the direction from the substrate to the first trench layer, the thickness of the capping layer is less than the distance between the substrate and the first trench layer; The capping layer forms a split energy band at its interface with the channel layer, thereby confining electrons in the capping layer when the electron mobility of the first channel layer is less than a first preset value and the hole mobility of the second channel layer is greater than a second preset value.

14. The chip according to claim 13, characterized in that, The first preset value is 200cm 2 / V·s, the second preset value is 110cm 2 / V·s.

15. The chip according to claim 14, characterized in that, The P-type transistor also includes the capping layer, which is located in the channel region of the P-type transistor.

16. The chip according to claim 15, characterized in that, The thickness of the portion of the capping layer located in the P-type transistor is less than the thickness of the portion of the capping layer located in the N-type transistor.

17. The chip according to any one of claims 13-16, characterized in that, Along the direction from the substrate toward the first channel layer, both the first channel layer and the second channel layer are multilayered, and the thickness of the capping layer is less than the distance between adjacent first channel layers and the distance between adjacent second channel layers.

18. A chip, characterized in that, Includes a substrate, and N-type transistors and P-type transistors disposed on the substrate; The N-type transistor includes a first channel layer, and the P-type transistor includes a second channel layer and a capping layer; the first channel layer and the second channel layer are made of the same material; The capping layer is located in the channel region of the P-type transistor and is disposed on the side of the channel layer facing and / or away from the substrate; Along the direction from the substrate to the second trench layer, the thickness of the capping layer is less than the distance between the substrate and the second trench layer; The capping layer forms a split energy band at its interface with the channel layer, so as to confine holes in the capping layer when the electron mobility of the first channel layer is greater than a third preset value and the hole mobility of the second channel layer is less than a fourth preset value.

19. The chip according to claim 18, characterized in that, The N-type transistor also includes the capping layer, which is located in the channel region of the N-type transistor.

20. The chip according to claim 19, characterized in that, The thickness of the portion of the capping layer located in the N-type transistor is less than the thickness of the portion of the capping layer located in the P-type transistor.

21. The chip according to any one of claims 18-20, characterized in that, Along the direction from the substrate toward the first channel layer, both the first channel layer and the second channel layer are multilayered, and the thickness of the capping layer is less than the distance between adjacent first channel layers and the distance between adjacent second channel layers.

22. A terminal, characterized in that, It includes a circuit board and a chip as described in any one of claims 13-17 or 18-21, the chip being disposed on the circuit board.

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