TVS diode surface passivation structure and preparation process thereof

Abstract

This invention provides a surface passivation structure for a TVS diode, comprising a glass layer in a mesa-shaped region on one or both sides of a silicon substrate; a protective layer is constructed between the silicon substrate and the glass layer, the protective layer comprising at least a polycrystalline silicon film layer, and silicon dioxide films are constructed between the polycrystalline silicon film layer and the silicon substrate, and between the polycrystalline silicon film layer and the glass layer. A fabrication process for the TVS diode surface passivation structure is also proposed. This invention provides a TVS diode surface passivation structure, a dual passivation protection structure that completely isolates the device from the external environment, ensuring excellent high reliability, chemical stability, and high-temperature characteristics; simultaneously, this structure exhibits low leakage current and high conductivity, maximizing IPP capability and reducing the influence of surface electric fields.

Description

Technical Field

[0001] This invention belongs to the field of surface passivation technology for semiconductor devices, and in particular relates to a surface passivation structure for TVS diodes and its fabrication process. Background Technology

[0002] In the industry, surface-in-passivation (SIN) structures for semiconductor Zener diodes typically employ a simple, single-layer glass layer as a protective dielectric film covering the semiconductor device surface. While this method is simple to manufacture and relatively inexpensive, its ability to fix and prevent harmful impurities (sodium ions, metal ions, etc.) from contaminating the device surface is poor, resulting in poor thermal stability and reliability after packaging. With the increasing demands for reliability in finished semiconductor rectifier devices, there is a need for a surface-in-passivation structure that is easy to implement in mass production, has good batch consistency, moderate cost, and high reliability. Summary of the Invention

[0003] This invention provides a passivation structure for TVS diodes and its fabrication process, which solves the technical problems of existing technologies that cannot effectively prevent harmful impurities (sodium ions, metal ions, etc.) from contaminating the device surface and the poor uniformity of passivation film thickness after the packaging temperature changes.

[0004] To solve at least one of the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0005] A TVS diode surface passivation structure includes a glass layer in a mesa-shaped area on one or both sides of a silicon substrate; a protective layer is constructed between the silicon substrate and the glass layer, the protective layer including at least a polycrystalline silicon film layer, and a silicon dioxide film layer is constructed between the polycrystalline silicon film layer and the silicon substrate, and between the polycrystalline silicon film layer and the glass layer.

[0006] Furthermore, the silicon dioxide film layer placed between the polycrystalline silicon film layer and the silicon substrate is a structural layer formed by chlorine-doped silicon dioxide;

[0007] The polycrystalline silicon film layer is a structural layer with semi-insulating polycrystalline silicon.

[0008] The silicon dioxide film layer placed between the polycrystalline silicon film layer and the glass layer is a structural layer formed of nitrogen-doped silicon dioxide.

[0009] Furthermore, the thickness of the silicon dioxide film layer constructed between the polycrystalline silicon film layer and the silicon substrate is less than the thickness of the polycrystalline silicon film layer.

[0010] Furthermore, the thickness of the silicon dioxide film layer constructed between the polycrystalline silicon film layer and the silicon substrate is 1000-3000 Å;

[0011] The thickness of the polycrystalline silicon film is 5000-10000 Å.

[0012] Furthermore, the thickness of the silicon dioxide film layer disposed between the polycrystalline silicon film layer and the glass layer is greater than the thickness of the silicon dioxide film layer disposed between the polycrystalline silicon film layer and the silicon substrate, but less than the thickness of the polycrystalline silicon film layer.

[0013] Furthermore, the thickness of the silicon dioxide film layer disposed between the polycrystalline silicon film layer and the glass layer is 2000-5000 Å.

[0014] Furthermore, a solder resist ring film layer is also constructed on the side of the glass layer away from the protective layer.

[0015] Furthermore, for a unidirectional TVS diode, the mesa-shaped region is constructed on one side of the silicon substrate, and a metal film layer is constructed between adjacent glass layers on the side of the silicon substrate with the mesa-shaped region and on the side of the silicon substrate without the mesa-shaped region.

[0016] For a bidirectional TVS diode, the mesa-shaped region is constructed on both sides of the silicon substrate, and a metal film layer is constructed between adjacent glass layers in the silicon substrate having the mesa-shaped region on each side.

[0017] A fabrication process for a surface passivation structure of a TVS diode, comprising the steps of fabricating the passivation structure as described in any of the preceding claims, including:

[0018] On the mesa-shaped region of the silicon substrate, the protective layer is prepared before the glass layer is prepared. During the preparation of the protective layer...

[0019] The silicon dioxide film layer, which is constructed between the polycrystalline silicon film layer and the silicon substrate, is prepared by oxidizing it with chlorine in water and oxygen at high temperature.

[0020] The silicon dioxide film layer, which is constructed between the polycrystalline silicon film layer and the glass layer, is formed by oxidizing silane and nitrous oxide under low pressure.

[0021] Furthermore, the growth temperature for preparing the silicon dioxide film layer placed between the polycrystalline silicon film layer and the silicon substrate is 900-1250℃, and the growth time is 60-180min.

[0022] The growth temperature for preparing the silicon dioxide film layer placed between the polycrystalline silicon film layer and the glass layer is 700-800℃, the growth time is 60-120min, and the pressure range is 300-500mtt.

[0023] Furthermore, the polycrystalline silicon film is prepared by low-pressure chemical vapor deposition, which involves growing a layer of polycrystalline silicon on a chlorine-doped silicon dioxide layer at a growth temperature of 600-700℃ and a growth time of 60-120 min.

[0024] Furthermore, the glass powder required for preparing the glass layer has a particle size of no more than 10 μm; and the temperature required for preparing the solder resist ring film layer is 300-500℃, and the time is 30-90 min.

[0025] Furthermore, the silicon substrate includes a P-type silicon wafer or an N-type silicon wafer, wherein the P-type silicon wafer is POCL3 and the N-type silicon wafer is BBr3.

[0026] The present invention discloses a TVS diode surface passivation structure and its fabrication process. In the mesa region of a unidirectional or bidirectional TVS diode, a special passivation protection layer is added between the glass layer and the silicon substrate. The protection layer includes a chlorine-doped silicon dioxide film, a semi-insulating polycrystalline silicon film, and a nitrogen-doped silicon dioxide film. This dual passivation protection structure completely isolates the device from the external environment, ensuring that the device has good high reliability, chemical stability, and high-temperature characteristics. At the same time, this structure has low leakage current and high conductivity, which can maximize the IPP capability and reduce the influence of the surface electric field. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a unidirectional TVS diode surface passivation structure according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of a unidirectional TVS diode surface passivation structure according to an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of a surface passivation structure for a bidirectional TVS diode according to an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of a surface passivation structure for a bidirectional TVS diode according to an embodiment of the present invention.

[0031] In the picture:

[0032] 10. Silicon substrate 11. Silicon wafer 12. Diffusion layer

[0033] 20. Countertop design area; 30. Protective layer; 31. Silica film layer

[0034] 32. Silica film layer; 33. Polycrystalline silicon film layer; 40. Glass layer

[0035] 50. Solder resist ring film layer; 60. Metal film layer Detailed Implementation

[0036] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0037] Example 1:

[0038] This embodiment proposes a surface passivation structure for a unidirectional TVS diode, such as... Figure 1 As shown, this structure is an N-type unidirectional TVS diode. The silicon substrate 10 includes three layers: a main silicon wafer 11 and P+ diffusion layers 12 and N+ diffusion layers 12 disposed on both sides of the silicon wafer. The main silicon wafer 11 is an N-type raw silicon wafer BBr3. The mesa molding area 20 is disposed on the side close to the P+ diffusion layer 12. A photoresist glass layer 40 is coated in the mesa molding area 20 in the silicon substrate 10, but a protective layer 30 is constructed between the silicon substrate 10 and the glass layer 40. The protective layer 30 includes at least a polycrystalline silicon film layer 33, and a silicon dioxide film layer 31 is grown between the polycrystalline silicon film layer 33 and the silicon substrate 10, and a silicon dioxide film layer 32 is grown between the polycrystalline silicon film layer 33 and the glass layer 40.

[0039] Specifically, the polycrystalline silicon film layer 33 is a semi-insulating polycrystalline silicon structural layer; the silicon dioxide film layer 31 disposed between the polycrystalline silicon film layer 33 and the silicon substrate 10 is a structural layer formed by chlorine-doped silicon dioxide; and the silicon dioxide film layer 32 disposed between the polycrystalline silicon film layer 33 and the glass layer 40 is a structural layer formed by nitrogen-doped silicon dioxide.

[0040] The silicon dioxide film 31 is silicon dioxide oxidized by chlorine doping in a quartz tube on a silicon substrate 10. During chlorine doping oxidation, the reaction product H2O is produced, which accelerates the oxidation process. The introduced chlorine accumulates near the Si-SiO2 interface, reacting with silicon to form chlorosilicides. Chlorosilicides have poor stability and easily transform into SiO2 in the presence of oxygen. Therefore, chlorine acts as a catalyst for the reaction between oxygen and silicon. Furthermore, chlorine doping oxidation can eliminate sodium ion contamination, improving the electrical performance and reliability of the device. This is because the introduction of chlorine during thermal oxidation results in a certain amount of chlorine atoms in the oxide layer, thereby reducing sodium ion contamination, passivating the activity of sodium ions in SiO2, suppressing or eliminating thermal oxidation defects, improving breakdown characteristics (IR), and enhancing reliability and stability.

[0041] Furthermore, a polycrystalline silicon film layer 33 is grown on top of the chlorine-doped silicon dioxide film layer 31. The polycrystalline silicon film layer 33 is fabricated using LPCVD (low-pressure chemical vapor deposition). During the fabrication process, the uniformity between film layers on a single wafer is controlled to within 5% in a single processing step of the polycrystalline silicon dioxide, making it practical for mass production and cost-controllable. The polycrystalline silicon film possesses ultra-high density, ultra-high hardness, exceptionally stable chemical properties, and excellent ion and water vapor barrier capabilities. A photoresist glass layer 40, made of a special glass passivation material, is then applied, concentrating the breakdown within the silicon material, thereby maximizing the breakdown voltage and reducing the influence of the surface electric field. The polycrystalline silicon film 33 can increase the adhesion and strength of silicon dioxide. In this embodiment, polycrystalline silicon is a form of elemental silicon. When molten elemental silicon solidifies under supercooled conditions, atoms arrange themselves into many crystal nuclei in a diamond lattice. If these nuclei grow into grains with different crystal orientations, these grains combine to crystallize into polycrystalline silicon. Therefore, the two homogeneous materials, single-crystal silicon and polycrystalline silicon, ensure excellent growth compatibility and adhesion. Furthermore, the polycrystalline silicon film 33 grown by LPCVD (low-pressure chemical vapor deposition) has a "rough" morphology due to the different crystal orientations of its nuclei, which helps to increase the bonding and adhesion of the silicon dioxide film. At the same time, in terms of electrical properties, polycrystalline silicon crystals have almost no conductivity and are semi-insulating, so they do not pose a leakage risk to the passivation layer.

[0042] A second silicon dioxide film 32 is then grown on top of the polycrystalline silicon film 33. This second silicon dioxide film 32 is generated under low pressure using a mixture of silane and nitrous oxide. Furthermore, the silicon dioxide film 32 obtained using silicon nitride can fix and prevent harmful impurities such as sodium ions and metal ions from entering the passivation structure within the multilayer composite surface. Additionally, the silicon dioxide film 32 is an inert dielectric, exhibiting superior dielectric properties compared to silicon dioxide films directly using glass. It has strong sodium resistance, good thermal stability, and can significantly improve the reliability and stability of the device.

[0043] Furthermore, the thickness of the silicon dioxide film 31, which is constructed between the polycrystalline silicon film 33 and the silicon substrate 10, is less than the thickness of the polycrystalline silicon film 33.

[0044] Preferably, the thickness of the silicon dioxide film 31, which is constructed between the polycrystalline silicon film 33 and the silicon substrate 10, is 1000-3000 Å; the thickness of the polycrystalline silicon film 33 is 5000-10000 Å.

[0045] Furthermore, the thickness of the second silicon dioxide film 32 disposed between the polycrystalline silicon film layer 33 and the glass layer 40 is greater than the thickness of the first silicon dioxide film 31 disposed between the polycrystalline silicon film layer 33 and the silicon substrate 10, but less than the thickness of the polycrystalline silicon film layer 33.

[0046] Furthermore, the thickness of the silicon dioxide film layer 32 disposed between the polycrystalline silicon film layer 33 and the glass layer 40 is 2000-5000 Å.

[0047] Furthermore, a solder resist ring film layer 50 is also constructed on the side of the glass layer 40 away from the protective layer 30.

[0048] Furthermore, for a unidirectional TVS diode, a mesa region 20 is constructed on one side of the silicon substrate 10. A metal film layer 60 is constructed between adjacent glass layers 40 on the side of the silicon substrate 10 with the mesa region 20, and also on the side of the silicon substrate 10 without the mesa region 20. Specifically, a metal film layer 60 is also provided between the solder resist ring layers 50 between two adjacent mesa regions 20; that is, the metal film layer 60 near the P+ diffusion layer 12 is located between the composite multilayer passivation regions. A metal film layer 60 is also provided on the side of the silicon substrate 10 near the N+ diffusion layer 12, located at the electrode lead on the other side.

[0049] The glass layer 40 is a photoresist slurry prepared with special glass powder, which can be uniformly attached to the silicon oxide film in the groove of the table surface using photoresist method, and then sintered at high temperature to form the structural layer. The solder resist ring layer 50 is an LTO film produced by LPCVD low-pressure chemical vapor deposition. The metal film layers 60 located on both sides of the silicon substrate 10 are formed by selective photolithography and selective etching to create electrode windows to be metallized, and then by electroless nickel-gold plating technology to form a metal structural layer with good contact with the silicon surface.

[0050] The structure in this embodiment concentrates the breakdown within the silicon substrate 10, thereby maximizing the breakdown voltage and reducing the influence of the surface electric field. When the device is reverse-biased, the negative charge of the P-type surface equals the positive charge of the N-type surface. Because the mesa region 20 of the PN junction is etched into a slope shape, the depletion layer is stretched on the surface of the mesa region 20, significantly reducing the influence of the surface electric field. When breakdown occurs, it does not occur on the device surface but within the silicon substrate 10. This optimized combination structure with low leakage current and high conductivity is achieved by using the structure in this embodiment, minimizing the influence of the surface electric field, combined with the selection of low resistivity silicon materials. Furthermore, a chlorine-doped silicon dioxide film 31, a polycrystalline silicon film 33, and a nitrogen-containing silicon dioxide film 32 serve as a protective layer 30. A dense, ultra-pure passivation glass layer 40 is then added to the passivation film of the protective layer 30. This double passivation protection structure completely isolates the device from the external environment, ensuring high reliability, chemical stability, and excellent high-temperature characteristics. Furthermore, the rational design of the device structure ensures a highly stable PN junction breakdown voltage. The passivated LTO solder mask ring 50 and the electroless nickel-plated metal film layers 60 on both sides of the device, followed by alloying, create excellent ohmic contact between the metal and the silicon surface. This ensures high stability and reliability during device packaging, making it suitable for applications in various fields.

[0051] Example 2:

[0052] like Figure 2 As shown, this structure is a unidirectional TVS diode. Compared with Embodiment 1, the biggest difference in this embodiment lies in the different structure of the silicon substrate 10. Specifically, the silicon substrate 10 includes a P-type body silicon wafer 11, which is a P-type raw silicon wafer POCL3; and an N+ diffusion layer 12 is only provided on one side of the body silicon wafer 11, and the mesa molding area 20 is only located on the side closest to the N+ diffusion layer 12; all other structures are the same.

[0053] Example 3:

[0054] like Figure 3 The structure described is a bidirectional TVS diode. Compared with Embodiment 1, the biggest difference in this embodiment is the different positions of the silicon substrate 10 and the mesa molding area 20; the mesa molding area 20 is located on both sides of the silicon substrate 10 and the structure of the N-type silicon substrate 10 is also different; correspondingly, the protective layer 30, the glass layer 40, the solder resist ring layer 50, and the metal film layer 60 are also located on both sides of the silicon substrate 10.

[0055] In this embodiment, the silicon substrate 10 includes an N-type bulk silicon wafer 11 and P+ diffusion layers 12 disposed on both sides of the silicon wafer 11. The P+ diffusion layers 12 on both sides of the silicon wafer 11 are identical.

[0056] Correspondingly, the tabletop shaping area 20 is located on both sides of the silicon substrate 10, and the structure of each tabletop shaping area 20 is the same, including a protective layer 30, and a glass layer 40 and a solder resist ring film layer 50 are sequentially provided above the protective layer 30.

[0057] For a bidirectional TVS diode, mesa regions 20 are formed on both sides of a silicon substrate 10, and a metal film layer 60 is formed between adjacent glass layers 40 in the silicon substrate 10 with mesa regions 20 on each side. That is, a metal film layer 60 is provided on the outer side of the P+ diffusion layer 12 between adjacent mesa regions 20.

[0058] Example 4:

[0059] like Figure 3 The structure described is a bidirectional TVS diode. The biggest difference between this embodiment and Embodiment 3 lies in the silicon substrate 10. Specifically, the silicon substrate 10 includes a P-type bulk silicon wafer 11 and N+ diffusion layers 12 disposed on both sides of the silicon wafer 11.

[0060] A fabrication process for a surface passivation structure of a TVS diode, comprising the steps of fabricating the passivation structure as described in any of the preceding claims, including:

[0061] Before fabricating the glass layer 40, a protective layer 30 is first prepared on the mesa-shaped region 20 in the silicon substrate 10. During the preparation of the protective layer 30...

[0062] The silicon dioxide film 31, which is constructed between the polycrystalline silicon film 33 and the silicon substrate 10, is made by oxidation with chlorine in water and oxygen at high temperature. The growth temperature is 900-1250℃ and the growth time is 60-180min.

[0063] The second silicon dioxide film layer, which is constructed between the polycrystalline silicon film layer 33 and the glass layer 40, is formed by oxidation of silane and nitrous oxide under low pressure. The growth temperature is 700-800℃, the growth time is 60-120min, and the pressure range is 300-500mtt.

[0064] Furthermore, the polycrystalline silicon film 33 is fabricated using low-pressure chemical vapor deposition, which involves growing a layer of polycrystalline silicon on a chlorine-doped silicon dioxide layer at a growth temperature of 600-700℃ and a growth time of 60-120 minutes.

[0065] Furthermore, the glass layer 40 is a photoresist slurry prepared from special glass powder, which can be uniformly attached to the silicon oxide film in the groove of the table surface using a photoresist method, and then sintered at high temperature to form a structural layer. The particle size of the glass powder required to prepare the glass layer 40 is no larger than 10 μm; and the temperature required to prepare the solder resist ring film layer is 300-500℃, and the time is 30-90 min.

[0066] Furthermore, the silicon substrate 10 includes a P-type silicon wafer or an N-type silicon wafer, wherein the P-type silicon wafer body is POCL3 and the N-type silicon wafer body is BBr3.

[0067] The solder resist ring film 50 is an LTO thin film produced by LPCVD low-pressure chemical vapor deposition at a growth temperature of 300-500℃ for 30-90 minutes.

[0068] The metal film 60 is formed by selective photolithography and selective etching to create electrode windows to be metallized, and then by electroless nickel-gold plating to form a metal structure layer with good contact with the silicon surface.

[0069] The present invention discloses a TVS diode surface passivation structure and its fabrication process. In the mesa region of a unidirectional or bidirectional TVS diode, a special passivation protection layer is added between the glass layer and the silicon substrate. The protection layer includes a chlorine-doped silicon dioxide film, a semi-insulating polycrystalline silicon film, and a nitrogen-doped silicon dioxide film. This dual passivation protection structure completely isolates the device from the external environment, ensuring that the device has good high reliability, chemical stability, and high-temperature characteristics. At the same time, this structure has low leakage current and high conductivity, which can maximize the IPP capability and reduce the influence of the surface electric field.

[0070] The embodiments of the present invention have been described in detail above. These descriptions are merely preferred embodiments and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the claims of this invention should still fall within the patent coverage of this invention.

Claims

1. A passivation structure for the surface layer of a TVS diode, characterized in that, A glass layer is included in the table-shaped area on one or both sides of the silicon substrate; a protective layer is constructed between the silicon substrate and the glass layer, the protective layer including at least a polycrystalline silicon film layer, and a silicon dioxide film layer is constructed between the polycrystalline silicon film layer and the silicon substrate, and between the polycrystalline silicon film layer and the glass layer. The silicon dioxide film layer placed between the polycrystalline silicon film layer and the silicon substrate is a structural layer formed of chlorine-doped silicon dioxide; The polycrystalline silicon film layer is a structural layer with semi-insulating polycrystalline silicon. The silicon dioxide film layer placed between the polycrystalline silicon film layer and the glass layer is a structural layer formed of nitrogen-doped silicon dioxide; The thickness of the silicon dioxide film layer, which is constructed between the polycrystalline silicon film layer and the silicon substrate, is less than the thickness of the polycrystalline silicon film layer. The thickness of the silicon dioxide film layer formed between the polycrystalline silicon film layer and the silicon substrate is 1000-3000 Å; the thickness of the polycrystalline silicon film layer is 5000-10000 Å. The thickness of the silicon dioxide film layer disposed between the polycrystalline silicon film layer and the glass layer is greater than the thickness of the silicon dioxide film layer disposed between the polycrystalline silicon film layer and the silicon substrate, but less than the thickness of the polycrystalline silicon film layer; The thickness of the silicon dioxide film layer disposed between the polycrystalline silicon film layer and the glass layer is 2000-5000 Å.

2. The TVS diode surface passivation structure according to claim 1, characterized in that, A solder resist ring film layer is also constructed on the side of the glass layer away from the protective layer.

3. The TVS diode surface passivation structure according to any one of claims 1-2, characterized in that, For a unidirectional TVS diode, the mesa-shaped region is constructed on one side of the silicon substrate, and a metal film layer is constructed between adjacent glass layers on the side of the silicon substrate with the mesa-shaped region and on the side of the silicon substrate without the mesa-shaped region. For a bidirectional TVS diode, the mesa-shaped region is constructed on both sides of the silicon substrate, and a metal film layer is constructed between adjacent glass layers in the silicon substrate having the mesa-shaped region on each side.

4. A fabrication process for a surface passivation structure of a TVS diode, characterized in that, Manufacturing the passivation structure as described in any one of claims 1-3, the steps include: On the mesa-shaped region of the silicon substrate, the protective layer is prepared before the glass layer is prepared. During the preparation of the protective layer... The silicon dioxide film layer, which is constructed between the polycrystalline silicon film layer and the silicon substrate, is prepared by oxidizing it with chlorine in water and oxygen at high temperature. The silicon dioxide film layer, which is constructed between the polycrystalline silicon film layer and the glass layer, is formed by oxidizing silane and nitrous oxide under low pressure.

5. The fabrication process of a TVS diode surface passivation structure according to claim 4, characterized in that, The growth temperature for preparing the silicon dioxide film layer placed between the polycrystalline silicon film layer and the silicon substrate is 900-1250℃, and the growth time is 60-180min. The growth temperature for preparing the silicon dioxide film layer placed between the polycrystalline silicon film layer and the glass layer is 700-800℃, the growth time is 60-120min, and the pressure range is 300-500mtt.

6. The fabrication process of a TVS diode surface passivation structure according to claim 4 or 5, characterized in that, The polycrystalline silicon film is prepared by low-pressure chemical vapor deposition, which involves growing a layer of polycrystalline silicon on a chlorine-doped silicon dioxide layer at a growth temperature of 600-700℃ and a growth time of 60-120 min.

7. The fabrication process of a TVS diode surface passivation structure according to claim 6, characterized in that, The glass powder required for preparing the glass layer has a particle size of no more than 10 μm; and the temperature required for preparing the solder resist ring film layer on the side of the glass layer away from the protective layer is 300-500℃ and the time is 30-90 min.

8. The fabrication process of a TVS diode surface passivation structure according to any one of claims 4-5 and 7, characterized in that, The silicon substrate includes a P-type silicon wafer or an N-type silicon wafer, wherein the P-type silicon wafer is POCL3 and the N-type silicon wafer is BBr3.

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