Audio nonlinearity elimination for switches used in audio and other applications

Abstract

One aspect includes an apparatus comprising: a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET. Another aspect includes a method comprising amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer; and applying the first voltage to a first source of the first FET.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 323,685, filed on May 18, 2021, and which is assigned to the assignee of the present application and is hereby expressly incorporated herein by reference as if fully set forth below and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure relate generally to signal nonlinear cancellation, and in particular, to audio nonlinear cancellation of switches for audio and other applications. Background Art

[0004] An integrated circuit (IC) can provide different types of data to one or more devices connected to a signal port, such as a universal serial bus (USB) port. For example, the devices connected to a USB port can vary widely. Some devices receive high-speed USB data (e.g., up to 10 GB per second), while other devices, such as audio devices, receive audio data at a much lower speed (e.g., 40 kilobytes per second). Due to the large speed differences and the common USB ports through which the data travels, there are many challenges in accommodating different types of data. Summary of the invention

[0005] A simplified overview of one or more implementations is presented below in order to provide a basic understanding of such implementations. This summary is not an extensive overview of all contemplated implementations, and is neither intended to identify key or important elements of all implementations nor to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to a more detailed description that is presented later.

[0006] One aspect of the present disclosure relates to an apparatus. The apparatus includes: a first amplifier; a first field effect transistor (FET) including a first source coupled to an output of the first amplifier and a first drain for coupling to a first load; and a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET.

[0007] Another aspect of the present disclosure relates to a method. The method includes: amplifying a first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage; and applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer.

[0008] Another aspect of the present disclosure relates to an apparatus. The apparatus includes: means for amplifying a first audio signal using a first audio amplifier to generate a first voltage; means for generating a first gate voltage based on the first voltage; and means for applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer.

[0009] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; at least one digital signal processing core coupled to the transceiver; a port configured to be connected to one of at least one audio transducer and a digital data device; at least one audio amplifier; at least one field effect transistor (FET) including a source and a drain, the source being coupled to an output of the at least one audio amplifier, respectively, and the drain being coupled to the port; and at least one gate drive circuit including an input coupled to the output of the at least one audio amplifier and an output coupled to a gate of the at least one FET.

[0010] To achieve the foregoing and related purposes, one or more implementations include the features fully described below and particularly pointed out in the claims. The following description and the accompanying drawings set forth in detail certain illustrative aspects of one or more implementations. However, these aspects are merely indicative of some of the various ways in which the principles of the various implementations may be employed and the described implementations are intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A block diagram / schematic diagram is illustrated of an example apparatus for transmitting different types of data via one or more common nodes according to one aspect of the present disclosure.

[0012] Figure 2 A block diagram / schematic diagram is illustrated of another example apparatus for transmitting different types of data via one or more common nodes according to another aspect of the disclosure.

[0013] Figure 3 A schematic diagram of an example apparatus for transmitting an analog audio signal to an audio transducer according to another aspect of the present disclosure is illustrated.

[0014] Figure 4 A schematic diagram of another example apparatus for transmitting an analog audio signal to an audio transducer according to another aspect of the present disclosure is illustrated.

[0015] Figure 5 A schematic diagram of an example voltage scaling circuit according to another aspect of the disclosure is illustrated.

[0016] Figure 6A schematic diagram of an example voltage summer and scaling circuit according to another aspect of the present disclosure is illustrated.

[0017] Figure 7 A flow chart illustrating an example method of transmitting an audio signal to an audio transducer according to another aspect of the disclosure is illustrated.

[0018] Figure 8 A block diagram of an example wireless communication device according to another aspect of the disclosure is illustrated.

[0019] 9A to 9C A schematic diagram of an exemplary gate drive circuit according to other aspects of the present disclosure is illustrated. DETAILED DESCRIPTION

[0020] The specific embodiments described below in conjunction with the accompanying drawings are intended as descriptions of various configurations and are not intended to represent the only configurations in which the concepts described herein can be practiced. The specific embodiments include specific details for the purpose of providing a thorough understanding of the various concepts. However, it is apparent to those skilled in the art that these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form in order to avoid blurring these concepts.

[0021] Figure 1 A block diagram / schematic diagram of an example apparatus 100 for transmitting different types of data via one or more common nodes according to one aspect of the present disclosure is illustrated. In this example, the different types of data include Universal Serial Bus (USB) digital data signals and analog audio signals. However, it should be understood that the concepts described herein can be directed to other types of signals.

[0022] The apparatus 100 includes an integrated circuit (IC) 110, which may be configured as a system on chip (SOC) or other types of ICs. The IC 110 includes an application processor (AP) 120, which is configured to generate a USB differential data signal including a negative differential component USB (DN) and a positive differential component USB (DP), where "D" represents data and "N" and "P" represent negative and positive, respectively. The IC 110 also includes an audio codec 130, which is configured to generate analog audio signals AUD (R) and AUD (L), where "R" represents a right channel signal component and "L" represents a left channel signal component.

[0023] The device 100 also includes a USB port 150, such as a USB-C port or a port that may be another version or type. Depending on the type of USB device, a USB device (e.g., a USB flash drive) can be connected to the USB port 150 to receive USB differential data signals USB (DN) and USB (DP) for storage and / or other purposes. An audio device (such as an audio transducer (headphones or speakers)) can also be connected to the USB port 150 to receive analog audio signals AUD (R) and AUD (L). Although not shown, the device 100 may include a device detector that is configured to determine whether the device connected to the USB port 150 is a type that receives USB differential data signals USB (DN) and USB (DP) or an audio device that receives analog audio signals AUD (R) and AUD (L).

[0024] The outputs of the AP 120 and the audio codec 130 may be connected to common nodes or pads 142, 144, and 146 (e.g., off-chip pads on a printed circuit board (PCB)). For example, the outputs USB (DN) and AUD (R) associated with the AP 120 and the audio codec 130 may be connected to a common node or pad 142, respectively. The outputs USB (DP) and AUD (L) associated with the AP 120 and the audio codec 130 may be connected to a common node or pad 144, respectively. The IC 110 may include a ground or return coupled to the node or pad 146. The apparatus 100 may also include switch devices SW1, SW2, and SW3 connected between the nodes or pads 142, 144, and 146 and the DN, DP, and sideband use (SBU) 1 / 2 terminals of the USB port 150, respectively.

[0025] One of the challenges of the apparatus 100 is that different types of data share common nodes or pads 142, 144, and 146 of the switch devices SW1-SW3, respectively. For example, the USB differential data signals USB(DN) and USB(DP) may have a much higher data rate or frequency bandwidth (e.g., up to 10 Gigabits per second (Gbps)) than the analog audio signals AUD(R) and AUD(L) (e.g., 48 kilobits per second (Kbps)). The analog audio signals AUD(R) and AUD(L) may include a total harmonic distortion (THD) of up to 110 or 120 dB.

[0026] The differences between the USB differential data signals and the analog audio signals provide competing characteristics for the switch devices SW1 to SW3 through which these signals propagate. For example, the relatively high data rate of the USB differential data signals dictates that the switch devices SW1-SW3 be made relatively small to keep the capacitance of these devices small so they do not affect the USB differential data signals. However, the analog audio signals require a relatively high THD, which dictates that the switch devices SW1-SW3 should be made relatively large to handle the relatively high power of the analog audio signals. For example, the terminals of the switch devices SW1-SW3 may need to handle voltages up to 20 volts.

[0027] Figure 2 A block diagram / schematic diagram of another example apparatus 200 for transmitting different types of data via one or more common nodes according to another aspect of the present disclosure is illustrated. The apparatus 200 may be an example more detailed implementation of the apparatus 100 discussed previously.

[0028] For example, IC 110 may include audio amplifiers 210 and 220, and a set of switching devices SWA-SWE. Audio amplifier 210 is configured to receive a right channel audio signal AUD(R), and audio amplifier 220 is configured to receive a left channel audio signal (L). Switching devices SWA-SWB are coupled between USB(DN) and USB(DP) outputs of an application processor (AP) and nodes or pads 242 and 244, respectively. Switching devices SWC and SWD are coupled between the outputs of audio amplifiers 210 and 220 and nodes or pads 242 and 244, respectively. Switching device SWE is coupled between ground and node or pad 246. The application processor (AP) may control the state (open / closed) of the set of switching devices SWA-SWE. The remaining circuitry of device 200 may be substantially the same as the circuitry of device 100. That is, apparatus 200 further includes a set of switch devices SW1 - SW3 that are respectively coupled between nodes or pads 242 , 244 , and 246 of USB port 250 and the DN, DP, and SBU1 / 2 terminals.

[0029] If the device 200 detects that a device connected to the USB port 250 will receive USB differential data signals, the application processor (AP) closes the switch devices SWA, SWB, SWE, and SW1-SW3, and opens SWC and SWD. In this configuration, the USB differential data signals USB(DN) and USB(DP) are sent to the device via the switch devices SWA / SW1 and SWB / SW2, and the loop USB differential data signals are grounded via SW3 / SWE. If the device 200 detects that a device connected to the USB port 250 is to receive analog audio signals, the application processor (AP) closes the switch devices SWC, SWD, SWE, and SW1-SW3, and opens SWA and SWB. In this configuration, the analog audio signals AUD(R) and AUD(L) are sent to the device via the switch devices SWC / SW1 and SWD / SW2, and the loop USB differential data signals are grounded via SW3 / SWE.

[0030] The same issues discussed above with respect to the same switch devices SW1-SW3 of the apparatus 100 still apply. That is, for the relatively high data rates of the USB differential data signals, the switch devices SW1-SW3 should be made relatively small to keep the capacitance associated with these devices low so that they do not adversely affect the USB differential data signals. To handle the THD requirements of the analog audio signals, the switch devices SW1-SW3 should be made relatively large to handle the relatively high power / voltage of the analog audio signals.

[0031] Figure 3 A schematic diagram of an example apparatus 300 for transmitting an analog audio signal to an audio transducer according to another aspect of the present disclosure is illustrated. In summary, the set of switch devices SW1-SW3 are configured as field effect transistors (FETs), such as n-channel metal oxide semiconductor field effect transistors (NMOS FETs). In addition, the apparatus 300 includes a gate drive circuit configured to provide a gate voltage to the switch FETs SW1-SW3 so that they operate in a more linear manner to reduce the THD of the analog audio signal. This allows the use of relatively small switch FETs SW1-SW3 so as not to significantly affect the USB differential data signal, while linearizing the operation of the switch FETs SW1-SW3 so that they can process the analog audio signal.

[0032] More specifically, the device 300 includes a first audio amplifier 310, a first gate drive circuit 350, and a first switch FET SW1. The device 300 also includes a second audio amplifier 320, a second gate drive circuit 360, and a second switch FET SW2. In addition, the device 300 includes a third gate drive circuit 370 and a third switch FET SW3. The first audio load R LA second audio load (R) such as a right channel audio transducer (eg, a headphone, an earpiece, or a speaker) is coupled or connected between the first switch FET SW1 and the third switch FET SW3. L (L) such as a left channel audio transducer (eg, a headphone, earpiece, or speaker) is coupled or connected between the second switching FET SW2 and the third switching FET SW3.

[0033] The first audio amplifier 310 includes an input configured to receive a right channel analog audio signal AUD(R) and amplify the analog audio signal AUD(R) to generate an output voltage VinR. The first gate drive circuit 350 includes a first voltage scaling device 352 and a first voltage summer 354. The first voltage scaling device 352 includes an input coupled to the output of the first audio amplifier 310 and is configured to scale the output voltage VinR by a scaling factor β. The first voltage summer 354 includes a first input coupled to the output of the first voltage scaling device 352, a second input configured to receive a direct current (DC) voltage VDCR, and an output configured to generate a first gate voltage VGR for the gate of the first switch FET SW1. Therefore, the first gate voltage VGR can be represented by the following equation:

[0034] VGR=VinR*β+VDCR Equation 1

[0035] The first audio amplifier 310 and / or the first gate drive circuit 350 may be part of an integrated circuit (IC) or a dedicated circuit system. The first switch FET SW1 includes a source (and body) coupled to the output of the first audio amplifier 310 via a node or pad 342, a gate coupled to the output of the first gate drive circuit 350, and coupled to the right channel audio load R L (R) is a drain of the first terminal.

[0036] The second audio amplifier 320 includes an input configured to receive a left channel analog audio signal AUD(L) and amplify the analog audio signal AUD(L) to generate an output voltage VinL. The second gate drive circuit 350 includes a second voltage scaling device 362 and a second voltage summer 364. The second voltage scaling device 362 includes an input coupled to the output of the second audio amplifier 320 and is configured to scale the output voltage VinL by a scaling factor α. The second voltage summer 364 includes a first input coupled to the output of the second voltage scaling device 362, a second input configured to receive a DC voltage VDCL, and an output configured to generate a second gate voltage VGL for the gate of the second switch FET SW2. Therefore, the second gate voltage VGL can be represented by the following equation:

[0037] VGL=VinL*α+VDCL Equation 2

[0038] The second audio amplifier 320 and / or the second gate drive circuit 360 may be part of an integrated circuit (IC) or dedicated circuitry. The second switch FET SW2 includes a source (and body) coupled to the output of the second audio amplifier 320 via a node or pad 344, a gate coupled to the output of the second gate drive circuit 360, and a gate coupled to the left channel audio load R L (L) is the drain of the first terminal.

[0039] The third gate drive circuit 370 includes a third voltage summer 372, a third voltage scaling device 374, and a fourth voltage summer 376. The third voltage summer 372 includes a first input and a second input coupled to the outputs of the first audio amplifier 310 and the second audio amplifier 320, respectively. Therefore, the third voltage summer 372 is configured to sum the output voltages VinR and VinL of the first audio amplifier 310 and the second audio amplifier 320, respectively. The third voltage scaling device 374 includes an input coupled to the output of the third voltage summer 372, and is configured to scale the sum of the output voltages VinR+VinL by a scaling factor γ. The fourth voltage summer 376 includes a first input coupled to the output of the third voltage scaling device 374, a second input configured to receive the DC voltage VDC0, and an output configured to generate a third gate voltage VG0 for the gate of the third switch FET SW3. Therefore, the third gate voltage VG0 can be represented by the following equation:

[0040] VG0=(VinR+VinL)*γ+VDC0 Equation 3

[0041] The third gate drive circuit 370 may be part of an integrated circuit (IC) or dedicated circuitry. The third switch FET SW1 includes a source (and body) coupled to ground via a node or pad 346, a gate coupled to the output of the third gate drive circuit 370, and a gate coupled to the right and left channel audio loads R L (R) and R L (L) is the drain of the corresponding second terminal.

[0042] The linearization operation of the switching FETs SW1-SW3 is as follows: If the switching FETs SW1-SW3 are operated by a constant gate voltage, the resistance of the FETs will change with the audio voltages VinR, VinL, and VinR+VinL because their corresponding gate-source voltages change with these voltages VinR, VinL, and VinR+VinL, respectively. The change in voltage combined with the change in the FET resistance produces a nonlinear response, thereby increasing the THD of the analog audio signal. However, the gate drive circuits 350, 360, and 370 generate gate voltages VGR, VGL, and VG0 that vary proportionally with the input voltages VinR, VinL, and VinR+VinL, respectively, according to equations 1-3. Since the gate voltage and the source voltage vary in a similar manner, the gate-to-source voltage of the FETs SW1-SW3 remains substantially constant; and therefore, the FET resistance remains substantially constant. This results in a more linear response of the switching FETs SW1-SW3; thereby, allowing the FETs to be made smaller for USB differential data purposes, and reducing THD for analog audio signal purposes.

[0043] As shown in Equations 1 to 3, the DC voltages VDCR, VDCL, and VDC0 applied to the gates of the switching FETs SW1-SW3 are used to keep the switching FETs SW1-SW3 minimally turned on or turned on to a certain extent, while the proportional components β*VinR, α*VinL, and γ*(VinR+VinL) drive the switching FETs SW1-SW3 more strongly in proportion to the voltages VinR, VinL, and (VinR+VinL) to produce a more linear response from the switching FETs SW1-SW3, respectively.

[0044] Figure 4 A schematic diagram of another example apparatus 400 for transmitting an analog audio signal to an audio transducer according to another aspect of the present disclosure is illustrated. Apparatus 400 is similar to apparatus 300 and includes many of the same elements, such as a first audio amplifier 410 and a second audio amplifier 420, a set of switching FETs SW1-SW3, a set of gate drive circuits 450, 460 and 470 including voltage scaling devices 452, 462 and 474, summers 454, 464 and 476, and an additional summer 474 in the case of gate drive circuit 470. The configuration and operation of these elements have been described with reference to the same elements in apparatus 300, and these elements are identified with the same reference numerals, except that the most significant bit in apparatus 400 is "4" instead of "3" in apparatus 300.

[0045] The device 400 also includes a set of body bias circuits 456, 466, and 480, which are configured to generate body voltages VBR, VBL, and VB0 for the set of switching FETs SW1-SW3, respectively. Therefore, the set of body bias circuits 456, 466, and 480 include a set of outputs coupled to the bodies of the set of switching FETs SW1-SW3, respectively (the body voltages VBR, VBL, and VB0 are generated at the set of outputs). It should be noted that the bodies of the switching FETs SW1-SW3 in the device 400 are not coupled to the corresponding sources of the FETs SW1-SW3, respectively.

[0046] The body bias circuit 456 is configured as a voltage scaling device configured to scale the voltage VinR at the output of the first audio amplifier 410 by a factor v to generate a body voltage VBR for the switch FET SW1. The body bias circuit 466 is configured as a voltage scaling device configured to scale the voltage VinL at the output of the second audio amplifier 420 by a factor μ to generate a body voltage VBL for the switch FET SW2. The body bias circuit 480 includes a voltage summer 482, which includes inputs coupled to the outputs of the first audio amplifier 410 and the second audio amplifier 420, respectively. Therefore, the voltage summer 482 is configured to sum the voltages VinR and VinL at the outputs of the first audio amplifier 410 and the second audio amplifier 420, respectively. The body bias circuit 480 also includes a voltage scaling device 484, which is configured to scale the sum of the voltages VinR and VinL by a factor x to generate a body voltage VB0 for the switch FET SW3.

[0047] The body bias circuits 456, 466, and 480 are particularly useful when the output voltages VinR, VinL, and VinR+VinL swing between positive and negative voltages. The scaling factors v, μ, and x can be configured to place the body voltages VBR, VBL, and VB0 substantially near the middle of the voltage swings of the voltages VinR, VinL, and VinR+VinL, respectively. In such cases, the drain-to-body voltage and the source-to-body voltage swing between similar voltage ranges. Therefore, the operation of the switching FETs SW1-SW3 is more symmetrical.

[0048] Figure 5A schematic diagram of an example voltage scaling circuit 500 according to another aspect of the present disclosure is illustrated. The voltage scaling circuit 500 may be an example of any of the previously discussed voltage scaling circuits 352, 362, 452, 456, 462, and 466. The voltage scaling circuit 500 is also shown with a corresponding audio amplifier 510, which may correspond to any of the previously discussed audio amplifiers 310, 320, 410, and 420.

[0049] The voltage scaling circuit 500 includes a differential amplifier 520, a first resistor R1, and a second resistor R2 that may be variable. The first resistor R1 and the second resistor R2 are coupled or connected in series between the output of the audio amplifier 510 and a voltage rail (e.g., ground). The differential amplifier 520 includes a first input (e.g., a positive input) coupled to the output of the audio amplifier 510, and a second input (e.g., a negative input) coupled to a node between the first resistor R1 and the second resistor R2. The control signal Vctrl1 <n:1>The net resistance of variable resistor R2 between the negative input of differential amplifier 520 and the voltage rail is controlled. If R T is the total resistance of the variable resistor R2, and R2 is also the net resistance of the variable resistor R2, then the net resistance R2 can be determined by the following equation:

[0050] R2=R T *(2 <n:1>< / n:1> / 2 N ) Equation 4

[0051] in <n:1>Is the control signal Vctrl1 <n:1>Assuming that the differential amplifier 520 has a unity gain, the differential amplifier 520 includes an output configured to generate a scaled voltage VS according to the following equation:

[0052]

[0053] Where R1 is the resistance of resistor R1. Therefore, by selecting / adjusting the resistors R1 and R2 corresponding to the voltage scaling circuits 352 / 452, 362 / 462, 456, and 466, the scaling factors β, α, ν, and μ can be set.

[0054] Figure 6 A schematic diagram of an example voltage summer and scaling circuit 600 according to another aspect of the present disclosure is illustrated. The voltage summer and scaling circuit 600 may be an example of a series connected voltage summer and voltage scaling circuit, such as the previously discussed summer-voltage scaling circuits 372-374, 472-474, and 482-484.

[0055] The voltage summer and scaling circuit 600 includes a summing amplifier 610, which includes inputs configured to receive output voltages VinR and VinL from the outputs of the first audio amplifier 310 / 410 and the second audio amplifier 320 / 420, respectively. Assuming that the summing amplifier 610 has a unity gain, the summing amplifier 610 is configured to generate the sum of the voltages VinR+VinL. The voltage summer and scaling circuit 600 also includes a differential amplifier 620, a first resistor R3 and a second resistor R4, and the second resistor R4 can be variable. The first resistor R3 and the second resistor R4 are coupled or connected in series between the output of the summing amplifier 610 and a voltage rail (e.g., ground). The differential amplifier 620 includes a first input (e.g., a positive input) coupled to the output of the summing amplifier 610 and a second input (e.g., a negative input) coupled to a node between the first resistor R3 and the second resistor R4. Control signal Vctrl2 <n:1>The net resistance of variable resistor R4 between the negative input of differential amplifier 620 and the voltage rail is controlled. If R T is the total resistance of the variable resistor R4, and R4 is also the net resistance of the variable resistor R4, then the net resistance R4 can be determined by the following equation:

[0056] R4=R T *(2 <n:1>< / n:1> / 2 N ) Equation 6

[0057] in <n:1>Is the control signal Vctrl2 <n:1>Assuming that the differential amplifier 620 has a unity gain, the differential amplifier 620 includes an output configured to generate a scaled voltage VS according to the following equation:

[0058]

[0059] Where R3 is the resistance of resistor R3. Therefore, by selecting / adjusting the resistors R3 and R4 corresponding to the voltage scaling circuits 374 / 474 and 484, the scaling factors γ and χ can be set.

[0060] Figure 7 A flow chart of an example method 700 for transmitting an audio signal to an audio transducer according to another aspect of the present disclosure is illustrated. The method 700 includes amplifying a first audio signal using a first audio amplifier to generate a first voltage (block 710). An example of components for amplifying a first audio signal using a first audio amplifier to generate a first voltage of any of the previously discussed audio amplifiers 310, 320, 410, and 420.

[0061] The method 700 also includes generating a first gate voltage based on the first voltage (block 720). Examples of components for generating the first gate voltage based on the first voltage include any of the gate drive circuits 350, 360, 450, 460, and 500 discussed previously.

[0062] The method 700 additionally includes applying a first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and the first audio transducer (block 730). Examples of means for applying the first gate voltage to the first gate of the first field effect transistor (FET) coupled between the first audio amplifier and the first audio transducer include coupling the gate drive circuits 350, 360, 450, 460, and 500 to the gates of the corresponding FETs SW1 and SW2.

[0063] The method 700 also includes applying the first voltage to the first source of the first FET. Examples of means for applying the first voltage to the first source of the first FET include coupling the outputs of amplifiers 310, 320, 410, and 420 to the sources of FETs SW1 and SW2.

[0064] The generation of the first gate voltage as detailed in block 720 may include scaling the first voltage by a first scaling factor to generate the first scaled voltage, and summing the first scaled voltage with a first direct current (DC) voltage to generate the first gate voltage. Examples of components for scaling the first voltage by the first scaling factor to generate the first scaled voltage include any of the voltage scaling circuits 352, 362, 374, 452, 464, and 474. Examples of components for summing the first scaled voltage with the first direct current (DC) voltage to generate the first gate voltage include any of the voltage summers 354, 364, 376, 454, 464, and 476.

[0065] The method 700 may also include: amplifying the second audio signal using a second audio amplifier to generate a second voltage; generating a second gate voltage based on the second voltage; applying the second gate voltage to a second gate of a second field effect transistor (FET) coupled between the second audio amplifier and the second audio transducer; and applying the second voltage to a second source of the second FET. The components for performing these operations have been previously discussed with reference to blocks 710, 720, 730, and 740.

[0066] The method 700 may also include generating a third gate voltage based on the sum of the first voltage and the second voltage, and applying the third gate voltage to a third gate of a third field effect transistor (FET) coupled between the first audio transducer and the second audio transducer and the voltage rail. Examples of components for generating the third gate voltage based on the sum of the first voltage and the second voltage include any of the first voltage summers 372 and 472, the voltage scaling devices 374 and 474, and the second voltage summers 376 and 476. Examples of components for applying the third gate voltage to a third gate of a third field effect transistor (FET) coupled between the first audio transducer and the second audio transducer and the voltage rail include coupling the output of the gate drive circuits 370 and 470 to the gate of the switch FET SW3.

[0067] In addition, method 700 may include: generating a first body voltage based on the first voltage; applying the first body voltage to the first body of the first FET; generating a second body voltage based on the second voltage; applying the second body voltage to the second body of the second FET; generating a third body voltage based on the sum of the first voltage and the second voltage; and applying the third body voltage to the third body of the third FET.

[0068] An example of a component for generating a first body voltage based on the first voltage includes body bias circuit 456. An example of a component for applying the first body voltage to the first body of the first FET includes coupling the output of body bias circuit 456 to the body of the switch FET SW1. An example of a component for generating a second body voltage based on the second voltage includes body bias circuit 466. An example of a component for applying the second body voltage to the second body of the second FET includes coupling the output of body bias circuit 466 to the body of the switch FET SW2. An example of a component for generating a third body voltage based on the sum of the first voltage and the second voltage includes body bias circuit 480. An example of a component for applying the third body voltage to the third body of the third FET includes coupling body bias circuit 480 to the body of the switch FET SW3.

[0069] Figure 8 A block diagram of an example wireless communication device 800 according to another aspect of the present disclosure is illustrated. The wireless communication device 800 includes at least one antenna 860 (e.g., at least one antenna array), a transceiver 850, and an integrated circuit (IC) 805 that can be configured as a system on a chip (SOC). The SOC 805 includes one or more digital signal processing cores 810, an application processor 815, an audio codec 820, a switch device SWA-SWF, and gate drive circuits GDC-R 825, GDC-L 830, and GDC-0835.

[0070] One or more digital signal processing cores 810 may be configured to process data to generate a baseband (BB) signal, and the transceiver 850 may be configured to process the baseband (BB) signal received from the one or more digital signal processing cores 810 to generate a radio frequency (RF) signal. The at least one antenna 860 may be configured to radiate an RF signal for wireless transmission to one or more remote devices. Similarly, at least one antenna 860 is configured to receive an RF signal from a remote device, and the transceiver 850 may be configured to process the RF signal received from at least one antenna 860 to generate a baseband (BB) signal. One or more digital signal processing cores 810 may be configured to process a baseband (BB) signal to extract data therefrom.

[0071] In USB mode, the application processor 815 may receive data from one or more digital signal processing cores 810 and generate USB differential data signals USB(DN) and USB(DP). The application processor 815 may provide the USB differential data signals USB(DN) and USB(DP) to the sources of the switch FETs SW1-SW2, respectively, via the closed switch devices SWA-SWB controlled by the mode selection signal generated by the application processor 815. In addition, in USB mode, the application processor 815 may receive the USB differential data signals USB(DN) and USB(DP), respectively, via the turned-on switch FETs SW1-SW2 and the closed switch devices SWA-SWB, and provide data to the one or more digital signal processing cores 810 based on the received USB differential data signals.

[0072] In audio mode, the audio codec 820 may receive data from one or more digital signal processing cores 810 and generate analog audio signals AUD(R) and AUD(L). The audio codec may provide analog audio signals AUD(R) and AUD(L) to the sources of the switch FETs SW1-SW2, respectively, via the closed SWC-SWD controlled by the mode selection signal. The gate drive circuit (GDC-R) 825 and GDC-L 830 are configured to generate gate voltages for the switch FETs SW1-SW2, respectively, proportional to the voltages VinR and VinL at the outputs AUD(R) and AUD(L), in audio mode.

[0073] The switch FET SW3 provides a ground or return for the audio transducers 870-R and 870-L connected to the USB port 840. The device 800 includes a gate drive circuit (GDC-0) 835 configured to generate a gate voltage for the switch FET SW3 proportional to the sum of the voltages VinR+VinL at the outputs AUD(R) and AUD(L) in the audio mode. The ground potential can be applied to the source of the switch device SW3 and the headphone reference (HPF REF) input of the audio codec 820 via the closed switch devices SWF and / or SWE. The drains of the switch device FETs SW1-SW3 are coupled to the DN, DP, and SBU1 / 2 terminals of the USB port 840; and when the audio transducers 870-R and 870-L are connected to the USB port, the positive terminals and the common return of the audio transducers 870-R and 870-L are coupled to the DN, DP, and SBU1 / 2 terminals of the USB port 840, respectively. Alternatively, a USB digital data device (eg, USB storage device, keyboard, mouse, etc.) may be connected to the USB port 840 instead of the audio transducer. In the USB mode, the switch device SWF may be closed.

[0074] Fig. 9A A schematic diagram of an exemplary gate drive circuit 900 according to another aspect of the present disclosure is illustrated. The gate drive circuit 900 may be an example of a more detailed implementation of the gate drive circuit GDC-R 825 discussed previously. The gate drive circuit 900 includes an audio mode gate drive sub-circuit 910, which includes: a voltage scaling (β) device 912, which includes an input coupled to an output of the AUD(R) output of the audio codec 820 and is configured to receive an input voltage VinR; and a summer 914, which includes a first input coupled to the output of the voltage scaling device 912, a second input configured to receive a DC voltage VDCR, and an output configured to generate an audio mode gate voltage AUD VGR for the first switch FET SW1.

[0075] The gate drive circuit 900 may further include a USB mode gate voltage VGR generator 916 configured to generate a USB mode gate voltage USB VGR to keep the first switch FET SW1 turned on in the USB mode. The gate drive circuit 900 also includes a multiplexer 920 including a first input coupled to the output of the audio mode gate drive subcircuit 910, a second input coupled to the output of the USB gate voltage generator 916, a selection input configured to receive a mode selection signal from the application processor 815, and an output configured to generate a gate voltage VGR for the first switch FET SW1. Therefore, if the mode selection signal indicates the audio mode, the multiplexer 920 outputs the audio mode gate voltage AUD VGR as the gate voltage VGR for the first switch FET SW1. If the mode selection signal indicates the USB mode, the multiplexer 920 outputs the USB mode gate voltage USB VGR as the gate voltage VGR for the first switch FET SW1.

[0076] Fig. 9B A schematic diagram of another exemplary gate drive circuit 930 according to another aspect of the present disclosure is illustrated. The gate drive circuit 930 can be an example of a more detailed implementation of the gate drive circuit GDC-L 830 discussed previously. The gate drive circuit 930 includes an audio mode gate drive sub-circuit 940, which includes: a voltage scaling (α) device 912, which includes an input coupled to the output of the AUD(L) output of the audio codec 820 and is configured to receive an input voltage VinL; and a summer 944, which includes a first input coupled to the output of the voltage scaling device 942, a second input configured to receive a DC voltage VDCL, and an output configured to generate an audio mode gate voltage AUD VGL for the second switch FET SW2.

[0077] The gate drive circuit 930 may also include a USB mode gate voltage VGL generator 946 configured to generate a USB mode gate voltage USB VGL to keep the second switch FET SW2 turned on in the USB mode. The gate drive circuit 930 also includes a multiplexer 950, which includes a first input coupled to the output of the audio mode gate drive subcircuit 940, a second input coupled to the output of the USB gate voltage generator 946, a selection input configured to receive a mode selection signal from the application processor 815, and an output configured to generate a gate voltage VGL for the second switch FET SW2. Therefore, if the mode selection signal indicates the audio mode, the multiplexer 950 outputs the audio mode gate voltage AUD VGL as the gate voltage VGL for the second switch FET SW2. If the mode selection signal indicates the USB mode, the multiplexer 950 outputs the USB mode gate voltage USB VGL as the gate voltage VGL for the second switch FET SW2.

[0078] Fig. 9C A schematic diagram of another exemplary gate drive circuit 960 according to another aspect of the present disclosure is illustrated. The gate drive circuit 960 may be an example of a more detailed implementation of the gate drive circuit GDC-0 835 discussed previously. The gate drive circuit 960 includes an audio mode gate drive subcircuit 970, which includes: a first summer 972 including an input coupled to the AUD(R) and AUD(L) outputs of the audio codec 820; a voltage scaling (γ) device 974 including an input coupled to the output of the first summer 972; and a second summer 976 including a first input coupled to the output of the voltage scaling device 974, a second input configured to receive a DC voltage VDC0, and an output configured to generate an audio mode gate voltage AUD VG0 for the third switch FET SW3.

[0079] The gate drive circuit 960 may further include a USB mode gate voltage VG0 generator 978 configured to generate a USB mode gate voltage USB VG0 to keep the third switch FET SW3 turned on in the USB mode. The gate drive circuit 960 also includes a multiplexer 980 including a first input coupled to the output of the audio mode gate drive subcircuit 970, a second input coupled to the output of the USB gate voltage generator 978, a selection input configured to receive a mode selection signal from the application processor 815, and an output configured to generate a gate voltage VG0 for the third switch FET SW3. Therefore, if the mode selection signal indicates the audio mode, the multiplexer 980 outputs the audio mode gate voltage AUD VG0 as the gate voltage VG0 for the third switch FET SW3. If the mode selection signal indicates the USB mode, the multiplexer 980 outputs the USB mode gate voltage USB VG0 as the gate voltage VG0 for the third switch FET SW3.

[0080] The foregoing description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the examples described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: First amplifier; a first field effect transistor (FET) including a first source coupled to the output of the first amplifier and a first drain for coupling to a first load; as well as a first gate drive circuit including an input coupled to the output of the first amplifier and an output coupled to a first gate of the first FET, The first gate driving circuit comprises: a voltage scaling device comprising an input coupled to the output of the first amplifier; as well as A voltage summer includes a first input coupled to the output of the voltage scaling device, a second input configured to receive a direct current (DC) voltage, and an output coupled to the first gate of the first FET.

2. The apparatus of claim 1 , wherein the voltage scaling device comprises: a first resistor and a second resistor coupled in series between the output of the first amplifier and a voltage rail; as well as A differential amplifier includes a first input coupled to the output of the first amplifier, a second input coupled to a node between the first resistor and the second resistor, and an output coupled to the first gate of the first FET. 3 . The apparatus of claim 1 , wherein the first amplifier comprises an input configured to receive an analog audio signal. The apparatus of claim 1 , wherein the first load comprises an audio converter.

5. The apparatus of claim 1, further comprising a universal serial bus (USB) port coupled between the first FET and the first load.

6. The apparatus according to claim 1, further comprising: A second amplifier; a second field effect transistor (FET) including a second source coupled to the output of the second amplifier, and a second drain for coupling to a second load; as well as A second gate drive circuit includes an input coupled to the output of the second amplifier and an output coupled to a second gate of the second FET.

7. The apparatus of claim 6, wherein the second gate drive circuit comprises a voltage scaling device including an input coupled to the output of the second amplifier.

8. The device according to claim 6, wherein the second gate drive circuit comprises: a voltage scaling device comprising an input coupled to said output of said second amplifier; as well as A voltage summer includes a first input coupled to the output of the voltage scaling device, a second input configured to receive a direct current (DC) voltage, and an output coupled to the second gate of the second FET.

9. The apparatus according to claim 6, further comprising: a third field effect transistor (FET) including a third source coupled to the voltage rail, and a third drain for coupling to the first load and the second load; as well as A third gate drive circuit includes a first input coupled to the output of the first amplifier, a second input coupled to the output of the second amplifier, and an output coupled to a third gate of the third FET.

10. The device according to claim 9, wherein the third gate driving circuit comprises: a first voltage summer including a first input coupled to the output of the first amplifier and a second input coupled to the output of the second amplifier; a voltage scaling device comprising an input coupled to said output of said first voltage summer; as well as A second voltage summer includes a first input coupled to the output of the voltage scaling device, a second input configured to receive a direct current (DC) voltage, and an output coupled to the third gate of the third FET.

11. The apparatus of claim 10, wherein the first voltage summer comprises a summing amplifier including a first input coupled to the output of the first amplifier and a second input coupled to the output of the second amplifier, and wherein the voltage scaling device comprises: a first resistor and a second resistor coupled in series between an output of the summing amplifier and a voltage rail; as well as A differential amplifier includes a first input coupled to the output of the summing amplifier, a second input coupled to a node between the first resistor and the second resistor, and an output coupled to the third gate of the third FET.

12. The apparatus of claim 1, further comprising a first body drive circuit comprising an input coupled to the output of the first amplifier and an output coupled to a first body of the first FET.

13. The apparatus of claim 12, wherein the first body driver circuit comprises a voltage scaling device.

14. The apparatus according to claim 12, further comprising: A second amplifier; a second field effect transistor (FET) including a second source coupled to the output of the second amplifier and a second drain for coupling to a second load; as well as A second gate drive circuit includes an input coupled to the output of the second amplifier and an output coupled to a second gate of the second FET.

15. The apparatus of claim 14, further comprising a second body drive circuit comprising an input coupled to the output of the second amplifier and an output coupled to a second body of the second FET.

16. The apparatus of claim 15, wherein the second body driving circuit comprises a voltage scaling device.

17. The apparatus according to claim 15, further comprising: a third field effect transistor (FET) including a third source coupled to the voltage rail, and a third drain for coupling to the first load and the second load; as well as A third gate drive circuit includes a first input coupled to the output of the first amplifier, a second input coupled to the output of the second amplifier, and an output coupled to a third gate of the third FET.

18. The apparatus of claim 17, further comprising a third body drive circuit comprising a first input coupled to the output of the first amplifier, a second input coupled to the output of the second amplifier, and an output of a third body coupled to the third FET.

19. The device according to claim 18, wherein the third body driving circuit comprises: a voltage summer including a first input coupled to the output of the first amplifier and a second input coupled to the output of the second amplifier; as well as A voltage scaling device includes an input coupled to the output of the voltage summer and an output coupled to the third body of the third FET.

20. A method comprising: amplifying the first audio signal using a first audio amplifier to generate a first voltage; generating a first gate voltage based on the first voltage, Wherein generating the first gate voltage comprises: scaling the first voltage by a first scaling factor to generate a first scaled voltage; and summing the first scaled voltage and a first direct current (DC) voltage to generate the first gate voltage; and The first gate voltage is applied to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer.

21. The method according to claim 20, further comprising: amplifying the second audio signal using a second audio amplifier to generate a second voltage; generating a second gate voltage based on the second voltage; as well as The second gate voltage is applied to a second gate of a second field effect transistor (FET) coupled between the second audio amplifier and a second audio transducer.

22. The method according to claim 21, further comprising: generating a third gate voltage based on a sum of the first voltage and the second voltage; as well as The third gate voltage is applied to a third gate of a third field effect transistor (FET) coupled between the first and second audio transducers and a voltage rail.

23. The method according to claim 22, further comprising: generating a first body voltage based on the first voltage; applying the first body voltage to the first body of the first FET; generating a second body voltage based on the second voltage; applying the second body voltage to the second body of the second FET; generating a third body voltage based on a sum of the first voltage and the second voltage; as well as The third body voltage is applied to a third body of the third FET.

24. An apparatus comprising: means for amplifying a first audio signal using a first audio amplifier to generate a first voltage; means for generating a first gate voltage based on the first voltage, Wherein generating the first gate voltage comprises: scaling the first voltage by a first scaling factor to generate a first scaled voltage; and summing the first scaled voltage and a first direct current (DC) voltage to generate the first gate voltage; and Means for applying the first gate voltage to a first gate of a first field effect transistor (FET) coupled between the first audio amplifier and a first audio transducer.

25. The apparatus according to claim 24, further comprising: means for amplifying the second audio signal using a second audio amplifier to generate a second voltage; means for generating a second gate voltage based on the second voltage; Means for applying the second gate voltage to a second gate of a second field effect transistor (FET) coupled between the second audio amplifier and a second audio transducer.

26. The apparatus according to claim 25, further comprising: means for generating a third gate voltage based on a sum of the first voltage and the second voltage; as well as Means for applying the third gate voltage to a third gate of a third field effect transistor (FET) coupled between the first and second audio transducers and a voltage rail.

27. A wireless communication device, comprising: at least one antenna; a transceiver coupled to the at least one antenna; at least one digital signal processing core coupled to the transceiver; a port configured to connect to one of at least one audio transducer and a digital data device; at least one audio amplifier; at least one field effect transistor (FET) including a source and a drain, the source being respectively coupled to an output of the at least one audio amplifier and the drain being coupled to the port; as well as at least one gate drive circuit comprising an input coupled to the output of the at least one audio amplifier and an output coupled to a gate of the at least one FET, Wherein the at least one gate drive circuit comprises: a voltage scaling device comprising an input coupled to said output of said at least one audio amplifier; as well as A voltage summer includes a first input coupled to the output of the voltage scaling device, a second input configured to receive a direct current (DC) voltage, and an output coupled to the gate of the at least one FET.

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