Wafer edge defect scanning method, computer device and readable storage medium

Abstract

This invention provides a method for scanning wafer edge defects. The method includes: performing a first scan on a wafer with edge defects from a batch of wafers to obtain its map; determining the location of the edge defects based on the map, and determining a defect scanning range based on the location of the edge defects, wherein the defect scanning range is a ring-shaped region located at the edge of the wafer, the center of which coincides with the center of the wafer; processing the position coordinates of the grains within the defect scanning range to form a region wafer map; performing a second scan on the grains within the defect scanning range based on the region wafer map, and establishing a new scan recipe; and using the new scan recipe to scan other wafers for edge defects. This invention solves the problem of low scanning efficiency for wafer edge defects in existing methods.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for scanning wafer edge defects, a computer device, and a readable storage medium. Background Technology

[0002] In semiconductor chip manufacturing processes, the establishment of a reasonable and efficient defect monitoring system can enable real-time monitoring of the status of wafer defects (caused by process or equipment abnormalities) and timely identification of the cause of defects. Therefore, it plays an important role in reducing defects and improving yield.

[0003] The current standard defect monitoring process involves scanning each wafer in the same batch using a scanner, transmitting the scanned image, and then manually checking the edges for any abnormal defects. Wafers with edge defects are then re-scanned for further defect detection. However, this approach wastes equipment capacity and hinders product flow. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a scanning method for wafer edge defects, which solves the problem of low scanning efficiency of existing wafer edge defects.

[0005] To achieve the above and other related objectives, the present invention provides a method for scanning wafer edge defects, the method comprising:

[0006] A first scan is performed on a wafer with edge defects in a batch of wafers to obtain its map image;

[0007] The location of the edge defect is determined based on the map, and the defect scanning range is determined based on the location of the edge defect, wherein the defect scanning range is an annular region located at the edge of the wafer, and its center coincides with the center of the wafer;

[0008] The position coordinates of the grains within the defect scanning range are processed to form a region wafer map;

[0009] A second scan is performed on the grains within the defect scanning range based on the wafer map of the region, and a new scan recipe is established;

[0010] The new scanning recipe is used to scan for edge defects on other wafers.

[0011] Optionally, the method of processing the position coordinates of the grains within the defect scanning range to form the region wafer map includes arranging the position coordinates of each grain in a manner from left to right and from top to bottom.

[0012] Optionally, the regional wafer map includes a rectangular wafer map.

[0013] Optionally, the length of the rectangular wafer pattern is the circumference of the wafer; the width of the rectangular wafer pattern is the width of the annular region.

[0014] Optionally, the method for performing a second scan of the grains within the defect scanning range based on the regional wafer image includes: scanning based on the width of the annular region.

[0015] Optionally, the new scan recipe includes different width values ​​for the annular region.

[0016] Accordingly, the present invention also provides a computer device, characterized in that it includes a processor and a memory, the processor being adapted to implement various instructions, and the memory being adapted to store multiple instructions, wherein the instructions are adapted to be loaded by the processor and executed as described above for scanning wafer edge defects.

[0017] Accordingly, the present invention also provides a computer-readable storage medium storing computer-executable instructions, wherein when the computer-executable instructions are executed, the wafer edge defect scanning method described above can be implemented.

[0018] As described above, the wafer edge defect scanning method, computer equipment, and readable storage medium of the present invention determine the defect scanning range, process the position coordinates of the dies within the defect scanning range to form a regional wafer map, establish a new scanning recipe based on the regional wafer map, and then use the new scanning recipe to scan edge defects of other wafers, thereby improving the wafer scanning efficiency and accuracy, reducing the impact of defects in other locations on wafer edge defects, and reducing the number of affected wafer batches, thereby increasing the machine's production capacity. Attached Figure Description

[0019] Figure 1 The flowchart shown is a method for scanning wafer edge defects according to the present invention. Detailed Implementation

[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0021] Please see Figure 1 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Although the illustrations only show components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation, the shape, quantity and proportion of each component in the actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0022] like Figure 1 As shown, this embodiment provides a method for scanning wafer edge defects, the method comprising:

[0023] A first scan is performed on a wafer with edge defects in a batch of wafers to obtain its map image;

[0024] The location of the edge defect is determined based on the map, and the defect scanning range is determined based on the location of the edge defect, wherein the defect scanning range is an annular region located at the edge of the wafer, and its center coincides with the center of the wafer;

[0025] The position coordinates of the grains within the defect scanning range are processed to form a region wafer map;

[0026] A second scan is performed on the grains within the defect scanning range based on the wafer map of the region, and a new scan recipe is established;

[0027] The new scanning recipe is used to scan for edge defects on other wafers.

[0028] In this embodiment, before performing the first scan on the wafer, it is necessary to determine whether there are edge defects in the batch of wafers, and select the wafers with edge defects. When performing the first scan on a wafer, the entire wafer is scanned, so the resulting map image is a graphic representation of the entire wafer.

[0029] Specifically, the method for processing the position coordinates of the grains within the defect scanning range to form the region wafer map includes arranging the position coordinates of each grain in a manner from left to right and from top to bottom.

[0030] In this embodiment, the position coordinates of each die obtained from scanning are rearranged in rows and columns. The purpose is to establish a new scanning recipe. By using the new scanning recipe to scan the edge defects of the wafer, the defect scanning time is reduced, the wafer scanning efficiency is improved, and the number of affected wafer batches is reduced, thereby increasing the machine's production capacity.

[0031] Specifically, the regional wafer map includes a rectangular wafer map.

[0032] More specifically, the length of the rectangular wafer pattern is the circumference of the wafer; the width of the rectangular wafer pattern is the width of the annular region.

[0033] In this embodiment, for a 12-inch wafer, the length of the rectangular wafer pattern is 300mm, and its width is determined according to the location of the edge defect.

[0034] Specifically, the method for performing a second scan of the grains within the defect scanning range based on the regional wafer image includes: scanning based on the width of the annular region.

[0035] In this embodiment, when scanning the edge defect, scanning based on the width of the annular region can greatly reduce the defect scanning time and improve scanning efficiency.

[0036] Specifically, the new scan recipe includes different width values ​​for the annular region.

[0037] In this embodiment, since different wafers may have different edge defect distribution areas (defect scanning ranges), that is, the annular area has different width values, the new scanning recipe needs to include different width values ​​to achieve scanning of edge defects of each wafer.

[0038] Accordingly, this embodiment also provides a computer device, including a processor and a memory, wherein the processor is adapted to implement various instructions, and the memory is adapted to store multiple instructions, wherein the instructions are adapted to be loaded by the processor and executed as described above for scanning wafer edge defects.

[0039] Accordingly, this embodiment also provides a computer-readable storage medium storing computer-executable instructions, wherein when the computer-executable instructions are executed, the wafer edge defect scanning method described above can be implemented.

[0040] In summary, the wafer edge defect scanning method, computer equipment, and readable storage medium of the present invention, by determining the defect scanning range, processing the position coordinates of the dies within the defect scanning range to form a regional wafer map, and establishing a new scanning recipe based on the regional wafer map, and then using the new scanning recipe to scan edge defects of other wafers, improves wafer scanning efficiency and accuracy, reduces the impact of defects in other locations on wafer edge defects, and reduces the number of affected wafer batches, thereby increasing machine throughput. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0041] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for scanning edge defects of a wafer, characterized in that, The method includes: Performing a first scan on a wafer with edge defects in a batch of wafers to obtain its Map; when performing the first scan on a wafer, the entire wafer is scanned, and the obtained Map is the graph of the entire wafer; Determining the location of the edge defect according to the Map, and determining the defect scanning range according to the location of the edge defect, wherein the defect scanning range is an annular area located at the edge of the wafer, and its center coincides with the center of the wafer; Processing the position coordinates of the die within the defect scanning range to form a regional wafer map; Performing a second scan on the die within the defect scanning range according to the regional wafer map, and establishing a new scan recipe; Using the new scan recipe to scan for edge defects on other wafers.

2. The scanning method for wafer edge defects according to claim 1, wherein The method of processing the position coordinates of the die within the defect scanning range to form the regional wafer map includes: arranging the position coordinates of each die in a left-to-right and top-to-bottom manner.

3. The scanning method for wafer edge defects according to claim 2, wherein The regional wafer map includes a rectangular wafer map.

4. The scanning method for wafer edge defects according to claim 3, wherein The length of the rectangular wafer map is the circumference of the wafer; the width of the rectangular wafer map is the width of the annular area.

5. The scanning method for wafer edge defects according to claim 4, wherein The method of performing a second scan on the die within the defect scanning range according to the regional wafer map includes: scanning according to the width of the annular area.

6. The scanning method for wafer edge defects according to any one of claims 1 to 5, characterized in that, The new scan recipe includes width values of different annular areas.

7. A computer device, characterized in that, Including a processor and a memory, the processor is adapted to implement each instruction, the memory is adapted to store multiple instructions, wherein the instructions are adapted to be loaded and executed by the processor to perform the wafer edge defect scanning method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that, Computer-executable instructions are stored on the computer-readable storage medium, wherein when the computer-executable instructions are executed, the wafer edge defect scanning method according to any one of claims 1 to 6 can be implemented.

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