LFMCW radiation source L array DBF direction finding method

Abstract

The application discloses a kind of L array DBF goniometry methods for LFMCW radiation source, the data received by L array is down-converted and extracted filtering in FPGA then according to two-dimensional linear array processing, utilize the advantage of parallel processing of FPGA, when DBF processing, two parallel routes of search and processing are divided, then the idea of two linear arrays and difference beam is FFT processed using the IP of FFT, after the result is converted into single-precision floating-point number, the data in FPGA is transmitted to ARM using the AXI IP of Zynq for subsequent processing and angle conversion.The application utilizes the low data amount DBF processing method, realizes the efficient transmission of data between FPGA and ARM by combining the AXI data line of Zynq series, greatly improves the overall performance of signal processing machine, ensures basic goniometry function while enhancing the real-time processing capability of system.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of radar signal processing, and particularly relates to a digital beam forming (DBF) angle measurement method for a linear frequency modulation continuous wave (LFMCW) signal processing system. BACKGROUND

[0002] In recent years, LFMCW radars are widely used in military detection and security protection fields due to their small size, no range blind area, low transmission power, and low interception probability. Foreign linear frequency modulation continuous wave radars based on inverse SAR technology are used for target identification imaging in the war zone, and LFMCW radars are mainly used in active detection and defense of ground armor and adaptive navigation. Therefore, the demand for LFMCW emitter detection technology has gradually developed.

[0003] In the early stage, due to the immaturity of radio frequency devices, it is difficult to synchronize between each receiving channel, so it is impossible to accumulate the space domain of each channel. Later, with the gradual maturity of radio frequency devices, each receiving channel is synchronized, and the space domain accumulation of a specific direction can be realized by digitally weighting the signals of each receiving channel in the signal processing process.

[0004] Generally, a signal processing machine includes a programmable logic unit for parallel processing of signals and a serial computing unit for complex calculations. For LFMCW system signal processing, the FPGA+DSP architecture is usually adopted. However, since FPGA and DSP are two independent chips, the data transmission rate between them is limited by the circuit board wiring and interface protocol. Although this has little effect in some signal processing scenarios with simple algorithms and small data volume, when the algorithm complexity of the system is improved and the data to be transmitted is too much, the data transmission rate between FPGA and DSP will become a bottleneck for real-time processing of LFMCW signals. For a multi-receiving unit array receiver, if a traditional array beam forming algorithm is used to process and measure the angle of the received signals, multiple digital beams need to be formed to cover the reconnaissance area. After processing each digital beam, the target beam and angle are determined by the sum-difference ratio. This processing method requires complete processing of each beam, resulting in excessive data and long search time. Although FPGA has the advantage of parallel processing, it is difficult to process all the echoes of the same array in parallel due to the limited logic resources of FPGA. In addition, the computing capacity of FPGA is limited, and subsequent processing needs to rely on computing units. On the one hand, the large data volume leads to long processing time of the serial computing unit. On the other hand, moving data from FPGA to the serial computing unit with floating point operation capability also consumes processing time, affecting the real-time processing capability of the radar system. SUMMARY

[0005] The application provides an L-array DBF angle measurement method for an LFMCW radiation source, and the data received by the L-array is down-converted and extracted and filtered in an FPGA, and then processed according to two linear arrays, the advantages of parallel processing of the FPGA are utilized, two paths are searched and processed in parallel during DBF processing, then the two linear arrays are FFT processed by using an FFT IP, the result is converted into a single-precision floating point number, and then the data in the FPGA is transmitted to an ARM for subsequent processing and angle conversion by using an AXI IP of the Zynq.

[0006] The technical solution of the application is as follows: an L-array DBF angle measurement method for an LFMCW radiation source, characterized by the following steps.

[0007] Step one: the digital signals collected by the signal processor AD are respectively down-converted and extracted and filtered, then stored in a FIFO buffer, and when the FIFO is full, the data is read out, and meanwhile, the ARM configures the addressing space M and N of ROM1 and ROM2 according to requirements, corresponding to the number of beams searched by the two linear arrays, and the step two is entered.

[0008] Step two: the data of each path corresponding to the transverse receiving unit after extraction and filtering is multiplied by the weighting factor with the address of 1 to M of ROM1 corresponding to the data of each path of the transverse receiving unit, to obtain the address of the weighting factor with the maximum sum of square values of beams, the address of the weighting factor is cached as the beam serial number, and a group of corresponding transverse maximum sum and difference beams are obtained; the data of each path corresponding to the longitudinal receiving unit after extraction and filtering is multiplied by the weighting factor with the address of 1 to N of ROM2 corresponding to the data of each path of the longitudinal receiving unit, to obtain the address of the weighting factor with the maximum sum of square values of beams, the address of the weighting factor is cached as the beam serial number, and a group of corresponding longitudinal maximum sum and difference beams are obtained, and the step three is entered.

[0009] Step three: the window function sampling points corresponding to the FFT point number are read out from the ROM, and multiplied by the two groups of sum and difference beams respectively, to obtain the sum and difference beam window processing data, complete the window processing to reduce the sidelobes, then the sum and difference beam window processing data are taken as the input of the FFT IP core, and the FFT operation is performed to obtain the sum and difference beam Fourier transform data, and the step four is entered.

[0010] Step 4: Input the sum and difference beam Fourier transform data into the sliding window threshold truncation module. The module processes the sum and difference beam Fourier transform data to obtain the target location and the beam weighting factor corresponding to the ROM1 and ROM2 addresses from Step 2. After truncating the data by determining the required number of bits for the target point using upper and lower amplitude limits, the result is converted to a floating-point value. After converting the data to single-precision floating-point numbers, the sum and difference beam Fourier transform floating-point data is cached in a FIFO, realizing clock domain transformation and data bit width adjustment from the FFT output clock to the AXI transmission clock. The sliding window threshold truncation module uses a two-dimensional sliding window with a fast time dimension and different beam dimensions. Each dimension uses a register to cache extreme values. While implementing signal pipelined processing in the time dimension, it compares the sum and difference beam Fourier transform floating-point data corresponding to the signal extreme values ​​in real time, thereby selecting the target location and beam in the beam dimension, and proceeding to Step 5.

[0011] Step 5: After the FIFO is full, edit the AXI IP working clock. This invention uses the AXI IP core to send the sum and difference beam Fourier transform floating-point data in the FIFO and the beam number in the register to the ARM via the AXI bus, and caches it in the DDR mounted on the ARM to realize real-time refresh and pipelined processing of the sum and difference beam Fourier transform floating-point data cached in the DDR. Proceed to Step 6.

[0012] Step Six: The ARM retrieves the DDR cache data from Step Five by address and performs sum-difference beam difference ratio calculation. The two sets of sum-difference ratio calculation results are looked up in the antenna pattern to obtain the target angles measured by the two linear arrays. The angle measurement results of the parallel linear array are converted into two-dimensional angle measurement results using the angle measurement method proposed in this invention to obtain the azimuth and elevation angles of the target. This completes one angle measurement.

[0013] Compared with the prior art, the significant advantages of this invention are:

[0014] (1) The present invention treats the receiving unit of the L array as two linear arrays. When performing DBF angle measurement, the two linear arrays are searched simultaneously. This is faster than performing two-dimensional search on the entire L array directly using DBF processing, reducing the search time and improving the system's response speed.

[0015] (2) During DBF processing, a sliding window threshold truncation module is used to achieve parallel processing and search comparison. One branch uses the weighting factors in the register to generate sum and difference beams for data stream processing and angle estimation; simultaneously, another branch uses the sliding window threshold truncation module to cyclically compare the upper and lower thresholds of the squared amplitude of each digital beam signal, and update the weighting factors and threshold values ​​in the corresponding registers in a timely manner. This parallel processing and search method can reduce search waiting time, eliminating the need to wait for all beams to be searched before processing, and effectively controlling the data width. Furthermore, the ARM can adjust the search angle by controlling the ROM addressing range during DBF, increasing system flexibility.

[0016] (3) This invention utilizes the low-data-volume DBF processing method, combined with the Zynq series AXI data line to achieve efficient data transmission between FPGA and ARM, which greatly improves the overall performance of the signal processor, ensures the basic angle measurement function, and enhances the real-time processing capability of the system. Attached Figure Description

[0017] Figure 1 Signal processing flow diagram for implementing DBF angle measurement for L array.

[0018] Figure 2 The state transition diagram is for the finite state machine controlling the DBF by the FPGA.

[0019] Figures 3(a) and 3(b) show the module division and data flow diagram for digital beamforming implementation.

[0020] Figure 4 This is a schematic diagram of the angle conversion between two linear arrays.

[0021] Figure 5 This is a schematic diagram of the sliding window threshold truncation module.

[0022] Figures 6(a), 6(b), 6(c), and 6(d) show the simulation angle measurement results of targets at different angles plotted in Matlab.

[0023] Figures 7(a) and 7(b) show the simulation angle measurement results of the target trajectory plotted in Matlab.

[0024] Figures 8(a) and 8(b) show the relationship between the root mean square error of the simulated angle estimate and the signal-to-noise ratio.

[0025] Figures 9(a) and 9(b) show the comparison between Modelsim and ILA results during beam switching.

[0026] Figures 10(a), 10(b), 10(c), and 10(d) show the data transmitted from Zynq to the computer and the angle measurement results in the actual system. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0028] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixing," etc., should be interpreted broadly. For example, "fixing" can mean a fixed connection, a detachable connection, or an integral part; "connection" can mean a mechanical connection or an electrical connection. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0029] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible to those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0030] The following section will further introduce the specific implementation method, as well as the technical difficulties and inventive points of this invention, using this design example as an example.

[0031] This invention proposes a digital beamforming (DBF) implementation method based on the Zynq series FPGA+ARM architecture. By performing DBF processing on the digital processing system of the L receiver array, it can ensure the angle measurement function for LFMCW signals, reduce the amount of data, and perform beam search within a specific range without affecting data stream transmission.

[0032] Step 1: The digital signals acquired by the signal processor AD are digitally down-converted and decimated and filtered, then buffered by FIFO. After the FIFO is full, the data is read out. At the same time, the ARM configures the address spaces M and N of ROM1 and ROM2 as required, corresponding to the number of beams searched by the two linear arrays.

[0033] Furthermore, the decimation filtering operation involves decimating the data after digital down-conversion. Because the sampling rate of the AD converter is much higher than twice the maximum frequency of the baseband signal, decimation reduces the amount of data. For example... Figure 1In this process, when using a FIFO for buffering, the FIFO's read clock frequency must be higher than its write clock frequency. Reading a full FIFO using a high-frequency read clock can accelerate subsequent processing. Simultaneously, buffering the echo signal in the FIFO allows for parallel processing in the time domain, reserving time for later processing. Before performing a search, the ARM can assign values ​​to the register controlling the ROM read address within the FPGA via the AXI data line, thereby controlling the number of search beams as needed.

[0034] Step 2: Extract the data from each channel of the decimated and filtered horizontal receiving unit, and cyclically multiply each channel of the data from the horizontal receiving unit with the weighting factors at addresses 1 to M in ROM1 to obtain the address of the weighting factor with the largest sum-beam square value. Cache this weighting factor address as the beam number and obtain a set of corresponding horizontal maximum sum-difference beams. Extract the data from each channel of the decimated and filtered vertical receiving unit, and cyclically multiply each channel of the data from the vertical receiving unit with the weighting factors at addresses 1 to N in ROM2 to obtain the address of the weighting factor with the largest sum-beam square value. Cache this weighting factor address as the beam number and obtain a set of corresponding vertical maximum sum-difference beams.

[0035] Furthermore, the receiving unit refers to each receiving antenna in the L-array antenna. The data received by the receiving antenna is mixed and then acquired by an AD converter. In this system, there are 16 receiving antennas horizontally and 16 receiving antennas vertically in the L-array, for a total of 31 (with one shared antenna in the middle). When the L-array is treated as two linear arrays of 16 receiving antennas each, each linear array has 16 data channels. Different weighting factors are stored in the ROM according to their addresses. When the 16 signals are multiplied by the weighting factors, it essentially performs phase compensation on the 16 signals to achieve different directions of the digital beam. Then, all 16 signals are added together to obtain the sum beam pointing to that beam. The left and right 8 signals are summed and then subtracted to obtain the difference beam pointing to that beam. The maximum addressing range of the ROM, i.e., the maximum number of weighting factors that can be stored, is calculated based on the maximum search range and the beamwidth of each linear array. While the weighting factors in the ROM are multiplied by the 16 echo signals in ascending order of address to obtain the sum and difference beams for digital beam searching, the weighting factors in the register are also multiplied by the 16 echo signals to obtain the sum and difference beams. Then, the sliding window thresholding module iteratively compares the results, and the weighting factor corresponding to the larger square value of the sum beam (i.e., the sum of the products of the I and Q signals) is selected. The operating state transition is as follows: Figure 2As shown in Figures 3(a) and 3(b), the weighting factor update process is performed simultaneously on both linear arrays to obtain two sets of sum and difference beams with I and Q paths. Beam selection is completed during DBF in the FPGA using this method. This has two advantages: first, the parallel one-dimensional searches are faster than the two-dimensional search; second, beam selection is completed within the FPGA, eliminating the need to process and transmit all directional digital beam signals, and allowing for timely beam updates during cross-beam angle measurement, as shown in Figures 9(a) and 9(b).

[0036] Step 3: Read the window function sampling points corresponding to the FFT points from the ROM and multiply them by the two sets of sum and difference beams respectively to obtain the sum and difference beam windowed processing data. The windowing process is completed to reduce sidelobes. Then, the sum and difference beam windowed processing data is used as the input of the FFT IP core to perform FFT operation and obtain the sum and difference beam Fourier transform data.

[0037] Furthermore, before performing FFT on the two sets of sum and difference signals, a pre-stored window function sequence is read from the ROM and multiplied by the IQ values ​​of the two sets of sum and difference signals respectively. Because the signals were truncated during time-domain separation, windowing is applied to suppress sidelobe amplitudes generated after FFT. This invention uses a Hamming window corresponding to the number of FFT points. Specifically, the window function's COE file is first exported from Matlab, and then imported into the ROM in Vivado. During windowing, the window function sequence in the ROM is read and multiplied by the signal. The FFT IP core interface in Vivado 2019.2 is in AXI format. During FFT, the `s_axis_data_tready` signal is checked. When this signal is high, `s_axis_data_tvalid` is set to 1, indicating that the data on the `s_axis_data_tdata` data line is valid. When the last data input is reached, `s_axis_data_tlast` is set to 1. After the FFT IP is calculated and the output FFT result is generated, `m_axis_data_tvalid` is set to 1. The obtained FFT result is output in `m_axis_data_tdata`, and the `tlast` signal is also used as a marker when the output is complete. After windowing, the processing time is further reduced by inputting the two sets of sum and difference signals into the 4-channel FFT for parallel calculation.

[0038] Step 4: Input the sum and difference beam Fourier transform data into the sliding window threshold truncation module. The module processes the sum and difference beam Fourier transform data to obtain the target location and beam weighting factor corresponding to the ROM1 and ROM2 addresses from Step 2. After truncating the data by determining the required number of bits for the target point based on amplitude upper and lower limits, the result is converted to a floating-point value. After converting the data to single-precision floating-point numbers, the sum and difference beam Fourier transform floating-point data is cached in a FIFO, realizing clock domain transformation and data bit width adjustment from the FFT output clock to the AXI transmission clock. The sliding window threshold truncation module uses a two-dimensional sliding window with a fast time dimension and different beam dimensions. Each dimension uses a register to cache extreme values. While implementing signal pipelined processing in the time dimension, it compares the sum and difference beam Fourier transform floating-point data corresponding to the signal extreme values ​​in real time, thereby selecting the target location and beam in the beam dimension. Specifically:

[0039] Furthermore, upon detecting that the FFT IP core output result flag `m_axis_data_tvaild` has gone high, indicating a valid FFT output, the output sum-difference beam Fourier transform data is split into two paths, 1 and 2. The first path's sum-difference beam Fourier transform data is sent to the sliding window threshold truncation module. The second path's sum-difference beam Fourier transform data is truncated and then converted from fixed-point to floating-point. The processing of the first path's sum-difference beam Fourier transform data is as follows... Figure 5As shown, RAM caching is performed first. Then, a sliding window comparison is conducted between the beams using two registers to obtain the beam with the largest sum-beam square value, and the address corresponding to the weighting factor of that beam in step two. In the fast time dimension, a sliding window comparison is conducted using three registers in another direction to estimate the maximum and minimum values ​​of the sum and difference beams, i.e., the upper and lower thresholds of the signal, thereby estimating the number of fixed-point bits required to represent the corresponding amplitude. If the number of bits is less than the number of bits of the Fourier transform data of the first sum and difference beam, it is truncated first, providing a basis for truncating the Fourier transform data of the second sum and difference beam. Then, the Fourier transform data of the second sum and difference beam undergoes fixed-point to floating-point conversion. In this way, on the one hand, continuous cyclic search and dynamic threshold setting of digital beams in both horizontal and vertical directions are achieved; on the other hand, this parallel operation reduces the time for beam search and threshold determination, further reducing the data volume from both the perspective of the number of beams and the data bit width. The reason for conducting a cyclic comparison of the sum-beam square value after FFT is to rely on the gain of FFT processing to further highlight the LFMCW signal from the received signal. The reason for performing fixed-point to floating-point conversion is that after passing through the multiplication IP core and FFT IP core, the 14-bit data acquired by the AD converter has been expanded. The AXI bus data line width, within the AXI IP core generated in Vivado, supports 32 bits. If the bit width of the FFT result is truncated, the dynamic range of the system will be reduced. Therefore, fixed-point to floating-point conversion is necessary to convert the sum and difference beam Fourier transform data into single-precision floating-point numbers, which are sufficient to represent the data range and facilitate subsequent data transmission. The converted single-precision floating-point numbers are then used as input to an instantiated dual-port independent clock FIFO. The input clock is 50MHz, the same as the fixed-point to floating-point conversion rate. The output clock is connected to the Zynq IP output, which outputs 115MHz. The FIFO's function is to implement cross-clock domain buffering, caching slow-speed data to a certain amount before transmitting it through the AXI data lines at a faster clock speed.

[0040] Step 5: After the FIFO is full, edit the AXI IP working clock. This invention uses the AXI IP core to send the sum and difference beam Fourier transform floating-point data in the FIFO and the beam number in the register to the ARM via the AXI bus, and caches it in the DDR connected to the ARM to realize real-time refresh and pipelined processing of the sum and difference beam Fourier transform floating-point data cached in the DDR, as detailed below:

[0041] Furthermore, an IP core in AXI bus format is generated in Vivado. This IP core transmits the data cached in the FIFO in step four to the ARM side via the AXI data line inside the Zynq through the FPGA. Compared to a signal processor with an FPGA+DSP architecture, Zynq's method of data transmission via the AXI bus within a single chip has two advantages: faster transmission speed (up to 370MB / s at a 32-bit width and a 115MHz clock speed), and more convenient data manipulation, eliminating the need for frequent cross-platform operations. This invention undergoes real-time modifications, setting the AXI core's operating clock, M_AXI_ACLK, to be driven by the same clock source derived from the Zynq as the FIFO read clock in step four. This achieves fast data readout from the FIFO while minimizing cross-clock domain operations. The data written through the AXI IP will be cached in the DDR mounted on the ARM. Therefore, the DDR address space must be configured in the Zynq IP in advance. This storage space must be larger than the amount of data transmitted in one transmission, that is, larger than the size of the FIFO in step four. When the first transmission is completed and the second transmission is performed when the FIFO is full, the transmission result will overwrite the first transmission result.

[0042] Step Six: The ARM retrieves the DDR cache data from Step Five by address and performs sum-difference beam ratio calculation. The two sets of sum-difference ratio calculation results are then looked up in a table on the antenna pattern to obtain the target angles measured by the two linear arrays. Using the angle measurement method proposed in this invention, the parallel linear array angle measurement results are converted into two-dimensional angle measurement results to obtain the target's azimuth and elevation angles. This completes one angle measurement operation, as detailed below:

[0043] Further, the ARM reads the data sent in step five from the DDR, divides the sum and difference beam extremes to obtain the sum-difference beam ratio, and uses this ratio and the antenna pattern to look up the target's angle within the beam. Simultaneously, using the weighting factor address and beamwidth from step two, the angle corresponding to the beam center position can be calculated. Based on the beam's pointing center angle and the target's angle within the beam, the target's angle relative to the normal plane of the linear array can be obtained. After obtaining the target's angle relative to the normal planes of the two linear arrays, conversion is needed to obtain the correct azimuth and elevation angles. For example... Figure 4 As shown, the angle 'a' between the target and the normal plane of the linear array is measured by two 16-element linear arrays on the Y-axis, and the angle 'b' between the target and the normal plane of the linear array is measured by two 16-element linear arrays on the Z-axis. Then, according to... Figure 4 The azimuth angle can be obtained by calculating the relationship shown. The elevation angle θ = a. Therefore, in the ARM, the sum-difference ratio is calculated by comparing the data. After looking up the angles measured by each linear array sum-difference beam in the table, trigonometric function operations are performed to obtain the azimuth and elevation angles of the target, completing one angle measurement. The simulation results of a single measurement using this angle measurement method are shown in Figures 6(a), 6(b), 6(c), and 6(d); the simulation results of the trajectory measurement of the moving target are shown in Figures 7(a) and 7(b); based on this, 500 Monte Carlo simulations were performed to obtain the root mean square error of the degree estimate and the relationship between the signal-to-noise ratio, as shown in Figures 8(a) and 8(b); the actual measurement results are shown in Figures 10(a), 10(b), 10(c), and 10(d).

[0044] This invention addresses the issues of large data volume and slow search response in two-dimensional angle measurement by proposing a DBF angle measurement method for an L-array LFMCW radiation source implemented using a Zynq series FPGA+ARM architecture. Within the FPGA, the data received from the L-array is processed as a two-dimensional linear array. Leveraging the parallel processing advantage of the FPGA, during DBF processing, a sliding window thresholding module is used to separate the search and processing into two parallel paths. Data transmission from the FPGA to the ARM is completed using the Zynq's AXI bus. This solves the problems of large data volume and slow beam-by-beam search response in two-dimensional angle measurement with L-arrays, improving the system's real-time performance.

Claims

1. A L-array DBF direction finding method for LFMCW radiation sources, characterized in that, The steps are as follows: Step one: the digital signals collected by the signal processor AD are respectively subjected to digital down-conversion and decimation filtering, and then are subjected to FIFO buffering, after the FIFO is filled, the data is read out, at the same time, the ARM configures the addressing space M and N of ROM1 and ROM2 according to the requirement, corresponding to the number of beams searched by the two linear arrays, and step two is entered; Step two: the data corresponding to each channel of the transverse receiving unit after decimation filtering is multiplied by the weighting factor corresponding to each channel of the transverse receiving unit and the address of ROM1 from 1 to M in a loop, to obtain the address of the weighting factor with the maximum sum of beam square values, buffer the weighting factor address as the beam serial number, and obtain a group of corresponding transverse maximum sum and difference beams; the data corresponding to each channel of the longitudinal receiving unit after decimation filtering is multiplied by the weighting factor corresponding to each channel of the longitudinal receiving unit and the address of ROM2 from 1 to N in a loop, to obtain the address of the weighting factor with the maximum sum of beam square values, buffer the weighting factor address as the beam serial number, and obtain a group of corresponding longitudinal maximum sum and difference beams, and step three is entered; Step three: the window function sampling points corresponding to the FFT point number are read out from the ROM and multiplied by the two groups of sum and difference beams respectively, to obtain the sum and difference beam window processing data, complete the window processing to reduce the sidelobe, then the sum and difference beam window processing data is taken as the input of the FFT IP core, and the FFT operation is performed to obtain the sum and difference beam Fourier transform data, and step four is entered; Step four: the sum and difference beam Fourier transform data is input into the sliding window threshold clipping module, the sum and difference beam Fourier transform data is processed in the sliding window threshold clipping module to obtain the ROM1 and ROM2 addresses in step two corresponding to the weighting factor of the beam where the target is located; the data is truncated after the number of bits is determined by the upper and lower limits of the amplitude, and the result is converted into a floating point value, the data is converted into a single precision floating point number, and the sum and difference beam Fourier transform floating point data is buffered to the FIFO, realizing the clock domain conversion and data bit width adjustment from the FFT output clock to the AXI transmission clock; the sliding window threshold clipping module adopts two-dimensional sliding window in the fast time dimension and the different beam dimension, each dimension adopts a register to buffer the extreme value, realizes the signal flow processing in the time dimension while comparing the signal extreme value in real time to obtain the sum and difference beam Fourier transform floating point data corresponding to the signal extreme value, so as to select the beam where the target is located in the beam dimension, and step five is entered; Step five: after the FIFO is programmed to be full, the AXI IP working clock is edited, the sum and difference beam Fourier transform floating point data in the FIFO and the beam serial number in the register are sent to the ARM through the AXI bus by using the AXI IP core, and are buffered in the DDR mounted by the ARM to realize the real-time refreshing and flow processing of the sum and difference beam Fourier transform floating point data buffered in the DDR, and step six is entered; Step six: the sum and difference beam Fourier transform floating point data buffered in the DDR is read out by the ARM, and the target position is calculated according to the sum and difference beam Fourier transform floating point data. Step six: ARM takes out the data in DDR cache in step five according to the address to calculate the sum-difference beam ratio, and obtains the target angle measured by two linear arrays by looking up the antenna pattern table of the two sets of sum-difference ratio calculation results. The parallel linear array measurement results are converted into two-dimensional measurement results by the proposed angle measurement method, and the azimuth and elevation angles of the target are obtained. Thus, one angle measurement is completed.

2. The method of claim 1, wherein, Step two: multiply each channel data corresponding to the transverse receiving unit after decimation filtering by the weighting factor corresponding to the address 1~M of the transverse receiving unit, to obtain the weighting factor address with the maximum sum beam square value. Cache the weighting factor address as the beam serial number, and obtain a set of corresponding transverse maximum sum-difference beams. Multiply each channel data corresponding to the longitudinal receiving unit after decimation filtering by the weighting factor corresponding to the address 1~N of the longitudinal receiving unit, to obtain the weighting factor address with the maximum sum beam square value. Cache the weighting factor address as the beam serial number, and obtain a set of corresponding longitudinal maximum sum-difference beams. The specific process is as follows: The receiving unit refers to each receiving antenna in the L array antenna. The data received by the receiving antenna is collected by AD after mixing. In the L array antenna, there are 16 receiving antennas in the transverse direction and 16 receiving antennas in the longitudinal direction, a total of 31, with one common in the middle. When the L array is regarded as two linear arrays with 16 receiving antennas respectively, each linear array has 16 channels of data. Different weighting factors are stored in the ROM according to the address. When the 16 channels of signals are multiplied by the weighting factors, the essence is to compensate the phase of the 16 channels of signals, realize the different pointing of the digital beam, and then add all the 16 channels of signals to obtain the sum beam under the pointing of the beam. The left and right 8 channels of signals are summed and then subtracted to obtain the difference beam under the pointing of the beam. According to the maximum range to be searched and the beam width of each linear array, the maximum addressing range of the ROM is calculated, i.e. the maximum number of weighting factors to be stored. When the weighting factors in the ROM are multiplied by the 16 channels of echo signals respectively according to the address increment to obtain the sum-difference beams, the weighting factors in the register are also multiplied by the 16 channels of echo signals to obtain the sum-difference beams at the same time. Then, the sliding window threshold interception module is used for cyclic comparison to obtain the weighting factor corresponding to the larger value of the square value of the sum beam. The two linear arrays are processed at the same time to obtain the IQ two channels of the two sets of sum-difference beams.

3. The method of claim 1, wherein, In step three, the window function sampling points corresponding to the FFT point number are read out from the ROM and multiplied by the two sets of sum-difference beams, respectively, to obtain the sum-difference beam windowing processing data, and the windowing processing is completed to reduce the sidelobe, as follows: a Hamming window corresponding to the FFT point number is used, the coe file is derived from the window function in Matlab, and then the coe file of the window function is imported into the ROM in Vivado, and the window function sequence in the ROM is read out and multiplied by the signal during the windowing processing; the interface of the FFT IP core in Vivado 2019.2 is in AXI format; when performing FFT, the s_axis_data_tready is judged, the s_axis_data_tvalid is set to 1 when the signal is high, indicating that the data on the s_axis_data_tdata data line is valid, and the s_axis_data_tlast value 1 is set when the data is input to the last data; when the FFT IP performs calculation, the m_axis_data_tvaild is set to 1, and the FFT result is obtained, which is output on the m_axis_data_tdata, and the tlast signal is also used as a flag when the output is completed; after the windowing processing, the two sets of sum-difference signals are input to the 4-way FFT for parallel calculation.

4. The method of claim 1, wherein, In step four, the sum-difference beam Fourier transform data is input into the sliding window threshold truncation module, and the sum-difference beam Fourier transform data is processed in the sliding window threshold truncation module to obtain the target address and the beam weighting factor corresponding to the ROM1 and ROM2 in step two; the amplitude upper and lower limits are determined to determine the number of bits of the specified point data, and the result is converted to a floating point value after truncation; after the data is converted to a single-precision floating point number, the sum-difference beam Fourier transform floating point data is cached to the FIFO, realizing the clock domain conversion and data bit width adjustment from the FFT output clock to the AXI transmission clock; the sliding window threshold truncation module uses two-dimensional sliding windows in the fast time dimension and different beam dimensions, each dimension uses a register to cache the extreme value, realizes signal flow processing in the time dimension while comparing the extreme value of the sum-difference beam Fourier transform floating point data in real time, and selects the target beam in the beam dimension, as follows: The first sum and difference beam Fourier transform data processing is firstly cached in RAM, and then the sliding window is compared between beams through two registers to obtain the beam with the maximum square value of the sum beam and the address corresponding to the weighting factor of the beam in step two; the maximum and minimum values of the sum and difference beam are estimated in the fast time dimension through the sliding window comparison of another direction three registers, that is, the upper and lower thresholds of the signal, so as to estimate the fixed-point digit number required to represent the corresponding amplitude, if it is less than the bit number of the first sum and difference beam Fourier transform data, the first sum and difference beam Fourier transform data is intercepted, and the judgment basis for the interception of the second sum and difference beam Fourier transform data of another road is provided; then the second sum and difference beam Fourier transform data is converted into fixed-point floating point; then the converted single-precision floating point number is input into the instantiated double-port independent always FIFO as input, the input clock is 50MHz and the fixed-point floating point conversion rate is the same, the output clock is connected with the Zynq IP output, and the output of the Zynq IP is 115MHz, the function of the FIFO is to realize the cross-clock-domain caching, and after the slow-rate data is cached to a certain number, the transmission is carried out through the AXI data line according to the faster clock.

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