A compressed hypergraph method and device for representing VLSI design
By setting weights, Boolean variables and identifiers for hyperedges and generating vector data structures, the problems of large storage space and low query efficiency of hypergraph representation in VLSI design are solved, and efficient hypergraph compression and query are achieved.
Patent Information
- Application Number
- CN202311212903.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-19
- Publication Date
- 2025-09-30
- Estimated Expiration
- 2043-09-19
AI Technical Summary
In the existing technology, the hypergraph representation method designed by VLSI occupies a large storage space, cannot effectively represent the direction of the hyperedge, and has low query efficiency, resulting in a long time spent on segmentation algorithm parsing and loading the hypergraph.
A compressed hypergraph method is adopted to set initial weights, Boolean variables and identifiers for hyperedges, traverse hyperedges and generate vector data structures including the directions of hyperedges, reduce storage space usage, and convert disk IO pressure into CPU computing pressure.
It effectively reduces storage space usage, improves query efficiency, and reduces disk IO pressure. It is suitable for hypergraph representation of large-scale VLSI designs.
Smart Images
Figure CN117194353B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit chip design, and in particular relates to a compressed hypergraph method and device for representing VLSI design. Background Art
[0002] Field Programmable Gate Arrays (FPGAs) have become a key platform for integrated circuit design and hardware simulation. FPGAs are used for logic verification in chip design. However, with the rapid increase in the scale and complexity of modern SoC designs, VLSI partitioning has become a critical step in IC design. The mathematical model for VLSI partitioning is typically developed from a graph theory perspective, mapping circuit topology relationships into a hypergraph.
[0003] Traditional methods typically represent hypergraphs as incidence matrices, where the rows and columns represent the hypergraph's nodes and hyperedges, respectively, and the matrix elements represent the associations between nodes and hyperedges. This incidence matrix representation consumes a significant amount of storage space, and it is impossible to directly represent the direction of hyperedges in a two-dimensional matrix. Furthermore, hypergraphs are often represented as adjacency lists and edge sets. While adjacency lists can save significant storage space compared to matrices, obtaining the in-degree and out-degree of a node requires traversing a linked list, resulting in low query efficiency. Furthermore, due to the complex interconnections within circuits, the resulting hypergraph structure typically has a significantly larger number of nets than nodes. This results in a less than ideal storage space requirement for representing hypergraphs as edge sets.
[0004] Therefore, when it comes to the hypergraph representation of VLSI design, the generated hypergraph net file usually faces the problem of occupying huge storage space, resulting in a lot of time wasted in subsequent segmentation algorithm parsing and reloading the hypergraph. There is an urgent need for a new method for hypergraph representation of VLSI design. Summary of the Invention
[0005] To address the above-mentioned problems in the related art, the present invention provides a method and apparatus for representing a compressed hypergraph for VLSI design. The technical problem to be solved by the present invention is achieved through the following technical solutions:
[0006] The present invention provides a compressed hypergraph method for representing VLSI design, comprising:
[0007] Obtaining a hypergraph to be compressed; the hypergraph includes multiple hyperedges, multiple driver nodes and load nodes, each hyperedge corresponds to a driver node and at least one load node;
[0008] Number the nodes to obtain unique numbers for each driver node and each load node;
[0009] An initial hyperedge weight, an initial Boolean variable, and an initial hyperedge identifier are set for each hyperedge; the hyperedge weight, the Boolean variable, and the hyperedge identifier of a hyperedge are respectively used to represent the number of hyperedges identical to the hyperedge, whether there is a hyperedge identical to the hyperedge among the traversed hyperedges, and whether a hyperedge having the same driving node as the hyperedge is the same hyperedge as the hyperedge;
[0010] Based on the initial hyperedge weight, the initial Boolean variable, and the initial hyperedge identifier, traversing each hyperedge and the corresponding driver node and load node, and obtaining a final hyperedge weight and a final hyperedge identifier for each different hyperedge after traversing the multiple hyperedges;
[0011] According to the number and number of load nodes of each different hyperedge, as well as the final hyperedge weight and the final hyperedge identifier, multiple different vector data structures are generated; the multiple different vector data structures constitute a hypergraph net file; the hypergraph net file contains the direction of the hyperedge.
[0012] The present invention also provides a compressed hypergraph device for representing a VLSI design, comprising:
[0013] An acquisition module, configured to acquire a hypergraph to be compressed; the hypergraph comprising a plurality of hyperedges, a plurality of driver nodes, and a load node, wherein each hyperedge corresponds to a driver node and at least one load node;
[0014] The numbering module is used to number the nodes and obtain a unique number for each driving node and each load node;
[0015] A setting module is used to set an initial hyperedge weight, an initial Boolean variable, and an initial hyperedge identifier for each hyperedge; the hyperedge weight, the Boolean variable, and the hyperedge identifier of a hyperedge are respectively used to represent the number of hyperedges identical to the hyperedge, whether there is a hyperedge identical to the hyperedge among the traversed hyperedges, and whether a hyperedge having the same driving node as the hyperedge is the same hyperedge as the hyperedge;
[0016] a traversal module, configured to traverse each hyperedge and the corresponding driver node and load node based on the initial hyperedge weight, the initial Boolean variable, and the initial hyperedge identifier, and obtain a final hyperedge weight and a final hyperedge identifier for each different hyperedge after traversing the multiple hyperedges;
[0017] A generation module is used to generate multiple different vector data structures according to the number and number of load nodes of each different hyperedge, as well as the final hyperedge weight and the final hyperedge identifier; the multiple different vector data structures constitute a hypergraph net file; the hypergraph net file contains the direction of the hyperedge.
[0018] The present invention also provides a computer-readable storage medium having a computer program stored therein, wherein the computer program is used to execute the steps in the above-mentioned method for representing a compressed hypergraph of a VLSI design.
[0019] The present invention has the following beneficial technical effects:
[0020] Compared to storing hypergraph incidence matrices in the traditional CSR format, the compression method proposed in the present invention can store the directions of hyperedges without adding additional storage space, thus reducing the space occupied by the hypergraph on the storage device. Furthermore, due to the inherent characteristics of VLSI design, the number of nets in the converted hypergraph is usually much greater than the number of nodes. Compared to the net*node size of the incidence matrix, the method proposed in the present invention can compress matrices of node*node size. Furthermore, when the subsequent segmentation algorithm needs to read the hypergraph file, the hypergraph net file generated by the present invention can convert the disk IO read and write pressure into CPU calculation pressure, thereby reducing the disk IO read and write pressure. The larger the hypergraph net file, the more obvious the advantages of the present invention's method of compressing and storing hypergraphs using multiple different vector data structures. Furthermore, the present invention can also solve the problem that the adjacency matrix cannot effectively distinguish whether a hyperedge with the same node as the out-degree point is a hyperedge containing multiple in-degree points, or several independent hyperedges each containing different in-degree points.
[0021] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] Figure 1 A flow chart of a compressed hypergraph method for representing VLSI designs provided by an embodiment of the present invention;
[0023] Figure 2 A schematic diagram of an exemplary hypergraph to be compressed provided in an embodiment of the present invention;
[0024] Figure 3 A schematic diagram of node numbering in an exemplary hypergraph provided by an embodiment of the present invention;
[0025] Figure 4 A schematic diagram illustrating an exemplary hyperedge according to an embodiment of the present invention;
[0026] Figure 5 Schematic diagram of four different data structures stored after compression provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0027] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.
[0028] In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.
[0029] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.
[0030] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple situations. A single processor or other unit can implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.
[0031] Figure 1 FIG. 1 is a flow chart of a compressed hypergraph method for representing VLSI design provided by an embodiment of the present invention. Figure 1 As shown, the method includes the following steps:
[0032] S101. Obtain a hypergraph to be compressed; the hypergraph includes multiple hyperedges, multiple driver nodes and load nodes, and each hyperedge corresponds to a driver node and at least one load node.
[0033] Specifically, a VLSI design file can be obtained and then read into an RTL parser to perform standardized refinement operations on the design and generate a design file based on netlist units. After generating the design file based on netlist units, the netlist in the file is obtained and traversed to map instances in the VLSI design file to nodes of a hypergraph and the interconnections between instances to hyperedges of the hypergraph, thereby parsing and converting the VLSI design file into a hypergraph. It should be noted that the instance corresponding to the node can be selected based on the actual situation of FPGA resources and user constraints.
[0034] S102: Number the nodes to obtain unique numbers for each driving node and each load node.
[0035] Specifically, the hypergraph includes multiple port nodes and multiple ordinary nodes, and the driving node of each hyperedge or each load node is a port node or an ordinary node; the multiple port nodes can be numbered in sequence starting from 0 to obtain the number of each port node; after the numbering of the multiple port nodes is completed, the multiple ordinary nodes are numbered in sequence in the numbering order of the multiple port nodes to obtain the number of each port node. In this way, the numbering of the driving node and load node of each hyperedge in the hypergraph is realized.
[0036] S103. Set an initial hyperedge weight, an initial Boolean variable, and an initial hyperedge identifier for each hyperedge; the hyperedge weight, Boolean variable, and hyperedge identifier of a hyperedge are respectively used to represent the number of hyperedges identical to the hyperedge, whether there is a hyperedge identical to the hyperedge among the traversed hyperedges, and whether a hyperedge with the same driving node as the hyperedge is the same hyperedge as the hyperedge.
[0037] Specifically, the hyperedge weight of a hyperedge is used to indicate the number of hyperedges identical to the hyperedge; the Boolean variable of a hyperedge is used to indicate whether the traversed hyperedges contain the same hyperedge as the hyperedge; and the hyperedge identifier of a hyperedge is used to indicate whether the hyperedge with the same driver node as the hyperedge is the same hyperedge as the hyperedge. For example, the initial hyperedge weight of each hyperedge is 1, the initial Boolean variable value is false, and the initial hyperedge identifier is 0.
[0038] S104. Based on the initial hyperedge weight, the initial Boolean variable, and the initial hyperedge identifier, traverse each hyperedge and the corresponding driving node and load node, and obtain the final hyperedge weight and final hyperedge identifier of each different hyperedge after traversing multiple hyperedges.
[0039] Here, S104 is implemented by the following steps:
[0040] S1041. When traversing to the current hyperedge, record the number of the driver node of the current hyperedge and the number of the load nodes of the current hyperedge.
[0041] S1042. Determine whether the number of the driving node of the current hyperedge has been traversed. If it has not been traversed, record the number of the load node of the current hyperedge, and keep the hyperedge weight and Boolean variable of the current hyperedge unchanged. According to the value of the maintained Boolean variable, keep the hyperedge identifier of the current hyperedge unchanged to complete the traversal of the current hyperedge.
[0042] Specifically, when the number of the driving node of the current hyperedge has not been traversed, the numbers of the load nodes of the current hyperedge are recorded, the hyperedge weight of the current hyperedge is kept to be 1, and the Boolean variable of the current hyperedge is kept to be false. Since the number of the driving node has not been traversed and the Boolean variable of the current hyperedge is false, the hyperedge flag of the current hyperedge is kept to be 0, and the traversal of the current hyperedge is completed.
[0043] S1043. When traversing, determine whether the load node of the traversed hyperedge that is the same as the driving node of the current hyperedge is the same as the load node of the current hyperedge. If they are not the same, record the number of the load node of the current hyperedge, and keep the hyperedge weight and Boolean variable of the current hyperedge unchanged. According to the value of the maintained Boolean variable, update the hyperedge identifier of the current hyperedge to complete the traversal of the current hyperedge; the updated hyperedge identifier is used to indicate that the current hyperedge and the traversed hyperedge that is the same as the driving node of the current hyperedge belong to different hyperedges.
[0044] Specifically, when the number of the driving node of the current hyperedge has been traversed, and the load node of the traversed hyperedge that is the same as the driving node of the current hyperedge is different from the load node of the current hyperedge, the numbers of the load nodes of the current hyperedge are recorded, the hyperedge weight of the current hyperedge is continued to be maintained, and the Boolean variable of the current hyperedge is continued to be false. Since the number of the driving node of the current hyperedge has been traversed and the Boolean variable of the current hyperedge is false, it can be seen that the hyperedge with the same driving node as the current hyperedge is a different hyperedge from the current hyperedge. Therefore, the hyperedge identifier of the current hyperedge is updated from 0 to 1.
[0045] S1044. When they are the same, update the hyperedge weight and Boolean variable of the traversed hyperedge with the same driving node as the current hyperedge, keep the hyperedge identifier of the traversed hyperedge with the same driving node as the current hyperedge unchanged according to the value of the updated Boolean variable, delete the initial hyperedge weight, initial Boolean variable and initial hyperedge identifier of the current hyperedge, and complete the traversal of the current hyperedge.
[0046] Specifically, when the number of the driving node of the current superedge has been traversed, and the load node of the traversed superedge that is the same as the driving node of the current superedge is the same as the load node of the current superedge, it means that the current superedge and the previously traversed superedge belong to the same superedge. Therefore, the current weight of the previously traversed superedge is increased by one, and the current Boolean variable of the previously traversed superedge is updated to true. Since the current Boolean variable of the previously traversed superedge is true, the superedge identifier of the previously traversed superedge is kept at 0, and the initial superedge weight, initial Boolean variable and initial superedge identifier of the current superedge are all deleted to complete the traversal of the current superedge.
[0047] S1045: Continue traversing the next hyperedge until multiple hyperedges are traversed, and obtain the final hyperedge weight and final hyperedge identifier of each different hyperedge.
[0048] After traversing the current hyperedge, the above principle can be used to continue traversing the next hyperedge until all hyperedges in the hypergraph are traversed, thereby obtaining the final hyperedge weights and final hyperedge identifiers of all different hyperedges in the hypergraph.
[0049] S105. Generate multiple different vector data structures according to the number and number of load nodes of each different hyperedge, as well as the final hyperedge weight and the final hyperedge identifier; the multiple different vector data structures constitute a hypergraph net file; the hypergraph net file includes the direction of the hyperedge.
[0050] Here, the multiple different vector data structures are specifically: a weight data structure for storing the hyperedge weight of the hyperedge to which each load node belongs (hereinafter referred to as value), a numbering data structure for storing the number of the load node of each hyperedge (hereinafter referred to as colPtr), a cumulative data structure for storing the cumulative value of the number of load nodes of the hyperedge to which each different driving node belongs (hereinafter referred to as rowPtr), and an identification data structure for storing the hyperedge identification (hereinafter referred to as loadId).
[0051] Here, the number of values stored in value, colPtr and loadId is the sum of the number of load nodes of all hyperedges in the hypergraph; the number of values stored in rowPtr is the number of different load nodes in the hypergraph plus one, and the value of the first storage position in rowPtr is a preset value, for example, it can be 0.
[0052] In some embodiments, S105 is implemented by the following steps:
[0053] S1051. According to the traversal order of the hyperedges, the numbers of the load nodes of different hyperedges are stored in sequence to obtain colPtr.
[0054] S1052. According to the traversal order of the hyperedge, the number of load nodes driven by driver nodes with different numbers is sequentially added and stored to obtain rowPtr; the load node of a hyperedge is the node driven by the driver node of the hyperedge.
[0055] S1053. According to the traversal order of the hyperedges, the final hyperedge weights of the different hyperedges are stored in sequence to obtain value; the storage location in colPtr used to store the number of each load node of each hyperedge corresponds one-to-one to a storage location in value, and the storage location in value is used to store the final hyperedge weight of the hyperedge.
[0056] S1054. According to the traversal order of the hyperedge, the final hyperedge identifiers of different hyperedges are stored in sequence to obtain loadId; the storage location in colPtr used to store the number of each load node of each hyperedge corresponds one-to-one to a storage location in loadId, and the storage location in loadId is used to store the final hyperedge identifier of the hyperedge.
[0057] Compared to storing hypergraph incidence matrices in the traditional CSR format, the compression method proposed in the present invention can store the directions of hyperedges without adding additional storage space, thus reducing the space occupied by the hypergraph on the storage device. Furthermore, due to the inherent characteristics of VLSI design, the number of nets in the converted hypergraph is usually much greater than the number of nodes. Compared to the net*node size of the incidence matrix, the method proposed in the present invention can compress matrices of node*node size. Furthermore, when the subsequent segmentation algorithm needs to read the hypergraph file, the hypergraph net file generated by the present invention can convert the disk IO read and write pressure into CPU calculation pressure, thereby reducing the disk IO read and write pressure. The larger the hypergraph net file, the more obvious the advantages of the present invention's method of compressing and storing hypergraphs using multiple different vector data structures. Furthermore, the present invention can also solve the problem that the adjacency matrix cannot effectively distinguish whether a hyperedge with the same node as the out-degree point is a hyperedge containing multiple in-degree points, or several independent hyperedges each containing different in-degree points.
[0058] The compression method of the present invention is described below with a specific example. Figure 2 is the hypergraph to be compressed, gp0~gp4 are port nodes, g0~g2 are common nodes, and by numbering gp0~gp4 and g0~g2 starting from 0, the unique numbers corresponding to gp0~gp4 and g0~g2 are obtained. Figure 3 shown. Figure 3 The hypergraph shown contains 8 hyperedges, and, as Figure 4As shown in the figure, these 8 hyperedges are 8 different hyperedges. These 8 hyperedges are traversed in the order of e1→e2→e3→e4→e5→e6→e7→e8. Before traversal, the initial hyperedge weights of these 8 hyperedges are all set to 1, the initial Boolean variables are all set to false, and the initial hyperedge identifiers (loadid) are all set to 0. The traversal process is as follows:
[0059] (1) First traverse the hyperedge e1, according to Figure 4 As shown, the number of the current driving node of e1 is recorded as 0, and the number of the load nodes of e1 is recorded as 1.
[0060] (2) Since the driver node with the number 0 has not been traversed before, the Boolean variable isre of e1 is kept false, the loadid of e1 is kept 0, and Figure 4 As shown, the load node number of e1 is recorded as 5, and the weight of e1 is kept as 1 to indicate that there is currently no hyperedge identical to e1, completing the traversal of e1.
[0061] (3) Then traverse e2, according to Figure 4 As shown, the number of the driving node of record e2 is 0, and the number of the load nodes of record e2 is 2.
[0062] (4) Since the driver node numbered 0 has been traversed before, and since the load nodes of e1 and e2 are different, the isre of e2 is kept false, but the loadid of e2 is incremented by one, that is, the loadid of e2 is updated to 1 to distinguish that although the driver nodes of e2 and e1 are the same, e2 and e1 are actually two different hyperedges, and according to Figure 4 As shown, the load nodes of record e2 are numbered 6 and 7, and the weight of e2 is updated to 1 to indicate that there is currently no hyperedge identical to e2.
[0063] (5) Then, traverse e3 using the same principle until e8 is traversed, and the final weight and loadid of each of the eight different hyperedges are obtained. Based on the final weight and loadid of each of the eight different hyperedges, as well as the number and number of load nodes of each of the eight different hyperedges, the final loadid of each hyperedge is generated. Figure 5 The value, colPtr, rowPtr, and loadId are shown, and the value of the first storage location in rowPtr is set to 0.
[0064] like Figure 5As shown in the figure, since the load nodes driven by the driver node numbered 0 are numbered 5, 6, and 7 respectively, the values stored in the first three storage locations of colPtr are 5, 6, and 7 respectively, and the value of the second storage location of rowPtr is 3, which indicates that the driver node numbered 0 drives 3 load nodes; since the load node of e1 is numbered 5, and Figure 3 There is no hyperedge identical to e1 in the hypergraph shown, so the final hyperedge weight of e1 is 1. Therefore, the value that should be stored in the storage location in value that corresponds to the storage location in colPtr that stores the number of the load node of e1 is 1. That is, the value that should be stored in the first storage location in value is 1. Since the load nodes of e2 are numbered 6 and 7, and Figure 3 There is no hyperedge identical to e2 in the hypergraph shown, so the final hyperedge weight of e2 is also 1. Therefore, the values stored in the two storage locations in value that correspond one-to-one to the storage locations storing the numbers of the load nodes of e2 in colPtr should both be 1, that is, the values stored in the second and third storage locations in value should be 1; since e1 and e2 are two different hyperedges, the only driving nodes of e1 and e2 are both 0. Therefore, the values stored in the two storage locations in loadId that correspond one-to-one to the second and third storage locations in colPtr should both be 1, and the value stored in the storage location in loadId that corresponds one-to-one to the first storage location in colPtr should be 0, to indicate that although e1 and e2 have the same driving nodes, they are two different hyperedges. Combining the values of the first three storage locations of value, the values of the first three storage locations of colPtr, the values of the first and second storage locations of rowPtr, and the values of the first three storage locations of loadId, we can know that the driving node of e1 is 0 and the load node is 5, the driving node of e2 is 0, and the load nodes are 6 and 7, and e1 and e2 are two different hyperedges.
[0065] Next, since the load nodes driven by the driver node numbered 1 are numbered 5 and 7 respectively, the values stored in the fourth and fifth storage locations of colPtr are 5 and 7 respectively, and the value of the third storage location of rowPtr is 5, which indicates that the two driver nodes numbered 0 and 1 drive a total of 5 load nodes; since the load node of e3 is numbered 5, and Figure 3 There is no hyperedge identical to e3 in the hypergraph shown, so the final hyperedge weight of e3 is also 1. Therefore, the value that should be stored in the storage location in value that corresponds to the storage location in colPtr that stores the number of the load node of e3 is 1. That is, the value that should be stored in the fourth storage location in value is 1. Since the load node of e4 is numbered 7, and Figure 3 In the hypergraph shown, there is no hyperedge identical to e4, so e4's final hyperedge weight is also 1. Therefore, the value stored in the storage location in value that corresponds to the storage location in colPtr storing the number of e4's load node should be 1, that is, the value stored in the fifth storage location in value should be 1. Since e3 and e4 are two different hyperedges, both have only the driver node 1. Therefore, the value stored in the storage location in loadId that corresponds to the fourth storage location in colPtr should be 0, and the value stored in the storage location in loadId that corresponds to the fifth storage location in colPtr should be 1, indicating that although e3 and e4 have the same driver node, they are two different hyperedges. Combining the values of the fourth and fifth storage locations in value, colPtr, and loadId, as well as the values of the first three storage locations in rowPtr, we can know that e3's driver node is 1 and its load node is 5, and e4's driver node is 1 and its load node is 7, and that e3 and e4 are two different hyperedges. Combining the values in the first five storage locations of value, colPtr, and loadId, and the values in the first three storage locations of rowPtr, we can know that e1, e2, e3, and e4 are different hyperedges, and we can know the driving node and load node of each of these four hyperedges.
[0066] The values in the remaining storage locations of value, colPtr, rowPtr, and loadId are determined in the same manner as described above, and will not be explained in detail. It should be noted that the above example illustrates the compression process and the resulting hypergraph net file, assuming that the hypergraph to be compressed does not contain identical hyperedges.
[0067] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.
Claims
1. A compressed hypergraph method for representing VLSI designs, characterized in that include: Obtain the hypergraph to be compressed; The hypergraph includes a plurality of hyperedges, a plurality of driver nodes and load nodes, each hyperedge corresponds to a driver node and at least one load node; Number the nodes to obtain unique numbers for each driver node and each load node; An initial hyperedge weight, an initial Boolean variable, and an initial hyperedge identifier are set for each hyperedge; the hyperedge weight, the Boolean variable, and the hyperedge identifier of a hyperedge are respectively used to represent the number of hyperedges identical to the hyperedge, whether there is a hyperedge identical to the hyperedge among the traversed hyperedges, and whether a hyperedge having the same driving node as the hyperedge is the same hyperedge as the hyperedge; Based on the initial hyperedge weight, the initial Boolean variable, and the initial hyperedge identifier, traversing each hyperedge and the corresponding driver node and load node, and obtaining a final hyperedge weight and a final hyperedge identifier for each different hyperedge after traversing the multiple hyperedges; According to the number and number of load nodes of each different hyperedge, as well as the final hyperedge weight and the final hyperedge identifier, multiple different vector data structures are generated; the multiple different vector data structures constitute a hypergraph net file; the hypergraph net file contains the direction of the hyperedge.
2. The compressed hypergraph method for representing VLSI design according to claim 1, wherein: The plurality of different vector data structures include: A weight data structure for storing the hyperedge weight of each hyperedge to which each load node belongs, a numbering data structure for storing the number of the load node of each hyperedge, a cumulative data structure for storing the cumulative value of the number of load nodes of the hyperedge to which each different driver node belongs, and an identification data structure for storing the hyperedge identification; The number of values stored in the weight data structure, the numbering data structure and the identification data structure is the sum of the number of load nodes of all hyperedges in the hypergraph; the number of values stored in the accumulation data structure is the number of different load nodes in the hypergraph plus one.
3. The compressed hypergraph method for representing VLSI design according to claim 1, wherein: The method of traversing each hyperedge and the corresponding driver node and load node based on the initial hyperedge weight, the initial Boolean variable, and the initial hyperedge identifier, and obtaining a final hyperedge weight and a final hyperedge identifier of each different hyperedge after traversing the multiple hyperedges, includes: When traversing to the current hyperedge, record the number of the driver node of the current hyperedge and the number of the load nodes of the current hyperedge; Determine whether the number of the driver node of the current hyperedge has been traversed, and if not, record the number of the load node of the current hyperedge, keep the hyperedge weight and Boolean variable of the current hyperedge unchanged, and keep the hyperedge identifier of the current hyperedge unchanged according to the value of the maintained Boolean variable, thereby completing the traversal of the current hyperedge; When traversing, determine whether the load node of the traversed hyperedge that is the same as the driving node of the current hyperedge is the same as the load node of the current hyperedge, and if they are not the same, record the number of the load node of the current hyperedge, and keep the hyperedge weight and Boolean variable of the current hyperedge unchanged, and update the hyperedge identifier of the current hyperedge according to the value of the maintained Boolean variable to complete the traversal of the current hyperedge; the updated hyperedge identifier is used to indicate that the current hyperedge and the traversed hyperedge that is the same as the driving node of the current hyperedge belong to different hyperedges; When they are the same, updating the hyperedge weight and Boolean variable of the traversed hyperedge with the same driving node as the current hyperedge, keeping the hyperedge identifier of the traversed hyperedge with the same driving node as the current hyperedge unchanged according to the value of the updated Boolean variable, deleting the initial hyperedge weight, the initial Boolean variable, and the initial hyperedge identifier of the current hyperedge, and completing the traversal of the current hyperedge; Continue traversing the next hyperedge until all the hyperedges are traversed, and obtain the final hyperedge weight and final hyperedge identifier of each different hyperedge.
4. The compressed hypergraph method for representing VLSI design according to claim 3, wherein: When the hyperedge has not been traversed, the number of the load node of the current hyperedge is recorded, the hyperedge weight and the Boolean variable of the current hyperedge are kept unchanged, and the hyperedge identifier of the current hyperedge is kept unchanged according to the value of the Boolean variable after the maintenance, including: When it has not been traversed, record the number of the load node of the current hyperedge, keep the hyperedge weight of the current hyperedge as the initial hyperedge weight, keep the Boolean variable of the current hyperedge as the initial Boolean variable, and keep the initial hyperedge identifier of the current hyperedge unchanged according to the initial Boolean variable of the current hyperedge.
5. The compressed hypergraph method for representing VLSI design according to claim 3, wherein: The initial Boolean variable of each hyperedge is false; when the values are the same, updating the hyperedge weight and Boolean variable of the traversed hyperedge with the same driving node as the current hyperedge, and keeping the hyperedge identifier of the traversed hyperedge with the same driving node as the current hyperedge unchanged according to the value of the updated Boolean variable, including: When they are the same, the current hyperedge weight of the traversed hyperedge with the same driving node as the current hyperedge is increased by one, and the current Boolean variable of the traversed hyperedge with the same driving node as the current hyperedge is updated to true. Based on true, the hyperedge identifier of the traversed hyperedge with the same driving node as the current hyperedge is kept unchanged.
6. The compressed hypergraph method for representing VLSI design according to claim 1 or 2, characterized in that: The multiple different vector data structures include: a weight data structure, a number data structure, an accumulation data structure, and an identification data structure; the multiple different vector data structures are generated according to the number and number of load nodes of each different hyperedge, as well as the final hyperedge weight and the final hyperedge identification, including: According to the traversal order of the hyperedges, the numbers of the load nodes of different hyperedges are stored in sequence to obtain the numbering data structure; According to the traversal order of the hyperedge, the number of load nodes driven by driver nodes with different numbers is sequentially added and stored to obtain the cumulative data structure; the load node of a hyperedge is the node driven by the driver node of the hyperedge; According to the traversal order of the hyperedges, the final hyperedge weights of the different hyperedges are sequentially stored to obtain the weight data structure; a storage location in the numbering data structure for storing the number of each load node of each hyperedge corresponds one-to-one to a storage location in the weight data structure, and the storage location in the weight data structure is used to store the final hyperedge weight of the hyperedge; According to the traversal order of the hyperedge, the final hyperedge identifiers of each different hyperedge are stored in sequence to obtain the identification data structure; the storage position in the numbering data structure used to store the number of each load node of each hyperedge corresponds one-to-one to a storage position in the identification data structure, and the storage position in the identification data structure is used to store the final hyperedge identifier of the hyperedge.
7. The compressed hypergraph method for representing VLSI design according to claim 1, wherein: The hypergraph includes a plurality of port nodes and a plurality of common nodes, and the driving node of each hyperedge or each load node is a port node or a common node; The node numbering is to obtain a unique number for each driving node and each load node, including: Numbering the multiple port nodes in sequence starting from 0 to obtain a number for each port node; After the numbering of the plurality of port nodes is completed, the plurality of common nodes are sequentially numbered in the order of the numbering of the plurality of port nodes to obtain a number for each port node.
8. The compressed hypergraph method for representing VLSI design according to claim 1, wherein: The step of obtaining a hypergraph to be compressed includes: Get VLSI design files; Parsing the VLSI design file using an RTL parser to obtain a design file based on a netlist unit; The design file based on the netlist unit is converted into a hypergraph to obtain the hypergraph to be compressed.
9. A compressed hypergraph apparatus for representing a VLSI design, characterized in that: include: An acquisition module, used to obtain the hypergraph to be compressed; The hypergraph includes a plurality of hyperedges, a plurality of driver nodes and load nodes, each hyperedge corresponds to a driver node and at least one load node; The numbering module is used to number the nodes and obtain a unique number for each driving node and each load node; A setting module is used to set an initial hyperedge weight, an initial Boolean variable, and an initial hyperedge identifier for each hyperedge; the hyperedge weight, the Boolean variable, and the hyperedge identifier of a hyperedge are respectively used to represent the number of hyperedges identical to the hyperedge, whether there is a hyperedge identical to the hyperedge among the traversed hyperedges, and whether a hyperedge having the same driving node as the hyperedge is the same hyperedge as the hyperedge; a traversal module, configured to traverse each hyperedge and the corresponding driver node and load node based on the initial hyperedge weight, the initial Boolean variable, and the initial hyperedge identifier, and obtain a final hyperedge weight and a final hyperedge identifier for each different hyperedge after traversing the multiple hyperedges; A generation module is used to generate multiple different vector data structures according to the number and number of load nodes of each different hyperedge, as well as the final hyperedge weight and the final hyperedge identifier; the multiple different vector data structures constitute a hypergraph net file; the hypergraph net file contains the direction of the hyperedge.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is used to execute the steps in any one of the methods of claims 1 to 8.