Silicon wafer impurity removal method, silicon wafer, preparation method and application thereof

Abstract

The present invention relates to a silicon wafer impurity removal method, a silicon wafer, and a preparation method and application thereof. The silicon wafer impurity removal method comprises the following steps: providing a bare silicon wafer, the bare silicon wafer having opposite front and back sides, both of which contain a mechanical damage layer; performing a texturing treatment on the front side of the bare silicon wafer to form a textured surface with a reflectivity of 7% to 15%, thereby preparing a silicon wafer intermediate; performing a diffusion treatment on the silicon wafer intermediate, wherein the front side of the silicon wafer intermediate is doped with phosphorus or boron and coated with silicon dioxide, and impurities in the silicon wafer intermediate migrate and gather toward the mechanical damage layer on the back side, forming an external gettering region coated with silicon dioxide; and removing the silicon dioxide coating layer on the surface of the external gettering region and the external gettering region. This method has the advantages of high gettering efficiency, mild conditions, simple operation, and low cost. Using the impurity-removed silicon wafer in a device can increase light absorption, improve short-circuit current, open-circuit voltage, fill factor, and cell photoelectric conversion efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic devices, and in particular to a silicon wafer impurity removal method, a silicon wafer, and a preparation method and application thereof. Background Art

[0002] Photovoltaic power generation is a technology that uses the photovoltaic effect at semiconductor interfaces to directly convert light energy into electrical energy. The key to this technology is the solar cell. Specifically, sunlight strikes the pn junction of a semiconductor, forming new hole-electron pairs. Under the influence of the built-in electric field within the pn junction, holes flow from the N region to the P region, and electrons flow from the P region to the N region. Once the circuit is connected, an electric current is generated. The most basic component of photovoltaic power generation is the solar cell (chip), which includes single-crystal silicon, polycrystalline silicon, amorphous silicon, and thin-film cells. Of these, single-crystal silicon and polycrystalline silicon cells are the most widely used.

[0003] Silicon wafers, the base material for solar cells, contain micro-defects and metallic impurities. These defects and impurities introduce multiple deep energy levels within the silicon band gap, becoming recombination centers for minority carriers and severely impacting the solar cell's photoelectric conversion efficiency. In single-crystal silicon, due to interactions between impurities and defects, heavy metal impurities or micro-defects migrate and recondense at certain temperatures. This phenomenon is exploited by introducing mechanical damage, defects, or depositing a thin film on the backside of the silicon wafer to remove impurities (known as external gettering). Alternatively, defects are introduced within the wafer to concentrate heavy metal impurities from the device's active region to specific areas (known as internal gettering). Traditional gettering methods suffer from low efficiency, high energy consumption, cumbersome operations, and high costs. Summary of the Invention

[0004] Based on this, it is necessary to provide a silicon wafer impurity removal method with high impurity removal efficiency, mild conditions, simple operation and low cost, and further obtain silicon wafers and apply them to photovoltaic devices.

[0005] The technical solution is as follows:

[0006] One aspect of the present invention provides a method for removing impurities from a silicon wafer, comprising the following steps:

[0007] Providing a bare silicon wafer, wherein the bare silicon wafer has a front side and a back side opposite to each other, and both sides include a mechanical damage layer;

[0008] Performing texturing on the front surface of the bare silicon wafer to form a textured surface with a reflectivity of 7% to 15%, thereby preparing a silicon wafer intermediate;

[0009] Diffusion treatment is performed on the silicon wafer intermediate, whereby the front side of the silicon wafer intermediate is doped with phosphorus or boron and coated with silicon dioxide, and impurities in the silicon wafer intermediate migrate and accumulate in the mechanical damage layer on the back side, forming an external gettering region which is coated with silicon dioxide;

[0010] The silicon dioxide coating layer on the surface of the external gettering region and the external gettering region are removed.

[0011] In some embodiments, the preparation of the silicon wafer intermediate comprises the following steps:

[0012] forming a first mask layer on the back side of the bare silicon wafer to prepare a first intermediate;

[0013] The first intermediate is subjected to texturing treatment to form a textured surface with a reflectivity of 7% to 15% on the front side of the first intermediate, thereby preparing the silicon wafer intermediate.

[0014] In some embodiments, the material of the first mask layer is silicon dioxide.

[0015] In some embodiments, the preparation of the silicon wafer intermediate comprises the following steps:

[0016] The texturing treatment is a wet texturing method, the solution used is alkali, and the temperature is 50°C to 85°C.

[0017] In some embodiments, before the step of performing diffusion treatment on the silicon wafer intermediate, the step of removing the first mask layer by acid etching is also included.

[0018] In some embodiments, the process parameters of the diffusion treatment include:

[0019] The temperature is 800° C. to 1200° C., the oxygen source ratio is 2 to 5, the time is 2.5 h to 4 h, and the furnace tube pressure is 50 mbar to 1160 mbar.

[0020] In some embodiments, the reflectivity of the silicon wafer surface obtained after removing the external gettering region is 20% to 50%.

[0021] In some embodiments, the method for removing the external gettering region is chemical polishing.

[0022] In some embodiments, the chemical polishing is selected from at least one of acid cleaning and alkaline cleaning;

[0023] The acid in the pickling is hydrofluoric acid (HF) or a mixed acid of nitric acid (HNO3) and hydrofluoric acid;

[0024] The alkali in the alkali washing is selected from one of potassium hydroxide (KOH) and sodium hydroxide (NaOH) or a mixture of the two.

[0025] In some embodiments, the method for removing the silicon dioxide coating layer on the surface of the external gettering region is HF pickling.

[0026] In some embodiments, the method for removing the silicon dioxide coating layer on the surface of the external gettering region is physical polishing.

[0027] In some embodiments, the method for removing the silicon dioxide coating layer on the surface of the external gettering region is magnetic polishing.

[0028] In some embodiments, before the step of texturing the front surface of the bare silicon wafer, the method further includes the step of cleaning the bare silicon wafer.

[0029] A second aspect of the present invention provides a method for preparing a silicon wafer, comprising the following steps:

[0030] removing impurities from the bare silicon wafer using the silicon wafer impurity removal method as described above to prepare a silicon wafer preform;

[0031] The silicon wafer preform is subjected to at least one of deposition of an anti-reflection passivation film, screen printing, and light injection annealing.

[0032] A third aspect of the present invention provides a silicon wafer, which is produced according to the method for producing a silicon wafer as described above.

[0033] A fourth aspect of the present invention provides a photovoltaic device comprising the silicon wafer as described above.

[0034] According to a fifth aspect of the present invention, a photovoltaic assembly is provided, which includes the photovoltaic device described above.

[0035] The present invention has at least the following beneficial effects:

[0036] The silicon wafer impurity removal method provided by the present invention mainly includes: performing texturing treatment on one surface (front side) of a bare silicon wafer to form a textured surface with a reflectivity of 7% to 15%, and not performing texturing treatment on the back side, retaining a mechanical damage layer, to prepare a single-sided texturing silicon wafer intermediate; performing phosphorus diffusion treatment on the silicon wafer intermediate, wherein phosphorus source doping is used as an internal impurity condition, and the mechanical damage layer on the back side is used as an external impurity condition. During the diffusion process, the front side is doped with dopants, and impurities migrate and gather toward the mechanical damage layer on the back side to form an external impurity gettering area and be coated with silicon dioxide; and combining the steps of removing the silicon dioxide coating layer on the surface of the external impurity gettering area and the external impurity gettering area, the purpose of removing impurities from the silicon wafer is achieved.

[0037] Clearly, the silicon wafer de-doping method of the present invention enables simultaneous gettering during the PN junction fabrication process. Furthermore, the method utilizes single-sided texturing, preserving greater silicon thickness than the currently commonly used trench-type double-sided texturing method. Using the de-doped silicon wafer in a device can increase light absorption, improve short-circuit current (Isc), open-circuit voltage, and fill factor, ultimately enhancing the device's photoelectric conversion efficiency. Furthermore, the method offers the advantages of simple processing, mild conditions, and low chemical costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a flow chart of a silicon wafer impurity removal method according to one embodiment of the present invention;

[0039] Figure 2 A flow chart of a silicon wafer impurity removal method and a schematic diagram of a silicon wafer structure according to an embodiment of the present invention; Figure 2 In the figure, 1 represents a bare silicon wafer, 2 represents a mechanically damaged layer, 2-1 represents a textured surface obtained by texturing after the damaged layer is removed, 3 represents an oxide layer mask, and 4 represents a diffusion layer and an oxide layer. DETAILED DESCRIPTION

[0040] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] Where “including,” “having,” and “comprising” are used herein, it is intended to cover a non-exclusive inclusion, and another component may also be added unless a clear limiting term such as “only,” “consisting of,” etc. is used.

[0043] In the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include at least one of such features.

[0044] The words "preferably", "more preferably", "preferably", "better" and the like in the present invention refer to embodiments of the present invention that may provide certain beneficial effects in certain circumstances. However, other embodiments may also be preferred under the same circumstances or other circumstances. In addition, the statement of one or more preferred embodiments does not imply that other embodiments are not available, nor is it intended to exclude other embodiments from the scope of the present invention. That is, in the present invention, "preferably", "more preferably", "preferably", "better" and the like are merely descriptions of implementation methods or examples with better effects, but do not constitute limitations on the scope of protection of the present invention. In the present invention, "further", "further", "particularly" and the like are used for descriptive purposes to indicate differences in content, but should not be understood as limitations on the scope of protection of the present invention.

[0045] In the present invention, "at least one" means more than one, such as one, two, or more than two. "Multiple" or "several" means at least two, such as two, three, etc., and "multi-layer" means at least two layers, such as two, three, etc., unless otherwise specifically defined. In the description of the present invention, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

[0046] When a numerical range is disclosed in the present invention, the above range is considered to be continuous and includes the minimum and maximum values ​​of the range, as well as every value between such minimum and maximum values. Further, when a range refers to an integer, every integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be combined. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all subranges included therein. And only some numerical ranges are specifically disclosed herein. However, any lower limit can be combined with any upper limit to form an unspecified range; and any lower limit can be combined with other lower limits to form an unspecified range, and similarly, any upper limit can be combined with any other upper limit to form an unspecified range. In addition, each separately disclosed point or single value itself can be combined as a lower limit or upper limit with any other point or single value or with other lower limits or upper limits to form an unspecified range.

[0047] Unless otherwise specified, all steps of the present invention may be performed sequentially or randomly. For example, the method includes steps (a) and (b), which means that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, the method may further include step (c), which means that step (c) may be added to the method in any order, for example, the method may include steps (a), (b), and (c), or may include steps (a), (c), and (b), or may include steps (c), (a), and (b), etc.

[0048] Unless mentioned otherwise, terms in the singular may include plural forms and should not be construed as having one number.

[0049] The temperature parameters in the present invention, unless otherwise specified, allow for either constant temperature treatment or treatment within a certain temperature range. The constant temperature treatment allows for temperature fluctuations within the precision range controlled by the instrument.

[0050] The weights of the relevant components mentioned in the examples of the present invention may not only refer to the specific content of each component, but also represent the weight ratios between the components. Therefore, as long as the content of the relevant components is proportionally increased or decreased according to the examples of the present invention, it is within the scope disclosed in the examples of the present invention. Specifically, the weights described in the examples of the present invention may be mass units known in the chemical industry, such as μg, mg, g, and kg.

[0051] In the present invention, when referring to a data range, if the unit is only after the right endpoint, it means that the units of the left and right endpoints are the same. For example, 800-850nm means that the units of the left endpoint "800" and the right endpoint "850" are both nm (nanometers).

[0052] In the present invention, “above” or “below” both include the number itself, for example, “below 1” means less than or equal to 1 (≤1), and “above 1” means greater than or equal to 1 (≥1).

[0053] In the present invention, room temperature refers to 10°C to 40°C, preferably 20°C to 30°C, and more preferably 25±2°C.

[0054] The vapor deposition method described in the present invention is preferably plasma enhanced chemical vapor deposition (PECVD).

[0055] In addition, the drawings are not drawn in a 1:1 scale, and the relative sizes of the elements are drawn in the drawings only as examples to facilitate understanding of the present invention, but are not necessarily drawn in true proportion. The proportions in the drawings do not constitute a limitation to the present invention.

[0056] Gettering technology is a highly effective method for reducing contamination during silicon wafer processing and device manufacturing, while improving device performance. By exploiting the tendency of impurities to accumulate in areas with imperfect lattices, they introduce defects, forming impurity-rich regions. This impurity-rich damaged region is then removed, partially removing impurities from the silicon wafer. This reduces the number of minority carrier recombination centers within the wafer, increases the short-circuit current of the cell, and thus improves the photovoltaic conversion efficiency of solar cells. To reduce wafer costs and maximize silicon ingot utilization, gettering is performed on low-quality wafers after reverse-cutting, reducing wafer costs while simultaneously improving cell efficiency.

[0057] A phosphorus diffusion process for internal gettering of silicon wafers has been reported. This involves placing cleaned and textured silicon wafers into a diffusion furnace, where nitrogen, oxygen, and phosphorus oxychloride are introduced for high-temperature diffusion. The diffusion process is divided into three deposition steps, each followed by a period of advancement, followed by cooling to room temperature. This approach can improve the average conversion efficiency of the cell. Alternatively, a phosphorus diffusion gettering process for silicon wafers used in solar cell manufacturing involves coating a phosphorus source onto the wafer surface or using a carrier gas to carry POCl3 into the diffusion furnace tube. Under a protective atmosphere, the wafer is heated at 800°C to 1050°C for 10 minutes, then heated at 500°C to 800°C for 20 minutes to 60 minutes. After cooling, the phosphorus-silicate glass layer is removed. This approach utilizes a variable temperature gettering method, combining the advantages of high-temperature dissolution and release of impurities with lower-temperature capture by the gettering layer. This approach can effectively reduce the content of metallic impurities in the silicon substrate and improve the light conversion efficiency of solar cells. However, the above schemes all use a diffusion process or a coating process to diffuse and getter the phosphorus source, and the phosphorus diffusion is carried out under high temperature conditions and the main method is internal gettering, which results in a long preparation process time and high cost.

[0058] Based on this, the present invention provides a silicon wafer impurity removal method with high impurity gettering efficiency, mild conditions, simple operation and low cost.

[0059] The technical solution is as follows:

[0060] See also Figure 1 The silicon wafer impurity removal method shown in one embodiment of the present invention includes the following steps:

[0061] Providing a bare silicon wafer, wherein the bare silicon wafer has a front side and a back side opposite to each other, and both sides include a mechanical damage layer;

[0062] Performing texturing on the front surface of the bare silicon wafer to form a textured surface with a reflectivity of 7% to 15%, thereby preparing a silicon wafer intermediate;

[0063] Diffusion treatment is performed on the silicon wafer intermediate, whereby the front side of the silicon wafer intermediate is doped with phosphorus or boron and coated with silicon dioxide, and impurities in the silicon wafer intermediate migrate and accumulate in the mechanical damage layer on the back side, forming an external gettering region which is coated with silicon dioxide;

[0064] The silicon dioxide coating layer on the surface of the external gettering region and the external gettering region are removed.

[0065] One surface (front side) of a bare silicon wafer is textured to form a textured surface with a reflectivity of 7% to 15%. The back side is not textured, and the mechanical damage layer is retained to prepare a single-sided textured silicon wafer intermediate. The silicon wafer intermediate is diffused, wherein an impurity source is doped with the silicon body to form a PN junction, and the mechanical damage layer on the back side serves as an external doping condition. During the diffusion process, the front side is doped with dopants, and impurities migrate and aggregate toward the mechanical damage layer on the back side to form an external doping area and be coated with silicon dioxide. Combined with the steps of removing the silicon dioxide coating layer on the surface of the external doping area and the external doping area, the purpose of removing impurities from the silicon wafer is achieved.

[0066] As can be seen, the silicon wafer de-doping method of the present invention can simultaneously perform gettering during the PN junction fabrication process. Furthermore, this method utilizes single-sided texturing, which preserves greater silicon thickness than the currently commonly used trench-type double-sided texturing method. Using the de-doped silicon wafer in devices can increase light absorption, improve short-circuit current (Isc), open-circuit voltage, and fill factor, ultimately enhancing the device's photoelectric conversion efficiency. Furthermore, this method offers the advantages of simple process, mild conditions, and low chemical costs.

[0067] The silicon wafer impurity removal method of the present invention will be further described below.

[0068] S100: providing a bare silicon wafer, wherein the bare silicon wafer has a front side and a back side opposite to each other, and both sides include a mechanical damage layer.

[0069] As the core component of solar cells, silicon wafers' quality directly impacts their overall performance. During production and processing, numerous processing defects are inevitably introduced. For example, silicon wafers may exhibit tool defects, chipped edges and notches, cracks / fissures, scratches, collapsed edges, bright spots and localized light scatterers, ripples and unevenness, orange peel, pits and hillocks, polishing mist, residual mechanical damage, and surface contamination. Preferably, in the present invention, the bare silicon wafer has opposing front and back sides, both of which contain a mechanical damage layer.

[0070] S200: performing texturing treatment on the front surface of the bare silicon wafer to form a textured surface with a reflectivity of 7% to 15%, thereby preparing a silicon wafer intermediate.

[0071] The present invention removes oil stains and metal impurities on the surface (front) of the silicon wafer through texturing treatment, reduces the mechanical damage layer on the surface of the silicon wafer, forms a pyramid structure on the front, and obtains a textured surface with a reflectivity of 7% to 15%. The textured surface is subsequently diffused to increase the silicon wafer's absorption of sunlight, reduce the reflectivity of light, increase the short-circuit current (Isc), and ultimately improve the photoelectric conversion efficiency of the device.

[0072] In some embodiments, the texturing treatment is wet texturing. Wet texturing is mainly an alkali etching method: it mainly uses alkali (such as sodium hydroxide solution) to etch the silicon wafer at a certain temperature.

[0073] In some embodiments, the texturing treatment on the front surface of the bare silicon wafer comprises the following steps:

[0074] The bare silicon wafer is mixed with alkaline solution and the texturing treatment is performed at 50° C. to 85° C.

[0075] In some embodiments, the alkali in the alkali solution is selected from one or a mixture of sodium hydroxide and potassium hydroxide, and the mixing ratio is not limited.

[0076] It can be understood that in the present invention, the reflectivity of the textured surface of the silicon wafer intermediate after texturing treatment is 7% to 15%, including but not limited to 7%, 8%, 9%, 10%, 11%, 12%, 13%, 14% or 15%.

[0077] Furthermore, in order to perform texturing on the front side of the bare silicon wafer while not performing texturing on the back side, S200 preferably includes the following steps S201, S202 and S203:

[0078] S201 forms a first mask layer on the back side of the bare silicon wafer to prepare a first intermediate;

[0079] S202 performs texturing treatment on the first intermediate to form a textured surface with a reflectivity of 7% to 15% on the front surface of the first intermediate, thereby preparing the silicon wafer intermediate;

[0080] S203: removing the first mask layer.

[0081] By masking the back of the bare silicon wafer, a mask layer is formed on its back to cover the mechanical damage layer, so that the mechanical damage is retained and used as a condition for external impurities in the future; then the front side without masking will form a textured surface with a reflectivity of 7% to 15%, and a silicon wafer intermediate with single-sided texture and single-sided retained mechanical damage layer is obtained.

[0082] In some embodiments, the material of the first mask layer is silicon dioxide.

[0083] Before the step of texturing the front surface of the bare silicon wafer, the method further includes the step of cleaning the bare silicon wafer. Optionally, the cleaning step is at least one of hydrogen peroxide cleaning and ozone cleaning.

[0084] In some embodiments, S201 forms a first mask layer on the back side of the bare silicon wafer, and preparing the first intermediate includes the following steps:

[0085] The bare silicon wafer is cleaned (e.g., with hydrogen peroxide or ozone) to remove surface oil and impurities. At the same time, a layer of silicon oxide is grown on both the front and back sides of the silicon wafer using hydrogen peroxide (or ozone). The silicon oxide on the back side serves as the first mask layer for subsequent deposition.

[0086] The silicon dioxide on the front and sides of the bare silicon wafer is removed to prepare a first intermediate. Preferably, the bare silicon wafer coated with silicon dioxide is passed through a chain machine, the surface of the bare silicon wafer is covered with a water film for protection, and the oxide layer on the front and sides is removed by HF.

[0087] In some embodiments, S202 performing texturing on the first intermediate comprises the following steps:

[0088] The first intermediate is mixed with alkali solution, and the texturing treatment is performed at 50° C. to 85° C.

[0089] In some embodiments, S203 removing the first mask layer includes the following steps:

[0090] The first intermediate is mixed with an acid solution, and the first mask layer is removed by etching.

[0091] S300: Diffusion treatment is performed on the silicon wafer intermediate. The front side of the silicon wafer intermediate is doped with phosphorus or boron and coated with silicon dioxide. Impurities in the silicon wafer intermediate migrate and gather toward the mechanical damage layer on the back side to form an external doping region coated with silicon dioxide.

[0092] An impurity doping layer is formed on the front of the silicon wafer to form a PN junction. The back side contains a mechanical damage layer. Impurities migrate and accumulate in the mechanical damage layer on the back side to form an external impurity absorption zone. In addition, a silicon dioxide coating layer will be formed on the surface of the silicon wafer during the phosphorus doping process. The silicon dioxide coating layer on the back side needs to be removed later.

[0093] In some embodiments, the process parameters of the diffusion treatment include:

[0094] The temperature is 800°C to 1200°C, the oxygen source ratio is 2 to 5, the time is 2.5 hours to 4 hours, and the furnace tube pressure is 50 mbar to 1160 mbar. The oxygen source ratio refers to the gas flow ratio of oxygen and diffusion source.

[0095] S400: removing the silicon dioxide coating layer on the surface of the external gettering region and the external gettering region.

[0096] S401: removing the silicon dioxide coating layer on the surface of the external gettering region.

[0097] In some embodiments, the method for removing the silicon dioxide coating layer on the surface of the external gettering region is HF pickling.

[0098] In some embodiments, the method for removing the silicon dioxide coating layer on the surface of the external gettering region is physical polishing.

[0099] In some embodiments, the method for removing the silicon dioxide coating layer on the surface of the external gettering region is magnetic polishing.

[0100] S402: removing the external gettering region.

[0101] In some embodiments, the method for removing the external gettering region is chemical polishing.

[0102] In some embodiments, the chemical polishing is selected from at least one of acid cleaning and alkaline cleaning;

[0103] The acid used in the pickling is hydrofluoric acid or a mixture of nitric acid and hydrofluoric acid;

[0104] The alkali in the alkali washing is selected from one of KOH and NaOH or a mixture of the two.

[0105] In some embodiments, the reflectivity of the silicon wafer surface obtained after removing the external impurity region is 20% to 50%, including but not limited to 20%, 22%, 25%, 30%, 32%, 35%, 40%, 42%, 45% or 50%.

[0106] In summary, the present invention retains the mechanical damage caused by diamond wire cutting on the back side during texturing, and only performs texturing on the front side; in the subsequent diffusion process, the phenomenon of high-temperature impurities migrating to the damaged layer and re-condensing is used to make the impurities accumulate on the back surface, and then the impurity area rich in the damaged layer is removed through the normal cleaning process, which has the advantages of high impurity absorption efficiency, mild conditions, simple operation, and low cost.

[0107] Figure 2 A flow chart of a silicon wafer impurity removal method and a schematic diagram of a silicon wafer structure according to an embodiment of the present invention; Figure 2 In the figure, 1 represents a bare silicon wafer, 2 represents a mechanically damaged layer, 2-1 represents a textured surface obtained by texturing after the damaged layer is removed, 3 represents an oxide layer mask, and 4 represents a diffusion layer and an oxide layer.

[0108] The present invention also provides a method for preparing a silicon wafer, comprising the following steps:

[0109] The bare silicon wafer is de-impurified by the silicon wafer de-impurification method as described above to prepare a silicon wafer preform;

[0110] The silicon wafer preform is subjected to at least one of deposition of an anti-reflection passivation film, screen printing, and light injection annealing.

[0111] The present invention also provides a silicon wafer, which is prepared according to the above-mentioned method for preparing the silicon wafer.

[0112] The present invention also provides a photovoltaic device, which includes the silicon wafer as described above.

[0113] The present invention also provides a photovoltaic assembly, which includes the photovoltaic device described above.

[0114] In order to make the purpose, technical solutions and advantages of the present invention more concise and clear, the present invention is illustrated by the following specific embodiments, but the present invention is by no means limited to these embodiments. The embodiments described below are only preferred embodiments of the present invention and can be used to describe the present invention. They should not be understood as limiting the scope of the present invention. It should be pointed out that any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0115] The following are specific embodiments:

[0116] Example 1

[0117] This embodiment provides a polycrystalline silicon photovoltaic device and a method for manufacturing the same, as follows:

[0118] (1) The bare silicon wafer is first cleaned with high-concentration hydrogen peroxide to remove oil and impurities on the surface. At the same time, the high-concentration hydrogen peroxide reacts to grow a layer of silicon oxide on the surface of the silicon wafer, which serves as a mask for the subsequent process.

[0119] (2) The silicon wafer passes through a chain machine, the surface of the silicon wafer is covered with a water film for protection, and the oxide layer on the bottom and sides is removed by HF;

[0120] (3) The silicon wafer with a single-sided oxide layer is textured in a tank machine, and a textured surface with a reflectivity of 10% is prepared at about 80°C, which serves as the front side of the battery. The side with the oxide layer is removed in a subsequent HF tank. This step ultimately results in a textured front side and a back side with a mechanical damage layer that has not been textured.

[0121] (4) The silicon wafer enters the furnace tube for diffusion normally. During the high-temperature diffusion process, dopants are diffused on the front side. Due to the mechanical damage layer on the back side, impurities in the silicon body migrate and accumulate on this side. At the same time, an oxide layer is prepared on the outermost layer of both sides as a subsequent mask.

[0122] (5) The battery is placed with the front side facing up and the back side facing down, and the oxide layer on the back side is removed by a chain machine. In the subsequent tank cleaning, the side where impurities are accumulated is removed, and the surface is prepared to a surface morphology with a reflectivity of 35% for subsequent battery preparation.

[0123] Example 2

[0124] This embodiment provides a polycrystalline silicon photovoltaic device and a method for manufacturing the same, as follows:

[0125] (1) The bare silicon wafer is first cleaned with high-concentration ozone to remove oil and impurities on the surface. At the same time, the high-concentration ozone reacts to grow a layer of silicon oxide on the surface of the silicon wafer, which serves as a mask for the subsequent process.

[0126] (2) The silicon wafer passes through a chain machine, the surface of the silicon wafer is covered with a water film for protection, and the oxide layer on the bottom and sides is removed by HF;

[0127] (3) The silicon wafer with a single-sided oxide layer is textured in a tank machine at about 85°C to form a textured surface with a reflectivity of 9%, which serves as the front side of the battery. The side with the oxide layer is removed in a subsequent HF tank. This step ultimately results in a textured front side and a back side with a mechanical damage layer that has not been textured.

[0128] (4) The silicon wafer enters the furnace tube for diffusion normally. During the high-temperature diffusion process, dopants are diffused on the front side. Due to the mechanical damage layer on the back side, impurities in the silicon body migrate and accumulate on this side. At the same time, an oxide layer is prepared on the outermost layer of both sides as a subsequent mask.

[0129] (5) The battery is placed with the front side facing up and the back side facing down, and the oxide layer on the back side is removed by a chain machine. In the subsequent tank cleaning, the side where impurities are accumulated is removed, and the surface is prepared to a surface morphology (reflectivity 28%) for subsequent battery preparation.

[0130] Comparative Example 1

[0131] (1) The silicon wafer is textured using a slot machine at around 80°C to form a textured surface with a reflectivity of 9%, which serves as the front side of the battery.

[0132] (2) The silicon wafer enters the furnace tube for diffusion normally. During the high-temperature diffusion process, dopants are diffused on the front side, and an oxide layer is prepared on the outermost layers of both sides as a subsequent mask.

[0133] (3) The battery is placed with the front side facing up and the back side facing down, and the oxide layer on the back side is removed by a chain machine. In the subsequent tank cleaning, the back doping layer is removed, and the surface is prepared to a surface morphology (reflectivity 20% to 50%) for subsequent battery preparation.

[0134] test

[0135] The electrical performance test is carried out by simulating light to test the conversion efficiency of the cell. The Halm tester is used to test the cell under the spectral irradiance of 1000w / m 2 The measurement was carried out under the conditions of AM1.5 spectrum and battery temperature of 25℃. The test results are shown in Table 1 below.

[0136] Table 1

[0137]

[0138] As can be seen from Table 1, the solar cells made of doped silicon wafers have increased light absorption and improved short-circuit current. At the same time, the impurities in the body are reduced, the body passivation effect and FF are improved, and the efficiency gain is relatively strong.

[0139] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The embodiments described above only express several implementation methods of the present invention, which are convenient for understanding the technical solutions of the present invention in a specific and detailed manner, but they cannot be understood as limiting the scope of protection of the invention patent. It should be pointed out that for ordinary technicians in this field, without departing from the concept of the present invention, several variations and improvements can be made, which all fall within the scope of protection of the present invention. It should be understood that the technical solutions obtained by those skilled in the art through logical analysis, reasoning or limited experiments on the basis of the technical solutions provided by the present invention are all within the scope of protection of the attached claims described in the present invention. Therefore, the scope of protection of the patent of the present invention shall be based on the content of the attached claims, and the description and drawings can be used to interpret the content of the claims.

Claims

1. A method for removing impurities from a silicon wafer, characterized in that: The steps include: Providing a bare silicon wafer, wherein the bare silicon wafer has a front side and a back side opposite to each other, and both sides include a mechanical damage layer; The front side of the bare silicon wafer is subjected to texturing treatment to form a textured surface with a reflectivity of 7% to 15%, thereby preparing a silicon wafer intermediate; wherein the silicon wafer intermediate is textured on one side and retains a mechanical damage layer on the other side; Diffusion treatment is performed on the silicon wafer intermediate, whereby the front side of the silicon wafer intermediate is doped with phosphorus or boron and coated with silicon dioxide, and impurities in the silicon wafer intermediate migrate and accumulate in the mechanical damage layer on the back side, forming an external gettering region which is coated with silicon dioxide; The silicon dioxide coating layer on the surface of the external gettering region and the external gettering region are removed, and the reflectivity of the silicon wafer surface obtained after removing the external gettering region is 20% to 50%.

2. The silicon wafer impurity removal method according to claim 1, characterized in that: The preparation of the silicon wafer intermediate comprises the following steps: forming a first mask layer on the back side of the bare silicon wafer to prepare a first intermediate; The first intermediate is subjected to texturing treatment to form a textured surface with a reflectivity of 7% to 15% on the front side of the first intermediate, thereby preparing the silicon wafer intermediate.

3. The silicon wafer impurity removal method according to claim 2, characterized in that: The material of the first mask layer is silicon dioxide.

4. The silicon wafer impurity removal method according to claim 2, characterized in that: The preparation of the silicon wafer intermediate comprises the following steps: The texturing treatment is a wet texturing method, the solution used is alkali, and the temperature is 50°C to 85°C.

5. The silicon wafer impurity removal method according to claim 2, characterized in that: Before the step of performing diffusion treatment on the silicon wafer intermediate, the method further includes a step of removing the first mask layer by acid etching.

6. The silicon wafer impurity removal method according to any one of claims 1 to 5, characterized in that: The process parameters of the diffusion treatment include: The temperature is 800° C. to 1200° C., the oxygen source ratio is 2 to 5, the time is 2.5 h to 4 h, and the furnace tube pressure is 50 mbar to 1160 mbar.

7. The silicon wafer impurity removal method according to any one of claims 1 to 5, characterized in that: The reflectivity of the silicon wafer surface obtained after removing the external gettering region is 20% to 35%.

8. The method for removing impurities from a silicon wafer according to any one of claims 1 to 5, characterized in that: The method for removing the external gettering region is chemical polishing.

9. The silicon wafer impurity removal method according to claim 8, characterized in that: The chemical polishing is selected from acid washing followed by alkaline washing; The acid used in the pickling is hydrofluoric acid or a mixture of nitric acid and hydrofluoric acid; The alkali in the alkali washing is selected from one or a mixture of potassium hydroxide and sodium hydroxide.

10. The silicon wafer impurity removal method according to any one of claims 1 to 5, characterized in that: The method for removing the silicon dioxide coating layer on the surface of the external gettering region is hydrofluoric acid pickling or physical polishing.

11. The silicon wafer impurity removal method according to any one of claims 1 to 5, characterized in that: Before the step of texturing the front surface of the bare silicon wafer, the method further includes the step of cleaning the bare silicon wafer.

12. A method for preparing a silicon wafer, characterized in that: The steps include: removing impurities from a bare silicon wafer using the silicon wafer impurity removal method according to any one of claims 1 to 11 to prepare a silicon wafer preform; The silicon wafer preform is subjected to at least one of deposition of an anti-reflection passivation film, screen printing, and light injection annealing.

13. A silicon wafer, characterized in that: The silicon wafer is prepared according to the method for preparing the silicon wafer according to claim 12.

14. A photovoltaic device, characterized in that: Including the silicon wafer as claimed in claim 13.

15. A photovoltaic module, characterized in that: The photovoltaic device according to claim 14.

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