Rail-to-rail operational amplifier circuit and applications thereof

Abstract

The application belongs to the technical field of operational amplifiers, and specifically provides a rail-to-rail operational amplifier circuit, which comprises: an input stage circuit using a source follower and an NMOS differential pair tube as a low-voltage rail, wherein the source follower is used for lifting the input voltage of the NMOS differential pair tube; an intermediate stage for collecting the converted current signal and converting it into a voltage output, and finally outputting after enhancing the driving capacity by an output stage. In this way, the input stage circuit has the ability of constant transconductance, compared with the traditional constant transconductance input stage, this implementation is direct and effective, the circuit structure is simple, and the circuit structure and the calibration circuit are multiplexed, thereby reducing the layout area.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of operational amplifier, in particular to a rail-to-rail operational amplifier circuit and application thereof. BACKGROUND

[0002] The input offset calibration precision of the traditional rail-to-rail operational amplifier is low and closely related to the input common-mode voltage, which leads to new offset error when the input common-mode voltage changes after the input offset calibration is completed under a certain input common-mode voltage. Because the internal circuit structure of the rail-to-rail operational amplifier is relatively complex, the offset introduced by the P-type and N-type input pair transistors and the amplification stage transistors is often different, and the offset introduced in the chip manufacturing process is also random. The offset of the operational amplifier often changes in three sections with the change of the common-mode voltage in the entire power supply range, so that the actual effect of the traditional offset calibration circuit is not good, and it is difficult to ensure that the input offset voltage of the calibrated operational amplifier remains consistent in the full voltage range. SUMMARY

[0003] The present application aims to at least solve one of the technical problems existing in the prior art, and proposes a rail-to-rail operational amplifier circuit.

[0004] In a first aspect, the present application provides a rail-to-rail operational amplifier circuit, comprising: a source follower and an NMOS differential pair transistor as a low-voltage rail input stage circuit, the source follower being used to raise the input voltage of the NMOS differential pair transistor;

[0005] An intermediate stage is used to collect the converted current signal and convert it into a voltage output, and finally output after the output stage enhances its driving ability.

[0006] Preferably, the mobility of the NMOS differential pair transistor is equal.

[0007] Preferably, it further comprises an input voltage detection stage circuit, the input voltage detection stage circuit comprising a transistor MN10, a transistor MN11, a transistor MN0 and a transistor MN1.

[0008] When the input voltage reaches a preset value, the transistor MN10 and the transistor MN11 start to conduct, and the transistors MN0 and MN1 in mirror relationship with the transistors MN10 and MN11 also conduct. The transistor of the current source Ibias is converted from the deep linear region to the saturation region, so that the current flowing through is increased. The current Ib1 obtained after mirroring, the current Ib2 obtained after the difference of the current, at this time the current Ib2 will be reduced.

[0009] When the input voltage reaches a critical value, transistors MN10 and MN11 are fully turned on. Ignoring circuit offset, current Ib1 is equal to current Ibias. At this time, current Ib2 is equal to zero. The tail current source of the differential pair of transistors on the low-voltage rail no longer has a bias current. The drain of the NMOS differential pair transistors becomes a high resistance point and does not affect the normal operation of transistors MN10 and MN11.

[0010] Preferably, the intermediate stage and the output stage both adopt a floating gate Class AB structure.

[0011] The present invention also provides an offset current generating circuit, which is used to perform offset calibration on the offset current generating circuit, including: injecting or extracting current into or from the intermediate stage through a 7-bit programmable current matrix to calibrate the mismatch generated by the operational amplifier during the manufacturing process.

[0012] The present invention also provides an offset voltage calibration circuit, which is used to calibrate the offset current generating circuit;

[0013] When the op amp is selected for offset calibration, the switch connecting the input terminals INP and INN to the internal op amp OPA is disconnected;

[0014] When the control signal cal_h_en is equal to "1", the high common mode voltage calibration is selected; when the control signal cal_l_en is equal to "1", the low common mode voltage calibration is selected.

[0015] Preferably, when the control signal cal_h_en is equal to "1", the calibration control bits are successively written with "1" from the highest bit to the lowest bit, and at the same time the self-calibration program detects the output voltage of the operational amplifier bit by bit.

[0016] Preferably, when the output voltage is flipped, the "N+1"-th digital code "guessed first" in the previous cycle will be changed in the next cycle, and the "N"-th digital code will be set to "1" at the same time; finally, when the control signal cal_eoc is set to "1", it marks the end of the entire self-calibration process by checking the calibration digital code value temporarily stored in the register.

[0017] Beneficial effects:

[0018] The application provides a novel rail-to-rail operational amplifier circuit, and based on the operational amplifier, a corresponding input offset voltage calibration circuit is provided, the calibration precision can be accurate to the full input common-mode voltage range, the input offset voltage is less than ±0.5mV, and an effective input offset voltage self-calibration algorithm is provided, the zeroing work of the offset voltage of the operational amplifier can be automatically completed through software configuration, and the calibration operation of the operational amplifier is further simplified. Compared with the traditional operational amplifier circuit, the circuit has the functions of constant transconductance rail-to-rail and self-calibration of the input offset voltage, so that the operational amplifier after input offset voltage calibration no longer changes with the changes of the input common-mode voltage, the power supply voltage and the load current. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 A rail-to-rail operational amplifier circuit is provided for the embodiment of the application.

[0020] Figure 2 A circuit structure diagram for realizing constant transconductance is provided for the embodiment of the application.

[0021] Figure 3 A offset current generation circuit diagram is provided for the embodiment of the application.

[0022] Figure 4 An offset calibration circuit diagram is provided for the embodiment of the application.

[0023] Figure 5 A floating gate level structure diagram is provided for the embodiment of the application.

[0024] Figure 6 An offset voltage calibration circuit diagram is provided for the embodiment of the application.

[0025] Figure 7 A timing diagram of the offset voltage self-calibration is provided for the embodiment of the application. DETAILED DESCRIPTION

[0026] In order for those skilled in the art to better understand the technical solutions of the application, the application will be further described in detail below with reference to the drawings and specific embodiments.

[0027] Unless otherwise defined, technical terms or scientific terms used in the present application shall have the same meaning as commonly understood by one of ordinary skill in the art to which the present application pertains. The terms "first", "second", and similar terms, used in the present application do not connote any order, quantity, or importance, but are used to identify different components. Also, the terms "a" and "an" and "the" and similar terms used herein do not denote a limitation of quantity and are used to describe at least one. The terms "comprising", "comprise" and "including", "include" or "contain" or "contains" are not used to the exclusion of other components or elements. The terms "connected" or "coupled" or similar terms are not limited to physical or mechanical connections or couplings, but also include electrical connections or couplings, whether direct or indirect. The terms "upper", "lower", "left", "right" and similar terms are used for relative positional relationship only and can change accordingly when the absolute position of the described object changes.

[0028] In the drawings, like reference numerals refer to like elements throughout the various figures. Portions of the figures can have not been drawn to scale for the sake of clarity.

[0029] Many specific details of the present application are described below. However, it will be apparent to those skilled in the art that the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the concepts of the present application.

[0030] A conventional rail-to-rail operational amplifier is composed of three parts, an input stage, an intermediate stage, and an output stage. The input stage is essentially a transconductance stage that converts an input voltage signal into a current signal. The intermediate stage collects the converted current signal and converts it into a voltage output. The output stage enhances the driving capability of the output.

[0031] In order to realize the rail-to-rail input voltage, the common way is to use PMOS differential pair and NMOS differential pair complementary, so that the low voltage domain input signal can be converted by PMOS differential pair, and the high voltage domain input signal can be processed by NMOS differential pair, greatly increasing the input range of the operational amplifier. Of course, in principle, there is a situation that NMOS and PMOS are turned on at the same time, at this time, two groups of differential pairs participate in the conversion of the transconductance stage, so that the transconductance efficiency is multiplied, which affects the linearity of the amplifier, and the common processing method is to increase the auxiliary circuit to realize the constant transconductance coefficient of the input stage. The operational amplifier has high symmetry requirement for the circuit, and in the circuit design, the internal current and node voltage of the operational amplifier are strictly matched to effectively reduce the system mismatch and reduce the DC offset. However, in actual chip processing, the manufactured devices inevitably have differences, resulting in threshold voltage, width-length ratio, Cox and other errors. This error will be directly presented in the form of offset voltage, and the offset voltage of the traditional operational amplifier without adding the offset calibration circuit will be close to ±10mV, which greatly affects the precision of the operational amplifier. The present application proposes a circuit optimization scheme for the two problems.

[0032] Embodiment one

[0033] As shown in Figure 1 and Figure 2 , the present application uses a source follower and an NMOS differential pair to replace a PMOS differential pair as an input stage of a low-voltage rail. As we all know, the mobility of an NMOS transistor is 2 to 3 times that of a PMOS transistor, so in order to match the same mobility, the number of PMOS transistors is 2 to 3 times that of NMOS transistors, and the layout area will increase significantly.

[0034] The present application uses a circuit structure of two pairs of NMOS transistors and a pair of source followers to realize rail-to-rail input level, compared with the traditional complementary input type of PMOS and NMOS, the mobility of the input differential pair of the present application is equal, so it is not necessary to compensate the mobility by different number of transistors, and the two pairs of NMOS transistors can be matched with each other at the time of layout drawing, so that the layout environment of the whole input stage is similar, and the circuit consistency is increased.

[0035] The transistor MN0 and the transistor MN1 are matched with the input differential pair MN10 and MN11, and together constitute an input voltage detection stage circuit. The NMOS differential pair includes the transistor MN8 and the transistor MN9, and the input voltage is raised by the source follower. Ignoring the sub-threshold conduction, when the input voltage is lower than the threshold voltage of the NMOS transistor, the differential pair works normally.

[0036] When the input voltage reaches the threshold voltage for NMOS transistor conduction, transistors MN10 and MN11 begin to conduct, and their mirrored transistors MN0 and MN1 also conduct. The transistors of current source Ibias transition from a deep linear region to a saturation region, increasing the current flowing through them. Current Ib1 is obtained by mirroring through transistors MP0, MP1, MP2, MP3 and MN2, MN3, MN4, and MN5. The difference between these currents yields current Ib2, which decreases. When the input voltage is sufficiently high, i.e., at the critical value, transistors MN10 and MN11 are fully turned on. Ignoring circuit offset, current Ib1 equals current Ibias, and current Ib2 equals zero. The tail current source of the differential pair of transistors on the low-voltage rail no longer has a bias current, and the drains of transistors MN8 and MN9 are at high resistance points, which do not affect the normal operation of transistors MN10 and MN11. In this way, the input stage circuit has the ability of constant transconductance. Compared with the traditional constant transconductance input stage, this implementation method is direct and effective, the circuit structure is simple, and the circuit structure and calibration circuit are reused to reduce the layout area.

[0037] Example 2

[0038] like Figure 3 As shown, based on the above-mentioned rail-to-rail operational amplifier circuit, the present invention proposes an offset current generation circuit, wherein the current generated in the Vcm_h_cal_current block diagram can be used to calibrate the high common-mode level, and the current generated in the Vcm_l_cal_current block diagram can be used to calibrate the low common-mode level, and the two do not affect each other. There will be a slight mutual influence during the transition phase between the two, but it can be ignored overall. The offset of the op amp can actually be attributed to the current mismatch between the two branches. By injecting or extracting a weak current into or from the half-circuit in the intermediate stage circuit, the offset of the entire op amp can be calibrated.

[0039] refer to Figure 4 , through the 7-bit programmable current matrix, the intermediate stage of the operational amplifier is injected or extracted with current, thereby calibrating the mismatch of the operational amplifier caused by the manufacturing process.

[0040] like Figure 5As shown, in order to reduce the static current of the operational amplifier, improve the driving ability, improve the DC gain and other aspects, the application adopts the very mature floating gate Class AB structure on the market as the intermediate stage and output stage of the operational amplifier. Transistors MP1 to MP4 and transistors MN1 to MN4 are in cascade form, which improves the output impedance of the first stage of the operational amplifier and improves the DC gain of the operational amplifier. The sizes of transistors MP5, MP6 and MP7 and transistors MN5, MN6 and MN7 are consistent, and the layout is strictly matched during the drawing process. The current flowing through the transistor MP0 to the transistor MP2 will be limited by the Vgsp9 of the transistor MP9. Similarly, the working current of the transistor MP0 to MP2 will also be controlled by the Vgsn9 of the transistor MN9. Therefore, the static bias current of the intermediate stage and output stage of the operational amplifier can be determined by the current Ib. When the output OUT needs to drive a large current, the output stage current can be dynamically adjusted through the transistor MP7 and the transistor MN7. For example, when the pull-down current required by the output OUT increases, the Vgsn0 of the transistor MN0 will increase at this time, which will cause the current flowing through the transistor MN7 to decrease, and the current flowing through the static tube MP7 will increase. Since the gate voltage of MP7 is fixed, the source voltage will be raised, thereby causing the vgsp0 of the transistor MP0 to decrease, which makes the current injection capability of MP0 weaken.

[0041] Example three

[0042] As Figure 6As shown, in order to make the offset voltage calibration process of the operational amplifier simple, and to cooperate with the self-calibration circuit operation, on the basis of the second embodiment, the present application proposes an offset voltage calibration circuit which can be configured in the chip. When the operational amplifier is selected for offset calibration, the control signal cal_mode_en is "1", the switches S1 and S2 are disconnected, and the switch S3 is closed, then the input terminals INP and INN are disconnected from the switches connected to the internal operational amplifier OPA. The same direction input terminal and the reverse input terminal of the internal operational amplifier are short-circuited, at this time the operational amplifier works in open loop mode, similar to a low-speed comparator circuit (the compensation circuit in the operational amplifier will affect the signal establishment process of the operational amplifier, resulting in slow flip time), because the direct current gain of the internal operational amplifier is high enough, once there is an offset in the input terminal of the operational amplifier (the internal offset is converted to the input), then the output terminal of the operational amplifier will be slowly pulled down or pulled up until the output voltage is saturated. Then, by using the property of the internal operational amplifier OPA, the size of the artificially introduced offset and the high and low level state of the signal D obtained after the output OUT of the operational amplifier passes through the buffer stage can be modified, that is, the calibration of the operational amplifier can be completed. Based on the architecture proposed in the foregoing, by switching the control signals cal_l_en and cal_h_en, the operational amplifier can complete the offset calibration in the full common mode range. The self-calibration part circuit is written in verilog language to meet the functional RTL file, and after digital synthesis, layout and wiring, the corresponding netlist is imported into the circuit.

[0043] In combination with the provided offset voltage calibration circuit, the present application provides a timing diagram of some important nodes in the calibration process, wherein the clock frequency of the clock signal cal_clk is equal to 1KHz, when a pulse signal of the control signal cal_soc appears, the whole self-calibration program starts to run, the self-calibration program will automatically calibrate the high and low common mode of the operational amplifier in two cases respectively, when the control signal cal_h_en is equal to "1", the high common mode voltage calibration is selected; when the control signal cal_l_en is equal to "1", the low common mode voltage calibration is selected.

[0044] If the control signal cal_h_en is equal to "1", the calibration control bit cal_h<6:0> will perform the "1" operation by approaching from the highest bit to the lowest bit, at the same time, the self-calibration program will detect the output voltage of the operational amplifier bit by bit, if the output voltage exists the flip phenomenon, the "N+1" bit digital code will be changed in the next cycle, and the "N" bit digital code will be set to "1" at the same time. Finally, when the control signal cal_eoc is set to "1", it indicates that the whole self-calibration process is completed, the calibration digital code value temporarily stored in the register can be checked by reading the register operation.

[0045] The application combines the offset calibration circuit of the operational amplifier with the binary search algorithm to perform offset self-calibration operation in two cases of low input common-mode voltage and high input common-mode voltage, thereby realizing calibration in the full common-mode input range.

[0046] The application adopts the common-mode level detection technology and the tail current dynamic adjustment technology instead of the traditional 'one-time current method', 'three-time current method','maximum current method' and the like to realize the constant transconductance of the input stage, greatly simplifies the circuit structure, realizes more concise control logic, and can be multiplexed with the function of generating the offset calibration current, so that one circuit structure realizes two functions and improves the circuit design efficiency.

[0047] The application adopts the 7-bit offset calibration current array to calibrate the input offset of the operational amplifier, and only two calibration steps can cover the entire common-mode input voltage range.

[0048] The application adopts the CLASS AB output stage with the symmetric floating gate structure to realize stable current distribution of the amplification stage and reduce the static current of the output stage, realizes the CLASS AB output form through the floating gate structure, can push and pull the current of not more than 1mA, and enhances the driving capability of the entire operational amplifier.

[0049] The application adopts the on-chip calibration circuit combined with the self-calibration algorithm, only needs the digital circuit part to provide a low-speed clock signal and configure the corresponding control register, can realize zeroing of the offset voltage of the operational amplifier, outputs an end flag bit after the self-calibration process of the operational amplifier is completed, reads the corresponding calibration register at this time, and writes the digital code into the Flash, so that the calibration process is completed.

[0050] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the application, but the application is not limited thereto. Those skilled in the art can make various modifications and improvements without departing from the spirit and essence of the application, and these modifications and improvements are also regarded as the protection scope of the application.

Claims

1. A rail-to-rail operational amplifier circuit, characterized by, The application relates to a rail-to-rail operational amplifier circuit. The rail-to-rail operational amplifier circuit comprises an input stage circuit, a middle stage and an output stage. The input stage circuit comprises a source follower and an NMOS differential pair tube, the source follower is used for lifting the input voltage of the NMOS differential pair tube, and the NMOS differential pair tube has equal mobility. The rail-to-rail operational amplifier circuit further comprises an input voltage detection stage circuit, the transistor MN0 and the transistor MN1 are matched with the transistor MN10 and the transistor MN11, and the transistor MN0, the transistor MN1, the transistor MN10 and the transistor MN11 jointly form the input voltage detection stage circuit. The transistor MN0 and the transistor MN1 are both provided with current bias through a first bias current source Ibias, and the transistor MN10 and the transistor MN11 are both provided with current bias through a bias current source N-tail2. The transistor MN2 to the transistor MN5 form a first stable current mirror, the transistor MN2 and the transistor MN4 form a primary side of the first stable current mirror, the transistor MN3 and the transistor MN5 form a secondary side of the first stable current mirror, the transistor MP0 to the transistor MP3 form a second stable current mirror, the transistor MP0 and the transistor MP2 form a primary side of the second stable current mirror, the transistor MP1 and the transistor MP3 form a secondary side of the second stable current mirror, and the primary side of the first stable current mirror and the secondary side of the second stable current mirror are connected in series. The transistor MN3 and the transistor MN5 are connected in series to form a first branch, the input current of the first branch is Ib1, the transistor MN7 and the transistor MN6 are connected in series to form a second branch, the input current of the second branch is Ib2, the source of the transistor MN3 and the source of the transistor MN6 are connected to the ground, and the drain of the transistor MN5 and the drain of the transistor MN7 are connected to the output end of a second bias current source Ibias. The transistor MP0 and the transistor MP2 are connected in series to form a third branch, the transistor MP1 and the transistor MP3 are connected in series to form a fourth branch, and the third branch is connected to the drain of the transistor MN0 and the drain of the transistor MN1 and is connected to the input end of the first bias current source Ibias. The gate of the transistor MP0 and the gate of the transistor MP1 are connected, the source of the transistor MP0 and the source of the transistor MP1 are connected and are connected to a power supply VDDA, the source of the transistor MP2 is connected to the drain of the transistor MP0, the drain of the transistor MP2 is connected to the drain of the transistor MN0, the drain of the transistor MN1, the gate of the transistor MP0 and the gate of the transistor MP1, and the gate of the transistor MP2 and the gate of the transistor MP3 are connected, and the source of the transistor MP3 is connected to the drain of the transistor MP1. The drain of the transistor MN4 is connected to the drain of the transistor MP3 and is connected to the gate of the transistor MN2 and the gate of the transistor MN3. When the input voltage gradually rises to a preset value, the transistor MN10 and the transistor MN11 begin to conduct, the transistor MN0 and the transistor MN1 in mirror relationship with the transistor MN10 and the transistor MN11 also conduct, the transistor of the first bias current source Ibias converts from the deep linear region to the saturation region, so that the current flowing through the transistor MN10, the transistor MN11, the transistor MN0 and the transistor MN1 increases, and the current Ib1 obtained through the transistor MP0, the transistor MP1, the transistor MP2, the transistor MP3 and the mirror of the transistor MN2, the transistor MN3, the transistor MN4 and the transistor MN5 also increases; When Ib1 increases, the current Ib1 and the second bias current Ibias current difference to obtain the current Ib2, at this time the current Ib2 will decrease; When the input voltage is high to the critical value, after the transistor MN10 and the transistor MN11 are completely turned on, under the condition of ignoring the circuit offset, the current Ib1 is equal to the current Ibias of the second bias current source, at this time the current Ib2 is equal to zero, the tail current source of the NMOS differential pair tube of the low voltage rail no longer exists the bias current, the drain of the NMOS differential pair tube is a high resistance point, and the normal work of the transistor MN10 and MN11 is not affected; the intermediate stage and the output stage adopt the floating gate Class AB structure. Among them, the transistor MN0 to the transistor MN11 are NMOS transistors, and the transistor MP0 to MP3 are PMOS transistors.

2. A misregulation current generating circuit characterized by comprising: The offset current generating circuit is used for offset calibration of the rail-to-rail operational amplifier circuit as claimed in claim 1, comprising: through the 7-bit programmable current matrix, the current is injected or extracted to the intermediate stage, so as to realize the calibration of the mismatch of the operational amplifier due to the manufacturing process.

3. A misregulation voltage calibration circuit, characterized by, The offset voltage calibration circuit is used for calibration of the offset current generating circuit as claimed in claim 2; When the operational amplifier is selected for offset calibration, the switch connecting the input end INP and INN with the internal operational amplifier OPA is disconnected; When the control signal cal_h_en is equal to "1", the high common mode voltage condition calibration is selected; when the control signal cal_l_en is equal to "1", the low common mode voltage condition calibration is selected.

4. The misregulation voltage calibration circuit of claim 3, wherein, When the control signal cal_h_en is equal to "1", the calibration control bit is written "1" from the highest bit to the lowest bit in turn, and at the same time, the self-calibration program detects the output voltage of the operational amplifier bit by bit.

5. The misregulation voltage calibration circuit of claim 3, wherein, When the output voltage exists the flip phenomenon, the "N+1" bit digital code "guessed" in the last cycle will be changed in the next cycle, and the "N" bit digital code will be set "1" at the same time; finally, when the control signal cal_eoc is set "1", it indicates that the whole self-calibration process is completed, and the calibration digital code value temporarily stored in the register is checked.

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