A two-stage fully differential operational amplifier with high bandwidth rail-to-rail input for switching power supplies

Abstract

The application discloses a two-stage full-differential operational amplifier with high-bandwidth rail-to-rail input applied to a switching power supply, realizes the combination of the high-bandwidth operational amplifier and the switching power supply, and provides the possibility for further improvement of the switching frequency of the switching power supply. The two stages of the operational amplifier are differential structures, wherein the first stage adopts PMOS and NMOS as input tubes, and rail-to-rail input can be realized. Meanwhile, the first-stage load adopts two MOS tubes as resistors for biasing, thereby improving the gain and bandwidth. The second stage adopts a five-tube transconductance operational amplifier structure, and the two stages are differential structures, thereby improving the bandwidth of the operational amplifier. The operational amplifier is applied to a volt-second balance subtractor and an error amplifier part in a double-clamp buck-boost transformer, meets the system requirement index, and improves the overall performance of the double-clamp buck-boost transformer.

Description

Technical Field

[0001] This invention belongs to the field of operational amplifiers and switching power supplies, and particularly relates to the application of a high-bandwidth rail-to-rail input two-stage fully differential operational amplifier in switching power supplies to improve the performance of switching power supplies. Background Technology

[0002] Operational amplifiers (op-amps) are the most basic structure in analog circuits and an indispensable part of every analog circuit. They enable various functions such as computation and signal amplification. Switching power supplies, as a type of analog circuit, rely heavily on op-amps. For example, the performance of op-amps used in error amplifiers significantly impacts the overall functionality and performance of the switching power supply. With the increasing integration of control modules into chips and the development of various power devices, the switching frequency of switching power supplies is constantly increasing. This necessitates that the op-amps used in switching power supplies handle increasingly higher signal bandwidths.

[0003] However, current switching power supplies use basic low-bandwidth operational amplifiers, which were sufficient for applications with switching frequencies below MHz. However, as switching frequencies continue to increase, the bandwidth of signals that the controller needs to process also increases accordingly. The previously used low-bandwidth operational amplifiers have become a significant factor limiting the improvement of switching power supply switching frequencies. Summary of the Invention

[0004] The purpose of this invention is to apply a two-stage differential high-bandwidth rail-to-rail input operational amplifier to a switching power supply to meet the required specifications of a high-frequency switching power supply, thereby solving the technical problems mentioned in the background art.

[0005] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0006] A high-bandwidth rail-to-rail input two-stage fully differential operational amplifier for use in switching power supplies, wherein the operational amplifier has two gain stages and both gain stages are fully differential, wherein the first stage uses PMOS and NMOS as input transistors to achieve rail-to-rail input;

[0007] Meanwhile, the first-stage load uses MOSFETs as resistors for biasing, including PMOS load and NMOS load. MP5 and MN3 constitute the tail current source of the first-stage differential structure.

[0008] The second stage uses a five-transistor transconductance operational amplifier structure. Both stages are differential structures, which improves the bandwidth of the op-amp. This includes the differential input pair of transistors in the second stage and the load of the second stage. MN10 is the tail current source of the differential structure in the second stage.

[0009] The upper part of the first-stage input transistor is connected to a PMOS load and a PMOS tail current source MP5, and the lower part is connected to an NMOS load and an NMOS tail current source MN3.

[0010] The first-stage input transistor is connected to the gate of the second-stage differential input pair; the lower part of the second-stage differential input pair is connected to the tail current source MN10, and the upper part is connected to the PMOS load.

[0011] Furthermore, in the high-bandwidth rail-to-rail input two-stage fully differential operational amplifier applied to a switching power supply, the input transistors include a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, and a second N-type transistor MN2; the PMOS loads include a third P-type transistor MP3, a fourth P-type transistor MP4, a sixth P-type transistor MP6, and a seventh P-type transistor MP7; the NMOS loads include a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth N-type transistor MN5, a sixth N-type transistor MN6, and a seventh N-type transistor MN7; the differential input pair of the second stage includes an eighth N-type transistor MN8 and a ninth N-type transistor MN9; the load of the second stage includes an eighth P-type transistor MP8 and a ninth P-type transistor MP9;

[0012] The power supply voltage source VDD is connected to the source of the fifth P-type transistor MP5, the sixth P-type transistor MP6, the seventh P-type transistor MP7, the eighth P-type transistor MP8, and the ninth P-type transistor MP9. The first DC bias voltage Vp is connected to the gate of the first P-type transistor MP1 and the first N-type transistor MN1. The second DC bias voltage Vp1 is connected to the gate of the fifth P-type transistor MP5. The third DC bias voltage Vp2 is connected to the gate of the third P-type transistor MP3 and the fourth P-type transistor MP4. The fourth DC bias voltage VN is connected to the gate of the second P-type transistor MP2 and the second N-type transistor MN2. The fifth DC bias voltage V... N1 is connected to the gates of the third N-type transistor MN3 and the tenth N-type transistor MN10. The sixth DC bias voltage VN2 is connected to the gates of the fourth N-type transistor MN4 and the fifth N-type transistor MN5. The source of the first P-type transistor MP1 is connected to the drain of the fifth P-type transistor MP5 and the source of the second P-type transistor MP2. The drain of the first P-type transistor MP1 is connected to the drains of the first N-type transistor MN1, the sixth N-type transistor MN6, the sixth P-type transistor MP6, the drain of the fourth N-type transistor MN4, and the drain of the third P-type transistor MP3. The drain of the first P-type transistor MP1 is connected to the ninth P-type transistor MP9. The gate of the second P-type transistor MP2 is connected to the drain of the fourth P-type transistor MP4, the seventh P-type transistor MP7, the second N-type transistor MN2, the fifth N-type transistor MN5, the seventh N-type transistor MN7, and the gate of the eighth N-type transistor MN8. The source of the third P-type transistor MP3 is connected to the gate of the sixth P-type transistor MP6, the seventh P-type transistor MP7, and the source of the fourth P-type transistor MP4. The gate of the eighth P-type transistor MP8 is connected to its drain and the gate of the ninth P-type transistor MP9, as well as the drain of the eighth N-type transistor MN8. The drain of the ninth P-type transistor MP9 is connected to the ninth N-type transistor MN9. The drain of the first N-type transistor MN1 is connected to the source of the second N-type transistor MN2 and the drain of the third N-type transistor MN3. The sources of the third N-type transistor MN3, the sixth N-type transistor MN6, and the seventh N-type transistor MN7 are grounded. The drain of the fourth N-type transistor MN4 is connected to the source of the fifth N-type transistor MN5. The gate of the sixth N-type transistor MN6 is connected to the gate of the seventh N-type transistor MN7. The source of the eighth N-type transistor MN8 is connected to the source of the ninth N-type transistor MN9 and the drain of the tenth N-type transistor MN10. The source of the tenth N-type transistor MN10 is grounded.

[0013] This invention discloses a high-bandwidth rail-to-rail input two-stage fully differential operational amplifier for switching power supplies, offering the following advantages: The invention employs a two-stage fully differential operational amplifier, with both stages being differential structures. The first stage uses both PMOS and NMOS transistors as input transistors, enabling rail-to-rail input. Simultaneously, the first stage load uses two MOS transistors as resistors for biasing, improving gain and bandwidth. The second stage utilizes a five-transistor transconductance operational amplifier structure. Since both stages are differential structures, this further enhances the op-amp's bandwidth. Applied to the volt-second balance subtractor and error amplifier sections of a dual-clamp step-up / step-down transformer, it meets system requirements, improves the overall performance of the dual-clamp step-up / step-down transformer, and provides the possibility for further increasing the frequency of the switching power supply. Attached Figure Description

[0014] Figure 1 This is a block diagram of the topology of the dual-clamp buck-boost converter to which this invention is applied, the volt-second balance detection circuit, and the control signals Q1 and Q3.

[0015] Figure 2 This is a circuit diagram of the two-stage high-bandwidth rail-to-rail input operational amplifier used in this invention;

[0016] Figure 3 These are simulation diagrams of the amplitude-frequency response curve and phase-frequency response curve of the operational amplifier used in this invention at a TT process angle of 27°;

[0017] Figure 4 These are simulation diagrams of the amplitude-frequency response curves and phase-frequency response curves of the operational amplifier used in this invention at different process angles and temperatures;

[0018] Figure 5 This is a simulation diagram of the power supply rejection ratio of the operational amplifier used in this invention;

[0019] Figure 6 This is a simulation diagram of the common-mode rejection ratio of the operational amplifier used in this invention;

[0020] Figure 7 This is a simulation diagram of the equivalent input noise of the operational amplifier used in this invention;

[0021] Figure 8 This is a timing simulation diagram of the operational amplifier of the present invention applied to the volt-second balancing circuit in a dual-clamp buck-boost converter.

[0022] The markings in the diagram are as follows: 001, input transistor; 002, PMOS load; 003, NMOS load; 004, differential input pair of transistors in the second stage; 005, load of the second stage. Detailed Implementation

[0023] To better understand the purpose, structure, and function of this invention, the following detailed description, in conjunction with the accompanying drawings, provides an explanation of a high-bandwidth rail-to-rail input two-stage fully differential operational amplifier for use in switching power supplies.

[0024] Figure 1 This diagram shows the topology of the dual-clamp buck-boost converter to which this invention is applied, along with the volt-second balance detection circuit and the control signals for Q1 and Q3. This converter is an isolated discontinuous buck-boost converter built upon a four-switch buck-boost converter. It requires determining the turn-off time of switch Q3 based on the volt-second balance of the inductor to prevent magnetic saturation of the inductor. In this topology, the inductor current waveform is a triangular wave. To achieve the volt-second balance function, the waveform of the inductor current needs to be simulated. As the switching frequency increases, the frequency of the inductor current waveform also increases. To detect the inductor current waveform, a higher bandwidth operational amplifier is needed to meet the demands of the continuously increasing switching frequency. aS and V bS These are the voltages V across the inductor. a and V b The result obtained after voltage division and integration using resistors and capacitors serves as the input for volt-second balance. A subtractor then determines whether volt-second balance has been achieved to control the turn-off of transistor Q3. For increasing the switching frequency, due to V... aS and V bS It is a triangular wave signal with the same switching frequency and period, so increasing the switching frequency will also lead to an increase in the signal bandwidth that the subtractor op-amp needs to process, which places demands on the bandwidth performance of the operational amplifier. In the topology, the control signals of transistors Q1 and Q3 are connected... Figure 1 The output signals of the two SR flip-flops in the lower half, V aS and V bS Connect the two input terminals of the volt-second balanced subtractor. The start-of-cycle signal turns on the sampling switch via an SR flip-flop, sampling the output of the subtractor through a capacitor. Simultaneously, the start-of-cycle signal turns on Q1 via the SR flip-flop, and this Q1 signal also turns off the sampling switch. Therefore, V S&H This refers to the subtractor output voltage value at the beginning of each cycle. V aS and V bS Connect the two input terminals of the subtractor so that the output current of the subtractor can track the change in inductor current. VDD is a 5V power supply voltage, V as V is the voltage at the left end of the inductor. a The voltage value after integration, V bS V is the voltage at the left end of the inductor. b The voltage value after integration. Since the inductor current is the integral of the voltage across the inductor, V aS and V bS Subtraction can simulate inductor current. The subtractor output is V.Sen Its waveform maintains the same shape as the inductor current waveform. V Sen and V S&H Connected to the two inputs of the comparator respectively, when V Sen and V S&H When the voltage values ​​are equal again, the comparator output voltage flips, reaching the volt-second balance stage. The comparator output voltage serves as the turn-off signal for transistor Q3, and turning off Q3 via the SR flip-flop achieves volt-second balance for the inductor. Since the final output signal of the subtractor maintains the same waveform as the inductor current, the bandwidth that the subtractor can process increases accordingly as the converter switching frequency increases. Therefore, the bandwidth requirement of the operational amplifier needed to construct the subtractor also increases. This invention proposes applying two stages of fully differential high-bandwidth operational amplifiers to the switching power supply circuit to meet the requirements of increased switching frequency. These two stages of operational amplifiers are used as the subtractor in the volt-second balance module to verify whether the specifications are met.

[0025] Figure 2 This is the circuit diagram of the operational amplifier of the present invention. As shown in the figure, both stages of the operational amplifier are differential structures. The first stage uses both PMOS and NMOS transistors as input transistors 001, enabling rail-to-rail input. Simultaneously, the first stage load uses MOS transistors MP3, MP4, MN4, and MN5 as resistors for biasing, improving gain and bandwidth. 002 is the PMOS load, 003 is the NMOS load, and MP5 and MN3 are the tail current sources of the first stage differential structure. The second stage uses a five-transistor transconductance operational amplifier structure, with both stages being differential structures, further improving the operational amplifier's bandwidth. 004 is the differential input pair of the second stage, 005 is the load of the second stage, and MN10 is the tail current source of the second stage differential structure. The upper part of the first stage input transistor 001 is connected to the PMOS load 002 and the PMOS tail current source MP5, and the lower part is connected to the NMOS load 003 and the NMOS tail current source MN3.

[0026] Input transistor 001 includes a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, and a second N-type transistor MN2; PMOS load 002 includes a third P-type transistor MP3, a fourth P-type transistor MP4, a sixth P-type transistor MP6, and a seventh P-type transistor MP7; NMOS load 003 includes a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth N-type transistor MN5, a sixth N-type transistor MN6, and a seventh N-type transistor MN7; the second-stage differential input pair 004 includes an eighth N-type transistor MN8 and a ninth N-type transistor MN9; the second-stage load 005 includes an eighth P-type transistor MP8 and a ninth P-type transistor MP9.

[0027] The outputs of the first stage are the drains of MP1 and MN1. The drains of MP2 and MN2 are connected to the gates of the second-stage differential input pair transistors 004, namely the gates of MN8 and MN9. The lower part of the second-stage differential input pair transistors is connected to the tail current source MN10, and the upper part is connected to the PMOS load 005. The output of the second stage, which is also the output of the entire operational amplifier, is the drain of MN9 and MP9.

[0028] In the circuit shown in the diagram, the power supply voltage source VDD is connected to the sources of MP5, MP6, MP7, MP8, and MP9; the DC bias voltage Vp is connected to the gates of MP1 and MN1; the DC bias voltage Vp1 is connected to the gate of MP5; the DC bias voltage Vp2 is connected to the gates of MP3 and MP4; the DC bias voltage VN is connected to the gates of MP2 and MN2; the DC bias voltage VN1 is connected to the gates of MN3 and MN10; the DC bias voltage VN2 is connected to the gates of MN4 and MN5; the source of MP1 is connected to the drain of MP5 and the source of MP2; the drain of MP1 is connected to the drains of MN1, MN6, MP6, and the drains of MN4 and MP3; and MP1... The drain of MP2 is connected to the gate of MP9. The drain of MP2 is connected to the drains of MP4, MP7, MN2, MN5, MN7 and the gate of MN8. The source of MP3 is connected to the gates of MP6, MP7 and the source of MP4. The gate of MP8 is connected to the drain of MP9 and the drain of MN8. The drain of MP9 is connected to the drain of MN9 and outputs Vout from this interface. The source of MN1 is connected to the source of MN2 and the drain of MN3. The sources of MN3, MN6 and MN7 are grounded. The drain of MN4 is connected to the source of MN5. The gate of MN6 is connected to the gate of MN7. The source of MN8 is connected to the source of MN9 and the drain of MN10. The source of MN10 is grounded.

[0029] Figure 3 This paper presents simulation results of the amplitude-frequency and phase-frequency response curves of the operational amplifier of this invention at a time-to-time (TT) process angle and 27°. The simulation results were obtained using a circuit built and tested using the BCD process. The circuit's static power consumption is 140uA. Based on previous simulation results, the circuit bandwidth can reach 400MHz while satisfying the phase margin. The simulation results demonstrate that this operational amplifier can achieve a wide bandwidth, meeting the requirements for increased switching frequency in switching power supplies. Figure 4 This is a simulation of the operational amplifier process angle in this invention. The simulation results include nine cases with process angles of tt, ss, and ff at temperatures of -40°, 27°, and 125° respectively. The simulation shows that the operational amplifier of this invention can maintain stability and achieve a large bandwidth under different process angles and temperatures.

[0030] Figure 5 The simulation diagram shows the power supply rejection ratio (PSRR) of the operational amplifier used in this invention. The simulation results show that the PSRR can reach -94dB at low frequencies. Figure 6The simulation diagram shows the common-mode rejection ratio of the operational amplifier used in this invention. The simulation results show that the common-mode rejection ratio can reach -58.6dB at low frequencies. Figure 7 The simulation results show the equivalent input noise of the operational amplifier in this invention. The simulation results indicate that the equivalent input noise at a frequency of 1kHz is...

[0031] Figure 8 This invention relates to an operational amplifier applied to a subtractor in a volt-second balance detection circuit of a dual-clamp step-up / step-down transformer. The figure shows the relevant waveforms of the volt-second balance subtractor. Simulation results show that the voltages at the positive and negative terminals of the subtractor remain consistent, exhibiting good tracking performance, and the bandwidth meets signal transmission requirements. VSEN represents the waveform at the subtractor's output, which should change in the same way as the inductor current waveform. L2 represents the current waveform on the magnetizing inductor. Simulation results show that the subtractor's bandwidth is greater than the triangular wave spectrum range, and it can basically output a triangular wave that changes in the same way as the magnetizing inductor current waveform, meeting the system's requirements.

[0032] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A high-bandwidth rail-to-rail input two-stage fully differential operational amplifier for use in switching power supplies, characterized in that, The operational amplifier has two gain stages, both of which are fully differential structures. The first stage uses both PMOS and NMOS as input transistors (001) to achieve rail-to-rail input. Meanwhile, the first-stage load uses MOS transistors as resistors for biasing, including PMOS load (002) and NMOS load (003). MP5 and MN3 constitute the tail current source of the first-stage differential structure. The second stage uses a five-transistor transconductance operational amplifier structure. Both stages are differential structures, which improves the bandwidth of the op-amp. It includes the differential input pair (004) of the second stage and the load (005) of the second stage. MN10 is the tail current source of the differential structure of the second stage. The upper part of the first-stage input transistor (001) is connected to the PMOS load (002) and the PMOS tail current source MP5, and the lower part is connected to the NMOS load (003) and the NMOS tail current source MN3. The first-stage input transistor (001) is connected to the gate terminal of the second-stage differential input pair transistor (004); the lower part of the second-stage differential input pair transistor (004) is connected to the tail current source MN10, and the upper part is connected to the PMOS load (005). In the high-bandwidth rail-to-rail input two-stage fully differential operational amplifier applied to a switching power supply, the input transistors (001) include a first P-type transistor MP1, a second P-type transistor MP2, a first N-type transistor MN1, and a second N-type transistor MN2; the PMOS load (002) includes a third P-type transistor MP3, a fourth P-type transistor MP4, a sixth P-type transistor MP6, and a seventh P-type transistor MP7; the NMOS load (003) includes a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth N-type transistor MN5, a sixth N-type transistor MN6, and a seventh N-type transistor MN7; the differential input pair (004) of the second stage includes an eighth N-type transistor MN8 and a ninth N-type transistor MN9; and the load (005) of the second stage includes an eighth P-type transistor MP8 and a ninth P-type transistor MP9. The power supply voltage source VDD is connected to the source of the fifth P-type transistor MP5, the sixth P-type transistor MP6, the seventh P-type transistor MP7, the eighth P-type transistor MP8, and the ninth P-type transistor MP9. The first DC bias voltage Vp is connected to the gate of the first P-type transistor MP1 and the first N-type transistor MN1. The second DC bias voltage Vp1 is connected to the gate of the fifth P-type transistor MP5. The third DC bias voltage Vp2 is connected to the gate of the third P-type transistor MP3 and the fourth P-type transistor MP4. The fourth DC bias voltage VN is connected to the gate of the second P-type transistor MP2 and the second N-type transistor MN2. The fifth DC bias voltage V... N1 is connected to the gates of the third N-type transistor MN3 and the tenth N-type transistor MN10. The sixth DC bias voltage VN2 is connected to the gates of the fourth N-type transistor MN4 and the fifth N-type transistor MN5. The source of the first P-type transistor MP1 is connected to the drain of the fifth P-type transistor MP5 and the source of the second P-type transistor MP2. The drain of the first P-type transistor MP1 is connected to the drains of the first N-type transistor MN1, the sixth N-type transistor MN6, the sixth P-type transistor MP6, the fourth N-type transistor MN4, and the third P-type transistor MP3. The drain of the first P-type transistor MP1 is connected to the ninth N-type transistor MN9. The gate of the second P-type transistor MP2 is connected to the drain of the fourth P-type transistor MP4, the seventh P-type transistor MP7, the second N-type transistor MN2, the fifth N-type transistor MN5, the seventh N-type transistor MN7, and the gate of the eighth N-type transistor MN8. The source of the third P-type transistor MP3 is connected to the gate of the sixth P-type transistor MP6, the seventh P-type transistor MP7, and the source of the fourth P-type transistor MP4. The gate of the eighth P-type transistor MP8 is connected to its drain and the gate of the ninth P-type transistor MP9, as well as the drain of the eighth N-type transistor MN8. The drain of the ninth P-type transistor MP9 is connected to the ninth N-type transistor MN9. The drain of the first N-type transistor MN1 is connected to the source of the second N-type transistor MN2 and the drain of the third N-type transistor MN3. The sources of the third N-type transistor MN3, the sixth N-type transistor MN6, and the seventh N-type transistor MN7 are grounded. The source of the fourth N-type transistor MN4 is connected to the source of the fifth N-type transistor MN5. The gate of the sixth N-type transistor MN6 is connected to the gate of the seventh N-type transistor MN7. The source of the eighth N-type transistor MN8 is connected to the source of the ninth N-type transistor MN9 and the drain of the tenth N-type transistor MN10. The source of the tenth N-type transistor MN10 is grounded.

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