A multi-channel radio frequency assembly integrated full-digital phased array antenna system

Abstract

This invention discloses a fully digital phased array antenna system integrating multi-channel radio frequency components, comprising an antenna radiating element, a limiting low-noise amplifier module, 32-channel radio frequency components, a central control component, a synchronization and timing system, a display and control central processing unit, and a secondary power supply. The antenna system integrates a highly integrated 32-channel radio frequency component, the operating status of which is controlled by the central control component. Each 32-channel radio frequency component integrates an independent 32-channel radio frequency link, an analog-to-digital converter, a programmable logic unit, and an optical fiber transmission module. This antenna system achieves all beamforming and signal processing functions in the digital domain, meeting the requirements of high bandwidth, multi-functionality, high flexibility, and intelligence. It synchronizes the clock and data of multiple radio frequency component channels between and within the array board according to clock and synchronization signals, enabling simultaneous multi-beamforming without increasing system size, weight, or complexity.

Description

Technical Field

[0001] This invention belongs to the field of phased array antenna technology and relates to a fully digital phased array antenna system integrating multi-channel radio frequency components. Background Technology

[0002] Phased array antenna technology, by precisely controlling the phase and amplitude of electromagnetic waves from each radiating antenna element in the array, enables rapid beam scanning in space and has become a core component of modern radar, communication, and electronic warfare systems. Currently, the most widely used phased array technology is based on an analog beamforming architecture, where each antenna element is connected to an independent amplitude and phase control circuit consisting of analog phase shifters and attenuators. Analog phased array antenna systems achieve array trimming and beamforming by programmably setting the phase-shifting and attenuator states of the analog phase shifters and attenuators.

[0003] The phased array antenna with analog beamforming architecture has inherent defects: analog phase shifters are usually equal-phase shifters. When processing broadband signals, different frequency components will have their beam pointing shifted after the same phase shift. This phenomenon is called "beam squinting," which means there is aperture transit time and frequency dispersion. This severely limits the instantaneous bandwidth of the system, making it difficult to apply to ultra-wideband radar or high-speed communication. The analog beamforming network can only generate one fixed phase distribution at a time, that is, it can only form one beam. To achieve multiple beams working simultaneously, multiple complete analog networks need to be replicated, such as integrating multiple beamforming phase shifters and attenuators through power splitting and power combining networks. This leads to an exponential increase in system size, weight, cost, and complexity. The amplitude and phase characteristics of a large number of analog devices are prone to drift with temperature and time. It is difficult to maintain consistency between channels in the long term. To maintain performance, it is necessary to rely on a complex and frequent online calibration system, which results in high operation and maintenance costs.

[0004] To address the above issues and effectively overcome the inherent limitations of analog beamforming architectures, phased array antenna system architectures will evolve from analog beamforming to a fully digital architecture, driven by theoretical and technological advancements. The core feature of a fully digital phased array is the provision of independent RF transceiver channels and high-speed data converters for each antenna element, enabling all beamforming and signal processing functions to be performed in the digital domain. Theoretically, this architecture can completely eliminate beam squint, provide the maximum degrees of freedom equal to the number of array elements, and possess unparalleled software reconfigurability and functional flexibility.

[0005] In summary, existing analog phased array architectures, due to their inherent limitations, cannot meet the future system requirements for ultra-wideband, multifunctionality, high flexibility, and intelligence. Therefore, there is an urgent need for an engineering-feasible all-digital phased array system solution to overcome these bottlenecks and promote the practical application and industrialization of this technology. Summary of the Invention

[0006] In order to overcome the shortcomings of the prior art, the present invention provides a fully digital phased array antenna system integrating multi-channel radio frequency components.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: A fully digital phased array antenna system integrating multiple radio frequency components includes an antenna radiating element, a limiting low-noise amplifier module, radio frequency components, a central control component, a synchronization and timing system, and a display and control central processing unit. The antenna radiating element and the limiting low-noise amplifier module are respectively connected to the radio frequency channel output port of the radio frequency component via radio frequency cables. Multiple radio frequency components, the synchronization and timing system, and the display and control central processing unit are respectively connected to the central control component via cables to form a communication connection. The synchronization and timing system outputs a reference clock to the central control component. The central control component generates a clock signal and a synchronization signal according to the reference clock and outputs them to multiple radio frequency components for synchronization. The display and control central processing unit is connected to the radio frequency components via optical fiber. The display and control central processing unit performs digital domain beamforming and signal processing on the channel data acquired by the radio frequency components.

[0008] Furthermore, the radio frequency component integrates 32 radio frequency front-end links, which are interconnected with radio frequency signals via SMP connectors. The radio frequency front-end links integrate FPGAs to sample baseband data of the receiving channel in the digital domain.

[0009] Furthermore, the radio frequency component receives the clock signal and synchronization signal output by the central control component, distributes them through the clock power divider network and the synchronization network, and outputs them to each radio frequency front-end link to achieve synchronization of 32 radio frequency front-end links.

[0010] Furthermore, the central control component includes an FPGA and a clock distributor. The central control component receives the reference clock from the synchronization timing system, converts it through a balun, and then inputs it to the clock distributor. The clock distributor inputs the clock signal to the FPGA for synchronization, generates a synchronization signal and a clock signal, and outputs them to the radio frequency component for synchronization through a multi-level clock distributor.

[0011] Furthermore, the central control component receives the 1pps signal and absolute time signal from the synchronization timing system to determine the radar's operating basis based on the predetermined absolute time, and distributes them to multiple radio frequency components. When the absolute time arrives, the radio frequency components are triggered to synchronize, and the arrival time of the next synchronization moment is confirmed based on the radar's operating mode. When the next synchronization moment arrives, the radio frequency components are triggered to synchronize again, thus completing the synchronization timing of the radio frequency components.

[0012] Furthermore, the clock distributor includes a master clock distributor and six slave clock distributors. The master clock distributor generates clock signals and reference signals and distributes them to the six slave clock distributors. The six slave clock distributors generate twelve signals and distribute them to the radio frequency components.

[0013] Furthermore, the central control component receives calibration instructions sent by the display and control central processor, outputs radio frequency calibration signals to the calibration antenna and / or radio frequency components, the calibration antenna and / or radio frequency components collect signals and transmit data back to the display and control central processor, and performs calibration of the centering control component and / or radio frequency components.

[0014] Furthermore, it also includes a secondary power supply, which outputs four power signals to provide power to the central control component, the synchronization timing system, the display and control central processing unit, and the radio frequency component, respectively.

[0015] Furthermore, the radio frequency (RF) components are configured with twelve units, each equipped with three RS422 interface communication signals for uplink control, synchronous timing transmission, and self-test signal feedback, respectively. Each RF component includes a photoelectric conversion module for baseband data upload / download, a temperature sensor for onboard temperature monitoring, a TTL / UART module, a JTAG controller, a component operating power supply, and a component thermal control power supply. The TTL / UART module, JTAG controller, component operating power supply, and component thermal control power supply are interconnected with external systems via J30J interfaces. The central control component sends control information to the RF components, including radar operating mode, calibration information, beam-related information, and waveform parameter information.

[0016] In summary, the advantages of this invention are: This invention provides a fully digital phased array antenna system integrating multi-channel radio frequency components. The antenna system comprises an antenna radiating element, a limiting low-noise amplifier module, 32-channel radio frequency components, a central control component, a synchronization and timing system, a display and control central processing unit, and a secondary power supply. The system integrates a highly integrated 32-channel radio frequency component, the operation of which is controlled by the central control component. Each 32-channel radio frequency component integrates an independent 32-channel radio frequency link, an analog-to-digital converter, a programmable logic unit, and an optical fiber transmission module. This antenna system achieves all beamforming and signal processing functions in the digital domain, meeting the requirements of high bandwidth, multi-functionality, high flexibility, and intelligence. Simultaneously with digital domain beamforming and signal processing, clock and data synchronization is performed between and within multiple radio frequency component channels across the entire array based on clock and synchronization signals, enabling simultaneous multi-beamforming without increasing system size, weight, or complexity. Attached Figure Description

[0017] Figure 1 This is a block diagram of the connection of a fully digital phased array antenna system; Figure 2 This is a block diagram of the internal functional modules of a highly integrated 32-channel RF component; Figure 3This is a system block diagram of the internal functional modules of the central control component; Figure 4 Block diagram of multi-channel inter-board synchronization of an all-digital phased array antenna system. Detailed Implementation

[0018] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In this embodiment of the invention, all directional indicators (such as up, down, left, right, front, back, lateral, longitudinal, etc.) are only used to explain the relative positional relationship and movement of each component in a specific posture. If the specific posture changes, the directional indicator will also change accordingly.

[0021] Due to installation errors and other reasons, the parallel relationship referred to in the embodiments of the present invention may actually be an approximate parallel relationship, and the perpendicular relationship may actually be an approximate perpendicular relationship.

[0022] This invention provides a fully digital phased array antenna system integrating multi-channel radio frequency components, such as... Figure 1As shown, the system consists of an antenna radiating element, a limiting low-noise amplifier module, a 32-channel RF receiving component, a central control component, a synchronization and timing system, a display and control / central processing unit (CPU), and a secondary power supply. The all-digital phased array antenna system integrates twelve 32-channel RF components. All RF channel outputs of the RF components are connected to the independent antenna radiating element and limiting low-noise amplifier module via RF cables. The RF components supply power (VCC_5V) to the limiting low-noise amplifier module via low-frequency cables. Data from each channel acquired by the 32-channel RF components is transmitted to the CPU via optical fiber. The CPU contains 12 optical fiber channels. After receiving data from each channel, the CPU performs beamforming and signal processing in the digital domain. The 32-channel RF components and the central control component are interconnected via J30J cables for communication. Each RF component includes a 21-channel low-frequency interface J30J-21. The central control component includes two 51-channel low-frequency interfaces J30J-51, which are interconnected with the RF components via J30J low-frequency cables. Each RF component includes three RS422 interface communication signals, used for uplink control, synchronization timing transmission, and self-test signal feedback, respectively. Each 32-channel RF component inputs one 100MHz clock signal (RF_100MHz) and one 10MHz synchronization signal (SYN_10MHz), generated by the central control component. The RF component power input includes one 12V_1V power supply and one thermal control_18V power supply, with power signals output from the secondary power supply. The 12V_1 power supply powers the various modules within the RF component, while the thermal control_18V power supply powers the thermal control module within the RF component. The synchronization timing system outputs a 100MHz reference clock to the central control component, which generates multi-channel synchronization and clock signals based on the reference clock and outputs them to the twelve 32-channel RF components. The central control component and the synchronization timing system are interconnected via a J30J cable for transmitting 1pps_LVDS signals and RS232_time signal. The central control component and the display and control central processing unit are interconnected via a J30J cable for Ethernet communication. The central control unit outputs eight RF calibration signals to the calibration antenna to achieve system calibration. The secondary power supply outputs four 12V power signals (Power 12V_1, Power 12V_2, Power 12V_3, Power 12V_4) and one thermal control 18V signal to power the central control group, the synchronization and timing system, the display and control central processor, and the twelve 32-channel RF components.

[0023] The system block diagram of the 32-channel receiver component is as follows: Figure 2As shown, the system integrates 32 independent RF front-end links, each consisting of an amplifier (LNA), mixer, filter (LPF), analog-to-digital converter (ADC), and baseband signal processing module. The RF signals of the 32-channel RF components are interconnected with the RF front-end links via an SMP (Surface Mount Technology) interface. The digital domain uses an FPGA to sample the baseband data from the receiving channels. The RF components internally integrate a JFM7K325TFFG900 FPGA, configured with 4Gbit DDR3 memory and FLASH. The reference clock and synchronization signals for the 32-channel RF components are output from the central control component, input through an SMP connector, and then distributed through a clock power divider network and the FPGA's on-chip synchronization network before being output to each RF front-end link to achieve synchronization of the 32 receiving channels within the component. The 32-channel RF components internally integrate a 4-receive, 4-light-to-electric converter module with a transmission rate of up to 10Gbps, and interconnect with external components via a miniaturized MT connector, supporting the data throughput of the 32-channel components. To detect characteristic values ​​such as power and temperature of the RF front-end circuit, the component is equipped with an internal temperature sensor for real-time monitoring of the board temperature. The system also includes a TTL / UART module for external interconnection via a J30J connector; a JTAG controller for external interconnection via a J30J interface; and one external 12V power supply and one 18V power supply with J30J interfaces. One of these is for component operation, and the other is for component thermal control. The component operation power supply network consists of multiple point-of-load power supplies and voltage regulators, supplying power to the various components within the component.

[0024] The internal functional module block diagram of the central control component is as follows: Figure 3As shown, the main function of the central control unit is system control. It executes control commands, controls the working mode of the 32-channel RF components and the display and control central processing unit, and feeds back the status information of the central control unit and RF components to the display and control central processing unit for monitoring. Simultaneously, it generates calibration signals and clock signals for the timing components. The central control unit consists of modules for clock reception and distribution, display and control command reception and transmission, power supply, calibration signal generation and power division, system temperature feedback, RF interaction RS422 serial port, absolute time RS232 serial port, 1pps reception, working mode transmission, and reception feedback status. The central control unit integrates FPGA, DAC, clock distributor, and power division network. The FPGA is used for protocol calculation, calibration control, timing synchronization, sending information to the RF, and receiving RF feedback status. The central control unit receives a 100MHz reference clock from the synchronization and timing system through an SMP connector. After balun conversion, it is input to the internal clock distributor to generate the timing reference clock for this operation. The clock distributor inputs the 100MHz clock signal to the FPGA for synchronization and outputs it to the SMP connector through a multi-stage clock distributor for RF component synchronization. The central control unit receives the 1pps signal and absolute time signal from the synchronization and timing system via the J30J-9ZK connector to determine the predetermined absolute time for radar operation. The central control unit receives the absolute time calculated by the synchronization and timing unit and distributes it to the twelve 32-channel RF components via two J30J-51ZK connectors (XS1 and XS2) containing 51 signals each. The central control unit operates according to the absolute time, triggering an operation when the absolute time arrives, completing the first synchronization operation. It can then infer the arrival time of the next synchronization moment based on the radar's operating mode and trigger again, thus completing the synchronization timing operation. The central control unit sends control information to the 32-channel RF components via the two J30J-51ZK connectors (XS1 and XS2) containing 51 signals each, including radar operating mode, calibration information, beam-related information, and waveform parameters. The 32-channel RF components feed back their operating status to the central control unit, including whether they successfully received the frame header and their self-test status. The central control unit receives wireless calibration commands from the display and control central processing unit (CPU). The CPU controls the DA module via FPGA to transmit calibration point-frequency signals. After balun conversion, the 1:8 RF switches sequentially open to transmit the signals to the system's calibration antenna. The central control unit also receives RF channel calibration commands from the CPU. The CPU controls the DA module via FPGA to transmit calibration point-frequency signals. After balun conversion and power amplification, the calibration signals are output to the 1:2 and 1:8 power dividers, and simultaneously transmitted to the 32-channel RF component. The RF component acquires the received signals and transmits the data via fiber optic cable to the CPU for amplitude and phase error analysis and calibration.The central control component automatically detects faults and monitors the status of the unit during operation, assists in completing the system's closed-loop autonomous testing function, and sends operational status messages to the central processing unit (CPU) via the network port. The central control component receives instructions from the CPU and controls the system's operating mode. In radar mode, the central control component receives waveform parameter settings from the CPU and sends the packet header and data to the 32-channel RF component. The central control component samples the temperature signals from the 32-channel RF component, monitors its temperature status in real time, receives temperature feedback, and performs control accordingly.

[0025] Antenna system inter-board multi-functional synchronization block diagram as follows Figure 4 As shown, clock and data synchronization between and within the entire array board is achieved by a clock distributor. The 32-channel RF components are synchronized internally using a phase-consistent reference clock REF_CLK network and a synchronization signal SYNC network. The central control component uses a clock distributor with multi-channel synchronization and frequency division forwarding capabilities. Inter-array channel synchronization is achieved by the timing system providing a 100MHz reference clock to the central control component. The internal clock distributor (main 1) of the central control component generates a 100MHz clock signal based on the reference clock and distributes it to clock distributors (secondary 1) to (secondary 6), generating 12 coherent 100MHz clocks, which are then distributed to the 12 32-channel RF components via coaxial cables. Simultaneously, the internal FPGA of the central control component generates a 10MHz reference signal. The internal clock distributor (main 1) distributes the 10MHz synchronization SYNC signal generated by the FPGA to clock distributors (secondary 1) to (secondary 6), generating 12 10MHz synchronization signals, which are then distributed to the 12 32-channel RF components via coaxial cables.

[0026] Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort should fall within the scope of protection of the present invention.

Claims

1. A fully digital phased array antenna system integrating multi-channel radio frequency components, characterized in that, The system includes an antenna radiating unit, a limiting low-noise amplifier module, radio frequency (RF) components, a central control unit, a synchronization and timing system, and a display and control central processing unit. The antenna radiating unit and the limiting low-noise amplifier module are connected to the RF channel output ports of the RF components via RF cables. Multiple RF components, the synchronization and timing system, and the display and control central processing unit are connected to the central control unit via cables to form a communication connection. The synchronization and timing system outputs a reference clock to the central control unit. The central control unit generates a clock signal and a synchronization signal based on the reference clock and outputs them to multiple RF components for synchronization. The display and control central processing unit is connected to the RF components via optical fiber. The display and control central processing unit performs digital domain beamforming and signal processing on the channel data acquired by the RF components.

2. The all-digital phased array antenna system integrating multi-channel radio frequency components according to claim 1, characterized in that, The radio frequency component integrates 32 radio frequency front-end links, which are interconnected with radio frequency signals via SMP connectors. The radio frequency front-end links integrate FPGAs to sample baseband data of the receiving channel in the digital domain.

3. The all-digital phased array antenna system integrating multi-channel radio frequency components according to claim 2, characterized in that, The radio frequency component receives the clock signal and synchronization signal output by the central control component, distributes them through the clock power divider network and the synchronization network, and outputs them to each radio frequency front-end link to achieve synchronization of 32 radio frequency front-end links.

4. The all-digital phased array antenna system integrating multi-channel radio frequency components according to claim 1, characterized in that, The central control component includes an FPGA and a clock distributor. The central control component receives the reference clock from the synchronization timing system, converts it through a balun, and then inputs it to the clock distributor. The clock distributor inputs the clock signal to the FPGA for synchronization, generates a synchronization signal and a clock signal, and outputs them to the radio frequency component for synchronization through a multi-stage clock distributor.

5. The all-digital phased array antenna system integrating multi-channel radio frequency components according to claim 4, characterized in that, The central control component receives the 1pps signal and absolute time signal from the synchronization and timing system to determine the radar's operating basis based on the predetermined absolute time, and distributes them to multiple radio frequency components. When the absolute time arrives, the radio frequency components are triggered to synchronize, and the arrival time of the next synchronization moment is confirmed based on the radar's operating mode. When the next synchronization moment arrives, the radio frequency components are triggered to synchronize again, thus completing the synchronization timing of the radio frequency components.

6. The all-digital phased array antenna system integrating multi-channel radio frequency components according to claim 4, characterized in that, The clock distributor includes a master clock distributor and six slave clock distributors. The master clock distributor generates clock signals and reference signals and distributes them to the six slave clock distributors. The six slave clock distributors generate twelve signals and distribute them to the radio frequency components.

7. The all-digital phased array antenna system integrating multi-channel radio frequency components according to claim 1, characterized in that, The central control unit receives calibration instructions sent by the display and control central processor, outputs radio frequency calibration signals to the calibration antenna and / or radio frequency components, the calibration antenna and / or radio frequency components collect signals and transmit data back to the display and control central processor, and performs calibration on the central control unit and / or radio frequency components.

8. The all-digital phased array antenna system integrating multi-channel radio frequency components according to claim 1, characterized in that, It also includes a secondary power supply, which outputs four power signals to provide power to the central control component, the synchronization timing system, the display and control central processor, and the radio frequency component.

9. A fully digital phased array antenna system integrating multi-channel radio frequency components according to claim 1, characterized in that, The radio frequency (RF) components are configured with twelve units, each equipped with three RS422 interface communication signals for uplink control, synchronous timing transmission, and self-test signal feedback, respectively. Each RF component includes a photoelectric conversion module for baseband data upload / download, a temperature sensor for onboard temperature monitoring, a TTL / UART module, a JTAG controller, a component operating power supply, and a component thermal control power supply. The TTL / UART module, JTAG controller, component operating power supply, and component thermal control power supply are interconnected with external systems via J30J interfaces. The central control component sends control information to the RF components, including radar operating mode, calibration information, beam-related information, and waveform parameter information.

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