Phase loss detection circuit, method, detection equipment and storage medium

Abstract

This application relates to a phase loss detection circuit, method, detection device, and storage medium. The circuit includes a sampling module, a detection module, an analog-to-digital converter (ADC), a judgment module, and a microprocessor. After sampling and detecting the three-phase power signal, the ADC converts the three-phase analog signal into a digital signal. The judgment module then performs logical operations on the obtained digital signal to obtain a signal characterizing whether the three-phase power signal is missing a phase. The microprocessor then performs identification and analysis to output the phase loss detection result. This enables phase loss detection of a three-phase power supply, achieving the technical effect of improving detection efficiency.

Description

Technical Field

[0001] This application relates to the technical field of defect detection, and in particular to a phase loss detection circuit, method, detection device, and storage medium. Background Technology

[0002] With the advancement of mechanization in society, household appliances and large electrical equipment all require a three-phase power supply to provide a safe and stable voltage input in order to ensure the safe and normal operation of high-power equipment. However, due to reasons such as aging of equipment wiring, poor contact of sockets, or circuit damage, the three-phase power supply may experience a phase loss, causing circuit failure or endangering life.

[0003] Power phase loss mainly occurs in three-phase motor units. This fault can occur before startup and during operation, affecting the normal operation of downstream loads. When a phase is lost in a three-phase power supply, the voltage is low, causing downstream stages to malfunction. When a phase is lost in a compressor's three-phase power supply, it can cause overcurrent, thus stopping the compressor from working. Summary of the Invention

[0004] In view of this, in order to solve the technical problem of the difficulty in detecting phase loss faults in three-phase power supplies, this application provides a phase loss detection circuit, method, detection equipment and storage medium.

[0005] In a first aspect, embodiments of this application provide a phase loss detection circuit, including:

[0006] Sampling module, detection module, analog-to-digital converter, judgment module, and microprocessor;

[0007] The first input terminal of the sampling module is connected to the first phase power signal output terminal, the second input terminal is connected to the second phase power signal output terminal, the third input terminal is connected to the third phase power signal output terminal, and the output terminal is connected to the input terminal of the detection module.

[0008] The output of the detection module is connected to the input of the analog-to-digital converter;

[0009] The output of the analog-to-digital converter is connected to the input of the judgment module;

[0010] The first output terminal of the judgment module is connected to the first input terminal of the microprocessor, the second output terminal is connected to the second input terminal of the microprocessor, and the third output terminal is connected to the third input terminal of the microprocessor.

[0011] In one possible implementation, the sampling module samples the input first-phase power signal, second-phase power signal, and third-phase power signal respectively. After the sampling current signal is input, the detection module detects the current signal and outputs a current detection signal to the analog-to-digital converter. The analog-to-digital converter converts the analog signal of the current detection signal into a digital signal of current. After judgment by the judgment module, it outputs a status signal corresponding to the three-phase power signal to the microprocessor, so that the microprocessor can determine the phase loss state of the circuit according to the status signal.

[0012] In one possible implementation, the sampling module includes: a back-end load unit, a first current sampling unit, a second current sampling unit, and a third current sampling unit;

[0013] The first end of the back-end load unit is connected to the first input end of the first current sampling unit, the second end is connected to the first input end of the second current sampling unit, and the third end is connected to the first input end of the third current sampling unit.

[0014] The second input terminal of the first current sampling unit is connected to the output terminal of the first phase power signal, and the output terminal is connected to the first input terminal of the detection module.

[0015] The second input terminal of the second current sampling unit is connected to the output terminal of the second phase power signal, and the output terminal is connected to the second input terminal of the detection module;

[0016] The second input terminal of the third current sampling unit is connected to the output terminal of the third phase power signal, and the output terminal is connected to the third input terminal of the detection module.

[0017] In one possible implementation, the detection module includes: a first detection submodule, a second detection submodule, and a third detection submodule;

[0018] The input terminal of the first detection submodule is connected to the first output terminal of the sampling module, and the output terminal is connected to the first input terminal of the analog-to-digital converter;

[0019] The input terminal of the second detection submodule is connected to the second output terminal of the sampling module, and the output terminal is connected to the second input terminal of the analog-to-digital converter;

[0020] The input terminal of the third detection submodule is connected to the third output terminal of the sampling module, and the output terminal is connected to the third input terminal of the analog-to-digital converter.

[0021] In one possible implementation, the first detection submodule, the second detection submodule, and the third detection submodule have the same structure, and the first detection submodule includes: a first hysteresis comparison unit and a first filtering unit;

[0022] The input terminal of the first hysteresis comparison unit is connected to the first output terminal of the sampling module, and the output terminal is connected to the input terminal of the first filtering unit.

[0023] The output of the first filtering unit is connected to the first input of the analog-to-digital converter;

[0024] The second detection submodule includes: a second hysteresis comparison unit and a second filtering unit;

[0025] The input terminal of the second hysteresis comparison unit is connected to the second output terminal of the sampling module, and the output terminal is connected to the input terminal of the second filtering unit;

[0026] The output of the second filtering unit is connected to the second input of the analog-to-digital converter;

[0027] The third detection submodule includes: a third hysteresis comparison unit and a third filtering unit;

[0028] The input terminal of the third hysteresis comparison unit is connected to the third output terminal of the sampling module, and the output terminal is connected to the input terminal of the third filtering unit.

[0029] The output of the third filtering unit is connected to the third input of the analog-to-digital converter.

[0030] In one possible implementation, the first hysteresis comparator unit includes: a first variable resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first amplifier, and a first Zener diode;

[0031] One end of the first variable resistor is connected to the positive input terminal of the first amplifier and the first output terminal of the sampling module, and the other end is connected to one end of the second resistor and one end of the third resistor;

[0032] The other end of the second resistor is connected to the first ground terminal;

[0033] The other end of the third resistor is connected to one end of the fourth resistor and the inverting input terminal of the first amplifier;

[0034] The other end of the fourth resistor is connected to one end of the fifth resistor;

[0035] The other end of the fifth resistor is connected to the output terminal of the first amplifier, one end of the first Zener diode, and the input terminal of the first filter unit;

[0036] The other end of the first Zener diode is connected to the second ground terminal;

[0037] The first filter unit includes: a sixth resistor and a first capacitor;

[0038] One end of the sixth resistor is connected to the output of the first hysteresis comparator, and the other end is connected to one end of the first capacitor and the first input of the analog-to-digital converter.

[0039] The other end of the first capacitor is connected to the second ground terminal.

[0040] In one possible implementation, the second hysteresis comparator unit includes: a second variable resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a second amplifier, and a second Zener diode;

[0041] One end of the second variable resistor is connected to the positive input terminal of the second amplifier and the second output terminal of the sampling module, and the other end is connected to one end of the seventh resistor and one end of the eighth resistor;

[0042] The other end of the seventh resistor is connected to the third ground terminal;

[0043] The other end of the eighth resistor is connected to one end of the ninth resistor and the inverting input terminal of the second amplifier;

[0044] The other end of the ninth resistor is connected to one end of the tenth resistor;

[0045] The other end of the tenth resistor is connected to the output terminal of the second amplifier, one end of the second Zener diode, and the input terminal of the second filter unit;

[0046] The other end of the second Zener diode is connected to the fourth ground terminal;

[0047] The second filter unit includes: an eleventh resistor and a second capacitor;

[0048] One end of the eleventh resistor is connected to the output terminal of the second hysteresis comparator, and the other end is connected to one end of the second capacitor and the second input terminal of the analog-to-digital converter.

[0049] The other end of the second capacitor is connected to the fourth ground terminal.

[0050] In one possible implementation, the third hysteresis comparator unit includes: a third variable resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third amplifier, and a third Zener diode;

[0051] One end of the third variable resistor is connected to the positive input terminal of the third amplifier and the third output terminal of the sampling module, and the other end is connected to one end of the twelfth resistor and one end of the thirteenth resistor.

[0052] The other end of the twelfth resistor is connected to the fifth ground terminal;

[0053] The other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the inverting input terminal of the third amplifier;

[0054] The other end of the fourteenth resistor is connected to one end of the fifteenth resistor;

[0055] The other end of the fifteenth resistor is connected to the output terminal of the third amplifier, one end of the third Zener diode, and the input terminal of the third filter unit;

[0056] The other end of the third Zener diode is connected to the sixth grounding terminal;

[0057] The third filter unit includes: a sixteenth resistor and a third capacitor;

[0058] One end of the sixteenth resistor is connected to the output terminal of the third hysteresis comparator, and the other end is connected to one end of the third capacitor and the third input terminal of the analog-to-digital converter.

[0059] The other end of the third capacitor is connected to the sixth ground terminal.

[0060] In one possible implementation, the judgment module includes: a first judgment submodule, a second judgment submodule, and a third judgment submodule;

[0061] The first input terminal of the first judgment submodule is connected to the first output terminal of the analog-to-digital converter, the second input terminal is connected to the second output terminal of the analog-to-digital converter, the third input terminal is connected to the third output terminal of the analog-to-digital converter, and the output terminal is connected to the first input terminal of the microprocessor.

[0062] The first input terminal of the second judgment submodule is connected to the second output terminal of the analog-to-digital converter, the second input terminal is connected to the third output terminal of the analog-to-digital converter, the third input terminal is connected to the first output terminal of the analog-to-digital converter, and the output terminal is connected to the second input terminal of the microprocessor.

[0063] The first input terminal of the third judgment submodule is connected to the third output terminal of the analog-to-digital converter, the second input terminal is connected to the first output terminal of the analog-to-digital converter, the third input terminal is connected to the second output terminal of the analog-to-digital converter, and the output terminal is connected to the third input terminal of the microprocessor.

[0064] In one possible implementation, the first judgment submodule, the second judgment submodule, and the third judgment submodule have the same structure, and the first judgment submodule includes: a first XOR gate and a first flip-flop;

[0065] The first input terminal of the first XOR gate is connected to the first output terminal of the analog-to-digital converter, the second input terminal is connected to the second output terminal of the analog-to-digital converter, and the output terminal is connected to the input terminal of the first flip-flop.

[0066] The clock signal input terminal of the first flip-flop is connected to the third output terminal of the analog-to-digital converter, and the output terminal is connected to the first input terminal of the microprocessor.

[0067] The second judgment submodule includes: a second XOR gate and a second flip-flop;

[0068] The first input of the second XOR gate is connected to the second output of the analog-to-digital converter, the second input is connected to the third output of the analog-to-digital converter, and the output is connected to the input of the second flip-flop.

[0069] The clock signal input terminal of the second flip-flop is connected to the first output terminal of the analog-to-digital converter, and the output terminal is connected to the second input terminal of the microprocessor;

[0070] The third judgment submodule includes: a third XOR gate and a third flip-flop;

[0071] The first input terminal of the third XOR gate is connected to the third output terminal of the analog-to-digital converter, the second input terminal is connected to the first output terminal of the analog-to-digital converter, and the output terminal is connected to the input terminal of the third flip-flop.

[0072] The clock signal input terminal of the third flip-flop is connected to the second output terminal of the analog-to-digital converter, and the output terminal is connected to the third input terminal of the microprocessor.

[0073] In a second aspect, embodiments of this application provide a phase loss detection method, applied to any of the phase loss detection circuits described in the first aspect, comprising:

[0074] The initial power signal corresponding to the three-phase power supply is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal.

[0075] The judgment module performs logical operations on the digital signal to obtain the target signal, which represents the power supply phase loss information.

[0076] The phase loss result corresponding to the three-phase power supply is determined based on the target signal.

[0077] In one possible implementation, before performing analog-to-digital conversion on the initial power signal corresponding to the acquired three-phase power supply via the analog-to-digital converter, the method further includes:

[0078] The sampling module is used to collect the first phase sampling signal, the second phase sampling signal, and the third phase sampling signal corresponding to the three-phase power supply.

[0079] Current detection is performed on the first phase sampling signal, the second phase sampling signal, and the third phase sampling signal respectively to obtain the first phase initial power supply signal, the second phase initial power supply signal, and the third phase initial power supply signal of the three-phase power supply.

[0080] In one possible implementation, the step of converting the initial power signal corresponding to the acquired three-phase power supply to a digital signal using an analog-to-digital converter includes:

[0081] The initial power signal of the first phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the first phase.

[0082] The initial power signal of the second phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the second phase.

[0083] The initial power signal of the third phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the third phase.

[0084] In one possible implementation, the step of the judgment module performing logical operations on the digital signal to obtain the target signal includes:

[0085] The first XOR signal is obtained by performing an XOR operation on the first digital signal and the second digital signal through the first XOR gate.

[0086] The first target signal is output after the logic control of the first flip-flop based on the first XOR signal and the third digital signal.

[0087] The second XOR gate is used to perform an XOR operation on the second digital signal and the third digital signal to obtain the corresponding second XOR signal.

[0088] The second target signal is output after the logic control of the second flip-flop based on the second XOR signal and the first digital signal.

[0089] The first digital signal and the third digital signal are XORed by the third XOR gate to obtain the corresponding third XOR signal.

[0090] The third target signal is output after the third XOR signal and the second digital signal are controlled by the logic of the third flip-flop.

[0091] In one possible implementation, determining the phase loss result corresponding to the three-phase power supply based on the target signal includes:

[0092] Determine whether the first target signal is equal to the first phase loss value, simultaneously determine whether the second target signal is equal to the second phase loss value, and determine whether the third target signal is equal to the third phase loss value, and determine the corresponding phase loss result;

[0093] When the first target signal is equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the first phase loss result;

[0094] Based on the first phase loss result, it is determined that the first phase power signal has a phase loss;

[0095] When the first target signal is not equal to the first phase loss value, the second target signal is equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the second phase loss result;

[0096] Based on the second phase loss result, it is determined that there is a phase loss in the second phase power supply signal;

[0097] When the first target signal is not equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is equal to the third phase loss value, the phase loss result is determined to be the third phase loss result;

[0098] Based on the third phase loss result, it is determined that the third phase power signal has a phase loss;

[0099] When the first target signal is not equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the fourth phase loss result;

[0100] Based on the fourth phase loss result, it is determined that the circuit does not have a phase loss.

[0101] Thirdly, embodiments of this application provide a detection device, including: a processor and a memory, wherein the processor is configured to execute a phase loss detection program stored in the memory to implement any of the phase loss detection methods described in the second aspect.

[0102] Fourthly, embodiments of this application provide a storage medium storing one or more programs, which can be executed by one or more processors to implement any of the phase loss detection methods described in the second aspect.

[0103] The phase loss detection circuit provided in this application embodiment comprises a sampling module, a detection module, an analog-to-digital converter (ADC), a judgment module, and a microprocessor. The sampling module has a first input connected to the first phase power signal output, a second input connected to the second phase power signal output, a third input connected to the third phase power signal output, and an output connected to the input of the detection module. The detection module's output is connected to the input of the ADC. The ADC's output is connected to the input of the judgment module. The judgment module's first output is connected to the first input of the microprocessor, a second output connected to the second input, and a third output connected to the third input. By sampling and detecting the three-phase power signals, the ADC converts the three-phase analog signals into digital signals. The judgment module then performs logical operations on the obtained digital signals to obtain signals characterizing whether a phase is missing in the three-phase power signal. The microprocessor then identifies and analyzes these signals, outputting the phase loss detection result. This solution enables phase loss detection of three-phase power supplies, achieving the technical effect of improving detection efficiency. Attached Figure Description

[0104] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0105] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0106] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0107] Figure 1 This is a schematic diagram of a phase loss detection circuit provided in an embodiment of this application;

[0108] Figure 2 This is a schematic diagram of another phase loss detection circuit provided in an embodiment of this application;

[0109] Figure 3a A waveform diagram of the three-phase sampling current when a three-phase power supply is normally connected, provided in an embodiment of this application;

[0110] Figure 3bA waveform diagram of the sampling current when the U-phase power signal in a three-phase power supply is missing, provided in an embodiment of this application;

[0111] Figure 3c A waveform diagram of the sampling current when the V-phase power signal is missing in a three-phase power supply, provided as an embodiment of this application;

[0112] Figure 3d A waveform diagram of the sampling current when the W-phase power signal is missing in a three-phase power supply, provided as an embodiment of this application;

[0113] Figure 4 A waveform diagram of an analog signal when a three-phase power supply is normally connected, provided in an embodiment of this application;

[0114] Figure 5a A truth table for a first judgment submodule in a phase loss detection circuit provided in an embodiment of this application;

[0115] Figure 5b A truth table for a second judgment submodule in a phase loss detection circuit provided in an embodiment of this application;

[0116] Figure 5c A truth table for a third judgment submodule in a phase loss detection circuit provided in an embodiment of this application;

[0117] Figure 6 This is a schematic diagram of another phase loss detection circuit provided in an embodiment of this application;

[0118] Figure 7 A schematic flowchart illustrating a phase loss detection method provided in an embodiment of this application;

[0119] Figure 8 A schematic flowchart of another phase loss detection method provided in an embodiment of this application;

[0120] Figure 9 This is a schematic diagram of the structure of a testing device provided in an embodiment of this application. Detailed Implementation

[0121] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0122] The terms "comprising" and "having" in the embodiments of this application are used to indicate an open-ended inclusion, meaning that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second," etc., are used only as labels and are not intended to limit the number of objects. Furthermore, the different elements and areas in the drawings are only schematic, therefore this application is not limited to the dimensions or distances shown in the drawings.

[0123] To facilitate understanding of the embodiments of this application, the following will provide further explanation and description with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of this application.

[0124] Figure 1 This is a schematic diagram of a phase loss detection circuit provided in an embodiment of this application. It is applied in the phase loss detection process of three-phase power supply equipment. Figure 1 The provided diagram shows that the phase loss detection circuit specifically includes:

[0125] The system includes a sampling module 11, a detection module 12, an analog-to-digital converter 13, a judgment module 14, and a microprocessor 15.

[0126] The first input terminal of the sampling module 11 is connected to the output terminal of the first phase power signal L1, the second input terminal is connected to the output terminal of the second phase power signal L2, the third input terminal is connected to the output terminal of the third phase power signal L3, and the output terminal is connected to the input terminal of the detection module 12.

[0127] The output of the detection module 12 is connected to the input of the analog-to-digital converter 13.

[0128] The output of analog-to-digital converter 13 is connected to the input of judgment module 14.

[0129] The first output terminal of the judgment module 14 is connected to the first input terminal of the microprocessor 15, the second output terminal is connected to the second input terminal of the microprocessor 15, and the third output terminal is connected to the third input terminal of the microprocessor 15.

[0130] The sampling module 11 samples the first phase power signal L1, the second phase power signal L2, and the third phase power signal L3 respectively. The detection module 12 detects the current signal after it is sampled and outputs the current detection signal to the analog-to-digital converter 13. The analog-to-digital converter 13 converts the analog signal of the current detection signal into a digital signal of the current. After the judgment module 14 makes a judgment, it outputs the status signal corresponding to the three-phase power signal to the microprocessor 15 so that the microprocessor 15 can determine the phase loss state of the circuit according to the status signal.

[0131] Furthermore, the sampling module 11 samples the current of the input first-phase power signal L1, second-phase power signal L2, and third-phase power signal L3 respectively to obtain sampled current signals. After the detection module 12 detects and amplifies the sampled current signals, it outputs three analog signals corresponding to the three-phase power supply. After analog-to-digital conversion by the analog-to-digital converter 13, the three analog signals corresponding to the three-phase power supply are converted into three digital signals. The three digital signals are then logically judged to output three judgment signals. The judgment signal representing the phase loss state is input to the microprocessor 15. After analysis and judgment by the microprocessor 15, it is determined whether there is a phase loss phenomenon in the current circuit. Furthermore, according to the pre-set rules, the phase loss is located based on the different values ​​of the three judgment signals, thereby achieving the purpose of detecting whether there is a phase loss phenomenon in the three-phase power supply and locating the defect, thus realizing the phase loss detection of the three-phase power supply and achieving the technical effect of improving the detection efficiency.

[0132] The phase loss detection circuit provided in this application embodiment comprises a sampling module, a detection module, an analog-to-digital converter (ADC), a judgment module, and a microprocessor. The sampling module has its first input connected to the first phase power signal output, its second input connected to the second phase power signal output, its third input connected to the third phase power signal output, and its output connected to the input of the detection module. The detection module's output is connected to the input of the ADC. The ADC's output is connected to the input of the judgment module. The judgment module's first output is connected to the first input of the microprocessor, its second output connected to the second input, and its third output connected to the third input. After sampling and detecting the three-phase power signals, the ADC converts the three-phase analog signals into digital signals. The judgment module then performs logical operations on the obtained digital signals to obtain signals characterizing whether a phase is missing in the three-phase power signal. The microprocessor then identifies and analyzes these signals, outputting the phase loss detection result. This solution enables phase loss detection of three-phase power supplies, achieving the technical effect of improving detection efficiency.

[0133] In one possible implementation, the sampling module includes: a back-end load unit, a first current sampling unit, a second current sampling unit, and a third current sampling unit; a first terminal of the back-end load unit is connected to a first input terminal of the first current sampling unit, a second terminal is connected to a first input terminal of the second current sampling unit, and a third terminal is connected to a first input terminal of the third current sampling unit; a second input terminal of the first current sampling unit is connected to an output terminal of the first phase power signal, and an output terminal is connected to a first input terminal of the detection module; a second input terminal of the second current sampling unit is connected to an output terminal of the second phase power signal, and an output terminal is connected to a second input terminal of the detection module; a second input terminal of the third current sampling unit is connected to an output terminal of the third phase power signal, and an output terminal is connected to a third input terminal of the detection module.

[0134] In one possible implementation, the detection module includes: a first detection submodule, a second detection submodule, and a third detection submodule; the input terminal of the first detection submodule is connected to the first output terminal of the sampling module, and the output terminal is connected to the first input terminal of the analog-to-digital converter; the input terminal of the second detection submodule is connected to the second output terminal of the sampling module, and the output terminal is connected to the second input terminal of the analog-to-digital converter; the input terminal of the third detection submodule is connected to the third output terminal of the sampling module, and the output terminal is connected to the third input terminal of the analog-to-digital converter.

[0135] In one possible implementation, the first detection submodule, the second detection submodule, and the third detection submodule have the same structure. The first detection submodule includes: a first hysteresis comparison unit and a first filtering unit; the input terminal of the first hysteresis comparison unit is connected to the first output terminal of the sampling module, and the output terminal is connected to the input terminal of the first filtering unit; the output terminal of the first filtering unit is connected to the first input terminal of the analog-to-digital converter. The second detection submodule includes: a second hysteresis comparison unit and a second filtering unit; the input terminal of the second hysteresis comparison unit is connected to the second output terminal of the sampling module, and the output terminal is connected to the input terminal of the second filtering unit; the output terminal of the second filtering unit is connected to the second input terminal of the analog-to-digital converter. The third detection submodule includes: a third hysteresis comparison unit and a third filtering unit; the input terminal of the third hysteresis comparison unit is connected to the third output terminal of the sampling module, and the output terminal is connected to the input terminal of the third filtering unit; the output terminal of the third filtering unit is connected to the third input terminal of the analog-to-digital converter.

[0136] In one possible implementation, the first hysteresis comparator unit includes: a first variable resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first amplifier, and a first Zener diode; one end of the first variable resistor is connected to the positive input terminal of the first amplifier and the first output terminal of the sampling module, and the other end is connected to one end of the second resistor and one end of the third resistor; the other end of the second resistor is connected to a first ground terminal; the other end of the third resistor is connected to one end of the fourth resistor and the inverting input terminal of the first amplifier; the other end of the fourth resistor is connected to one end of the fifth resistor; the other end of the fifth resistor is connected to the output terminal of the first amplifier, one end of the first Zener diode, and the input terminal of the first filter unit; the other end of the first Zener diode is connected to a second ground terminal; the first filter unit includes: a sixth resistor and a first capacitor; one end of the sixth resistor is connected to the output terminal of the first hysteresis comparator unit, and the other end is connected to one end of the first capacitor and the first input terminal of the analog-to-digital converter; the other end of the first capacitor is connected to a second ground terminal.

[0137] In one possible implementation, the second hysteresis comparator unit includes: a second variable resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a second amplifier, and a second Zener diode; one end of the second variable resistor is connected to the positive input terminal of the second amplifier and the second output terminal of the sampling module, and the other end is connected to one end of the seventh resistor and one end of the eighth resistor; the other end of the seventh resistor is connected to a third ground terminal; the other end of the eighth resistor is connected to one end of the ninth resistor and the inverting input terminal of the second amplifier; the other end of the ninth resistor is connected to one end of the tenth resistor; the other end of the tenth resistor is connected to the output terminal of the second amplifier, one end of the second Zener diode, and the input terminal of the second filter unit; the other end of the second Zener diode is connected to a fourth ground terminal; the second filter unit includes: an eleventh resistor and a second capacitor; one end of the eleventh resistor is connected to the output terminal of the second hysteresis comparator unit, and the other end is connected to one end of the second capacitor and the second input terminal of the analog-to-digital converter; the other end of the second capacitor is connected to the fourth ground terminal.

[0138] In one possible implementation, the third hysteresis comparator unit includes: a third variable resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third amplifier, and a third Zener diode; one end of the third variable resistor is connected to the positive input terminal of the third amplifier and the third output terminal of the sampling module, and the other end is connected to one end of the twelfth resistor and one end of the thirteenth resistor; the other end of the twelfth resistor is connected to the fifth ground terminal; the other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the inverting input terminal of the third amplifier; the other end of the fourteenth resistor is connected to one end of the fifteenth resistor; the other end of the fifteenth resistor is connected to the output terminal of the third amplifier, one end of the third Zener diode, and the input terminal of the third filter unit; the other end of the third Zener diode is connected to the sixth ground terminal; the third filter unit includes: a sixteenth resistor and a third capacitor; one end of the sixteenth resistor is connected to the output terminal of the third hysteresis comparator unit, and the other end is connected to one end of the third capacitor and the third input terminal of the analog-to-digital converter; the other end of the third capacitor is connected to the sixth ground terminal.

[0139] In one possible implementation, the judgment module includes: a first judgment submodule, a second judgment submodule, and a third judgment submodule; the first judgment submodule has a first input terminal connected to a first output terminal of the analog-to-digital converter (ADC), a second input terminal connected to a second output terminal of the ADC, a third input terminal connected to a third output terminal of the ADC, and an output terminal connected to a first input terminal of the microprocessor; the second judgment submodule has a first input terminal connected to a second output terminal of the ADC, a second input terminal connected to a third output terminal of the ADC, a third input terminal connected to a first output terminal of the ADC, and an output terminal connected to a second input terminal of the microprocessor; the third judgment submodule has a first input terminal connected to a third output terminal of the ADC, a second input terminal connected to a first output terminal of the ADC, a third input terminal connected to a second output terminal of the ADC, and an output terminal connected to a third input terminal of the microprocessor.

[0140] In one possible implementation, the first, second, and third judgment submodules have the same structure. The first judgment submodule includes: a first XOR gate and a first flip-flop; the first input of the first XOR gate is connected to the first output of the analog-to-digital converter (ADC), the second input is connected to the second output of the ADC, and the output is connected to the input of the first flip-flop; the clock signal input of the first flip-flop is connected to the third output of the ADC, and the output is connected to the first input of the microprocessor. The second judgment submodule includes: a second XOR gate and a second flip-flop; the first input of the second XOR gate is connected to the second output of the ADC, the second input is connected to the third output of the ADC, and the output is connected to the input of the second flip-flop; the clock signal input of the second flip-flop is connected to the first output of the ADC, and the output is connected to the second input of the microprocessor. The third judgment submodule includes: a third XOR gate and a third flip-flop; the first input of the third XOR gate is connected to the third output of the ADC, the second input is connected to the first output of the ADC, and the output is connected to the input of the third flip-flop; the clock signal input of the third flip-flop is connected to the second output of the ADC, and the output is connected to the third input of the microprocessor.

[0141] The following description will be based on an example of a sampling module including a back-end load unit, a first current sampling unit, a second current sampling unit, and a third current sampling unit; a detection module including a first detection submodule, a second detection submodule, and a third detection submodule; an analog-to-digital converter; and a judgment module including a first judgment submodule, a second judgment submodule, and a third judgment submodule, and a microprocessor. Figure 2 This is a schematic diagram of another phase loss detection circuit provided in an embodiment of this application. Figure 2 This is based on the previous embodiment. Figure 2The provided diagram shows that the phase loss detection circuit specifically includes:

[0142] The system includes a sampling module 11, a detection module 12, an analog-to-digital converter 13, a judgment module 14, and a microprocessor 15.

[0143] according to Figure 2 The provided diagram shows that the sampling module 11 in the phase loss detection circuit includes: a back-end load unit 111, a first current sampling unit 112, a second current sampling unit 113, and a third current sampling unit 114.

[0144] The first end of the back-end load unit 111 is connected to the first input end of the first current sampling unit 112, the second end is connected to the first input end of the second current sampling unit 113, and the third end is connected to the first input end of the third current sampling unit 114.

[0145] The second input terminal of the first current sampling unit 112 is connected to the output terminal of the first phase power signal L1, and the output terminal is connected to the first input terminal of the detection module 12.

[0146] The second input terminal of the second current sampling unit 113 is connected to the output terminal of the second phase power signal L2, and the output terminal is connected to the second input terminal of the detection module 12.

[0147] The second input terminal of the third current sampling unit 114 is connected to the output terminal of the third phase power signal L3, and the output terminal is connected to the third input terminal of the detection module 12.

[0148] To avoid sampling errors caused by a single cycle, sampling is performed over three cycles. Therefore, the sampling module collects signals for a total of three cycles.

[0149] Furthermore, the first phase power signal L1 in the three-phase power signal is sampled by the first current sampling unit 112 to obtain the first phase sampling current IU. Similarly, the second phase power signal L2 is sampled by the second current sampling unit 113 to obtain the second phase sampling current IV, and the third phase power signal L3 is sampled by the third current sampling unit 114 to obtain the third phase sampling current IW. The detection module detects and amplifies the three sampled currents and outputs the corresponding first-phase analog signal, second-phase analog signal, and third-phase analog signal. These are then converted to digital signals by the analog-to-digital converter 13 to obtain the first-phase digital signal, second-phase digital signal, and third-phase digital signal. The judgment module performs logical judgment on the three digital signals to obtain three judgment signals. Different judgment results are set according to the different values ​​of the obtained judgment signals to represent different phase loss results. The microprocessor sends a control signal to block the three-phase power supply from power failure, thereby achieving the purpose of protecting the circuit safety. This demonstrates the technical effect of phase loss location in the three-phase power supply phase loss detection process.

[0150] according to Figure 2 The provided diagram shows that the detection module 12 in the phase loss detection circuit includes: a first detection submodule 121, a second detection submodule 122, and a third detection submodule 123.

[0151] The input terminal of the first detection submodule 121 is connected to the first output terminal of the sampling module 11, and the output terminal is connected to the first input terminal of the analog-to-digital converter 13.

[0152] The input terminal of the second detection submodule 122 is connected to the second output terminal of the sampling module 11, and the output terminal is connected to the second input terminal of the analog-to-digital converter 13.

[0153] The input terminal of the third detection submodule 123 is connected to the third output terminal of the sampling module 11, and the output terminal is connected to the third input terminal of the analog-to-digital converter 13.

[0154] Furthermore, the three signals of the three-phase power supply are processed by the sampling module 11 to output three sampled current signals. These three sampled current signals are then input into the detection module 12 for current detection. Specifically, the first sampled current signal is input into the first detection submodule 121 for current detection and amplification, outputting a stable first-phase analog signal X1. Similarly, the second sampled current signal is input into the second detection submodule 122 for current detection and amplification, outputting a stable second-phase analog signal X2. The third sampled current signal is input into the third detection submodule 123 for current detection and amplification, outputting a stable third-phase analog signal X3. The first-phase analog signal X1 is then converted to digital signal U1 using the analog-to-digital converter 13. Similarly, the second-phase analog signal X2 is converted to digital signal U2 using the analog-to-digital converter 13. Finally, the third-phase analog signal X3 is converted to digital signal U3 using the analog-to-digital converter 13. The judgment module then performs logical judgments on the three digital signals to obtain three judgment signals, which represent the current phase loss state of the circuit and further locate the phase loss according to different set reference values, thereby realizing the phase loss detection of the three-phase power supply.

[0155] according to Figure 2 The provided diagram shows that the judgment module 14 in the phase loss detection circuit includes: a first judgment submodule 141, a second judgment submodule 142, and a third judgment submodule 143.

[0156] The first input terminal of the first judgment submodule 141 is connected to the first output terminal of the analog-to-digital converter 13, the second input terminal is connected to the second output terminal of the analog-to-digital converter 13, the third input terminal is connected to the third output terminal of the analog-to-digital converter 13, and the output terminal is connected to the first input terminal of the microprocessor 15.

[0157] The first input terminal of the second judgment submodule 142 is connected to the second output terminal of the analog-to-digital converter 13, the second input terminal is connected to the third output terminal of the analog-to-digital converter 13, the third input terminal is connected to the first output terminal of the analog-to-digital converter 13, and the output terminal is connected to the second input terminal of the microprocessor 15.

[0158] The first input terminal of the third judgment submodule 143 is connected to the third output terminal of the analog-to-digital converter 13, the second input terminal is connected to the first output terminal of the analog-to-digital converter 13, the third input terminal is connected to the second output terminal of the analog-to-digital converter 13, and the output terminal is connected to the third input terminal of the microprocessor 15.

[0159] Furthermore, the analog-to-digital converter 13 outputs a first-phase digital signal U1, a second-phase digital signal U2, and a third-phase digital signal U3. The first judgment submodule then performs logical operations on these three digital signals. For example, it performs an XOR operation on the first and second-phase digital signals to obtain the first-phase XOR result. This first-phase XOR result is then compared with the third-phase digital signal to trigger a judgment, outputting a first-phase judgment signal Q1. Similarly, the second judgment submodule performs an XOR operation and triggers a judgment on the three digital signals to output a second-phase judgment signal Q2. The third judgment submodule performs an XOR operation and triggers a judgment on the three digital signals to output a third-phase judgment signal Q3. The values ​​of the three judgment signals represent different phase loss states. For example, setting Q1 = 1, Q2 = 0, and Q3 = 0 indicates a phase loss in the first-phase power signal; setting Q1 = 0, Q2 = 1, and Q3 = 0 indicates a phase loss in the second-phase power signal; and setting Q1 = 0, Q2 = 0, and Q3 = 1 indicates a phase loss in the third-phase power signal. The opposite values ​​can also be set using this method. Furthermore, based on the different values ​​of the three judgment signals obtained by the microprocessor 15, the current phase loss state of the circuit is analyzed, thereby realizing the phase loss detection of the three-phase power supply and achieving the technical effect of improving detection efficiency.

[0160] The following will describe the back-end load unit, first sampling unit, second sampling unit, and third sampling unit. The first detection submodule includes: a first hysteresis comparison unit and a first filtering unit; the second detection submodule includes: a second hysteresis comparison unit and a second filtering unit; the third detection submodule includes: a third hysteresis comparison unit and a third filtering unit; the first hysteresis comparison unit includes: a first variable resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first amplifier, and a first Zener diode; the second hysteresis comparison unit includes: a second variable resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a second amplifier, and... The second Zener diode, the third hysteresis comparator unit includes: a third variable resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third amplifier, and a third Zener diode; the first filter unit includes: a sixth resistor and a first capacitor; the second filter unit includes: an eleventh resistor and a second capacitor; the third filter unit includes: a sixteenth resistor and a third capacitor; the analog-to-digital converter, the first judgment submodule includes: a first XOR gate and a first flip-flop; the second judgment submodule includes: a second XOR gate and a second flip-flop; the third judgment submodule includes: a third XOR gate and a third flip-flop; and the microprocessor will be used as an example for introduction. Figure 6 This is a schematic diagram of another phase loss detection circuit provided in an embodiment of this application. Figure 6 This is based on the first embodiment. Figure 6 The provided diagram shows that the phase loss detection circuit specifically includes:

[0161] The back-end load unit 111, the first sampling unit 112, the second sampling unit 113, the third sampling unit 114, the first detection submodule 121, the second detection submodule 122, the third detection submodule 123, the analog-to-digital converter 13, the first judgment submodule 141, the second judgment submodule 142, the third judgment submodule 143, and the microprocessor MCU.

[0162] according to Figure 6 The provided diagram shows that the first detection submodule 121, the second detection submodule 122, and the third detection submodule 123 in the phase loss detection circuit have the same structure. The first detection submodule 121 includes: a first hysteresis comparison unit 211 and a first filtering unit 212.

[0163] The input terminal of the first hysteresis comparison unit 211 is connected to the first output terminal of the sampling module 11, and the output terminal is connected to the input terminal of the first filtering unit 212.

[0164] The output of the first filter unit 212 is connected to the first input of the analog-to-digital converter 13.

[0165] The second detection submodule 122 includes: a second hysteresis comparison unit 221 and a second filtering unit 222.

[0166] The input terminal of the second hysteresis comparison unit 221 is connected to the second output terminal of the sampling module 11, and the output terminal is connected to the input terminal of the second filtering unit 222.

[0167] The output of the second filter unit 222 is connected to the second input of the analog-to-digital converter 13.

[0168] The third detection submodule 123 includes: a third hysteresis comparison unit 231 and a third filtering unit 232.

[0169] The input terminal of the third hysteresis comparison unit 231 is connected to the third output terminal of the sampling module 11, and the output terminal is connected to the input terminal of the third filtering unit 232.

[0170] The output of the third filter unit 232 is connected to the third input of the analog-to-digital converter 13.

[0171] Furthermore, according to Figure 6 The provided diagram shows that the three-phase power signals undergo current sampling processing by a sampling module. Specifically, the first-phase power signal L1 is sampled to obtain the first-phase sampling current IU, the second-phase power signal L2 is sampled to obtain the second-phase sampling current IV, and the third-phase power signal L3 is sampled to obtain the third-phase sampling current IW. After the first-phase sampling current IU is amplified by the first hysteresis comparator 211, it is filtered by the first filter unit 212 to obtain a stable first-phase analog signal X1. Similarly, after the second-phase sampling current IV is amplified by the second hysteresis comparator 221, it is filtered by the second filter unit 222 to obtain a stable second-phase analog signal X2. After the third-phase sampling current IW is amplified by the third hysteresis comparator 231, it is filtered by the third filter unit 232 to obtain a stable third-phase analog signal X3. The analog-to-digital converter converts the first-phase analog signal X1 into the first-phase digital signal U1, the second-phase analog signal X2 into the second-phase digital signal U2, and the third-phase analog signal X3 into the third-phase digital signal U3. After performing logical judgment on the three digital signals, a judgment signal representing the phase loss state is output and transmitted to the microprocessor MCU for analysis and output control signal to achieve the purpose of protecting the circuit and realizing the purpose of phase loss detection of three-phase power supply.

[0172] according to Figure 6 The provided diagram shows that the first hysteresis comparison unit 211 in the phase loss detection circuit includes: a first variable resistor R11, a second resistor R12, a third resistor R13, a fourth resistor R14, a fifth resistor R15, a first amplifier T1, and a first Zener diode VD1.

[0173] One end of the first variable resistor R11 is connected to the positive input terminal of the first amplifier T1 and the first output terminal of the sampling module 11, and the other end is connected to one end of the second resistor R12 and one end of the third resistor R13.

[0174] The other end of the second resistor R12 is connected to the first ground terminal.

[0175] The other end of the third resistor R13 is connected to one end of the fourth resistor R14 and the inverting input terminal of the first amplifier T1.

[0176] The other end of the fourth resistor R14 is connected to one end of the fifth resistor R15.

[0177] The other end of the fifth resistor R15 is connected to the output of the first amplifier T1, one end of the first Zener diode VD1, and the input of the first filter unit 212.

[0178] The other end of the first Zener diode VD1 is connected to the second ground terminal.

[0179] The first filter unit 212 includes: a sixth resistor R16 and a first capacitor C1.

[0180] One end of the sixth resistor R16 is connected to the output of the first hysteresis comparator 211, and the other end is connected to one end of the first capacitor C1 and the first input of the analog-to-digital converter 13.

[0181] The other end of the first capacitor C1 is connected to the second ground terminal.

[0182] according to Figure 6 The provided diagram shows that the second hysteresis comparison unit 221 in the phase loss detection circuit includes: a second variable resistor R21, a seventh resistor R22, an eighth resistor R23, a ninth resistor R24, a tenth resistor R25, a second amplifier T2, and a second Zener diode VD2.

[0183] One end of the second variable resistor R21 is connected to the positive input terminal of the second amplifier T2 and the second output terminal of the sampling module 11, and the other end is connected to one end of the seventh resistor R22 and one end of the eighth resistor R23.

[0184] The other end of the seventh resistor R22 is connected to the third ground terminal.

[0185] The other end of the eighth resistor R23 is connected to one end of the ninth resistor R24 ​​and the inverting input of the second amplifier T2.

[0186] The other end of the ninth resistor R24 ​​is connected to one end of the tenth resistor R25.

[0187] The other end of the tenth resistor R25 is connected to the output of the second amplifier T2, one end of the second Zener diode VD2, and the input of the second filter unit 222.

[0188] The other end of the second Zener diode VD2 is connected to the fourth ground terminal.

[0189] The second filter unit 222 includes: an eleventh resistor R26 and a second capacitor C2.

[0190] One end of the eleventh resistor R26 is connected to the output of the second hysteresis comparator 221, and the other end is connected to one end of the second capacitor C2 and the second input of the analog-to-digital converter 13.

[0191] The other end of the second capacitor C2 is connected to the fourth ground terminal.

[0192] according to Figure 6 The provided diagram shows that the third hysteresis comparison unit 231 in the phase loss detection circuit includes: a third variable resistor R31, a twelfth resistor R32, a thirteenth resistor R33, a fourteenth resistor R34, a fifteenth resistor R35, a third amplifier T3, and a third Zener diode VD3.

[0193] One end of the third variable resistor R31 is connected to the positive input terminal of the third amplifier T3 and the third output terminal of the sampling module 11, and the other end is connected to one end of the twelfth resistor R32 and one end of the thirteenth resistor R33.

[0194] The other end of the twelfth resistor R32 is connected to the fifth ground terminal.

[0195] The other end of the thirteenth resistor R33 is connected to one end of the fourteenth resistor R34 and the inverting input of the third amplifier T3.

[0196] The other end of the fourteenth resistor R34 is connected to one end of the fifteenth resistor R35.

[0197] The other end of the fifteenth resistor R35 is connected to the output of the third amplifier T3, one end of the third Zener diode VD3, and the input of the third filter unit 232.

[0198] The other end of the third Zener diode VD3 is connected to the sixth ground terminal.

[0199] The third filter unit 232 includes: a sixteenth resistor R36 and a third capacitor C3.

[0200] One end of the sixteenth resistor R36 is connected to the output of the third hysteresis comparator 231, and the other end is connected to one end of the third capacitor C3 and the third input of the analog-to-digital converter 13.

[0201] The other end of the third capacitor C3 is connected to the sixth ground terminal.

[0202] according to Figure 6 The provided diagram illustrates how the sampling sensor in the first sampling unit of the sampling module samples the second-phase power signal to obtain IU, the sampling sensor in the second sampling unit samples the second-phase power signal to obtain IV, and the sampling sensor in the third sampling unit samples the third-phase power signal to obtain IW. Signal waveforms at different times are acquired for different phase loss states. Figure 3a This application provides a waveform diagram of the three-phase sampling current when a three-phase power supply is normally connected. Figure 3b This application provides a waveform diagram of the sampling current when the U-phase power signal in a three-phase power supply is missing a phase, as shown in the embodiment of the present application. Figure 3c This application provides a waveform diagram of the sampling current when the V-phase power signal is missing in a three-phase power supply. Figure 3d The waveform diagram of the sampling current when the W-phase power signal is missing in a three-phase power supply provided in this application embodiment.

[0203] Furthermore, the three signals corresponding to the three-phase power supply signals are sampled and then enter the first hysteresis comparison unit, the second hysteresis comparison unit, and the third hysteresis comparison unit. The first detection submodule, the second detection submodule, and the third detection submodule have the same structure and function. The first variable resistor R11 in the first detection submodule is a sliding rheostat used to determine the base voltage Ua and -Ua of the first amplifier T1. Simultaneously, the non-inverting input of the first amplifier T1 is connected to the output of the sampled current of each phase, and the inverting input is the reference voltage. When the sampled current value is greater than Ua, the first amplifier T1 acts as a hysteresis comparator and outputs a high level; when the sampled current value is less than -Ua, the first amplifier T1 acts as a hysteresis comparator and outputs a low level. The corresponding first filtering unit forms an RC filter circuit through the sixth resistor R16 and the first capacitor C1, providing a stable analog signal output to the analog-to-digital converter.

[0204] The waveform of the corresponding analog signal is as follows: Figure 4 As shown, Figure 4 This application provides a waveform diagram of the analog signal when a three-phase power supply is normally connected. By viewing the waveform diagram, the output waveforms of the first-phase analog signal X1, the second-phase analog signal X2, and the third-phase analog signal X3 corresponding to the time during normal operation can be clearly seen. This provides a reference for determining the logical judgment of the judgment module.

[0205] according to Figure 6 The provided diagram shows that the first judgment submodule 141, the second judgment submodule 142, and the third judgment submodule 143 in the phase loss detection circuit have the same structure. The first judgment submodule 141 includes: a first XOR gate P1 and a first flip-flop D1.

[0206] The first input of the first XOR gate P1 is connected to the first output of the analog-to-digital converter 13, the second input is connected to the second output of the analog-to-digital converter 13, and the output is connected to the input of the first flip-flop D1.

[0207] The clock signal input terminal CLR of the first flip-flop D1 is connected to the third output terminal of the analog-to-digital converter 13, and the output terminal is connected to the first input terminal of the microprocessor MCU.

[0208] The second judgment submodule 142 includes: a second XOR gate P2 and a second flip-flop D2.

[0209] The first input of the second XOR gate P2 is connected to the second output of the analog-to-digital converter 13, the second input is connected to the third output of the analog-to-digital converter 13, and the output is connected to the input of the second flip-flop D2.

[0210] The clock signal input terminal CLR of the second flip-flop D2 is connected to the first output terminal of the analog-to-digital converter 13, and the output terminal is connected to the second input terminal of the microprocessor MCU.

[0211] The third judgment submodule 143 includes: a third XOR gate P3 and a third flip-flop D3.

[0212] The first input of the third XOR gate P3 is connected to the third output of the analog-to-digital converter 13, the second input is connected to the first output of the analog-to-digital converter 13, and the output is connected to the input of the third flip-flop D3.

[0213] The clock signal input terminal CLR of the third flip-flop D3 is connected to the second output terminal of the analog-to-digital converter 13, and the output terminal is connected to the third input terminal of the microprocessor MCU.

[0214] Furthermore, the first, second, and third judgment submodules perform logical operations on the first-phase digital signal U1, the second-phase digital signal U2, and the third-phase digital signal U3 to obtain judgment signals, specifically the first judgment signal Q1, the second judgment signal Q2, and the third judgment signal Q3. The magnitude of these three signals is then used to determine the phase loss situation in the circuit and locate the missing phase. Figure 5a This is a truth table for the first judgment submodule in a phase loss detection circuit provided in an embodiment of this application. Figure 5b This is a truth table for a second judgment submodule in a phase loss detection circuit provided in an embodiment of this application. Figure 5c This is a truth table for a third judgment submodule in a phase loss detection circuit provided in an embodiment of this application.

[0215] In one possible scenario, the first-phase power signal L1, the second-phase power signal L2, and the third-phase power signal L3 are sampled to obtain the first-phase sampled current IU, the second-phase sampled current IV, and the third-phase sampled current IW. These three sampled currents are then input to the corresponding detection modules for the three current sampling channels. After amplification and filtering by the hysteresis comparison and filtering units in the first, second, and third detection submodules, the detection modules output the first-phase analog signal X1, the second-phase analog signal X2, and the third-phase analog signal X3, respectively. Figure 4 The waveforms shown are as follows. Three analog signals are converted by an analog-to-digital converter (e.g., ADC) to output the first-phase digital signal U1, the second-phase digital signal U2, and the third-phase digital signal U3 from the judgment module. These three digital signals undergo logical operations using an XOR gate and a D flip-flop to obtain the final judgment signals, corresponding to the first-phase judgment signal Q1, the second-phase judgment signal Q2, and the third-phase judgment signal Q3. These three digital signals Q1, Q2, and Q3 are input to the microprocessor MCU, which can determine the specific three-phase power supply phase loss condition based on the detected signals.

[0216] When the three-phase power supply is normally connected, the sampled current waveform is as follows: Figure 3a As shown, the current frequencies of each phase are consistent, with a period difference of T / 3. The current sensor in the T / 3 sampling module transmits the detected current signal to the detection module. The reference voltages of the hysteresis comparison unit are Ua and -Ua, respectively. The current sensor output signal is compared with the reference voltage; when it is greater than Ua, it outputs a high level, and when it is less than -Ua, it outputs a low level. The analog voltage signals output by the three phases U, V, and W are as follows: Figure 4 As shown. The voltage signal is converted into a digital high / low level signal by an analog-to-digital converter and input to the digital logic judgment module. When the three-phase power supply is normally connected, the truth tables of the three judgment circuits are as follows: Figure 5a , Figure 5b , Figure 5c As shown, Q1 = Q2 = Q3 = 1, the three-way judgment circuit continuously outputs a high level, and the microprocessor MCU receives the three high-level signals and then judges that the three-phase power supply is normally connected.

[0217] When the first phase U in a three-phase power supply is missing, the sampled current waveform is as follows: Figure 3b As shown, at this time, the analog signal output by the first detection submodule remains 0, and the analog signals output by the second and third detection submodules are as follows: Figure 4As shown by X2 and X3, the analog signals from the three-channel detection submodule are converted from analog to digital and then input to the three-channel judgment submodule for logical judgment. Specifically, when the first phase U is missing, the first-phase digital signal U1 is low. U1 serves as the clock signal for the second flip-flop, causing the second flip-flop to malfunction, resulting in the second-phase judgment signal Q2 remaining continuously at 0. According to... Figure 3b The waveform shows that during the time period t3-t5, the value of IV is greater than Ua, indicating a high level, thus resulting in the second-phase digital signal U2 = 1. Simultaneously, the value of IW is less than -Ua, indicating a low level, thus resulting in the third-phase digital signal U3 = 0 during the t3-t5 time period. Based on the magnitudes of these three values, by searching... Figure 5a The truth table of the first judgment submodule shows that when the clock signal of the first judgment circuit is at its rising edge, the output value XOR1 = 1 is obtained after passing through the first XOR gate, therefore the first phase judgment signal Q1 = 1 is output; according to the lookup... Figure 5c The truth table of the third judgment submodule shows that when the clock signal of the third detection circuit is at its rising edge, the first phase digital signal U1 and the third phase digital signal U3 are XORed by the third XOR gate to obtain XOR3 = 0. Therefore, the third phase judgment signal Q3 = 0 is output. That is, when the three-phase power supply U phase is missing, the judgment signals (Q1, Q2, Q3) received by the microprocessor MCU are 1, 0, and 0 respectively, which serve as the basis for judging the missing phase of the power supply U phase.

[0218] When the second phase V of a three-phase power supply is missing, the sampled current waveform is as follows: Figure 3c As shown, at this time, the analog signal output by the second detection submodule remains 0, and the analog signals output by the first and third detection submodules are as follows: Figure 4 As shown by X1 and X3, the analog signals from the three-channel detection submodule are converted from analog to digital and then input to the three-channel judgment submodule for logical judgment. Specifically, when the second phase V is missing, the second-phase digital signal U2 is low, i.e., U2 = 0. U2 serves as the clock signal for the third flip-flop, causing it to malfunction, resulting in the third-phase judgment signal Q3 remaining continuously at 0. According to... Figure 3c The waveform shows that during the time period t5-t7, the value of IW is greater than Ua, indicating a high level, thus resulting in the third-phase digital signal U3 = 1. Simultaneously, the value of IU is less than -Ua, indicating a low level, thus resulting in the first-phase digital signal having U1 = 0 during the t5-t7 time period. Based on the magnitudes of these three values, by searching... Figure 5a The truth table of the first judgment submodule shows that when the clock signal of the first judgment circuit is at the rising edge, the output value of the first XOR gate after XOR processing of the first phase digital signal U1 and the second phase digital signal U2 is XOR1 = 0, therefore the first phase judgment signal Q1 is output as 0; according to the search... Figure 5bThe truth table of the second judgment submodule shows that when the clock signal of the second detection circuit is at its rising edge, the second phase digital signal U2 and the third phase digital signal U3 are XORed by the second XOR gate to obtain XOR2 = 1, thus outputting the second phase judgment signal Q2 = 1. That is, when the three-phase power supply V phase is missing, the judgment signals (Q1, Q2, Q3) received by the microprocessor MCU are 0, 1, and 0 respectively, which serve as the basis for judging the missing phase of the power supply V phase.

[0219] When the third phase W in a three-phase power supply is missing, the sampled current waveform is as follows: Figure 3d As shown, at this time, the analog signal output by the third detection submodule remains 0, and the analog signals output by the first and second detection submodules are as follows: Figure 4 As shown by X1 and X2, the analog signals from the three-channel detection submodule are converted from analog to digital and then input to the three-channel judgment submodule for logical judgment. Specifically, when the third phase W is missing, the third-phase digital signal U3 is low, i.e., U3 = 0. Phase U3 serves as the clock signal for the first flip-flop, causing it to malfunction, resulting in the first-phase judgment signal Q1 remaining at 0. Figure 3d The waveform shows that during the time period t1-t3, the value of IU is greater than Ua, indicating a high level, thus resulting in the first phase digital signal U1 = 1. Simultaneously, the value of IV is less than -Ua, indicating a low level, thus resulting in the second phase digital signal having U2 = 0 during the t1-t3 time period. Based on the magnitudes of these three values, by searching... Figure 5b The truth table of the second judgment submodule shows that when the clock signal of the second judgment circuit is at the rising edge, the second phase digital signal U2 and the third phase digital signal U3 are XORed to obtain the output value of the second XOR gate XOR2 = 0, therefore the second phase judgment signal Q2 = 0 is output; according to the search... Figure 5c The truth table of the third judgment submodule shows that when the clock signal of the third detection circuit is at its rising edge, the first phase digital signal U1 and the third phase digital signal U3 are XORed by the third XOR gate to obtain XOR3 = 1. Therefore, the third phase judgment signal Q3 = 1 is output. That is, when the three-phase power supply W phase is missing, the judgment signals (Q1, Q2, Q3) received by the microprocessor MCU are 0, 0, and 1 respectively, which serve as the basis for judging the missing phase of the power supply W phase.

[0220] This application provides a phase loss detection circuit. After passing through a sampling module and a detection module, an analog signal is output. An analog-to-digital converter converts the analog signal into a digital signal and inputs it to a judgment module. After logical operations, a corresponding judgment signal is obtained, thereby accurately determining whether a phase loss exists in the three-phase power supply. This achieves phase loss detection of a three-phase power supply, thus improving detection efficiency.

[0221] Figure 7This is a schematic flowchart illustrating a phase loss detection method provided in an embodiment of this application. It is applied during the phase loss detection process. According to... Figure 7 The provided diagram illustrates that the phase loss detection method specifically includes:

[0222] S701. The initial power signal corresponding to the three-phase power supply is collected and converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal.

[0223] This application is used in the phase loss detection process. After the sampling module and the detection module output analog signals, the analog-to-digital converter converts the analog signals into digital signals and inputs them to the logic judgment module. After logical operations, the corresponding judgment signal is obtained, thereby accurately determining whether there is a phase loss in the three-phase power supply.

[0224] S702. The judgment module performs logical operations on the digital signal to obtain the target signal, which represents the power supply phase loss information.

[0225] S703. Determine the phase loss result corresponding to the three-phase power supply based on the target signal.

[0226] The sampling module performs current sampling and current detection on the input first-phase power signal, second-phase power signal, and third-phase power signal (i.e., the initial power signal) to obtain the corresponding analog signals.

[0227] The analog-to-digital converter converts analog signals into digital current signals. After logical judgment by the judgment module, it outputs the target signal corresponding to the three-phase power supply signal to the microprocessor, so that the microprocessor can determine the phase loss state of the circuit according to the target signal.

[0228] The phase loss detection method provided in this application embodiment converts the initial power signal corresponding to the three-phase power supply into a digital signal using an analog-to-digital converter (ADC). A judgment module performs logical operations on the digital signal to obtain a target signal, which represents the phase loss information of the power supply. The phase loss result corresponding to the three-phase power supply is determined based on the target signal. After passing through the sampling module and the detection module, an analog signal is output. The ADC converts the analog signal into a digital signal and inputs it to the judgment module. Logical operations are then performed to obtain the corresponding judgment signal, thereby accurately determining whether a phase loss exists in the three-phase power supply. This method achieves phase loss detection of a three-phase power supply, thus improving detection efficiency.

[0229] Figure 8 This is a flowchart illustrating another phase loss detection method provided in an embodiment of this application. Figure 8 This is based on the previous embodiment. Figure 8 The provided diagram shows that the phase loss detection method also includes:

[0230] S801. The sampling module is used to collect the first phase sampling signal, the second phase sampling signal and the third phase sampling signal corresponding to the three-phase power supply.

[0231] S802. Perform current detection on the first phase sampling signal, the second phase sampling signal and the third phase sampling signal respectively to obtain the first phase initial power supply signal, the second phase initial power supply signal and the third phase initial power supply signal of the three-phase power supply.

[0232] The three-phase power supply mentioned here can be understood as the first-phase power signal L1, the second-phase power signal L2, and the third-phase power signal L3. The first-phase sampling signal is IU, the second-phase sampling signal is IV, and the third-phase sampling signal is IW. The first-phase initial power signal is X1, the second-phase initial power signal is X2, and the third-phase initial power signal is X3.

[0233] Furthermore, by sampling and detecting the first phase power signal L1, the second phase power signal L2, and the third phase power signal L3 in the phase loss detection circuit, the initial power signal of the first phase is X1, the initial power signal of the second phase is X2, and the initial power signal of the third phase is X3.

[0234] S803. The initial power supply signal of the first phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the first phase.

[0235] S804. The initial power supply signal of the second phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the second phase.

[0236] S805: The initial power supply signal of the third phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the third phase.

[0237] The first phase digital signal is referred to as U1, the second phase digital signal as U2, and the third phase digital signal as U3.

[0238] Furthermore, the initial power supply signals X1 (first phase), X2 (second phase), and X3 (third phase) obtained are converted from analog to digital by analog-to-digital converters to obtain the corresponding digital signals U1 (first phase), U2 (second phase), and U3 (third phase). These three digital signals will serve as the basis for the next step of phase loss analysis.

[0239] S806. Perform an XOR operation on the first digital signal and the second digital signal through the first XOR gate to obtain the corresponding first XOR signal.

[0240] S807: Based on the logic control of the first XOR signal and the third digital signal through the first flip-flop, the first target signal is output.

[0241] The first XOR gate mentioned here is P1, and the first XOR signal is XOR1.

[0242] Furthermore, the magnitude of the first target signal is determined by the state of the first flip-flop, which is determined based on the magnitudes of the first XOR signal and the third digital signal. For example, when the first digital signal is 1 and the second digital signal is 0, the first XOR signal is XOR1 = 1, and the output of the first flip-flop is used as the first target signal Q1 = 1.

[0243] S808: Perform an XOR operation on the second digital signal and the third digital signal through the second XOR gate to obtain the corresponding second XOR signal.

[0244] S809: The second target signal is output after the logic control of the second flip-flop based on the second XOR signal and the first digital signal.

[0245] The second XOR gate mentioned here is P2, and the second XOR signal is XOR2.

[0246] Furthermore, the magnitude of the second target signal is determined by the state of the second flip-flop, which is determined based on the magnitudes of the second XOR signal and the first digital signal. For example, when the second digital signal is 0 and the third digital signal is 0, the second XOR signal is XOR2 = 0, and the output of the second flip-flop is then used as the second target signal Q2 = 0.

[0247] S810: Perform an XOR operation on the first digital signal and the third digital signal through the third XOR gate to obtain the corresponding third XOR signal.

[0248] S811 outputs the third target signal based on the logic control of the third XOR signal and the second digital signal through the third flip-flop.

[0249] The third XOR gate mentioned here is P3, and the third XOR signal is XOR3.

[0250] Furthermore, the magnitude of the third target signal is determined by the state of the third flip-flop, which is determined based on the magnitudes of the third XOR signal and the second digital signal. For example, when the first digital signal is 1 and the third digital signal is 0, the third XOR signal is XOR3 = 1, and the output of the third flip-flop is used as the third target signal Q3 = 1.

[0251] S812. Determine whether the first target signal is equal to the first phase loss value, and at the same time determine whether the second target signal is equal to the second phase loss value, and determine whether the third target signal is equal to the third phase loss value, and determine the corresponding phase loss result.

[0252] S813. When the first target signal is equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the first phase loss result.

[0253] S814. Based on the first phase loss result, it is determined that there is a phase loss in the first phase power supply signal.

[0254] The first phase loss value mentioned here can be understood as a set value, for example, set to 1. When the first target signal is 1, it is determined that the first phase power signal has a phase loss phenomenon. Similarly, a second phase loss value is set as a reference for judging the second target signal. A third phase loss value is set as a reference for judging the third target signal.

[0255] In one possible scenario, the first, second, and third phase loss values ​​are set to 1. When a phase loss occurs in the three-phase power supply, the values ​​corresponding to the first, second, and third target signals are set to 1, 0, and 0 respectively, which are used as the set phase loss values ​​for the first phase of the three-phase power supply signal. This indicates that the first phase of the power supply signal is missing, while the second and third phase power supply signals are output normally. That is, when the first phase of the three-phase power supply is missing, the judgment signals (Q1, Q2, Q3) received by the microprocessor MCU are 1, 0, and 0 respectively, which serve as the basis for judging the U-phase phase loss of the power supply.

[0256] S815. When the first target signal is not equal to the first phase loss value, the second target signal is equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the second phase loss result.

[0257] S816. Based on the second phase loss result, it is determined that there is a phase loss in the second phase power signal.

[0258] In one possible scenario, the first, second, and third phase loss values ​​are set to 1. When a phase loss occurs in the three-phase power supply, the values ​​corresponding to the first, second, and third target signals are set to 0, 1, and 0 respectively, which are used as the set phase loss values ​​for the second phase of the three-phase power supply signal. This indicates that the second phase of the power supply signal is missing, while the first and third phase power supply signals are output normally. That is, when the second phase of the three-phase power supply is missing, the judgment signals (Q1, Q2, Q3) received by the microprocessor MCU are 0, 1, and 0 respectively, which serve as the basis for judging the V-phase of the power supply to be missing.

[0259] S817. When the first target signal is not equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is equal to the third phase loss value, the phase loss result is determined to be the third phase loss result.

[0260] S818. Based on the result of the third phase loss, it is determined that there is a phase loss in the third phase power supply signal.

[0261] In one possible scenario, the first, second, and third phase loss values ​​are set to 1. When a phase loss occurs in the three-phase power supply, the values ​​corresponding to the first, second, and third target signals are set to 0, 0, and 1, respectively, as the set phase loss values ​​for the third phase of the three-phase power supply signal. This indicates that the third phase of the power supply signal is missing, while the first and second phase power supply signals are output normally. That is, when the third phase of the three-phase power supply is missing, the judgment signals (Q1, Q2, Q3) received by the microprocessor MCU are 0, 0, and 1, respectively, which serve as the basis for judging the U-phase phase loss of the power supply.

[0262] S819. When the first target signal is not equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the fourth phase loss result.

[0263] S820: Based on the fourth phase loss result, it is determined that there is no phase loss in the circuit.

[0264] In one possible scenario, the first phase loss value, the second phase loss value, and the third phase loss value are set to 1. When the values ​​of the first target signal, the second target signal, and the third target signal are 1, 1, and 1 respectively, it indicates that the three-phase power supply signal is in a normal state. That is, when the three-phase power supply is operating normally, the judgment signals (Q1, Q2, Q3) received by the microprocessor MCU are 1, 1, and 1 respectively. At this time, the three judgment circuits continuously output high level, and the microprocessor MCU determines that the three-phase power supply is normally connected when it receives the three high level signals.

[0265] This application provides a phase loss detection method. By setting a phase loss value, after sampling and detecting the three-phase power supply signal, an analog-to-digital converter is used to output a digital signal, and then a target signal is obtained through logical judgment. By setting the phase loss value, the phase loss state of the power supply is determined, thereby realizing the phase loss detection of the three-phase power supply and achieving the technical effect of improving detection efficiency.

[0266] Figure 9 This is a schematic diagram of the structure of a detection device provided in an embodiment of this application. Figure 9 The detection device 900 shown includes at least one processor 901, a memory 902, at least one network interface 904, and other user interfaces 903. The various components in the detection device 900 are coupled together via a bus system 905. It is understood that the bus system 905 is used to implement communication between these components. In addition to a data bus, the bus system 905 also includes a power bus, a control bus, and a status signal bus. However, for clarity, ... Figure 9The general labeled all buses as Bus System 905.

[0267] The user interface 903 may include a display, keyboard, or clicking device (e.g., mouse, trackball, touchpad, or touchscreen).

[0268] It is understood that the memory 902 in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 902 described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0269] In some implementations, memory 902 stores elements, executable units or data structures, or subsets thereof, or extended sets thereof: operating system 9021 and application program 9022.

[0270] The operating system 9021 includes various system programs, such as the framework layer, core library layer, and driver layer, used to implement various basic business functions and handle hardware-based tasks. The application program 9022 includes various applications, such as a media player and a browser, used to implement various application functions. The program implementing the method of this application embodiment can be included in the application program 9022.

[0271] In this embodiment, by calling a program or instruction stored in memory 902, specifically a program or instruction stored in application program 9022, processor 901 executes the method steps provided in each method embodiment, including, for example:

[0272] The initial power signals corresponding to the three-phase power supply are converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signals. The digital signals are then subjected to logical operations by a judgment module to obtain the target signal, which represents the phase loss information of the power supply. The phase loss result corresponding to the three-phase power supply is determined based on the target signal.

[0273] The methods disclosed in the embodiments of this application can be applied to or implemented by processor 901. Processor 901 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware or by instructions in the form of software in processor 901. The processor 901 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or can be executed by a combination of hardware and software units in the decoding processor. The software units may be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 902. Processor 901 reads the information in memory 902 and, in conjunction with its hardware, completes the steps of the above method.

[0274] It is understood that the embodiments described herein can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described herein, or combinations thereof.

[0275] For software implementation, the techniques described herein can be implemented by units that perform the functions described herein. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0276] The detection equipment provided in this embodiment can be as follows: Figure 9 The detection device shown can perform the following: Figure 7-8 All steps of the phase loss detection method are then implemented to achieve... Figure 7-8 For details on the technical effectiveness of the phase loss detection method shown, please refer to [link / reference]. Figure 7-8 The relevant descriptions are presented concisely and will not be elaborated upon here.

[0277] This application also provides a storage medium (computer-readable storage medium). This storage medium stores one or more programs. The storage medium may include volatile memory, such as random access memory; it may also include non-volatile memory, such as read-only memory, flash memory, hard disk, or solid-state drive; and it may also include combinations of the above types of memory.

[0278] One or more programs in the storage medium can be executed by one or more processors to implement the phase loss detection method described above, which is executed on the phase loss detection device side.

[0279] The processor is used to execute a phase loss detection program stored in the memory to implement the following steps of the phase loss detection method executed on the phase loss detection device side:

[0280] The initial power signals corresponding to the three-phase power supply are converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signals. The digital signals are then subjected to logical operations by a judgment module to obtain the target signal, which represents the phase loss information of the power supply. The phase loss result corresponding to the three-phase power supply is determined based on the target signal.

[0281] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0282] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0283] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A phase loss detection circuit, characterized in that, include: Sampling module, detection module, analog-to-digital converter, judgment module, and microprocessor; The first input terminal of the sampling module is connected to the first phase power signal output terminal, the second input terminal is connected to the second phase power signal output terminal, the third input terminal is connected to the third phase power signal output terminal, and the output terminal is connected to the input terminal of the detection module. The output of the detection module is connected to the input of the analog-to-digital converter; The output of the analog-to-digital converter is connected to the input of the judgment module; The first output terminal of the judgment module is connected to the first input terminal of the microprocessor, the second output terminal is connected to the second input terminal of the microprocessor, and the third output terminal is connected to the third input terminal of the microprocessor. The judgment module includes: a first judgment submodule, a second judgment submodule, and a third judgment submodule; The sampling module samples the input first-phase power signal, second-phase power signal, and third-phase power signal respectively. The detection module detects the current signal after inputting the sampled current signal and outputs a current detection signal to the analog-to-digital converter. The analog-to-digital converter converts the analog signal of the current detection signal into a digital current signal, which includes a first-phase digital signal, a second-phase digital signal, and a third-phase digital signal. The first judgment submodule performs an XOR operation and trigger judgment on the digital current signal and outputs a first-phase judgment signal. The second judgment submodule performs an XOR operation and trigger judgment on the digital current signal and outputs a second-phase judgment signal. The third judgment submodule performs an XOR operation and trigger judgment on the digital current signal and outputs a third-phase judgment signal. The microprocessor determines the corresponding phase loss state of the circuit based on the values ​​of the three judgment signals.

2. The circuit according to claim 1, characterized in that, The sampling module includes: a back-end load unit, a first current sampling unit, a second current sampling unit, and a third current sampling unit; The first end of the back-end load unit is connected to the first input end of the first current sampling unit, the second end is connected to the first input end of the second current sampling unit, and the third end is connected to the first input end of the third current sampling unit. The second input terminal of the first current sampling unit is connected to the output terminal of the first phase power signal, and the output terminal is connected to the first input terminal of the detection module. The second input terminal of the second current sampling unit is connected to the output terminal of the second phase power signal, and the output terminal is connected to the second input terminal of the detection module; The second input terminal of the third current sampling unit is connected to the output terminal of the third phase power signal, and the output terminal is connected to the third input terminal of the detection module.

3. The circuit according to claim 1, characterized in that, The detection module includes: a first detection submodule, a second detection submodule, and a third detection submodule; The input terminal of the first detection submodule is connected to the first output terminal of the sampling module, and the output terminal is connected to the first input terminal of the analog-to-digital converter; The input terminal of the second detection submodule is connected to the second output terminal of the sampling module, and the output terminal is connected to the second input terminal of the analog-to-digital converter; The input terminal of the third detection submodule is connected to the third output terminal of the sampling module, and the output terminal is connected to the third input terminal of the analog-to-digital converter.

4. The circuit according to claim 3, characterized in that, The first detection submodule, the second detection submodule, and the third detection submodule have the same structure. The first detection submodule includes: a first hysteresis comparison unit and a first filtering unit. The input terminal of the first hysteresis comparison unit is connected to the first output terminal of the sampling module, and the output terminal is connected to the input terminal of the first filtering unit. The output of the first filtering unit is connected to the first input of the analog-to-digital converter; The second detection submodule includes: a second hysteresis comparison unit and a second filtering unit; The input terminal of the second hysteresis comparison unit is connected to the second output terminal of the sampling module, and the output terminal is connected to the input terminal of the second filtering unit; The output of the second filtering unit is connected to the second input of the analog-to-digital converter; The third detection submodule includes: a third hysteresis comparison unit and a third filtering unit; The input terminal of the third hysteresis comparison unit is connected to the third output terminal of the sampling module, and the output terminal is connected to the input terminal of the third filtering unit. The output of the third filtering unit is connected to the third input of the analog-to-digital converter.

5. The circuit according to claim 4, characterized in that, The first hysteresis comparator unit includes: a first variable resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a first amplifier, and a first Zener diode; One end of the first variable resistor is connected to the positive input terminal of the first amplifier and the first output terminal of the sampling module, and the other end is connected to one end of the second resistor and one end of the third resistor; The other end of the second resistor is connected to the first ground terminal; The other end of the third resistor is connected to one end of the fourth resistor and the inverting input terminal of the first amplifier; The other end of the fourth resistor is connected to one end of the fifth resistor; The other end of the fifth resistor is connected to the output terminal of the first amplifier, one end of the first Zener diode, and the input terminal of the first filter unit; The other end of the first Zener diode is connected to the second ground terminal; The first filter unit includes: a sixth resistor and a first capacitor; One end of the sixth resistor is connected to the output of the first hysteresis comparator, and the other end is connected to one end of the first capacitor and the first input of the analog-to-digital converter. The other end of the first capacitor is connected to the second ground terminal.

6. The circuit according to claim 4, characterized in that, The second hysteresis comparator unit includes: a second variable resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a second amplifier, and a second Zener diode; One end of the second variable resistor is connected to the positive input terminal of the second amplifier and the second output terminal of the sampling module, and the other end is connected to one end of the seventh resistor and one end of the eighth resistor; The other end of the seventh resistor is connected to the third ground terminal; The other end of the eighth resistor is connected to one end of the ninth resistor and the inverting input terminal of the second amplifier; The other end of the ninth resistor is connected to one end of the tenth resistor; The other end of the tenth resistor is connected to the output terminal of the second amplifier, one end of the second Zener diode, and the input terminal of the second filter unit; The other end of the second Zener diode is connected to the fourth ground terminal; The second filter unit includes: an eleventh resistor and a second capacitor; One end of the eleventh resistor is connected to the output terminal of the second hysteresis comparator, and the other end is connected to one end of the second capacitor and the second input terminal of the analog-to-digital converter. The other end of the second capacitor is connected to the fourth ground terminal.

7. The circuit according to claim 4, characterized in that, The third hysteresis comparator unit includes: a third variable resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a fifteenth resistor, a third amplifier, and a third Zener diode; One end of the third variable resistor is connected to the positive input terminal of the third amplifier and the third output terminal of the sampling module, and the other end is connected to one end of the twelfth resistor and one end of the thirteenth resistor. The other end of the twelfth resistor is connected to the fifth ground terminal; The other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the inverting input terminal of the third amplifier; The other end of the fourteenth resistor is connected to one end of the fifteenth resistor; The other end of the fifteenth resistor is connected to the output terminal of the third amplifier, one end of the third Zener diode, and the input terminal of the third filter unit; The other end of the third Zener diode is connected to the sixth grounding terminal; The third filter unit includes: a sixteenth resistor and a third capacitor; One end of the sixteenth resistor is connected to the output terminal of the third hysteresis comparator, and the other end is connected to one end of the third capacitor and the third input terminal of the analog-to-digital converter. The other end of the third capacitor is connected to the sixth ground terminal.

8. The circuit according to claim 1, characterized in that, The first input terminal of the first judgment submodule is connected to the first output terminal of the analog-to-digital converter, the second input terminal is connected to the second output terminal of the analog-to-digital converter, the third input terminal is connected to the third output terminal of the analog-to-digital converter, and the output terminal is connected to the first input terminal of the microprocessor. The first input terminal of the second judgment submodule is connected to the second output terminal of the analog-to-digital converter, the second input terminal is connected to the third output terminal of the analog-to-digital converter, the third input terminal is connected to the first output terminal of the analog-to-digital converter, and the output terminal is connected to the second input terminal of the microprocessor. The first input terminal of the third judgment submodule is connected to the third output terminal of the analog-to-digital converter, the second input terminal is connected to the first output terminal of the analog-to-digital converter, the third input terminal is connected to the second output terminal of the analog-to-digital converter, and the output terminal is connected to the third input terminal of the microprocessor.

9. The circuit according to claim 8, characterized in that, The first judgment submodule, the second judgment submodule and the third judgment submodule have the same structure. The first judgment submodule includes: a first XOR gate and a first flip-flop. The first input terminal of the first XOR gate is connected to the first output terminal of the analog-to-digital converter, the second input terminal is connected to the second output terminal of the analog-to-digital converter, and the output terminal is connected to the input terminal of the first flip-flop. The clock signal input terminal of the first flip-flop is connected to the third output terminal of the analog-to-digital converter, and the output terminal is connected to the first input terminal of the microprocessor. The second judgment submodule includes: a second XOR gate and a second flip-flop; The first input of the second XOR gate is connected to the second output of the analog-to-digital converter, the second input is connected to the third output of the analog-to-digital converter, and the output is connected to the input of the second flip-flop. The clock signal input terminal of the second flip-flop is connected to the first output terminal of the analog-to-digital converter, and the output terminal is connected to the second input terminal of the microprocessor; The third judgment submodule includes: a third XOR gate and a third flip-flop; The first input terminal of the third XOR gate is connected to the third output terminal of the analog-to-digital converter, the second input terminal is connected to the first output terminal of the analog-to-digital converter, and the output terminal is connected to the input terminal of the third flip-flop. The clock signal input terminal of the third flip-flop is connected to the second output terminal of the analog-to-digital converter, and the output terminal is connected to the third input terminal of the microprocessor.

10. A phase loss detection method, applied to the phase loss detection circuit according to any one of claims 1 to 9, characterized in that, include: The initial power signal corresponding to the three-phase power supply is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal. The judgment module performs logical operations on the digital signal to obtain the target signal, which represents the power supply phase loss information. The phase loss result corresponding to the three-phase power supply is determined based on the target signal.

11. The method according to claim 10, characterized in that, Before performing analog-to-digital conversion on the initial power signal corresponding to the acquired three-phase power supply via the analog-to-digital converter, the method further includes: The sampling module is used to collect the first phase sampling signal, the second phase sampling signal, and the third phase sampling signal corresponding to the three-phase power supply. Current detection is performed on the first phase sampling signal, the second phase sampling signal, and the third phase sampling signal respectively to obtain the first phase initial power supply signal, the second phase initial power supply signal, and the third phase initial power supply signal of the three-phase power supply.

12. The method according to claim 11, characterized in that, The process of converting the initial power signal corresponding to the three-phase power supply acquired by the analog-to-digital converter to obtain the corresponding digital signal includes: The initial power signal of the first phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the first phase. The initial power signal of the second phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the second phase. The initial power signal of the third phase is converted from analog to digital by an analog-to-digital converter to obtain the corresponding digital signal of the third phase.

13. The method according to claim 12, characterized in that, The step of performing logical operations on the digital signal based on the judgment module to obtain the target signal includes: The first XOR signal is obtained by performing an XOR operation on the first digital signal and the second digital signal through the first XOR gate. The first target signal is output after the logic control of the first flip-flop based on the first XOR signal and the third digital signal. The second XOR gate is used to perform an XOR operation on the second digital signal and the third digital signal to obtain the corresponding second XOR signal. The second target signal is output after the logic control of the second flip-flop based on the second XOR signal and the first digital signal. The first digital signal and the third digital signal are XORed by the third XOR gate to obtain the corresponding third XOR signal. The third target signal is output after the third XOR signal and the second digital signal are controlled by the logic of the third flip-flop.

14. The method according to claim 13, characterized in that, The determination of the phase loss result corresponding to the three-phase power supply based on the target signal includes: Determine whether the first target signal is equal to the first phase loss value, simultaneously determine whether the second target signal is equal to the second phase loss value, and determine whether the third target signal is equal to the third phase loss value, and determine the corresponding phase loss result; When the first target signal is equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the first phase loss result; Based on the first phase loss result, it is determined that the first phase power signal has a phase loss; When the first target signal is not equal to the first phase loss value, the second target signal is equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the second phase loss result; Based on the second phase loss result, it is determined that there is a phase loss in the second phase power supply signal; When the first target signal is not equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is equal to the third phase loss value, the phase loss result is determined to be the third phase loss result; Based on the third phase loss result, it is determined that the third phase power signal has a phase loss; When the first target signal is not equal to the first phase loss value, the second target signal is not equal to the second phase loss value, and the third target signal is not equal to the third phase loss value, the phase loss result is determined to be the fourth phase loss result; Based on the fourth phase loss result, it is determined that the circuit does not have a phase loss.

15. A testing device, characterized in that, include: A processor and a memory, the processor being configured to execute a phase loss detection program stored in the memory to implement the phase loss detection method according to any one of claims 11 to 14.

16. A storage medium, characterized in that, The storage medium stores one or more programs, which can be executed by one or more processors to implement the phase loss detection method according to any one of claims 11 to 14.

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