A modular multilevel converter switching loss optimization method and system

Abstract

The application provides a modular multilevel converter switch loss optimization method and system, and relates to the field of multilevel power electronic converters. The modular multilevel converter switch loss optimization method is based on a low switching frequency (LSF) voltage balancing method with a balance adjustment coefficient n ban introduced, bridge arm submodule capacitor voltages are continuously sampled within a period of time, the maximum bridge arm capacitor voltage u c_max and the minimum bridge arm capacitor voltage u c_min are compared, and the submodule dispersion degree sigma is calculated; whether n ban is 0 is judged according to the submodule capacitor voltage fluctuation degree and the dispersion degree. When n ban is not 0, the capacitor voltage fluctuation is small, but the switching frequency and the switching loss of the submodule switching device are increased, so the value of n ban is determined according to different operating states of the MMC, the submodule switching frequency and the switching loss can be effectively reduced, and the service life of the device is prolonged.

Description

Technical Field

[0001] This invention relates to the field of multilevel power electronic converter technology, specifically to a method and system for optimizing switching losses in a modular multilevel converter. Background Technology

[0002] MMC (Modular Multilevel Converter) adopts a modular structure and has attracted widespread attention in fields such as flexible DC transmission, renewable energy grid connection and motor drive due to its advantages such as high reliability, good output characteristics, flexible structural adjustment and redundancy control.

[0003] Because the power devices in the modular multilevel converter (MMC) submodules operate at high frequencies, they incur significant switching losses, leading to reduced device lifespan and increased MMC operating costs. When the MMC employs a low switching frequency (LSF) voltage balancing method with a balancing coefficient nban (where nban is not zero), capacitor voltage fluctuations are smaller, but this increases the switching frequency and losses of the submodule switching devices; the larger nban is, the greater the switching frequency and losses. Therefore, there is still considerable room for optimization regarding losses under different MMC operating conditions. Lower switching losses are beneficial for the efficient and stable operation of the modular multilevel converter system.

[0004] To address the loss optimization problem of modular multilevel converters, conventional methods aim to reduce losses by changing the circuit topology of the modular multilevel converter or by rematching the modulation strategy. However, these methods lead to increased construction costs and increased complexity of control algorithms, limiting their application in practical engineering. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] To address the shortcomings of existing technologies, this invention provides a method and system for optimizing switching losses in modular multilevel converters, which can effectively reduce the switching frequency and switching losses of sub-modules and extend the service life of devices.

[0007] (II) Technical Solution

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] Firstly, a method for optimizing switching losses in a modular multilevel converter is provided. The modular multilevel converter consists of six bridge arms, each containing N sub-modules with identical topologies and a bridge arm inductor L0. Each sub-module is a half-bridge structure, composed of a first diode D1, a second diode D2, a first IGBT power switch T1, a second IGBT power switch T2, and a capacitor C0. The method for optimizing switching losses in each bridge arm includes the following steps:

[0010] Based on the AC side current model of a modular multilevel converter, within Δt, f s The voltage of the capacitors of N sub-modules in the frequency sampling bridge arm is used to obtain i sampling sequences, where i = 1, 2, ..., N;

[0011] Obtain the maximum value u of the capacitor voltage of the i-th submodule within Δt. ci_max and minimum value u ci_min ;

[0012] Calculate the voltage dispersion σ of the capacitor in the submodule;

[0013] The maximum value u of the bridge arm capacitor voltage obtained by comparison cmax and minimum value u cmi ;

[0014] Determine the degree of voltage fluctuation and dispersion of the submodule capacitors, and select an appropriate n. ban To reduce switching frequency and switching losses;

[0015] Introducing the balance adjustment coefficient n ban Achieve voltage balance at low switching frequencies;

[0016] After waiting for a time interval, the above steps are repeated sequentially. To ensure good control, the time interval is less than Δt.

[0017] Preferably, the i sampling sequences are specifically u ci :u ci [1],u ci [1]…u ci [f s ·Δt], where i=1,2…N.

[0018] Preferably, the maximum value of the capacitor voltage u of the i-th submodule within Δt is... ci_max and minimum value u ci_min Specifically:

[0019] u ci_max =max[u ci [1],u ci [2]…u ci [fs·Δt]]

[0020] u ci_min =min[u ci [1],u ci [2]…u ci [fs·Δt]]

[0021] Where i = 1, 2, ..., N.

[0022] Preferably, the capacitor voltage dispersion σ is as follows:

[0023]

[0024] Preferably, the maximum voltage u of the bridge arm capacitor is... c_max and minimum value u c_min Specifically:

[0025] u c_max =max[u c1_max ,u c2_max …u cN_max ]

[0026] u c_min =min[u c1_min ,u c2_min …u cN_min ].

[0027] Preferably, the threshold value for capacitor voltage fluctuation is u. max and u min The threshold for capacitor voltage dispersion is σ. limit Generally, u is taken. max It is 1.2 pu, u min It is 0.8pu, σ limit Generally less than 0.03.

[0028] Preferred, n ban The selection criteria are:

[0029] If u c_max >u max At this time n ban =1; if u c_min min At this time n ban =1;

[0030] If u c_max max u c_min >u min And σ>σ limit At this time n ban =1;

[0031] If u c_max max u c_min ​​​>u min And σ < σ limit At this time n ban =0.

[0032] Preferably, a balance adjustment coefficient n is introduced. ban The specific steps to achieve low switching frequency voltage balance are as follows:

[0033] The number of sub-modules n that need to be activated within this control cycle is obtained based on the reference voltage. new And the number of sub-modules n deployed in the previous control cycle old Calculate the number of newly added sub-modules Δn incre =n new -n old ;

[0034] For n in the input state old The voltages of each submodule are sorted to obtain sequence A: 1…n old For submodules nn that are in the state of being cut off old Sort the sequences to obtain sequence B: 1…nn old ;

[0035] Calculate the actual number of submodules that need to be added or removed, Δn. adj =|Δn incre |+n ba ;

[0036] If the bridge arm current i u is positive and Δn incre =0: Remove sequence A from sequence 1 to n ban The corresponding submodule is input into sequence B, n+1-n ban ~nn old The corresponding submodule; if the bridge arm current i u is positive and Δn incre >0: Removal sequence A from 1 to n adj The corresponding submodule is input into sequence B, n+1-n ban ~nn old The corresponding submodule; if the bridge arm current i u is positive and Δn incre <0: Removal sequence A from 1 to n ban The corresponding submodule is input into sequence B, n+1-n adj ~nn old The corresponding submodule; if the bridge arm current i u Negative and Δn incre =0: Remove n+1-n from sequence A ban ~n old The corresponding submodule is input into sequence B from 1 to n. banThe corresponding submodule; if the bridge arm current i u Negative and Δn incre >0: Remove n+1-n from sequence A adj ~n old The corresponding submodule is input into sequence B from 1 to n. ban The corresponding submodule; if the bridge arm current i u Negative and Δn incre <0: Remove n+1-n from sequence A ban ~n old The corresponding submodule is input into sequence B from 1 to n. adj corresponding submodule

[0037] Secondly, a modular multilevel converter switching loss optimization system is provided, characterized in that the modular multilevel converter consists of six bridge arms, each bridge arm containing N sub-modules with identical topologies and a bridge arm inductor L0; the sub-module is a half-bridge structure, consisting of a first diode D1, a second diode D2, a first IGBT power switch T1, a second IGBT power switch T2, and a capacitor C0; the switching loss optimization method for each bridge arm includes the following modules:

[0038] The sampling module is used to sample the AC side current model of a modular multilevel converter within Δt, using f... s The voltage of the capacitors of N sub-modules in the frequency sampling bridge arm is used to obtain i sampling sequences, where i = 1, 2, ..., N;

[0039] The acquisition module is used to obtain the maximum value u of the capacitor voltage of the i-th submodule within Δt. ci_max and minimum value u c i _ mi n ;

[0040] The calculation module is used to calculate the voltage dispersion σ of the capacitor in the submodule.

[0041] The comparison module is used to compare the obtained maximum value u of the bridge arm capacitor voltage. cmax and minimum value u cmi ;

[0042] The judgment module is used to determine the degree of fluctuation and dispersion of the capacitor voltage in the submodule, and to select an appropriate n. ban To reduce switching frequency and switching losses;

[0043] The adjustment module is used to introduce the balance adjustment coefficient n. ban Achieve voltage balance at low switching frequency.

[0044] Thirdly, a computing device is provided, comprising:

[0045] One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, and the one or more programs include instructions for performing any of the methods described.

[0046] (III) Beneficial Effects

[0047] (1) The present invention provides a method and system for optimizing switching losses in a modular multilevel converter, which determines n based on different operating states of the MMC. ban The value of can effectively reduce the switching frequency and switching losses of the submodule, and the control algorithm is simple and easy to implement.

[0048] (2) The present invention provides a method and system for optimizing the switching losses of a modular multilevel converter. It does not require changing the topology of the modular multilevel converter sub-modules, does not increase the construction cost of the modular multilevel converter, and is easy to implement in existing modular multilevel converter systems, thus having strong practicality.

[0049] (3) The present invention provides a modular multilevel converter switching loss optimization method and system, which can ensure that the capacitor voltage fluctuation and dispersion are within a reasonable range and have almost no impact on the output power quality. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the overall method flow of an embodiment of the present invention;

[0051] Figure 2 This is a schematic diagram of the topology of a three-phase modular multilevel converter according to an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of the topology of the half-bridge submodule according to an embodiment of the present invention;

[0053] Figure 4 This is a flowchart of the low switching frequency (LSF) voltage balancing method used in this embodiment of the invention. Detailed Implementation

[0054] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0055] Example

[0056] like Figure 1As shown, this embodiment of the invention provides a method for optimizing switching losses in a modular multilevel converter. Please refer to [link to relevant documentation]. Figure 2 and Figure 3 The modular multilevel converter consists of six bridge arms, each containing N sub-modules (SMs) with identical topologies and one bridge arm inductor L0. Each sub-module is a half-bridge structure, composed of a first diode D1, a second diode D2, a first IGBT power switch T1, a second IGBT power switch T2, and a capacitor C0, where N is an integer. Based on the AC side current model of the modular multilevel converter, when operating at low power levels, the sub-module switching signals and bridge arm currents are sampled, and the voltage change and voltage fluctuation of each sub-module capacitor within one fundamental frequency cycle are calculated. Since the bridge arm current is small and the sub-module capacitor voltage fluctuation is small when the modular multilevel converter operates at low power levels, if the sub-module capacitor voltage fluctuation is less than 10%, the capacitor voltage control cycle can be reduced, thereby reducing the switching frequency and switching losses. The optimization method for the switching losses of each bridge arm includes the following steps:

[0057] Based on the AC side current model of a modular multilevel converter, within Δt, f s The voltage of the capacitors of N sub-modules in the frequency sampling bridge arm is used to obtain i sampling sequences, where i = 1, 2, ..., N;

[0058] Obtain the maximum value u of the capacitor voltage of the i-th submodule within Δt. ci_max and minimum value u ci_min ;

[0059] Calculate the voltage dispersion σ of the capacitor in the submodule;

[0060] The maximum value u of the bridge arm capacitor voltage obtained by comparison cmax and minimum value u cmi ;

[0061] Determine the degree of voltage fluctuation and dispersion of the submodule capacitors, and select an appropriate n. ban To reduce switching frequency and switching losses;

[0062] Introducing the balance adjustment coefficient n ban Achieve low switching frequency (LSF) voltage balance;

[0063] After waiting for a time interval (e.g., 0.5 seconds), repeat the above steps sequentially, with the time interval being less than Δt.

[0064] Furthermore, the i sampling sequences are specifically u ci :u ci [1],u ci [1]…u ci [f s·Δt], where i=1,2…N.

[0065] Furthermore, the maximum value u of the capacitor voltage of the i-th submodule within Δt. ci_max and minimum value u ci_min Specifically:

[0066] u ci_max =max[u ci [1],u ci [2]…u ci [fs·Δt]]

[0067] u ci_min =min[u ci [1],u ci [2]…u ci [fs·Δt]]

[0068] Where i = 1, 2, ..., N.

[0069] Furthermore, the capacitor voltage dispersion σ is specifically:

[0070]

[0071] Furthermore, the maximum voltage u of the bridge arm capacitor c_max and minimum value u c_min Specifically:

[0072] u c_max =max[u c1_max ,u c2_max …u cN_max ]

[0073] u c_min =min[u c1_min ,u c2_min …u cN_min ].

[0074] Furthermore, the threshold for capacitor voltage fluctuation is u. max and u min The threshold for capacitor voltage dispersion is σ. limit To avoid affecting the normal operation of MMC, u is taken. max It is 1.2 pu, u min It is 0.8pu, σ limit Generally less than 0.03.

[0075] Furthermore, n ban The selection criteria are:

[0076] If u c_max >u max At this time n ban =1; if uc_min min At this time n ban =1;

[0077] If u c_max max u c_min >u min And σ>σ limit At this time n ban =1;

[0078] If u c_max max u c_min >u min And σ < σ limit At this time n ban =0;

[0079] n is determined based on the different operating states of the MMC. ban The value of can effectively reduce the switching frequency and switching losses of the submodule, and extend the service life of the device.

[0080] Please see Figure 4 Furthermore, a balance adjustment coefficient n is introduced. ban The specific steps to achieve low switching frequency voltage balance are as follows:

[0081] The number of sub-modules n that need to be activated within this control cycle is obtained based on the reference voltage. new And the number of sub-modules n deployed in the previous control cycle old Calculate the number of newly added sub-modules Δn incre =n new -n old ;

[0082] For n in the input state old The voltages of each submodule are sorted to obtain sequence A: 1…n old For submodules nn that are in the state of being cut off old Sort the sequences to obtain sequence B: 1…nn old ;

[0083] Calculate the actual number of submodules that need to be added or removed, Δn. adj =|Δn incre |+n ba ;

[0084] If the bridge arm current i u is positive and Δn incre =0: Remove sequence A from sequence 1 to n ban The corresponding submodule is input into sequence B, n+1-n ban ~nn old The corresponding submodule; if the bridge arm current i​​​u is positive and Δn incre >0: Removal sequence A from 1 to n adj The corresponding submodule is input into sequence B, n+1-n ban ~nn old The corresponding submodule; if the bridge arm current i u is positive and Δn incre <0: Removal sequence A from 1 to n ban The corresponding submodule is input into sequence B, n+1-n adj ~nn old The corresponding submodule; if the bridge arm current i u Negative and Δn incre =0: Remove n+1-n from sequence A ban ~n old The corresponding submodule is input into sequence B from 1 to n. ban The corresponding submodule; if the bridge arm current i u Negative and Δn incre >0: Remove n+1-n from sequence A adj ~n old The corresponding submodule is input into sequence B from 1 to n. ban The corresponding submodule; if the bridge arm current i u Negative and Δn incre <0: Remove n+1-n from sequence A ban ~n old The corresponding submodule is input into sequence B from 1 to n. adj The corresponding submodule;

[0085] n ban When ≠0, it is beneficial for adjusting voltage balance: even if Δn incre =0, n represents the input or output state with the highest or lowest voltage. ban Each submodule will still be either switched on or off. Therefore, large capacitor voltage fluctuations can be avoided, but this increases the switching frequency and switching losses of the submodule's switching devices. This method determines n based on different operating states of the MMC. ban The value of can effectively reduce the switching frequency and switching losses of the submodule, and extend the service life of the device.

[0086] Another embodiment of the present invention provides a modular multilevel converter switching loss optimization system, characterized in that the modular multilevel converter consists of six bridge arms, each bridge arm comprising N sub-modules with identical topologies and a bridge arm inductor L0; the sub-module is a half-bridge structure, consisting of a first diode D1, a second diode D2, a first IGBT power switch T1, a second IGBT power switch T2, and a capacitor C0; the switching loss optimization method for each bridge arm includes the following modules:

[0087] The sampling module is used to sample the AC side current model of a modular multilevel converter within Δt, using f... s The voltage of the capacitors of N sub-modules in the frequency sampling bridge arm is used to obtain i sampling sequences, where i = 1, 2, ..., N;

[0088] The acquisition module is used to obtain the maximum value u of the capacitor voltage of the i-th submodule within Δt. ci_max and minimum value u ci_min ;

[0089] The calculation module is used to calculate the voltage dispersion σ of the capacitor in the submodule.

[0090] The comparison module is used to compare the obtained maximum value u of the bridge arm capacitor voltage. cmax and minimum value u cmi ;

[0091] The judgment module is used to determine the degree of fluctuation and dispersion of the capacitor voltage in the submodule, and to select an appropriate n. ban To reduce switching frequency and switching losses;

[0092] The adjustment module is used to introduce the balance adjustment coefficient n. ban Achieve voltage balance at low switching frequency.

[0093] Embodiments of this application may be provided as methods or computer program products. Therefore, this application may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application may be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0094] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0095] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0096] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0097] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for optimizing switching losses in a modular multilevel converter, wherein the modular multilevel converter consists of six bridge arms, each bridge arm comprising N sub-modules with identical topologies and a bridge arm inductor L0; the sub-modules are half-bridge structures, consisting of a first diode D1, a second diode D2, a first IGBT power switch T1, a second IGBT power switch T2, and a capacitor C0, characterized in that... The method for optimizing the switching losses of each bridge arm includes the following steps: Based on the AC side current model of a modular multilevel converter, in Δ t Inner f s In the frequency sampling bridge arm N The capacitor voltage of each submodule is obtained. i samples, of which, i =1,2… N ; Obtain Δ t Inner i Maximum voltage of capacitor in each submodule u ci_max and minimum value u ci_min ; Calculate the capacitor voltage dispersion of the submodule σ ; The maximum value of the bridge arm capacitor voltage obtained by comparison u c_max and minimum value u c_min ; Determine the degree of voltage fluctuation and dispersion of the submodule capacitors, and select appropriate... n ban To reduce switching frequency and switching losses; Introducing a balance adjustment coefficient n ban Achieve voltage balance at low switching frequencies; After waiting for a time interval, the above steps are repeated sequentially, where the time interval is less than Δ. t ; n ban The selection criteria are: like u c_max > u max ,at this time n ban =1; if u c_min < u min ,at this time n ban =1; like u c_max < u max , u c_min > u min and σ>σ limit ,at this time n ban =1; like u c_max < u max , u c_min > u min and σ<σ limit ,at this time n ban =0; in, u max and u min This is the threshold for the degree of capacitor voltage fluctuation. σ limit This is the threshold for the degree of dispersion of capacitor voltage; Introducing a balance adjustment coefficient n ban The specific steps to achieve low switching frequency voltage balance are as follows: The number of sub-modules that need to be activated within the control cycle is determined based on the reference voltage. n new The number of sub-modules deployed in the previous control cycle n old Calculate the number of newly added sub-modules Δ n incre = n new - n old ; For those in a state of engagement n old The voltages of each submodule are sorted to obtain sequence A: 1… n old For submodules in the state of being cut off n - n old Sort the sequences to get sequence B: 1… n - n old ; Calculate the actual number of submodules that need to be added or removed Δ n adj =|Δ n incre |+ n ban ; If the bridge arm current i u is positive and Δ n incre =0: Exclude 1~ in sequence A n ban The corresponding submodule is added to sequence B. n +1- n ban ~ n - n old The corresponding submodule; If the bridge arm current i u is positive and Δ n incre >0: Exclude 1~ in sequence A n adj The corresponding submodule is added to sequence B. n +1- n ban ~ n - n old The corresponding submodule; If the bridge arm current i u is positive and Δ n incre <0: Exclude 1~ in sequence A n ban The corresponding submodule is added to sequence B. n +1- n adj ~ n - n old The corresponding submodule; If the bridge arm current i u Negative and Δ n incre =0: Exclude sequence A n +1- n ban ~ n old The corresponding submodule is added to sequence B, 1~ n ban The corresponding submodule; If the bridge arm current i u Negative and Δ n incre >0: excision sequence A n +1- n adj ~ n old The corresponding submodule is added to sequence B, 1~ n ban The corresponding submodule; If the bridge arm current i u Negative and Δ n incre <0: excise sequence A n +1- n ban ~ n old The corresponding submodule is added to sequence B, 1~ n adj The corresponding submodule.

2. The method for optimizing switching losses in a modular multilevel converter according to claim 1, characterized in that: i Each sampling sequence is specifically... : ,in, i =1,2… N .

3. The method for optimizing switching losses in a modular multilevel converter according to claim 2, characterized in that: Δ t Inner i Maximum voltage of capacitor in each submodule u ci_max and minimum value u ci_min Specifically: in, i =1,2… N .

4. The method for optimizing switching losses in a modular multilevel converter according to claim 3, characterized in that: capacitor voltage dispersion σ Specifically: 。 5. The method for optimizing switching losses in a modular multilevel converter according to claim 4, characterized in that: Maximum voltage of bridge arm capacitor u c_max and minimum value u c_min Specifically: 。 6. The method for optimizing switching losses in a modular multilevel converter according to claim 5, characterized in that: Pick u max It is 1.2 pu. u min It is 0.8 pu. σ limit Less than 0.

03.

7. A modular multilevel converter switching loss optimization system, characterized in that, The modular multilevel converter consists of six bridge arms, each containing N sub-modules with identical topologies and a bridge arm inductor L0. Each sub-module is a half-bridge structure, consisting of a first diode D1, a second diode D2, a first IGBT power switch T1, a second IGBT power switch T2, and a capacitor C0. The key feature is that the switching loss optimization method for each bridge arm includes the following modules: The sampling module is used to sample the AC side current model of a modular multilevel converter in Δ t Inner f s In the frequency sampling bridge arm N The capacitor voltage of each submodule is obtained. i samples, of which, i =1,2… N ; The acquisition module is used to obtain Δ t Inner i Maximum voltage of capacitor in each submodule u ci_max and minimum value u ci_min ; The calculation module is used to calculate the capacitor voltage dispersion of the submodule. σ ; The comparison module is used to compare the maximum values ​​of the obtained bridge arm capacitor voltages. u cmax and minimum value u cmi ; The judgment module is used to determine the degree of fluctuation and dispersion of the capacitor voltage in the submodule and select an appropriate... n ban To reduce switching frequency and switching losses; The adjustment module is used to introduce the balance adjustment coefficient. n ban Achieve voltage balance at low switching frequencies; n ban The selection criteria are: like u c_max > u max ,at this time n ban =1; if u c_min < u min ,at this time n ban =1; like u c_max < u max , u c_min > u min and σ>σ limit ,at this time n ban =1; like u c_max < u max , u c_min > u min and σ<σ limit ,at this time n ban =0; in, u max and u min This is the threshold for the degree of capacitor voltage fluctuation. σ limit This is the threshold for the degree of dispersion of capacitor voltage; Introducing a balance adjustment coefficient n ban The specific steps to achieve low switching frequency voltage balance are as follows: The number of sub-modules that need to be activated within the control cycle is determined based on the reference voltage. n new The number of sub-modules deployed in the previous control cycle n old Calculate the number of newly added sub-modules Δ n incre = n new - n old ; For those in a state of engagement n old The voltages of each submodule are sorted to obtain sequence A: 1… n old For submodules in the state of being cut off n - n old Sort the sequences to get sequence B: 1… n - n old ; Calculate the actual number of submodules that need to be added or removed Δ n adj =|Δ n incre |+ n ban ; If the bridge arm current i u is positive and Δ n incre =0: Exclude 1~ in sequence A n ban The corresponding submodule is added to sequence B. n +1- n ban ~ n - n old The corresponding submodule; If the bridge arm current i u is positive and Δ n incre >0: Exclude 1~ in sequence A n adj The corresponding submodule is added to sequence B. n +1- n ban ~ n - n old The corresponding submodule; If the bridge arm current i u is positive and Δ n incre <0: Exclude 1~ in sequence A n ban The corresponding submodule is added to sequence B. n +1- n adj ~ n - n old The corresponding submodule; If the bridge arm current i u Negative and Δ n incre =0: Exclude sequence A n +1- n ban ~ n old The corresponding submodule is added to sequence B, 1~ n ban The corresponding submodule; If the bridge arm current i u Negative and Δ n incre >0: excision sequence A n +1- n adj ~ n old The corresponding submodule is added to sequence B, 1~ n ban The corresponding submodule; If the bridge arm current i u Negative and Δ n incre <0: excise sequence A n +1- n ban ~ n old The corresponding submodule is added to sequence B, 1~ n adj The corresponding submodule.

8. A computing device, characterized in that, include: One or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs including instructions for performing any of the methods according to claims 1-6.

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