Inverter for thermal protection and method for measuring junction temperature

Abstract

The present disclosure relates to an inverter for thermal protection and a method of measuring junction temperature. A three-phase load is powered by an SPWM driven inverter having a single-shunt topology. During operation, the drain-source resistance of the transistor of each leg of the inverter is determined. An interpolation is performed on the assumed drain-source resistance of the transistor at different temperatures to produce a non-linear model of the drain-source resistance of the transistor versus temperature, and a temperature value of the transistor is estimated using the drain-source resistance determined during operation and the non-linear model. The drive of the inverter can be adjusted so that the conductivity of each leg is set so that the power delivered by that leg is as high as possible without exceeding an allowed drain current threshold representing a threshold junction temperature. Furthermore, if the temperature of the transistor exceeds the threshold temperature, the drive of the inverter can be stopped.

Description

Technical Field

[0001] This disclosure generally relates to inverters for driving three-phase motors, and more specifically to methods for protecting the transistors of these inverters from thermal stress based on estimated junction temperatures of these transistors. Background Technology

[0002] In three-phase electrical equipment such as three-phase motors driven by three-phase inverters, it is desirable to know the temperature of the motor's power devices in order to modify the operation of these power devices to provide them with protection from thermal stress.

[0003] This can be done using thermal sensors housed within the enclosure of the three-phase electrical equipment. However, these sensors cannot provide measurements of the junction temperature within each power device of the three-phase equipment, which changes more rapidly than the temperature within the enclosure near each power device. Furthermore, the accuracy of this temperature measurement is affected by the location of the temperature sensor, heat from other sources, the layout of the motor circuitry, and load balance. The inaccuracy due to load imbalance is particularly concerning when using a single temperature sensor within the enclosure, even if there are multiple power devices in the three-phase equipment—imbalance can cause the temperatures of the power devices to differ from one another, and the temperature data provided by a single temperature sensor may not reflect the additional hazards of the power device with the highest junction temperature.

[0004] Another method to determine the temperature of power devices within a motor is to calculate the drain-source resistance (RDSon) of these devices and combine it with data from a temperature sensor inside the housing to form an estimate of the junction temperature. However, this depends on the accuracy of the RDSon calculation, and RDSon itself varies with junction temperature.

[0005] Therefore, there is a need to further develop technologies that allow for accurate estimation of the junction temperature of power devices within three-phase electronic devices in terms of precision and response time. Summary of the Invention

[0006] In inverters utilizing multiple power devices, thermal stress can damage these devices, making it desirable to maintain their stability for robust inverter operation. This paper discloses a technique in which the calibrated drain-source resistance (RDSon) of the power devices can be determined over a temperature range and then used to estimate the junction temperature of the power devices during operation. Based on this estimated junction temperature, the drain current within the power devices can be limited instantaneously, enabling the power devices to continuously deliver the highest potential they can safely deliver throughout the entire operating temperature range.

[0007] This document discloses an electrical device comprising an inverter system to be coupled to phase windings of a motor to drive the motor. The inverter system includes switching branches coupled between a DC power supply voltage node and an intermediate node, each switching branch having terminals for a corresponding phase winding to be coupled to the motor. Shunt resistors are coupled between the intermediate node and ground. Control circuitry is configured to apply control signals to the switching branches according to a control scheme, causing the inverter to drive the phase windings of the motor with multiphase AC power signals.

[0008] The control scheme is divided into zones, and each zone is further divided into time periods. The control circuitry is configured to, during at least some zones of the control scheme: during a first given time period: measure the shunt voltage across a shunt resistor; and measure the drain-source voltage of a first calibration transistor, which is a transistor in a given switching branch; and determine the drain-source resistance of the first calibration transistor based on the resistance of the shunt resistor, the drain-source voltage of the first calibration transistor measured during the first given time period, and the shunt voltage measured during the first given time period.

[0009] The control circuitry is also configured to control the drive of a given switching branch, determine the temperature of the first calibration transistor during the drive of the motor by the inverter system based on the drain-source resistance of the first calibration transistor, modify the drive of the given switching branch to maintain the conductivity of the first calibration transistor at a maximum level, at which the temperature of the first calibration transistor is kept below a threshold temperature, and stop the drive of the given switching branch when the temperature of the first calibration transistor exceeds the threshold temperature.

[0010] The control circuitry can also be configured to interpolate, during the calibration phase, an assumed value of the drain-source resistance of the first calibration transistor for a given temperature value, thereby generating a nonlinear model of the drain-source resistance of the first calibration transistor with respect to temperature. The control circuitry can use the nonlinear model and the drain-source resistance of the first calibration transistor to determine the temperature of the first calibration transistor.

[0011] The control circuitry can also be configured to normalize the assumed value of the drain-source resistance of the first calibration transistor during the calibration phase, before performing interpolation.

[0012] The housing may at least house the switching branch and the shunt resistor, and a temperature sensor is positioned within the housing. The control circuitry may also be configured to, during the calibration phase: read the internal temperature of the housing from the temperature sensor; determine the expected drain-source resistance of the first calibration transistor from an assumed value of the drain-source resistance of the first calibration transistor for a given temperature value; determine the ratio between the drain-source resistance of the first calibration transistor and the expected drain-source resistance of the first calibration transistor; and, before performing interpolation, calibrate the assumed value of the drain-source resistance of the first calibration transistor for a given temperature value using the determined ratio, such that interpolation is performed on the calibrated assumed value of the drain-source resistance of the first calibration transistor for a given temperature value.

[0013] The control circuitry can also be configured to normalize the assumed value of the drain-source resistance of the first calibration transistor during the calibration phase, before determining the expected drain-source resistance of the first calibration transistor for the read temperature.

[0014] Interpolation can produce a second-order nonlinear model representing the relationship between the drain-source resistance of the first calibration transistor and temperature.

[0015] The motor may have a first-phase winding, a second-phase winding, and a third-phase winding. The switching branches may include: a first switching branch coupled between the DC power supply voltage node and the intermediate node, the first switching branch having a first terminal to be coupled to the first-phase winding; a second switching branch coupled between the DC power supply voltage node and the intermediate node, the second switching branch having a second terminal to be coupled to the second-phase winding; and a third switching branch coupled between the DC power supply voltage node and the intermediate node, the third switching branch having a third terminal to be coupled to the third-phase winding. The control scheme may be a space vector pulse width modulation (SVPWM) scheme, with six partitions, each of which is divided into multiple time periods.

[0016] Multiphase AC signals can be three-phase AC power signals. The control circuit can apply control signals to the first, second, and third switch branches according to the SVPWM scheme, so that the inverter drives the first, second, and third phase windings of the motor with the three-phase AC power signals.

[0017] The first given time period can be a second time period of at least some partitions of the SVPWM scheme. The control circuitry can be configured to: during at least some partitions of the SVPWM scheme, during the fourth time period: measure the drain-source voltage of the first calibration transistor; and measure the drain-source voltage of the transistor under test, which is the transistor of the next switching branch;

[0018] The control circuitry can also be configured to, during at least some partitions of the SVPWM scheme, determine the phase current of a given phase winding coupled to a given switching branch based on the drain-source voltage and drain-source resistance of a first calibration transistor measured during a fourth time period; determine the phase current of a next phase winding coupled to a next switching branch based on the drain-source voltage of the measured transistor measured during the fourth time period and the drain-source resistance of the measured transistor known from previous partitions of the SVPWM scheme; and determine the phase current of the remaining phase windings coupled to the remaining switching branches based on the phase current of the given phase winding and the phase current of the next phase winding.

[0019] The control circuitry can control the driving of the first, second, and third switching branches based on the phase current of a given phase winding, the phase current of the next phase winding, and the phase current of the remaining phase winding. The control circuitry can also be configured to: determine the temperature of the measured transistor during motor driving by the inverter system based on the drain-source resistance of the measured transistor; modify the driving of the next switching branch to maintain the conductivity of the measured transistor at a maximum level, where the temperature of the measured transistor remains below a threshold temperature; and stop the driving of the next switching branch when the temperature of the measured transistor exceeds the threshold temperature.

[0020] The first calibration transistor can be the low-side transistor of a given switching branch, and the transistor being measured can be the low-side transistor of the next switching branch.

[0021] The control circuit can determine the drain-source resistance of the first calibration transistor as:

[0022]

[0023] Where Rshunt is the resistance of the shunt resistor, V1phase2 is the drain-source voltage of the first calibration transistor measured during the second time period, and Vshunt2 is the shunt voltage measured during the second time period.

[0024] The control circuit device can determine the phase current of a given phase winding as follows:

[0025] Iphase1 = y1phase4 / Rds (calibration transistor)

[0026] V1phase4 is the drain-source voltage of the first calibration transistor measured during the fourth time period, and Rds (calibration transistor) is the drain-source resistance of the first calibration transistor.

[0027] The control circuit device can determine the phase current of the next phase winding as follows:

[0028] Iphase2 = y2phase4 / Rds (transistor under test)

[0029] V2phase4 is the drain-source voltage of the transistor under test measured during the fourth time period, and Rds (transistor under test) is the drain-source resistance of the transistor under test known from the previous SVPWM partition.

[0030] The control circuit device can determine the phase current of the remaining phase winding as follows:

[0031] Iphase3=-(Iphase1+Iphase2).

[0032] This document also discloses an inverter system to be coupled to a three-phase winding of a motor. The inverter system includes: a first switching branch coupled between a DC power supply voltage node and an intermediate node, the first switching branch having a first terminal of a first phase winding to be coupled to the motor; a second switching branch coupled between a DC power supply voltage node and an intermediate node, the second switching branch having a second terminal of a second phase winding to be coupled to the motor; a third switching branch coupled between a DC power supply voltage node and an intermediate node, the third switching branch having a third terminal of a third phase winding to be coupled to the motor; and a shunt resistor coupled between the intermediate node and ground.

[0033] The control circuit is configured to apply control signals to the first, second, and third switching branches according to a space vector pulse width modulation (SVPWM) scheme to drive the first, second, and third phase windings of the motor with a three-phase AC power signal. The SVPWM scheme is divided into six partitions, each partition being further divided into multiple time periods, including a first time period, a second time period, a third time period, and a fourth time period.

[0034] The control circuitry is configured to, during at least some partitions of the SVPWM scheme, during a second time period of a plurality of time periods: measure the shunt voltage across the shunt resistor; and measure the drain-source voltage of a first calibration transistor, which is a transistor for a given switching branch.

[0035] The control circuitry is also configured to, during at least some partitions of the SVPWM scheme, during a third time period of a plurality of time periods: measure the shunt voltage across the shunt resistor; measure the drain-source voltage of the second calibration transistor, which is the transistor of the next switching branch; and measure the drain-source voltage of the first calibration transistor.

[0036] The control scheme is also configured to, during at least some partitions of the SVPWM scheme, during the fourth time period of a plurality of time periods: measure the drain-source voltage of the first calibration transistor; measure the drain-source voltage of the second calibration transistor; and measure the drain-source voltage of the transistor under test, which is a transistor of the remaining switching branch.

[0037] The control circuitry is further configured to, during at least some partitions of the SVPWM scheme: determine the drain-source resistance of the first calibration transistor based on the resistance of the shunt resistor, the drain-source voltage of the first calibration transistor measured during the second time period, and the shunt voltage measured during the second time period; determine the drain-source resistance of the second calibration transistor based on the resistance of the shunt resistor, the drain-source resistance of the first calibration transistor, the drain-source voltage of the first calibration transistor measured during the fourth time period, the drain-source voltage of the second calibration transistor measured during the fourth time period, and the shunt voltage measured during the fourth time period; determine the phase current of a given phase winding coupled to a given switching branch based on the drain-source voltage of the first calibration transistor measured during the fourth time period and the drain-source resistance of the first calibration transistor; determine the phase current of a next phase winding coupled to a next switching branch based on the drain-source voltage of the second calibration transistor measured during the fourth time period and the drain-source resistance of the second calibration transistor; and determine the phase current of the remaining phase winding coupled to the remaining switching branches based on the phase current of the given phase winding and the phase current of the next phase winding.

[0038] The control circuitry is further configured to: control the driving of a first switching branch, a second switching branch, and a third switching branch based on the phase current of a given phase winding, the phase current of the next phase winding, and the phase current of the remaining phase winding; determine the temperature of the first calibration transistor during the driving of the motor by the inverter system based on the drain-source resistance of the first calibration transistor; modify the driving of the given switching branch to maintain the conductivity of the first calibration transistor at a maximum level, where the temperature of the first calibration transistor remains below a threshold temperature; stop the driving of the given switching branch when the temperature of the first calibration transistor exceeds the threshold temperature; determine the temperature of the measured transistor during the driving of the motor by the inverter system based on the drain-source resistance of the measured transistor; modify the driving of the next switching branch to maintain the conductivity of the measured transistor at a maximum level, where the temperature of the measured transistor remains below a threshold temperature; and stop the driving of the next switching branch when the temperature of the measured transistor exceeds the threshold temperature.

[0039] The control circuitry can also be configured to interpolate, during the calibration phase, an assumed value of the drain-source resistance of the first calibration transistor for a given temperature value, thereby generating a nonlinear model of the drain-source resistance of the first calibration transistor with respect to temperature. The control circuitry can use the nonlinear model and the drain-source resistance of the first calibration transistor to determine the temperature of the first calibration transistor.

[0040] The control circuitry can also be configured to normalize the assumed value of the drain-source resistance of the first calibration transistor during the calibration phase, before performing interpolation.

[0041] The housing may at least house a first switching branch, a second switching branch, and a third switching branch, as well as a shunt resistor, and a temperature sensor is positioned within the housing. The control circuitry may also be configured to, during the calibration phase: read the internal temperature of the housing from the temperature sensor; determine, from an assumed value of the drain-source resistance of the first calibration transistor for a given temperature value, a desired drain-source resistance of the first calibration transistor for the read temperature; determine a ratio between the drain-source resistance of the first calibration transistor and the desired drain-source resistance of the first calibration transistor; and, before performing interpolation, calibrate the assumed value of the drain-source resistance of the first calibration transistor for a given temperature value using the determined ratio, such that interpolation is performed on the calibrated assumed value of the drain-source resistance of the first calibration transistor for the given temperature value.

[0042] The control circuitry can also be configured to normalize the assumed value of the drain-source resistance of the first calibration transistor during the calibration phase, before determining the expected drain-source resistance of the first calibration transistor for the read temperature.

[0043] Interpolation can produce a second-order nonlinear model representing the relationship between the drain-source resistance of the first calibration transistor and temperature. Attached Figure Description

[0044] Figure 1A This is a block diagram of an electric motor that can employ the technology described in this article;

[0045] Figure 1B It is shown by Figure 1A A block diagram of the functions performed by the motor control circuitry when executing the techniques described herein;

[0046] Figure 2 It is a graph of six-part space vectors used for space vector pulse width modulation (SVPWM);

[0047] Figures 3A-3F These are charts that illustrate the process during the six partitions of SVPWM. Figure 1A The operation of a three-phase inverter in a power system is described, and the method for performing the calculations described herein is illustrated. Figure 1A The sampling point for determining the first phase current of the transistor drain-source resistance of the inverter;

[0048] Figure 4 This is a diagram illustrating the operation of the three-phase inverter of the power system in Figure 1 during the fourth partition of SVPWM, and showing the calculations used to perform the calculations described herein. Figure 1A The sampling point for determining the second-phase current of the transistor drain-source resistance in the inverter;

[0049] Figure 5 It is a graph showing a sample of assumed values ​​for the drain-source resistance of a given transistor and a hypothetical temperature at those drain-source resistance values;

[0050] Figure 6 This is a graph showing the relationship between drain-source resistance and temperature using a nonlinear model, which is used in this paper to determine the temperature of the inverter's transistors; and

[0051] Figure 7 It shows when according to Figure 1B When the function shown is operated Figure 1A A graph showing the drain current versus temperature in an electric motor. Detailed Implementation

[0052] The following disclosure enables those skilled in the art to make and use the subject matter disclosed herein. The general principles described herein can be applied to embodiments and applications other than those detailed above, without departing from the spirit and scope of this disclosure. This disclosure is not intended to be limited to the embodiments shown, but should be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

[0053] like Figure 1A As shown, the power system 10 disclosed herein includes a three-phase inverter bridge 12 that supplies power to a motor 11 (e.g., an electric motor). The three-phase inverter bridge 12 includes six power switches (n-channel transistors) MN1, MN2, MN3, MN4, MN5, and MN6. Techniques are disclosed herein for: determining the drain-source resistance RDS of these transistors MN1-MN6 of the bridge 12 during operation; determining the temperature of these transistors using the determination result of RDS; and, knowing the transistor temperatures in real time, modifying the inverter operation of the bridge 12 in real time to protect the transistors from thermal stress while delivering the maximum amount of power that the transistors are capable of under given current operating conditions.

[0054] Now, returning to the description of power system 10, although Figure 1A An n-channel MOSFET is shown, but the power system 10 can utilize any suitable power switching device, as long as the voltage drop across the power switching device is a function of the current flowing through the power switching device.

[0055] Specifically, the drain of n-channel transistor MN1 is coupled to the power supply voltage Vcc, the source is coupled to terminal U, and the gate is coupled to receive the control signal Uh; the drain of n-channel transistor MN2 is coupled to terminal U, the source is coupled to the first terminal of the common shunt resistor Rshunt, and the gate is coupled to receive the control signal Ul. The drain of N-channel transistor MN3 is coupled to the power supply voltage Vcc, the source is coupled to terminal V, and the gate is coupled to receive the control signal Vh; the drain of n-channel transistor MN4 is coupled to terminal V, the source is coupled to the first terminal of the common shunt resistor Rshunt, and the gate is coupled to receive the control signal Vl. The drain of N-channel transistor MN5 is coupled to the power supply voltage Vcc, the source is coupled to terminal W, and the gate is coupled to receive the control signal Wh; the drain of n-channel transistor MN6 is coupled to terminal W, the source is coupled to the first terminal of the common shunt resistor Rshunt, and the gate is coupled to receive the control signal Whl.

[0056] Three impedance elements Zu, Zv, and Zw are located between terminals U, V, and W of the three-phase inverter bridge 12 and voltage sources Vswu, Vswv, and Vsww, respectively. Voltage sources Vswu, Vswv, and Vsww are coupled to each other at the center node N. The impedance elements Zu, Zv, and Zw, along with the voltage sources Vswu, Vswv, and Vsww, represent the equivalent circuit of the three-phase windings of a three-way connected load motor 11 configured to be driven by the three-phase inverter bridge 12, in which phase currents Iu, Iv, and Iw flow.

[0057] A single common current sensing resistor Rshunt is connected between the source of n-channel transistors MN2, MN4, and MN6 and ground, and is therefore used to sense the DC current Ishunt returning to the power supply PSUP.

[0058] When current flows from terminals U, V, and W to the phase windings, the phase current is assumed to be positive, while when it flows to ground, the DC current Ishunt is assumed to be positive.

[0059] Complementary pulse width modulation (PWM) signals Uh, Ul and Vh, Vl and Wh, Vl control the high-side transistors and low-side transistors of each branch of the three-phase bridge 12 (i.e., MN1, MN2 and MN3, MN4 and MN5, MN6, respectively), with dead-time insertion to eliminate the risk of two transistors in a given branch of the three-phase bridge 12 being simultaneously on, which could potentially cause a short circuit.

[0060] The inductive characteristics of the load on motor 11 and the resulting phase lag between current and voltage may cause an irreversible reduction in the peak-to-peak voltage of the 120° electrically out-of-phase voltage waveform generated on the phase windings Zu, Zv, Zw when driven by the corresponding PWM signals Uh, Ul and Vh, Vl and Wh, Wl.

[0061] The amplification / filtering / digitization block 14 receives the voltage Vshunt across resistor Rshunt, the drain-source voltage Vu of MN2, the drain-source voltage Vv of MN4, and the drain-source voltage Vw of MN6 as feedback, adjusts these signals, and transmits them to the microcontroller 13 in an adjusted form. The microcontroller 13 generates control signals Uh, Ul for MN1-MN2, control signals Vh, Vl for MN3-MN4, and control signals Wh, Wl for MN5-MN6. Note that in some instances, amplification and / or filtering may be optional. The amplification / filtering / digitization block 14 and the microcontroller 13 are part of the control circuitry device 15.

[0062] The methods and techniques described herein are used to determine the phase currents Iu, Iv, and Iw of a motor 11 powered by a three-phase bridge 12 controlled by space vector pulse width modulation (SVPWM). However, the disclosed techniques are applicable to any motor powered by a three-phase inverter controlled by any PWM scheme.

[0063] For each configuration of the low-side transistors MN2, MN4, and MN6 of the three branches of the three-phase bridge 12, the current flowing in the shunt resistor Rshunt connected between the source and ground of MN2, MN4, and MN6 is indicated in Table 1 below.

[0064]

[0065]

[0066] As understood by those skilled in the art, SVPWM is a modulation scheme used to apply a given voltage vector to the motor to simulate a three-phase sinusoidal waveform (“space vector”, which is simply the vector sum of the three phase voltages Vu, Vv, Vw generated by the three-phase bridge 12 when modulated according to SVPWM) by switching the transistors MN1-MN6 of the three-phase bridge 12 in different configurations at different time periods in the above diagram.

[0067] As those skilled in the art will understand, a complete cycle of SVPWM modulation is divided into six "partitions". The space vector used can be... Figure 2 This is shown graphically. As you will see, each partition contains seven time periods.

[0068] This document describes a technique for accurately determining the phase currents Iu, Iv, and Iw of a three-phase bridge 12 using a single-shunt Rshunt topology. Based on these determined phase currents (used as feedback), in some cases, the microcontroller 13 can generate control signals Uh, Ul for MN1-MN2, Vh, Vl for MN3-MN4, and Wh, Wl for MN5-MN6 to control the motor 11 and improve its operation.

[0069] First-phase current determination technique (for high motor speeds)

[0070] Now refer to Figures 3A-3F Describe the first technique. Note: References. Figures 3A-3F The described technique is particularly useful for applications with high motor speeds. Typically, this technique operates by measuring Vshunt and one of voltages Vu, Vv, and Vw during the second time period of each SVPWM partition. From these two measured voltages, the drain-source resistance of voltage Vu, Vv, or Vw across the measured transistor (e.g., MN2, MN4, MN6) is calculated. This drain-source resistance can be referred to as the calibrated drain-source resistance of that SVPWM partition (the sample drain-source resistance of the transistor at that moment, taking into account various conditions that may affect the drain-source resistance, such as temperature, gate current, drain current, etc.), and the corresponding transistor can be referred to as the calibrated transistor. Then, during the fourth time period of each SVPWM partition, the voltages Vu, Vv, or Vw measured during the second time period are measured again, and another voltage Vu, Vv, or Vv across the corresponding transistor (e.g., MN2, MN4, MN6) is measured. The transistor corresponding to the voltage read during the fourth time period of each SVPWM partition can be referred to as the read transistor.

[0071] The phase current (flowing through the calibrated transistor) is calculated using the calibrated drain-source resistance and the voltage measured again during the fourth period of the SVPWM partition. Then, the phase current (flowing through the read transistor) is calculated using the voltage across the other read transistor measured during the fourth period, and the drain-source resistance across that read transistor (calculated during a previous period of the SVPWM). Finally, since the sum of the phase currents is known to be zero, the other phase current can be calculated from the two calculated phase currents of that SVPWM partition.

[0072] Therefore, the first technique can be simply summarized as the following steps performed on each SVPWM partition:

[0073] 1. During the second time period of the SVPWM partition, measure Vshunt and the phase voltage (Vu, Vv, or Vw) corresponding to the voltage across the transistor to be calibrated.

[0074] 2. Calculate the calibrated drain-source resistance RDS of the calibrated transistor (MN2, MN4, or MN6) as follows:

[0075]

[0076] Wherein, “calibrated transistor” is the transistor calibrated during this partition of SVPWM, “Rshunt” is the resistance of resistor Rshunt, “Vshunt2” is the voltage across Rshunt during the second phase of this partition of SVPWM, and “Vphase2” is the voltage across the calibrated transistor during the second phase of this partition of SVPWM.

[0077] 3. During the fourth time period of the SVPWM partition, measure the voltage across the calibrated transistor and the voltage across another transistor (MN2, MN4, or MN6).

[0078] 4. Calculate the phase current of the transistor being calibrated, as follows:

[0079] Iphase (the calibrated transistor) = Vphase4 / Rds (the calibrated transistor) where "the calibrated transistor" is the transistor being calibrated during the partition of SVPWM, and "Vphase4" is the voltage across the calibrated transistor during the fourth period of the partition of SVPWM.

[0080] 5. Calculate the phase current of the read transistor (excluding the calibrated transistor) across which the voltage was measured during step 3, as follows:

[0081] Iphase (transistor being read) = V (transistor being read) / Rds (transistor being read)

[0082] The “Read Transistor” is a transistor other than the calibrated transistor whose voltage is measured during step 3, the “V (Read Transistor)” is the voltage across the “Read Transistor” measured during step 3, and the “Rds (Read Transistor)” is the drain-source resistance of the “Read Transistor” calculated during the previous partition of SVPWM when calibrating this partition.

[0083] 6. Calculate the phase current of the remaining transistors as follows:

[0084] I_other = -[I_phase(the transistor being calibrated) + I_phase(the transistor being read)]

[0085] Note that the values ​​measured during the second time period of the SVPWM partition will be measured simultaneously, substantially simultaneously, or as close in time as possible (e.g., 1 μs or less; the greater the power, the greater the inductance of motor 10, and the higher the DC voltage VCC). This measurement involves digitizing the measured values ​​through amplification / filtering / digitization block 14, and these values ​​can be sampled once to produce their digitized version, or they can be sampled multiple times and these samples are averaged, filtered, dithered, etc., to produce a digitized version.

[0086] Furthermore, the values ​​measured during the third time period of the SVPWM partition will be measured simultaneously, substantially simultaneously, or as close as possible in time. This measurement involves digitizing the measured values ​​through amplification / filtering / digitization block 14, and these values ​​can be sampled once to produce their digitized version, or they can be sampled multiple times and these samples are averaged, filtered, jittered, etc., to produce a digitized version.

[0087] The values ​​measured during the fourth time period of the SVPWM partition will be measured simultaneously, substantially simultaneously, or as close as possible in time. This measurement involves digitizing the measured values ​​through amplification / filtering / digitization block 14, and these values ​​can be sampled once to produce their digitized version, or they can be sampled multiple times and these samples are averaged, filtered, jittered, etc. to produce a digitized version.

[0088] The chart shown below summarizes which transistors are calibrated and which are read for each partition of SVPWM when using the first technique.

[0089]

[0090] Note that in this diagram, the selection of the second transistor to be read during the fourth time period (e.g., MN4 in partition 1, MN2 in partition 2, MN6 in partition 3, MN4 in partition 4, MN2 in partition 5, and MN6 in partition 6) takes into account the two maximum duty cycles available in each partition. Another transistor could be selected (e.g., MN6 in the case of partition 1), but its duty cycle might not be long enough to complete the sampling of the voltage across that transistor. Therefore, those skilled in the art will recognize that this diagram illustrates an optimized selection of the transistor to be read based on this objective, and other selections are possible depending on different objectives, or in cases where a different PWM modulation technique is used instead of SVPWM.

[0091] As can be seen from the chart, the oldest calibration drain-source resistances used are the three oldest partitions.

[0092] Now refer to Figures 3A-3FThe complete cycle of this first technology is illustrated graphically and mathematically.

[0093] A. First SVPWM partition

[0094] Now we move to the first SVPWM partition, where the phase current determination technique continues over seven periods P1-P7. From the beginning of the second period to the end of the sixth period, Ul is high (which turns on MN2), from the beginning of the third period to the end of the fifth period, Vl is high (which turns on MN4), and during the fourth period, Wl is high (which turns on MN6). Wh, Vh, and Uh are complementary to Wl, Vl, and Ul, and therefore the operation of transistors MN1, MN3, and MN5 is complementary to the operation of transistors MN2, MN4, and MN6 as described above.

[0095] During the first SVPWM partition, the phase currents Iu, Iv, and Iw are calculated as follows. It should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt, Vu, Vv, and Vw in the measurement steps described below, and the microcontroller 13 sequentially generates control signals Uh, Ul, Vh, Vl, Wh, and Wl.

[0096] During the second time period, the shunt voltage Vshunt across the shunt resistor Rsh is measured and stabilizes at the value of Vu2_sh, and the voltage Vu is measured and stabilizes at -Vu2_mos. Therefore, the drain-source voltage of MN2 can be calculated as follows:

[0097]

[0098] During the fourth time period, voltages Vu and Vv are measured and stabilize at values ​​of Vu4_mos and Vv4_mos, respectively. The phase currents Iu, Iv, and Iw can now be calculated. Specifically, with the value of RdsMN2, the phase current Iu can be calculated as follows:

[0099] Iu=Vu4_mos / RdsMN2

[0100] With the value of RdsMN4 from the previous calculation, the phase current Iv can be calculated as follows:

[0101] Iv=Vv4_mos / RdsMN4

[0102] Since the sum of the phase currents Iu, Iv, and Iw is zero, Iw can be calculated as follows:

[0103] Iw=-(Vu4_mos / RdsMN2+Vv4_mos / RdsMN4)

[0104] The values ​​of Vshunt and Vu measured during the second time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vshunt and Vu using amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vshunt and Vu, or they can be sampled multiple times and these samples averaged to produce digital versions of Vshunt and Vu.

[0105] Similarly, the values ​​of Vu and Vv measured during the fourth time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vu and Vv via amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vu and Vv, or they can be sampled multiple times and these samples averaged to produce digital versions of Vu and Vv.

[0106] B. Second SVPWM partition

[0107] Now we move to the second SVPWM partition, where the phase current determination technique continues over seven time periods P1-P7. It can be seen that from the beginning of the third time period to the end of the fifth time period, Ul is high (turning on MN2); from the beginning of the second time period to the end of the sixth time period, Vl is high (turning on MN4); and during the fourth time period, Wl is high (turning on MN6). Wh, Vh, and Uh are complementary to Wl, Vl, and Ul, and therefore the operation of transistors MN1, MN3, and MN5 is complementary to the operation of transistors MN2, MN4, and MN6 as described above.

[0108] During the second SVPWM partition, the phase currents Iu, Iv, and Iw are calculated as follows. It should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt, Vu, Vv, and Vw in the measurement steps described below, and the microcontroller 13 sequentially generates control signals Uh, Ul, Vh, Vl, Wh, and Wl.

[0109] During the second time period, the shunt voltage Vshunt across the shunt resistor Rsh is measured and stabilizes at the value of Vv2_sh, and the voltage Vv is measured and stabilizes at -Vv2_mos. Therefore, the drain-source voltage of MN4 can be calculated as follows:

[0110]

[0111] During the fourth time period, voltages Vu and Vv are measured and stabilize at values ​​of Vu4_mos and Vv4_mos, respectively. The phase currents Iu, Iv, and Iw can now be calculated. Specifically, with the value of RdsMN4, the phase current Iv can be calculated as follows:

[0112] Iv=Vv4_mos / RdsMN4

[0113] With the value of RdsMN2 from the first partition of SVPWM, the phase current Iu can be calculated as follows:

[0114] Iu=Vu4_mos / RdsMN2

[0115] Since the sum of the phase currents Iu, Iv, and Iw is zero, Iw can be calculated as follows:

[0116] Iw=-(Vu4_mos / RdsMN2+Vv4_mos / RdsMN4)

[0117] The values ​​of Vshunt and Vv measured during the second time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vshunt and Vu through amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vshunt and Vv, or they can be sampled multiple times and these samples averaged to produce digital versions of Vshunt and Vv.

[0118] Similarly, the values ​​of Vu and Vv measured during the fourth time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vu and Vv via amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vu and Vv, or they can be sampled multiple times and these samples averaged to produce digital versions of Vu and Vv.

[0119] C. Third SVPWM partition

[0120] Now we move to the third SVPWM partition, where the phase current determination technique continues over the seven time periods P1-P7. It can be seen that during the fourth time period, Ul is high (turning on MN2); from the beginning of the second time period to the end of the sixth time period, Vl is high (turning on MN4); and from the beginning of the third time period to the end of the fifth time period, Wl is high (turning on MN6). Wh, Vh, and Uh are complementary to Wl, Vl, and Ul, and therefore the operation of transistors MN1, MN3, and MN5 is complementary to the operation of transistors MN2, MN4, and MN6 as described above.

[0121] During the third SVPWM partition, the phase currents Iu, Iv, and Iw are calculated as follows. It should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt, Vu, Vv, and Vw in the measurement steps described below, and the microcontroller 13 sequentially generates control signals Uh, Ul, Vh, Vl, Wh, and Wl.

[0122] During the second time period, the shunt voltage Vshunt across the shunt resistor Rsh is measured and stabilizes at the value of Vv2_sh, and the voltage Vv is measured and stabilizes at -Vv2_mos. Therefore, the drain-source voltage of MN4 can be calculated as follows:

[0123]

[0124] During the fourth time period, voltages Vv and Vw are measured and stabilize at values ​​of Vv4_mos and Vw4_mos, respectively. The phase currents Iu, Iv, and Iw can now be calculated. Specifically, with the value of RdsMN4, the phase current Iv can be calculated as follows:

[0125] Iv=Vv4_mos / RdsMN4

[0126] With the value of RdsMN6 from the previous partition of SVPWM, the phase current Iw can be calculated as follows:

[0127] Iw=Vw4_mos / RdsMN6

[0128] Since the sum of the phase currents Iu, Iv, and Iw is zero, Iu can be calculated as follows:

[0129] Iu=-(Vv4_mos / RdsMN4+Vw4_mos / RdsMN6)

[0130] The values ​​of Vshunt and Vv measured during the second time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vshunt and Vu through amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vshunt and Vv, or they can be sampled multiple times and these samples averaged to produce digital versions of Vshunt and Vv.

[0131] Similarly, the values ​​of Vv and Vw measured during the fourth time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vv and Vw through amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vv and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vv and Vw.

[0132] D. Fourth SVPWM partition

[0133] Now we move to the fourth SVPWM partition, where the phase current determination technique continues over the seven time periods P1-P7. It can be seen that during the fourth time period, Ul is high (turning on MN2); from the beginning of the third time period to the end of the fifth time period, Vl is high (turning on MN4); and from the beginning of the second time period to the end of the sixth time period, Wl is high (turning on MN6). Wh, Vh, and Uh are complementary to Wl, Vl, and Ul, and therefore the operation of transistors MN1, MN3, and MN5 is complementary to the operation of transistors MN2, MN4, and MN6 as described above.

[0134] During the fourth SVPWM partition, the phase currents Iu, Iv, and Iw are calculated as follows. It should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt, Vu, Vv, and Vw in the measurement steps described below, and the microcontroller 13 sequentially generates control signals Uh, Ul, Vh, Vl, Wh, and Wl.

[0135] During the second time period, the shunt voltage Vshunt across the shunt resistor Rsh is measured and stabilizes at the value of Vw2_sh, and the voltage Vw is measured and stabilizes at the value of Vw2_mos. Therefore, the drain-source resistance of MN6 can be calculated as follows:

[0136]

[0137] During the fourth time period, voltage Vv is measured and stabilizes at the value of Vv4_mos, and voltage Vw is measured and stabilizes at the value of Vw4_mos. Now, with the value of RdsMN6 and the value of RdsMN4 from the previous SVPWM partition, the phase current Iv can be calculated as follows:

[0138] Iv=Vv4_mos / RdsMN4

[0139] The phase current Iw can then be calculated as follows:

[0140] Iw=Vw4_mos / RdsMN6

[0141] Since the sum of the phase currents Iu, Iv, and Iw is zero, Iu can be calculated as follows:

[0142] Iu=-(Vv4_mos / RdsMN4+Vw4_mos / RdsMN6)

[0143] The values ​​of Vshunt and Vw measured during the second time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vshunt and Vw using amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vshunt and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vshunt and Vw.

[0144] The values ​​of Vv and Vw measured during the fourth time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vv and Vw through amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vv and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vv and Vw.

[0145] E. Fifth SVPWM partition

[0146] Now we move to the fifth SVPWM partition, where the phase current determination technique continues over the seven time periods P1-P7. It can be seen that from the beginning of the third time period to the end of the fifth time period, Ul is high (causing MN2 to conduct); during the fourth time period, Vl is high (causing MN4 to conduct); and from the beginning of the second time period to the end of the sixth time period, Wl is high (causing MN6 to conduct). Wh, Vh, and Uh are complementary to Wl, Vl, and Ul, and therefore the operation of transistors MN1, MN3, and MN5 is complementary to the operation of transistors MN2, MN4, and MN6 as described above.

[0147] During the fifth SVPWM partition, the phase currents Iu, Iv, and Iw are calculated as follows. It should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt, Vu, Vv, and Vw in the measurement steps described below, and the microcontroller 13 sequentially generates control signals Uh, Ul, Vh, Vl, Wh, and Wl.

[0148] During the second time period, the shunt voltage Vshunt across the shunt resistor Rsh is measured and stabilizes at the value of Vw2_sh, and the voltage Vw is measured and stabilizes at the value of Vw2_mos. Therefore, the drain-source resistance of MN6 can be calculated as follows:

[0149]

[0150] During the fourth time period, voltage Vu is measured and stabilizes at the value of Vu4_mos, and voltage Vw is measured and stabilizes at the value of Vw4_mos. Now, with the value of RdsMN6 and the value of RdsMN2 from the previous SVPWM partition, the phase current Iv can be calculated as follows:

[0151] Iu=Vu4_mos / RdsMN2 Then, the phase current Iw can be calculated as follows:

[0152] Iw=Vw4_mos / RdsMN6

[0153] Since the sum of the phase currents Iu, Iv, and Iw is zero, Iv can be calculated as follows:

[0154] Iv=-(Vu4_mos / RdsMN2+Vw4_mos / RdsMN6)

[0155] The values ​​of Vshunt and Vw measured during the second time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vshunt and Vw using amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vshunt and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vshunt and Vw.

[0156] The values ​​of Vu and Vw measured during the fourth time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vu and Vw through amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vu and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vu and Vw.

[0157] F. Sixth SVPWM partition

[0158] Now we move to the sixth SVPWM partition, where the phase current determination technique continues over the seven time periods P1-P7. It can be seen that from the beginning of the second time period to the end of the sixth time period, Ul is high (turning on MN2); during the fourth time period, Vl is high (turning on MN4); and from the beginning of the third time period to the end of the fifth time period, Wl is high (turning on MN6). Wh, Vh, and Uh are complementary to Wl, Vl, and Ul, and therefore the operation of transistors MN1, MN3, and MN5 is complementary to the operation of transistors MN2, MN4, and MN6 as described above.

[0159] During the sixth SVPWM partition, the phase currents Iu, Iv, and Iw are calculated as follows. It should be understood that the amplification / filtering / digitization block 14 digitizes and adjusts Vshunt, Vu, Vv, and Vw in the measurement steps described below, and the microcontroller 13 sequentially generates control signals Uh, Ul, Vh, Vl, Wh, and Wl.

[0160] During the second time period, the shunt voltage Vshunt across the shunt resistor Rsh is measured and stabilizes at the value of Vu2_sh, and the voltage Vu is measured and stabilizes at the value of Vu2_mos. Therefore, the drain-source resistance of MN2 can be calculated as follows:

[0161]

[0162] During the fourth time period, voltage Vu is measured and stabilizes at the value of Vu4_mos, and voltage Vw is measured and stabilizes at the value of Vw4_mos. Now, with the value of RdsMN2 and the value of RdsMN6 from the previous SVPWM partition, the phase current Iu can be calculated as follows:

[0163] Iu=Vu4_mos / RdsMN2

[0164] The phase current Iw can then be calculated as follows:

[0165] Iw=Vw4_mos / RdsMN6

[0166] Since the sum of the phase currents Iu, Iv, and Iw is zero, Iv can be calculated as follows:

[0167] Iv=-(Vu4_mos / RdsMN2+Vw4_mos / RdsMN6)

[0168] The values ​​of Vshunt and Vu measured during the second time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vshunt and Vu using amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vshunt and Vu, or they can be sampled multiple times and these samples averaged to produce digital versions of Vshunt and Vu.

[0169] The values ​​of Vu and Vw measured during the fourth time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vu and Vw through amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vu and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vu and Vw.

[0170] A variant of the first technology (for low motor speeds)

[0171] Given the detailed disclosure above regarding how the first technology works, a diagram summarizing variations of the first technology to be used at lower motor speeds is provided below. The technology remains unchanged except for a change in the read transistors of certain sections of SVPWM. Therefore, only this variation is shown in the diagram, as those skilled in the art will (benefiting from the above disclosure) readily understand how this variation of the first technology is implemented.

[0172]

[0173] First technology (low-cost variant)

[0174] In view of the above detailed disclosure of how the first technology works, the following is a diagram summarizing the first variant of the first technology, in which the voltage of one phase in the phase is never measured.

[0175]

[0176] Second technology

[0177] The second technique will now be described. Typically, this technique works by measuring Vshunt and one of voltages Vu, Vv, and Vw during the second time period of each partition of the SVPWM, and calculating from these two measured voltages that voltage Vu, Vv, or Vw is the drain-source resistance of the transistor (e.g., MN2, MN4, MN6) measured across that transistor—this drain-source resistance can be referred to as the first calibrated drain-source resistance of that partition of the SVPWM, and the corresponding transistor can be referred to as the first calibrated transistor.

[0178] Next, during the third time period of each partition of SVPWM, the technique continues to measure Vshunt again, measuring the corresponding voltage Vu, Vv, or Vw across the first calibrated transistor, and measuring the voltage Vu, Vv, or Vw across the next transistor to be calibrated (which may be referred to as the second calibrated transistor). From these three measured voltages, the drain-source resistance of the second calibrated transistor can be calculated, and this drain-source resistance can be referred to as the second calibrated drain-source resistance.

[0179] Then, during the fourth time period of each partition of the SVPWM, the voltages Vu, Vv, or Vw measured during the third time period are measured again. The transistor corresponding to the voltage read during the fourth time period of each partition of the SVPWM can be referred to as the read transistor.

[0180] The phase current flowing through the first calibrated transistor is calculated using the drain-source resistance of the first calibrated transistor and the voltage across the first calibrated transistor measured again during the fourth time period. Then, the phase current flowing through the second calibrated transistor is calculated using the drain-source resistance of the second calibrated transistor and the voltage across the second calibrated transistor measured again during the fourth time period. Finally, since the sum of the phase currents is known to be zero, the remaining phase current can be calculated based on the two calculated phase currents for this partition of the SVPWM.

[0181] Therefore, the second technology can be simply summarized as follows:

[0182] 1. During the second time period of the SVPWM partition, measure Vshunt and the phase voltage (Vu, Vv, or Vw) corresponding to the voltage across the first transistor to be calibrated.

[0183] 2. Calculate the calibrated drain-source resistance RDS of the first calibrated transistor (MN2, MN4, or MN6) as follows:

[0184]

[0185] Wherein, “first calibrated transistor” is the first transistor calibrated during this partition of SVPWM, “Rshunt” is the resistance of resistor Rshunt, “Vshunt2” is the voltage across Rshunt during the second partition of SVPWM, and “V1phase2” is the voltage across the first calibrated transistor during the second partition of SVPWM.

[0186] 3. During the third time period of the SVPWM partition, measure Vshunt, the phase voltage (Vu, Vv or Vw) corresponding to the voltage across the first calibrated transistor, and the phase voltage (Vu, Vv or Vw) corresponding to the voltage across another transistor (MN2, MN4 or MN6) (which will become the second calibrated transistor).

[0187] 4. Calculate the calibrated drain-source resistance RDS of the second calibrated transistor (MN2, MN4, or MN6):

[0188]

[0189] Wherein, “second calibrated transistor” is the second transistor calibrated during this partition of VSPWM, “Rshunt” is the resistance of resistor Rshunt, “Vshunt3” is the voltage across Rshunt during the third phase of this partition of SVPWM, “V1phase3” is the voltage across the first calibrated transistor during the third phase of this partition of SVPWM, and “V2phase3” is the voltage across the second calibrated transistor during the third phase of this partition of SVPWM.

[0190] 5. During the fourth time period of this SVPWM partition, measure the voltage across the first calibrated transistor and the second calibrated transistor (MN2, MN4, or MN6).

[0191] 6. Calculate the phase current of the first transistor being calibrated, as follows:

[0192] Iphase (first calibrated transistor) = V1phase4 / Rds (first calibrated transistor)

[0193] The “first calibrated transistor” is the first transistor calibrated during this partition of SVPWM, and “V1phase4” is the voltage across the first calibrated transistor during the fourth period of this partition of SVPWM.

[0194] 7. Calculate the phase current of the second calibrated transistor as follows:

[0195] Iphase (second calibrated transistor) = V2phase4 / Rds (second calibrated transistor)

[0196] The “second calibrated transistor” is the second transistor calibrated during this partition of SVPWM, and “V2phase4” is the voltage across the second calibrated transistor during the fourth period of this partition of SVPWM.

[0197] 8. Calculate the phase current of the remaining transistors as follows:

[0198] Iphase(remaining transistor) = -[Iphase(first calibrated transistor) + Iphase(second calibrated transistor)]

[0199] Note that the values ​​measured during the second time period of the SVPWM partition will be measured simultaneously, substantially simultaneously, or as close as possible in time. This measurement involves digitizing the measured values ​​through amplification / filtering / digitization block 14, and these values ​​can be sampled once to produce their digitized version, or they can be sampled multiple times and these samples are averaged to produce a digitized version.

[0200] Furthermore, the values ​​measured during the third time period of the SVPWM partition will be measured simultaneously, substantially simultaneously, or as close as possible in time. This measurement involves digitizing the measured values ​​through amplification / filtering / digitization block 14, and these values ​​can be sampled once to produce their digitized version, or they can be sampled multiple times and these samples are averaged to produce a digitized version.

[0201] The values ​​measured during the fourth time period of the SVPWM partition will be measured simultaneously, substantially simultaneously, or as close as possible in time. This measurement involves digitizing the measured values ​​through amplification / filtering / digitization block 14, and these values ​​can be sampled once to produce their digitized version, or they can be sampled multiple times and these samples are averaged to produce a digitized version.

[0202] The chart below summarizes which transistors are calibrated and which are read for each partition of SVPWM when using the second technique.

[0203]

[0204] The example of this second technique is SVPWM partitioning. Figure 4 The diagram shows the fourth SVPWM, and the phase current determination technique continues over seven periods P1-P7. It can be seen that Wl is high (turning on MN6) from the beginning of the second period to the end of the sixth period, Vl is high (turning on MN4) from the beginning of the third period to the end of the fifth period, and Wl is high during the fourth period. Wh, Vh, and Uh are complementary to Wl, Vl, and Ul, and therefore the operation of transistors MN1, MN3, and MN5 is complementary to the operation of transistors MN2, MN4, and MN6 as described above.

[0205] During the fourth SVPWM partition, the phase currents Iu, Iv, and Iw are calculated as follows. It should be understood that the amplification / filtering / digitization block 14 digitizes and regulates Vshunt, Vu, Vv, and Vw in the measurement steps described below, and the microcontroller 13 sequentially generates control signals Uh, Ul, Vh, Vl, Wh, and Wl.

[0206] During the second time period, the shunt voltage Vshunt across the shunt resistor Rsh is measured and stabilizes at the value of Vw2_sh, and the voltage Vw is measured and stabilizes at the value of Vw2_mos. Therefore, the drain-source resistance of MN6 can be calculated as follows:

[0207]

[0208] During the third time period, the shunt voltage Vshunt was measured and stabilized at the value of Vu3_sh, the voltage Vv was measured and stabilized at the value of Vv3_mos, and the voltage Vw was measured and stabilized at the value of Vw3_mos. Therefore, the drain-source resistance of MN4 can be calculated as follows:

[0209]

[0210] During the fourth time period, voltage Vv is measured and stabilizes at a value of Vv4_mos, and voltage Vw is measured and stabilizes at a value of Vw4_mos. Now, with the values ​​of RdsMN6 and RdsMN4, the phase current Iv can be calculated as follows:

[0211] Iv=Vv4_mos / RdsMN4

[0212] The phase current Iw can then be calculated as follows:

[0213] Iw=Vw4_mos / RdsMN6

[0214] Since the sum of the phase currents Iu, Iv, and Iw is zero, Iu can be calculated as follows:

[0215] Iu=-(Vv4_mos / RdsMN4+Vw4_mos / RdsMN6)

[0216] The values ​​of Vshunt and Vw measured during the second time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vshunt and Vw using amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vshunt and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vshunt and Vw.

[0217] Similarly, the values ​​of Vshunt, Vv, and Vw measured during the third time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, this measurement involves digitizing the analog values ​​of Vshunt, Vv, and Vw using amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vshunt, Vv, and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vshunt, Vv, and Vw.

[0218] Similarly, the values ​​of Vv and Vw measured during the fourth time period will be measured simultaneously, substantially simultaneously, or as close as possible in time. Furthermore, the measurement involves digitizing the analog values ​​of Vv and Vw via amplification / filtering / digitization block 14, and these analog values ​​can be sampled once to produce digital versions of Vv and Vw, or they can be sampled multiple times and these samples averaged to produce digital versions of Vv and Vw.

[0219] Second technology (low-cost variant)

[0220] Given the detailed disclosure above on how the second technology works, the following is a diagram summarizing a first variant of the second technology, in which the voltage of one phase in the phase is never measured and the two transistors are not calibrated at every time period.

[0221]

[0222] General comments applicable to the first and second technologies

[0223] Although the above techniques have been described with respect to the measurement results of the voltage across the low-side transistor and the determination results of the drain-source resistance of the low-side transistor, those skilled in the art will understand that these techniques are equally applicable to the high-side transistor.

[0224] Compared to existing systems that utilize one shunt per phase winding or two shunts per phase winding, the technology disclosed herein reduces power losses, lowers production costs, and eliminates asymmetry in the three-phase inverter bridge.

[0225] Compared to existing technology systems that also utilize a shunt, the technique disclosed in this paper eliminates the difficulties encountered when reading voltage under boundary conditions and provides simultaneous or substantially simultaneous sampling of two-phase voltages (for more accurate results).

[0226] Furthermore, it should be noted that the above techniques can be applied to other PWM modes, such as sine wave, third harmonic, discontinuous SVPWM, etc. Although the specific measurements performed during which time periods may change, the transistor calibration concepts described above remain valid.

[0227] Further details of the above-described technology can be found in U.S. Patent 11,105,836, the contents of which are incorporated herein by reference in their entirety.

[0228] Temperature sensing using phase current determination technology

[0229] Now for reference Figure 1A The description covers the operation of temperature sensing of transistors MN1-MN6 in power system 10 and the modification of the inverter operation performed on them.

[0230] This operation continues during the calibration (e.g., "offline") phase and the operation (e.g., "online") phase. The calibration phase can be performed once after manufacturing, or it can be performed at each startup of the power system 10.

[0231] During the calibration phase, the microcontroller 13 uses an interpolation method to correlate the drain-source resistance of transistors MN1-MN6 with their junction temperatures. For this purpose, according to a simpler first technique, manufacturing tolerances and process variations can be ignored, and the junction temperature Tjunction (T-junction) at multiple different RDSON values ​​is determined by the microcontroller 13. This determination can be performed by assuming known values ​​(e.g., from the datasheets of transistors MN1-MN6) are true and normalizing these values. The following shows sample values ​​of Tjunction and normalized RDSON for transistors MN1-MN6.

[0232]

[0233]

[0234] Normalization can be performed by the microcontroller 13 based on known values ​​of RDSON at a given junction temperature, such as at a junction temperature Tjunction of 25°C. For example, the predicted value of RDSON at a junction temperature Tjunction of 25°C can be set to 1, and then the remainder of the predicted values ​​of RDSON at different junction temperatures Tjunctions can be normalized to this normalized RDSON value (25°C). For transistors MN1-MN6 of a given type, the sample normalized values ​​of RDSON for junction temperature Tjunction can be... Figure 5 As observed in the chart.

[0235] According to a more complex second technique, manufacturing tolerances and process variations are taken into account. Here, the motor 11 includes a housing 30 carrying transistors MN1-MN6, and a conventional temperature sensor 31 that provides a temperature output to the control circuitry 15. Therefore, during a calibration phase when the power system 10 is cold (e.g., having been inactive for a period of time), the temperature sensor 31 reads the temperature within the housing 30 and provides this reading to the microcontroller 13, and the RDSON values ​​of transistors MN2, MN4, and MN6 are read by the microcontroller 13 at the cold temperatures present during the calibration phase. This reading is obtained at a cold temperature because, when cold temperatures are present during the calibration phase, the reading will be approximately equivalent to the junction temperature Tjunction within transistors MN2, MN4, and MN6.

[0236] The microcontroller 13 calculates a calibration factor p_calib for each transistor MN2, MN4, and MN6, which is the ratio of the RDSON at the cold temperature (RDSON_Calibrate) to the expected assumed known value of RDSON at that temperature (RDSON_Typical). Then, the normalized junction temperature Tjunction at several different RDSON values ​​determined above according to the simpler first technique is multiplied by the calibration factor p_calib to produce calibrated, normalized values. The sample values ​​of Tjunction and calibrated, normalized RDSON for transistors MN2, MN4, and MN6 are shown below.

[0237] RDSON(mΩ) Tjunction (°C) 1.68×p_calib -50 1.92×p_calib -25 2.11×p_calib 0 2.40×p_calib 25 2.68×p_calib 50 2.97×p_calib 75 3.28×p_calib 100 3.64×p_calib 125 4.00×p_calib 150 4.39×p_calib 175

[0238] Using the values ​​of RDSON and Tjunction determined by either the simpler first technique or the more complex second technique, the microcontroller 13 performs a second-order polynomial interpolation method to determine the coefficients of the relationship function between Tjunction and RDSON. The resulting relationship function is:

[0239] f(x) = p1·x 2 +p2·x+p3,

[0240] Where f(x) is a Tjunction and x is an RDSON.

[0241] The sample relationship function determined as described above is in Figure 6 As shown in the chart.

[0242] The determination of the relational function concludes the calibration phase, and then the operation phase begins. During the operation phase, the inverter 12 is operated by the control circuit device 15 to drive the motor 11 as described above. The determined phase currents are used as feedback to control the generation of control signals Uh, Ul for MN1-MN2, control signals Vh, Vl for MN3-MN4, and control signals Wh, Wl for MN5-MN6. Furthermore, when calculating each value of RDSON for transistors MN2, MN4, and MN6, the microcontroller 13 uses the relational function to determine the current junction temperature Tjunction of these transistors. Below, since the current flowing through MN1 is the same as the current flowing through MN2, the current flowing through MN3 is the same as the current flowing through MN4, and since the current flowing through MN5 is the same as the current flowing through MN6, it can be assumed that the RDSON value of MN1 (and therefore the Tjunction value) is equal to the RDSON and Tjunction values ​​of MN2, the RDSON and Tjunction values ​​of MN3 are equal to the RDSON and Tjunction values ​​of MN4, and the RDSON and Tjunction values ​​of MN5 are equal to the RDSON and Tjunction values ​​of MN6.

[0243] The junction temperature Tjunction of transistors MN2, MN4, and MN6 is used to maintain the safe operation of transistors MN1-MN6, thereby avoiding thermal stress. See also... Figure 1B The function is described as follows: The determination of the phase currents and RDSON of transistors MN2, MN4, and MN6 is represented by current sampling 26 performed by microcontroller 13, and the determination of the Tjunction of each transistor is represented by Tjunction estimation 22 performed by microcontroller 22.

[0244] If Tjunction is greater than the maximum safe temperature Tmax of any of transistors MN2, MN4, and MN6, the microcontroller 13 executes overheat fault handling 24 to stop the inverter 12 from operating. To stop the inverter 12 from operating, the control function 21 of the microcontroller 13 stops providing control signals Uh, Ul, Vh, Vl, and Wh, Wl to the inverter 12.

[0245] Furthermore, for each transistor MN2, MN4, and MN6, if Tjunction is less than the maximum safe operating temperature Tmax, the microcontroller 13 executes a current limit threshold determination process 23. Through this process, the control function 21 of the microcontroller 13 determines and uses the maximum safe current of that Tjunction value to modify the supply of control signals Uh, Ul, Vh, Vl, and Wh, Wl to the inverter 12, thereby maintaining the current through the transistor at the maximum safe current of the current Tjunction value. Through this functionality, the maximum safe current through transistors MN2, MN4, and MN6, and correspondingly through transistors MN1, MN3, and MN5, is maintained regardless of the current operating temperature, and the current operating temperature is accurately determined. Since, as explained above, the Tjunction values ​​of MN1 and MN2 can be considered the same, therefore the Tjunction values ​​of MN3 and MN4 can be considered the same, and the Tjunction values ​​of MN5 and MN6 can be considered the same; the modification of the control for these transistor pairs is executed accordingly. For example, control signals Uh and Ul are modified in the same way as described above, control signals Vh and Vl are modified in the same way as described above, and control signals Wh and Wl are modified in the same way as described above. The result of this operation can be... Figure 7 As observed in the chart, Figure 7 This shows how the drain current of transistors MN1-MN6 decreases as temperature increases.

[0246] The benefits provided by this temperature measurement technique are clear. Since the actual junction temperatures of transistors MN2, MN4, and MN6 are determined, this technique is unaffected by the inaccuracies inherent in the use of conventional in-case temperature sensors, and by the inaccuracies arising from techniques that assume RDSON values ​​instead of directly measuring them. Furthermore, the junction temperature of each transistor can be determined using the technique described herein, in contrast to existing techniques that require the use of three or more conventional in-case temperature sensors to attempt to determine the junction temperature, and even then, this is not possible because the junction temperature changes at a much faster rate than the in-case temperature. Moreover, as explained, the dynamic adjustment of inverter 12 based on the thermal condition of each transistor helps to provide the highest possible power delivery at any given moment.

[0247] Although this disclosure has been described with respect to a limited number of embodiments, those skilled in the art who benefit from this disclosure will understand that other embodiments can be conceived without departing from the scope of this disclosure disclosed herein. Therefore, the scope of this disclosure should be limited only by the appended claims.

Claims

1. An electrical device comprising an inverter system to be coupled to phase windings of a motor to drive the motor, the inverter system comprising: A switching branch, coupled between a DC power supply voltage node and an intermediate node, wherein each switching branch has a terminal to be coupled to a corresponding phase winding of the motor; A shunt resistor is coupled between the intermediate node and ground; as well as A control circuit device is configured to apply a control signal to the switching branch according to a control scheme, so that the inverter drives the phase windings of the motor with a multiphase AC power signal; The control scheme is divided into zones, and each zone is further divided into time periods; The control circuitry is configured to operate during at least some partitions of the control scheme: During a first given time period: the shunt voltage across the shunt resistor is measured; and the drain-source voltage of the first calibration transistor, which is a transistor of a given switching branch, is measured; as well as The drain-source resistance of the first calibration transistor is determined based on the resistance of the shunt resistor, the drain-source voltage of the first calibration transistor measured during the first given time period, and the shunt voltage measured during the first given time period; and The control circuit device is further configured to: Control the drive of the given switch branch; The temperature of the first calibration transistor is determined based on the drain-source resistance of the first calibration transistor during the driving of the motor by the inverter system. The drive of the given switch branch is modified to maintain the conductivity of the first calibration transistor at a maximum level, wherein the temperature of the first calibration transistor is kept below a threshold temperature. as well as When the temperature of the first calibration transistor exceeds the threshold temperature, the driving of the given switching branch is stopped.

2. The electrical device of claim 1, wherein the control circuit device is further configured to: during a calibration phase, interpolate an assumed value of the drain-source resistance of the first calibration transistor for a given temperature value of the first calibration transistor, thereby generating a nonlinear model of the drain-source resistance of the first calibration transistor with respect to temperature; and wherein the control circuit device uses the nonlinear model and the drain-source resistance of the first calibration transistor to determine the temperature of the first calibration transistor.

3. The electrical device of claim 2, wherein the control circuit device is further configured to: normalize the assumed value of the drain-source resistance of the first calibration transistor during the calibration phase, prior to performing the interpolation.

4. The electrical equipment according to claim 2, further comprising a housing that at least supports the switching branch and the shunt resistor, wherein a temperature sensor is positioned within the housing; and The control circuitry is further configured to: The temperature inside the housing is read from the temperature sensor; From the assumed value of the drain-source resistance of the first calibration transistor for the given temperature value, determine the expected drain-source resistance of the first calibration transistor for the read temperature; Determine the ratio between the drain-source resistance of the first calibration transistor and the expected drain-source resistance of the first calibration transistor; as well as Before performing the interpolation, the assumed value of the drain-source resistance of the first calibration transistor for the given temperature value of the first calibration transistor is calibrated using the determined ratio, such that the interpolation is performed on the calibrated assumed value of the drain-source resistance of the first calibration transistor for the given temperature value of the first calibration transistor.

5. The electrical device of claim 4, wherein the control circuitry is further configured to: normalize the assumed value of the drain-source resistance of the first calibration transistor during the calibration phase, prior to determining the expected drain-source resistance of the first calibration transistor for the read temperature.

6. The electrical device of claim 2, wherein the interpolation generates a second-order nonlinear model representing the relationship between the drain-source resistance of the first calibrated transistor and temperature.

7. The electrical equipment according to claim 1, The motor described therein has a first phase winding, a second phase winding, and a third phase winding; The switch branch includes: A first switching branch is coupled between the DC power supply voltage node and the intermediate node, and the first switching branch has a first terminal to be coupled to the first phase winding. A second switching branch, coupled between the DC power supply voltage node and the intermediate node, has a second terminal to be coupled to the second phase winding; and The third switching branch is coupled between the DC power supply voltage node and the intermediate node, and the third switching branch has a third terminal to be coupled to the third phase winding. The control scheme mentioned above includes a space vector pulse width modulation (SVPWM) scheme, the partitions include six partitions, the time periods include multiple time periods, and each of the six partitions is divided into multiple time periods; The multiphase AC power signal mentioned above includes a three-phase AC power signal; The control circuit device applies the control signal to the first switch branch, the second switch branch and the third switch branch according to the SVPWM scheme, so that the inverter drives the first phase winding, the second phase winding and the third phase winding of the motor with the three-phase AC power signal; Wherein the first given time period is the second time period of at least some partitions of the SVPWM scheme; The control circuitry is configured to operate during at least some partitions of the SVPWM scheme: During the fourth time period: the drain-source voltage of the first calibration transistor is measured; and the drain-source voltage of the transistor under test, which is the transistor of the next switching branch, is measured; The phase current of a given phase winding coupled to the given switching branch is determined based on the drain-source voltage of the first calibration transistor and the drain-source resistance of the first calibration transistor measured during the fourth time period. The phase current of the next phase winding coupled to the next switching branch is determined based on the drain-source voltage of the measured transistor measured during the fourth time period and the drain-source resistance of the measured transistor known from previous partitions of the SVPWM scheme; and Based on the phase current of the given phase winding and the phase current of the next phase winding, determine the phase current of the remaining phase winding coupled to the remaining switch branch; and The control circuitry controls the driving of the first switching branch, the second switching branch, and the third switching branch based on the phase current of the given phase winding, the phase current of the next phase winding, and the phase current of the remaining phase winding; and The control circuit device is further configured to: The temperature of the measured transistor is determined based on the drain-source resistance of the measured transistor during the driving of the motor by the inverter system. Modify the drive of the next switching branch to maintain the conductivity of the measured transistor at a maximum level, whereby the temperature of the measured transistor remains below the threshold temperature; and When the temperature of the measured transistor exceeds the threshold temperature, the driving of the next switching branch is stopped.

8. The electrical device of claim 7, wherein the first calibration transistor is a low-side transistor of the given switching branch; and wherein the transistor being measured is a low-side transistor of the next switching branch.

9. The electrical apparatus of claim 7, wherein the control circuit device determines the drain-source resistance of the first calibration transistor as: Where Rshunt is the resistance of the shunt resistor, V1phase2 is the drain-source voltage of the first calibration transistor measured during the second time period, and Vshunt2 is the shunt voltage measured during the second time period.

10. The electrical apparatus of claim 9, wherein the control circuit device determines the phase current of the given phase winding as: Iphase1 = V1phase4 / Rds (calibration transistor) Wherein V1phase4 is the drain-source voltage of the first calibration transistor measured during the fourth time period, and Rds (calibration transistor) is the drain-source resistance of the first calibration transistor.

11. The electrical apparatus of claim 10, wherein the control circuit determines the phase current of the next phase winding as: Iphase2 = V2phase4 / Rds (the crystal being measured) Wherein V2phase4 is the drain-source voltage of the transistor under test measured during the fourth time period, and Rds (transistor under test) is the drain-source resistance of the transistor under test known from the previous SVPWM partition.

12. The electrical apparatus of claim 11, wherein the control circuit device determines the phase current of the remaining phase winding as: Iphase3=-(Iphase1+Iphase2).

13. An inverter system to be coupled to a three-phase winding of a motor, the inverter system comprising: The first switching branch is coupled between the DC power supply voltage node and the intermediate node, and the first switching branch has a first terminal to be coupled to the first phase winding of the motor. The second switching branch is coupled between the DC power supply voltage node and the intermediate node, and the second switching branch has a second terminal to be coupled to the second phase winding of the motor. The third switching branch is coupled between the DC power supply voltage node and the intermediate node, and the third switching branch has a third terminal to be coupled to the third phase winding of the motor. A shunt resistor is coupled between the intermediate node and ground; as well as The control circuit is configured to apply control signals to the first switch branch, the second switch branch and the third switch branch according to a space vector pulse width modulation (SVPWM) scheme to drive the first phase winding, the second phase winding and the third phase winding of the motor with a three-phase AC power signal; The SVPWM scheme is divided into six partitions, and each partition is further divided into multiple time periods, including the first time period, the second time period, the third time period, and the fourth time period. as well as The control circuitry is configured to operate during at least some partitions of the SVPWM scheme: During the second time period of the plurality of time periods: Measure the shunt voltage across the shunt resistor; as well as Measure the drain-source voltage of the first calibration transistor, which is a transistor of a given switching branch; During the third time period of the plurality of time periods: Measure the shunt voltage across the shunt resistor; Measure the drain-source voltage of the second calibration transistor, which is the transistor of the next switching branch; as well as Measure the drain-source voltage of the first calibration transistor; During the fourth time period of the plurality of time periods: Measure the drain-source voltage of the first calibration transistor; Measure the drain-source voltage of the second calibration transistor; as well as Measure the drain-source voltage of the transistor under test, wherein the transistor under test is a transistor of the remaining switching branch; The drain-source resistance of the first calibration transistor is determined based on the resistance of the shunt resistor, the drain-source voltage of the first calibration transistor measured during the second time period, and the shunt voltage measured during the second time period. The drain-source resistance of the second calibration transistor is determined based on the resistance of the shunt resistor, the drain-source resistance of the first calibration transistor, the drain-source voltage of the first calibration transistor measured during the fourth time period, the drain-source voltage of the second calibration transistor measured during the fourth time period, and the shunt voltage measured during the fourth time period. The phase current of a given phase winding coupled to the given switching branch is determined based on the drain-source voltage of the first calibration transistor and the drain-source resistance of the first calibration transistor measured during the fourth time period. The phase current of the next phase winding coupled to the next switching branch is determined based on the drain-source voltage of the second calibration transistor and the drain-source resistance of the second calibration transistor measured during the fourth time period. as well as The phase current of the remaining phase winding coupled to the remaining switch branch is determined based on the phase current of the given phase winding and the phase current of the next phase winding. The control circuit device is further configured to: The driving of the first switch branch, the second switch branch, and the third switch branch is controlled based on the phase current of the given phase winding, the phase current of the next phase winding, and the phase current of the remaining phase winding. The temperature of the first calibration transistor is determined based on the drain-source resistance of the first calibration transistor during the driving of the motor by the inverter system. The drive of the given switch branch is modified to maintain the conductivity of the first calibration transistor at a maximum level, wherein the temperature of the first calibration transistor is kept below a threshold temperature. When the temperature of the first calibration transistor exceeds the threshold temperature, the driving of the given switching branch is stopped; The temperature of the measured transistor is determined based on the drain-source resistance of the measured transistor during the driving of the motor by the inverter system. Modify the drive of the next switching branch to maintain the conductivity of the measured transistor at a maximum level, whereby the temperature of the measured transistor remains below the threshold temperature. as well as When the temperature of the measured transistor exceeds the threshold temperature, the driving of the next switching branch is stopped.

14. The inverter system of claim 13, wherein the control circuitry is further configured to: during a calibration phase, interpolate an assumed value of the drain-source resistance of the first calibration transistor for a given temperature value of the first calibration transistor, thereby generating a nonlinear model of the drain-source resistance of the first calibration transistor with respect to temperature; and wherein the control circuitry uses the nonlinear model and the drain-source resistance of the first calibration transistor to determine the temperature of the first calibration transistor.

15. The inverter system of claim 14, wherein the control circuitry is further configured to: normalize the assumed value of the drain-source resistance of the first calibration transistor during the calibration phase, prior to performing the interpolation.

16. The inverter system of claim 14, further comprising a housing that at least carries the first switching branch, the second switching branch, the third switching branch, and the shunt resistor, wherein a temperature sensor is positioned within the housing; and The control circuitry is further configured to: The temperature inside the housing is read from the temperature sensor; From the assumed value of the drain-source resistance of the first calibration transistor for the given temperature value, determine the expected drain-source resistance of the first calibration transistor for the read temperature; Determine the ratio between the drain-source resistance of the first calibration transistor and the expected drain-source resistance of the first calibration transistor; as well as Before performing the interpolation, the assumed value of the drain-source resistance of the first calibration transistor for the given temperature value of the first calibration transistor is calibrated using the determined ratio, such that the interpolation is performed on the calibrated assumed value of the drain-source resistance of the first calibration transistor for the given temperature value of the first calibration transistor.

17. The inverter system of claim 16, wherein the control circuitry is further configured to: normalize the assumed value of the drain-source resistance of the first calibration transistor during the calibration phase, prior to determining the expected drain-source resistance of the first calibration transistor for the read temperature.

18. The inverter system of claim 14, wherein the interpolation generates a second-order nonlinear model representing the relationship between the drain-source resistance of the first calibration transistor and temperature.

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