A narrow pulse suppression method and storage medium for a drive motor controller

Abstract

The present invention relates to the technical field of new energy vehicles, and particularly relates to a narrow pulse suppression method and storage medium for a drive motor controller. When PWM adopts a symmetric generation, up-down counting mode; in the stage where PWM changes from increasing to decreasing, when outputting a narrow pulse, a low-level output process is performed; in the stage where PWM changes from decreasing to increasing, when outputting a narrow pulse, the pulse is amplified to the minimum boundary value. This method eliminates the false RDY fault of the controller caused by narrow pulses.

Description

Technical Field

[0001] The present invention relates to the technical field of new energy vehicles, and particularly relates to a narrow pulse suppression method and a storage medium for a drive motor controller. Background Art

[0002] When the output modulation ratio of the motor is very high, it often outputs pulses with a very short high-level duration. We call such pulses narrow pulses. Since narrow pulses do not affect motor control, few people pay attention to them and suppress them. Since IGBT switching tubes require time, if the narrow pulse time is too short, the IGBT may need to be closed-loop again before it is fully opened. This working condition will affect the service life of the IGBT and also increase the heat generation of the IGBT.

[0003] In the space vector modulation mode, the duty ratios of the drive signals generated at different modulation ratios are different. As Figure 1 can be seen, when the modulation ratio is small, the duty ratio of the drive signal fluctuates around 0.5; when the modulation ratio is large, narrow pulses will appear in the drive. Two hazards of narrow pulses:

[0004] 1) The opening and closing of power switch devices require a certain amount of time. The occurrence of narrow pulses can cause the switch devices to fail and affect the safe operation of the switching tubes. In severe cases, the system will burn out and cause huge losses.

[0005] 2) The drive chip model that meets functional safety is: Infineon, 1EDI3021AS. This chip has a gate state monitoring function. When a level conversion occurs at the TOUT pin, it will monitor the IGBT gate voltage Vgate to ensure that the Vgate voltage reaches the expected value. When a level conversion occurs at the TOUT pin of the drive chip, if it is detected within 7.6 us that the IGBT gate voltage Vgate does not reach the expected value of 12.7V, a gatemonitoring fault will be reported and uploaded as an RDY fault within 2.5 us. If our narrow pulse signal is very narrow and the PWM pulse width of the drive signal TOUT output is less than 3 us, the gate voltage Vgate of the IGBT will not rise to the threshold (12.7V) within 3 us. After about 7 us detection cycle, it is determined as a gate monitoring fault and an RDY fault is reported. From this analysis, the PWM pulse width is too narrow, resulting in the IGBT gate voltage not being able to rise to the threshold of V(GATEVCCH)=Vcc2 - 2.1V = 12.7V within the specified time, and an RDY fault will be reported. That is, narrow pulses cause the controller to falsely report an RDY fault. Summary of the Invention

[0006] The object of the present invention is to provide a narrow pulse suppression method and a storage medium for a drive motor controller in view of the defects of the prior art, eliminating the false RDY fault of the controller caused by narrow pulses.

[0007] A narrow pulse suppression method for a drive motor controller provided by the present invention includes

[0008] When PWM adopts a symmetric generation and increasing-decreasing counting mode;

[0009] In the stage where PWM changes from increasing to decreasing, when outputting a narrow pulse, output a low level.

[0010] In the stage where PWM changes from decreasing to increasing, when outputting a narrow pulse, amplify the pulse to the minimum boundary value.

[0011] Preferably, the step of outputting a low level when outputting a narrow pulse in the stage where PWM changes from increasing to decreasing includes:

[0012] When cmp > (Ts / 2 - Td / 2), the comparison value remains unchanged;

[0013] Wherein, cmp is the comparison value, Ts is the period value, and Td is the dead time.

[0014] Preferably, the step of outputting a low level when outputting a narrow pulse in the stage where PWM changes from increasing to decreasing includes:

[0015] When (Ts / 2 - (T0 + Td) / 2) <= cmp <= (Ts / 2 - Td / 2), cmp = Ts / 2;

[0016] Wherein, cmp is the comparison value, Ts is the period value, Td is the dead time, and T0 is the minimum pulse value.

[0017] Preferably, the step of outputting a low level when outputting a narrow pulse in the stage where PWM changes from increasing to decreasing includes:

[0018] When cmp < (Ts / 2 - (T0 + Td) / 2), the comparison value remains unchanged;

[0019] Wherein, cmp is the comparison value, Ts is the period value, Td is the dead time, and T0 is the minimum pulse value.

[0020] Preferably, the step of amplifying the pulse to the minimum boundary value when outputting a narrow pulse in the stage where PWM changes from decreasing to increasing includes:

[0021] When cmp + cmp1 < Td, the comparison value remains unchanged;

[0022] Wherein, cmp is the comparison value, cmp1 is the comparison value of the previous cycle, and Td is the dead time.

[0023] More preferably, in the stage where PWM decreases and then increases, when outputting a narrow pulse, amplifying the pulse to the minimum boundary value includes:

[0024] When Td <= cmp + cmp1 < (T0 + Td), cmp = T0 + Td - cmp1;

[0025] Wherein, cmp is the comparison value, cmp1 is the comparison value of the previous cycle, Td is the dead time, and T0 is the minimum pulse value.

[0026] More preferably, in the stage where PWM decreases and then increases, when outputting a narrow pulse, amplifying the pulse to the minimum boundary value includes:

[0027] When cmp + cmp1 >= (T0 + Td), the comparison value remains unchanged;

[0028] Wherein, cmp is the comparison value, cmp1 is the comparison value of the previous cycle, Td is the dead time, and T0 is the minimum pulse value.

[0029] More preferably, when the PWM adopts a symmetric generation and increasing / decreasing counting mode, the comparison register loads the register value twice within one switching cycle. When the count value is equal to the comparison register value, the PWM will change the level according to the preset setting to generate a drive signal with a variable duty cycle.

[0030] More preferably, the method is applied to a drive chip with the model of Infineon, 1EDI3021AS.

[0031] The present invention also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the above-mentioned method are implemented.

[0032] The beneficial effects of the present invention are as follows: In the stage where PWM increases and then decreases, when outputting a narrow pulse, the output is processed as a low level; in the stage where PWM decreases and then increases, when outputting a narrow pulse, the pulse is amplified to the minimum boundary value. This makes the PWM pulse width (high-level time) output by TOUT at least greater than 3 us. When the high-level time output by TOUT is greater than 3 us, sufficient Vgate rising time is provided, the Vgate voltage can rise to 12.7V, and the RDY fault is no longer reported. Description of the Drawings

[0033] Figure 1 It is a schematic diagram of a narrow pulse that appears when the modulation is relatively large;

[0034] Figure 2 It is a schematic diagram of the method flow of the present invention;

[0035] Figure 3 Schematic diagram of the narrow pulse generated when changing from increasing to decreasing;

[0036] Figure 4 Schematic diagram of the narrow pulse generated when changing from decreasing to increasing;

[0037] Figure 5 Schematic diagram of the driving chip timing. Detailed implementation manners

[0038] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0039] It should be understood that when used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.

[0040] It should also be understood that the term "and / or" used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0041] As used in the specification of the present application and the appended claims, the term "if" can be interpreted as "when", "once", "in response to determining", or "in response to detecting" according to the context. Similarly, the phrase "if determined" or "if [the described condition or event] is detected" can be interpreted as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]" according to the context.

[0042] In addition, in the description of the specification of the present application and the appended claims, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance.

[0043] References to "an embodiment" or "some embodiments" etc. described in the specification of this application mean that specific features, structures, or characteristics described in connection with that embodiment are included in one or more embodiments of this application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized. "Plurality" means "two or more".

[0044] Embodiment 1

[0045] Figure 2 shows a structural schematic diagram of a narrow pulse suppression method for a drive motor controller provided by a preferred embodiment ( Figure 3 shows a first embodiment of this application). For the sake of convenience of description, only the parts related to this embodiment are shown and are described in detail as follows:

[0046] A narrow pulse suppression method for a drive motor controller, comprising

[0047] When PWM adopts symmetric generation and up-down counting mode;

[0048] In the stage where PWM changes from increasing to decreasing, when outputting a narrow pulse, perform an output low-level process;

[0049] In the stage where PWM changes from decreasing to increasing, when outputting a narrow pulse, amplify the pulse to the minimum boundary value.

[0050] When PWM adopts symmetric generation and up-down counting mode, the comparison register loads the register value twice within one switching period. When the count value is equal to the value of the comparison register, PWM will change the level according to the preset setting to generate a drive signal with a variable duty cycle. When using the up-down mode, EPWM configuration is required, the counter makes two comparisons, and corresponding actions are generated. When the values of the comparison register and the counter are equal in the decreasing or increasing mode, PWM will respectively flip to high and low levels.

[0051] Such as Figure 3As shown, when increasing from increasing to decreasing, EPWMXA generates a narrow pulse with a high level of t, a period value of Ts / 2, a comparison value of cmp, and a dead time of Td. If our minimum limit for the narrow pulse is T0, then when (Ts / 2 - cmp)*2 - Td < 0, the output pulse is completely eaten by the dead time, and there is no narrow pulse output at this time, and the output is low level; when 0 <= (Ts / 2 - cmp)*2 - Td <= T0, a narrow pulse will be output at this time, and the high level time of the pulse is less than T0; when (Ts / 2 - cmp)*2 - Td > T0, a wide pulse is output at this time, and the high level time of the pulse is greater than T0. To suppress the narrow pulse output, the following processing is done:

[0052] cmp = cmp when cmp > (Ts / 2 - Td / 2)

[0053] cmp = Ts / 2 when (Ts / 2 - (T0 + Td) / 2) <= cmp <= (Ts / 2 - Td / 2)

[0054] cmp = cmp when cmp < (Ts / 2 - (T0 + Td) / 2)

[0055] That is, when the comparison value is greater than half of the period value minus half of the dead time, the comparison value remains unchanged; when the comparison value is less than half of the period value minus half of the sum of the dead time and the minimum pulse value, the comparison value remains unchanged; otherwise, the comparison value is equal to the period value. It is equivalent to directly outputting a low level when outputting a narrow pulse.

[0056] As Figure 4 shown, when decreasing from decreasing to increasing, EPWMXB generates a narrow pulse with a high level of t, a period value of Ts / 2, the comparison value of the previous period is cmp1, the comparison value of this period is cmp, and the dead time is Td. If our minimum limit for the narrow pulse is T0, then when cmp1 + cmp - Td < 0, the output pulse is completely eaten by the dead time, and there is no narrow pulse output at this time, and the output is low level; when 0 <= cmp1 + cmp - Td < T0, a narrow pulse will be output at this time, and the high level time of the pulse is less than T0; when cmp1 + cmp - Td > T0, a wide pulse is output at this time, and the high level time of the pulse is greater than T0. To suppress the narrow pulse output, the following processing is done:

[0057] cmp = cmp when cmp + cmp1 < Td

[0058] cmp = T0 + Td - cmp1 when Td <= cmp + cmp1 < (T0 + Td)

[0059] cmp = cmp when cmp + cmp1 >= (T0 + Td)

[0060] When the sum of the comparison value and the comparison value of the previous cycle is less than the dead time, the comparison value remains unchanged; when the sum of the comparison value and the comparison value of the previous cycle is greater than the sum of the dead time and the minimum pulse value, the comparison value remains unchanged; otherwise, the comparison value is equal to the sum of the dead time and the minimum pulse value minus the comparison value of the previous cycle. This is equivalent to directly amplifying the pulse to the minimum boundary value when outputting a narrow pulse.

[0061] Embodiment 2

[0062] In this embodiment, the effectiveness of this method is verified with a specific motor.

[0063] The rated speed of the motor is 1500 rpm, and the peak speed is 3000 rpm. The model of the motor controller drive chip is: Infineon, 1EDI3021AS. This chip has a gate state monitoring function. When the no-load motor speed is pulled down to 1700 rpm without narrow pulse suppression, the controller reports an RDY fault, and this fault can be stably reproduced.

[0064] As Figure 5 As shown in the timing diagram of the drive chip, when a level conversion occurs at the TOUT pin of the drive chip, it will monitor the IGBT gate voltage Vgate to ensure that the Vgate voltage reaches the expected value. If it is detected that the Vgate voltage does not reach the expected value V(GATEVCCH) = Vcc2 - 2.1V = 12.7V within 7.6 us, it is determined as a gate monitoring fault, and it is uploaded as an RDY fault within 2.5 us.

[0065] After analysis, it is found that the narrow pulse causes the controller to misreport the RDY fault. After adding the narrow pulse suppression algorithm according to this method, the narrow pulse disappears, that is, the minimum PWM pulse width (high-level time) output by TOUT will be greater than 3 us. Because it takes time for the IGBT gate voltage Vgate to rise, when the high-level time output by TOUT is greater than 3 us, it is equivalent to providing enough time for Vgate to rise, and the Vgate voltage can rise to 12.7V, so the RDY fault is no longer reported.

[0066] It should be understood that the specific order or hierarchy of steps in the disclosed process is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of protection of the present disclosure. The appended method claims present the elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0067] In the foregoing detailed description, various features are combined in a single embodiment to simplify the present disclosure. This method of disclosure should not be interpreted as reflecting an intention that the embodiments of the claimed subject matter require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the invention lies in less than all of the features of a single disclosed embodiment. Accordingly, the appended claims are hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0068] The above-described disclosed embodiments are described to enable any person skilled in the art to make or use the present invention. For those skilled in the art, various modifications to these embodiments are obvious, and the general principles defined herein can be applied to other embodiments without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is not limited to the embodiments given herein, but is consistent with the broadest scope of the principles and novel features disclosed in this application.

[0069] The foregoing description includes examples of one or more embodiments. Of course, it is not possible to describe all possible combinations of components or methods for the purpose of describing the above embodiments, but those of ordinary skill in the art should recognize that the various embodiments can be further combined and arranged. Accordingly, the embodiments described herein are intended to cover all such changes, modifications, and variations that fall within the scope of the appended claims. In addition, with respect to the term "comprising" used in the specification or claims, this term is inclusive in a manner similar to the term "including", as interpreted when used as a transitional word in the claims. Further, any use of the term "or" in the claims or specification is to mean "non-exclusive or".

[0070] Those skilled in the art will also appreciate that the various illustrative logical blocks, units, and steps listed in the embodiments of the present invention can be implemented by electronic hardware, computer software, or a combination of the two. To clearly show the interchangeability of hardware and software, the various illustrative components, units, and steps have been generally described in terms of their functions. Whether such functions are implemented by hardware or software depends on the specific application and the design requirements of the overall system. Those skilled in the art can use various methods to implement the described functions for each specific application, but such implementation should not be construed as exceeding the scope of protection of the embodiments of the present invention.

[0071] In the embodiments of the present invention, the various illustrative logical blocks or units described can be implemented or operate the described functions by a general-purpose processor, a digital signal processor, an application specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of the above designs. The general-purpose processor can be a microprocessor, and optionally, the general-purpose processor can also be any conventional processor, controller, microcontroller or state machine. The processor can also be implemented by a combination of computing devices, such as a digital signal processor and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a digital signal processor core, or any other similar configuration.

[0072] The steps of the methods or algorithms described in the embodiments of the present invention can be directly embedded in hardware, software modules executed by the processor, or a combination of the two. The software modules can be stored in a RAM memory, a flash memory, a ROM memory, an EPROM memory, an EEPROM memory, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium in the art. Exemplarily, the storage medium can be connected to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Optionally, the storage medium can also be integrated into the processor. The processor and the storage medium can be disposed in an ASIC, and the ASIC can be disposed in a user terminal. Optionally, the processor and the storage medium can also be disposed in different components of the user terminal.

[0073] In one or more exemplary designs, the functions described in embodiments of the present invention may be implemented in hardware, software, firmware, or any combination of the three. If implemented in software, these functions may be stored on a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. A computer-readable medium includes both computer storage media and communication media that facilitate transfer of a computer program from one place to another. The storage media may be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. In addition, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, DSL, or wireless means such as infrared, radio, and microwave, it is included in the definition of computer-readable medium. Disk and disc include compact disk, laser disk, optical disk, DVD, floppy disk, and Blu-ray disk, where disks usually reproduce data magnetically, while discs usually reproduce data optically with lasers. The above combinations should also be included within the scope of computer-readable media.

[0074] The above-described embodiments are only used to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application and should all be included within the protection scope of the present application.

Claims

1. A narrow pulse suppression method for a drive motor controller, characterized in that: The method is applied to a drive chip with the model number Infineon, 1EDI3021AS, and includes When PWM adopts symmetric generation and up-down counting mode; In the stage where PWM changes from increasing to decreasing, when outputting a narrow pulse, output a low level; In the stage where PWM changes from decreasing to increasing, when outputting a narrow pulse, amplify the pulse to the minimum boundary value; In the stage where PWM changes from increasing to decreasing, when the comparison value is greater than half of the cycle value minus the dead time, the comparison value remains unchanged; when the comparison value is less than half of the sum of the cycle value minus the dead time and the minimum pulse value, the comparison value remains unchanged; otherwise, the comparison value is equal to the cycle value; In the stage where PWM changes from decreasing to increasing, when the sum of the comparison value and the comparison value of the previous cycle is less than the dead time, the comparison value remains unchanged; when the sum of the comparison value and the comparison value of the previous cycle is greater than the sum of the dead time and the minimum pulse value, the comparison value remains unchanged; otherwise, the comparison value is equal to the sum of the dead time and the minimum pulse value minus the comparison value of the previous cycle.

2. The narrow pulse suppression method for a drive motor controller according to claim 1, wherein The step of outputting a low level when outputting a narrow pulse in the stage where PWM changes from increasing to decreasing includes: When cmp > (Ts / 2 - Td / 2), the comparison value remains unchanged; Among them, cmp is the comparison value, Ts is the cycle value, and Td is the dead time.

3. The narrow pulse suppression method for a drive motor controller according to claim 1, wherein The step of outputting a low level when outputting a narrow pulse in the stage where PWM changes from increasing to decreasing includes: When (Ts / 2 - (T0 + Td) / 2) <= cmp <= (Ts / 2 - Td / 2), cmp = Ts / 2; Among them, cmp is the comparison value, Ts is the cycle value, Td is the dead time, and T0 is the minimum pulse value.

4. The narrow pulse suppression method for a drive motor controller according to claim 1, wherein, The step of outputting a low level when outputting a narrow pulse in the stage where PWM changes from increasing to decreasing includes: When cmp < (Ts / 2 - (T0 + Td) / 2), the comparison value remains unchanged; Among them, cmp is the comparison value, Ts is the cycle value, Td is the dead time, and T0 is the minimum pulse value.

5. The narrow pulse suppression method for a drive motor controller according to claim 1, wherein The step of amplifying the pulse to the minimum boundary value when outputting a narrow pulse in the stage where PWM changes from decreasing to increasing includes: When cmp + cmp1 < Td, the comparison value remains unchanged; Among them, cmp is the comparison value, cmp1 is the comparison value of the previous cycle, and Td is the dead time.

6. The narrow pulse suppression method for a drive motor controller according to claim 1, characterized in that The step of amplifying the pulse to the minimum boundary value when outputting a narrow pulse in the stage where PWM changes from decreasing to increasing includes: When Td <= cmp + cmp1 < (T0 + Td), cmp = T0 + Td - cmp1; Among them, cmp is the comparison value, cmp1 is the comparison value of the previous cycle, Td is the dead time, and T0 is the minimum pulse value.

7. The narrow pulse suppression method for a drive motor controller according to claim 1, characterized in that The step of amplifying the pulse to the minimum boundary value when outputting a narrow pulse in the stage where PWM changes from decreasing to increasing includes: When cmp + cmp1 >= (T0 + Td), the comparison value remains unchanged; Among them, cmp is the comparison value, cmp1 is the comparison value of the previous cycle, Td is the dead time, and T0 is the minimum pulse value.

8. The narrow pulse suppression method for a drive motor controller according to claim 1, characterized in that: When the PWM adopts a symmetric generation, up-down counting mode, the comparison register loads the register value twice within one switching period. When the count value is equal to the value of the comparison register, the PWM will change the level according to the preset to generate a drive signal with a variable duty cycle.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 8.

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