Memory devices, memory systems, and methods of operating the same

Abstract

A memory device includes a memory array including memory blocks and a control circuit coupled to the memory array. The control circuit is configured to: while performing a multiple-pass program operation, determine, during a non-final pass of programming of memory cells in a first memory sub-block of a first memory block, a verify cycle count of verify operations following programming of the memory cells in the first memory sub-block of the first memory block to one or more first target program states; and when programming memory cells in a second memory sub-block of the first memory block to the one or more first target program states using the same program and verify conditions as the first memory sub-block of the first memory block, during the non-final pass, at least not perform a verify operation corresponding to a last one of the verify cycle count.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese application No. 202210382032.7, filed on April 12, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to memory devices, memory systems, and methods of operating thereof. Background Technology

[0004] Non-volatile memory is widely used in electronic devices across various fields. Flash memory is one of the most widely used types of non-volatile memory that can be electrically erased and reprogrammed. Flash memory can include NOR and NAND architectures. The threshold voltage of each memory cell in flash memory is changed to the desired level to achieve various operations, such as reading, programming, and erasing. When operating flash memory, erase operations can be performed at the block level, programming operations at the page level, and read operations at the cell level. Multi-state flash memory can be programmed by identifying multiple different allowable threshold voltage ranges. Programming memory cells of multi-state flash memory typically involves multiple traversal programming, alternating between programming and verification operations. Therefore, the programming time is relatively long. Summary of the Invention

[0005] In one aspect, a memory device includes a memory array having memory blocks, each memory block including memory sub-blocks, and each memory sub-block including at least one memory cell. The memory device also includes control circuitry coupled to the memory array. The control circuitry is configured to: when performing multiple traversal programming operations on a first memory block of the memory block, during a non-last programming pass of a memory cell in a first memory sub-block of the first memory block, determine a verification loop count of a verification operation following programming the memory cell in the first memory sub-block of the first memory block to one or more first target programming states; and when programming a memory cell in a second memory sub-block of the first memory block to one or more first target programming states using the same programming and verification conditions as the first memory sub-block of the first memory block, during a non-last programming pass of a memory cell in the second memory sub-block of the first memory block, at least not perform a verification operation corresponding to the last verification loop count in the verification loop count.

[0006] In some implementations, programming memory cells in a first sub-block of a first memory block to one or more first target programming states includes programming memory cells in a first sub-block of a first memory block to multiple first target programming states.

[0007] In some implementations, when memory cells in a first sub-block of a first memory block are programmed to a plurality of first target programming states, the control circuit is further configured to: during a non-last programming pass of memory cells in a first sub-block of a first memory block, determine the verification cycle count for each verification operation following the programming of memory cells in a first sub-block of a first memory block to each first target programming state.

[0008] In some implementations, the control circuit is further configured to: during a non-last pass of programming of memory cells in a second sub-block of the first memory block, set the number of verification operations to be performed on memory cells in the second sub-block of the first memory block based on each verification cycle count in a determined verification cycle count corresponding to each first target programming state.

[0009] In some implementations, the first memory block is programmed multiple times by programming memory cells in the first memory block to a first verification level using a first incremental step pulse programming (ISPP) with a first step length during the first programming pass and programming memory cells to a second verification level using a second ISPP with a second step length during the last programming pass, wherein the first step length is greater than the second step length.

[0010] In some embodiments, the control circuit is configured to: when performing multiple traversal programming operations on the second storage block of the storage block, during the non-last programming of memory cells in the first storage sub-block of the second storage block, determine a verification loop count of the verification operation after programming the memory cells in the first storage sub-block of the second storage block to one or more second target programming states; and when programming the memory cells in the second storage sub-block of the second storage block to one or more second target programming states using the same programming and verification conditions as the first storage sub-block of the second storage block, during the non-last programming of memory cells in the second storage sub-block of the second storage block, at least not perform a verification operation corresponding to the last verification loop count in the verification loop count.

[0011] In some implementations, the memory array is a three-dimensional NAND memory array.

[0012] In another aspect, a memory device includes a memory array having memory blocks, each memory block including memory sub-blocks, and each memory sub-block including at least one memory cell. The memory device also includes control circuitry coupled to the memory array. The control circuitry is configured to: when performing multiple traversal programming operations on a first memory block of the memory block, during a non-last programming pass of a memory cell in a first memory sub-block of the first memory block, determine m verification cycle counts of verification operations following programming a memory cell in a first memory sub-block of the first memory block to one or more first target programming states, where m is an integer; and when programming a memory cell in a second memory sub-block of the first memory block to one or more first target programming states n times using the same programming and verification conditions as the first memory sub-block of the first memory block, where n is an integer and n is greater than 1 and less than m, during the (n+1)th to mth programming passes of a memory cell in a second memory sub-block of the first memory block, apply a programming voltage to the memory cell in the second memory sub-block of the first memory block using the same programming conditions as the first memory sub-block of the first memory block.

[0013] In some implementations, the control circuit is configured to: when a memory cell in a second sub-block of the first memory block is programmed to one or more first target programming states n times using the same programming and verification conditions as the first sub-block of the first memory block, where n is an integer and n is greater than 1 and less than m, after the (m+1)th programming pass of the memory cell in the second sub-block of the first memory block, prohibit the application of programming voltage to the memory cell in the second sub-block of the first memory block.

[0014] In some implementations, the restriction of applying programming voltage to memory cells in a second memory subblock of a first memory block is enforced by increasing the bit line voltage applied to the bit lines coupled to the memory array.

[0015] In another aspect, a programming operation method for a memory device is provided. The memory device includes a memory array, the memory array including memory blocks, each memory block including memory sub-blocks, and each memory sub-block including at least one memory cell. The programming operation method includes: when performing multiple traversal programming operations on a first memory block of the memory block, during a non-last programming pass of a memory cell in a first memory sub-block of the first memory block, determining a verification loop count of verification operations following programming the memory cell in the first memory sub-block of the first memory block to one or more first target programming states; and when programming a memory cell in a second memory sub-block of the first memory block to one or more first target programming states using the same programming and verification conditions as the first memory sub-block of the first memory block, during a non-last programming pass of the memory cell in the second memory sub-block of the first memory block, at least not performing a verification operation corresponding to the last verification loop count in the verification loop count.

[0016] In some implementations, programming the memory cells in the first sub-block of the first storage block to one or more first target programming states further includes programming the memory cells in the first sub-block of the first storage block to multiple first target programming states.

[0017] In some implementations, when programming memory cells in a first sub-block of a first storage block to a plurality of first target programming states, the method further includes: during a non-last pass of programming of memory cells in a first sub-block of a first storage block, determining a verification cycle count for each verification operation following programming of memory cells in a first sub-block of a first storage block to each first target programming state.

[0018] In some embodiments, the method further includes: during a non-last pass of programming of memory cells in a second sub-block of the first storage block, setting the number of verification operations to be performed on memory cells in the second sub-block of the first storage block based on each verification cycle count in a determined verification cycle count corresponding to each first target programming state.

[0019] In some implementations, the first memory block is programmed multiple times by programming memory cells in the first memory block to a first verification level using a first increment step pulse programming (ISPP) with a first step length during the first programming pass and programming memory cells to a second verification level using a second ISPP with a second step length during the last programming pass, wherein the first step length is greater than the second step length.

[0020] In some embodiments, the method further includes: when performing multiple traversal programming operations on a second storage block of a storage block, during a non-last programming pass of memory cells in a first storage sub-block of the second storage block, determining a verification loop count of verification operations following the programming of memory cells in the first storage sub-block of the second storage block to one or more second target programming states; and when programming memory cells in a second storage sub-block of the second storage block to one or more second target programming states using the same programming and verification conditions as the first storage sub-block of the second storage block, during a non-last programming pass of memory cells in the second storage sub-block of the second storage block, at least not performing a verification operation corresponding to the last verification loop count in the verification loop count.

[0021] In another aspect, a memory system includes a memory device. The memory device includes a memory array having memory blocks, each memory block including memory sub-blocks, and each memory sub-block including at least one memory cell. The memory device further includes control circuitry coupled to the memory array. The control circuitry is configured to: when performing multiple traversal programming operations on a first memory block of the memory block, during a non-last programming pass of a memory cell in a first memory sub-block of the first memory block, determine a verification loop count of a verification operation following programming a memory cell in the first memory sub-block of the first memory block to one or more first target programming states; and when programming a memory cell in a second memory sub-block of the first memory block to one or more first target programming states using the same programming and verification conditions as the first memory sub-block of the first memory block, during a non-last programming pass of a memory cell in the second memory sub-block of the first memory block, at least not perform a verification operation corresponding to the last verification loop count in the verification loop count. The memory system further includes a memory controller coupled to the memory device and configured to control the memory device.

[0022] In some implementations, when memory cells in a first sub-block of a first memory block are programmed to a plurality of first target programming states, the control circuit is further configured to: during a non-last programming pass of memory cells in a first sub-block of a first memory block, determine the verification cycle count for each verification operation following the programming of memory cells in a first sub-block of a first memory block to each first target programming state.

[0023] In some implementations, the control circuitry is further configured to: during a non-last pass of programming of memory cells in a second sub-block of the first memory block, set the number of verification operations to be performed on memory cells in the second sub-block of the first memory block based on each verification cycle count in a determined verification cycle count corresponding to each first target programming state.

[0024] In some implementations, the first memory block is programmed multiple times by programming memory cells in the first memory block to a first verification level using a first incremental step pulse programming (ISPP) with a first step length during the first programming pass and programming memory cells to a second verification level using a second ISPP with a second step length during the last programming pass, wherein the first step length is greater than the second step length.

[0025] In some embodiments, the control circuit is configured to: when performing multiple traversal programming operations on the second storage block of the storage block, during the non-last programming of memory cells in the first storage sub-block of the second storage block, determine a verification loop count of the verification operation after programming the memory cells in the first storage sub-block of the second storage block to one or more second target programming states; and when programming the memory cells in the second storage sub-block of the second storage block to one or more second target programming states using the same programming and verification conditions as the first storage sub-block of the second storage block, during the non-last programming of memory cells in the second storage sub-block of the second storage block, at least not perform a verification operation corresponding to the last verification loop count in the verification loop count.

[0026] In some implementations, the memory array is a three-dimensional (3D) NAND memory array, and the memory device is a 3D NAND memory device. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate various aspects of this disclosure and, together with the specification, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0028] Figure 1 This is a top view of a NAND string according to an embodiment of the present disclosure;

[0029] Figure 2 This is an equivalent circuit diagram of a NAND string according to an embodiment of the present disclosure;

[0030] Figure 3 This is a schematic diagram of an array structure of memory cells according to an embodiment of the present disclosure;

[0031] Figure 4 This is a perspective view as part of an exemplary embodiment of a monolithic three-dimensional (3D) memory array according to embodiments of the present disclosure;

[0032] Figure 5 This is a schematic structural diagram of a memory device having read / write circuitry for parallel reading and programming of memory cells according to embodiments of the present disclosure.

[0033] Figures 6A-6D It is the threshold voltage distribution of the memory cell according to the embodiments of this disclosure;

[0034] Figure 7 This is a schematic structural diagram of a step pulse in an incremental step pulse programming (ISPP) mode according to an embodiment of the present disclosure.

[0035] Figure 8 This is a schematic diagram of a verification voltage pulse according to an embodiment of the present disclosure;

[0036] Figure 9 This is a schematic structural diagram of a memory device according to an embodiment of the present disclosure;

[0037] Figure 10 This is a schematic diagram illustrating the programming and verification operations performed when using a Failure Bit Count (FBC) verification strategy according to an embodiment of this disclosure.

[0038] Figure 11 This is a schematic diagram illustrating the verification information required to program the memory cells coupled to word line WL10 in string 0 to each programming data state after adopting the programming method according to the embodiments of the present disclosure, as determined according to the embodiments of the present disclosure.

[0039] Figure 12 After adopting the programming method according to the embodiments of the present disclosure, the verification information required to program the memory cells coupled to word line WL10 in strings 1, 2 and 3 to each programming data state according to the embodiments of the present disclosure is used.

[0040] Figure 13 This is a schematic flowchart of a method for programming a memory device according to embodiments of the present disclosure;

[0041] Figure 14 This is a schematic structural diagram of a memory system according to an embodiment of the present disclosure;

[0042] Figure 15A This is a schematic diagram of an exemplary memory card having a memory system according to embodiments of the present disclosure; and

[0043] Figure 15B This is a schematic diagram of an exemplary solid-state drive (SSD) having a memory system according to an embodiment of the present disclosure.

[0044] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0045] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a," "an," or "described" can also be understood to express either a singular or a plural usage. Furthermore, the term "based on" can be understood not necessarily to express an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described, which also depends at least partly on the context.

[0046] It should be noted that in the embodiments provided in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a method or apparatus that includes a list of elements includes not only the elements explicitly described but also other elements not explicitly listed, or elements inherent to the implementation of the method or apparatus. Without further limitations, an element as defined by the phrase "comprising..." does not exclude the presence of additional related elements in the method or apparatus that includes that element, such as steps in the method or units in the apparatus. For example, the unit may be part of a circuit, part of a processor, part of a program or software, etc.

[0047] Although the memory device in this disclosure is shown as NAND flash memory, it should be understood that the solutions or techniques disclosed herein are not limited to applications in NAND flash memory, but can be applied to other types of memory devices, such as electrically erasable programmable read-only memory (EEPROM), NOR flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), etc.

[0048] The present disclosure will now be described in more detail with reference to the accompanying drawings and specific embodiments.

[0049] Figure 1 This is a top view of a NAND string according to some embodiments of the present disclosure, and Figure 2 yes Figure 1 The diagram shows the equivalent circuit of a NAND string. In a NAND-based flash memory system, multiple transistors are connected in series between two select gates (source gate and drain gate). The series connection of the transistors and the two select gates is called a NAND string. Figure 1 and 2As shown, the NAND string may include a top select gate SGD (on the drain side), a bottom select gate SGS (on the source side), a top dummy transistor SGDT, four transistors 101-104, and a bottom preset transistor SGST between the top select gate SGD and the bottom select gate SGS. The top select gate SGD connects the NAND string to a bit line via a bit line contact; the top select gate SGD is controlled by applying an appropriate voltage to the top select gate line SGDL. The bottom select gate SGS connects the NAND string to the source line; the bottom select gate SGS is controlled by applying an appropriate voltage to the bottom select gate line SGSL. Each of the top dummy transistor SGDT, the four transistors 101-104, and the bottom preset transistor SGST includes a control gate and a floating gate. For example, the top dummy transistor SGDT includes a control gate CGDT and a floating gate FGDT; transistor 101 includes a control gate 101CG1 and a floating gate 101FG1; transistor 102 includes a control gate 102CG1 and a floating gate 102FG1; transistor 103 includes a control gate 103CG1 and a floating gate 103FG1; transistor 104 includes a control gate 104CG1 and a floating gate 104FG1; and the bottom dummy transistor SGST includes a control gate CGST and a floating gate FGST. The control gate CGST is connected to the bottom dummy word line BDWL; control gates 101CG1-104CG1 are connected to word lines WL0-WL3 respectively; and the control gate CGDT is connected to the top dummy word line TSWL.

[0050] It should be noted that Figure 1 and 2 This is merely an exemplary illustration of four memory cells (transistors 101-104) used for read and write operations and two dummy memory cells (top dummy transistor SGDT and bottom dummy transistor SGST) used for read and write testing. In practical applications, NAND strings may include 8, 16, 32, 64, 128 memory cells, etc. That is, the number of memory cells or dummy memory cells in a NAND string does not limit the scope of this disclosure. Furthermore, a typical structure of a flash memory system using a NAND structure includes multiple NAND strings. Each NAND string is connected to the source line via a bottom select gate SGS controlled by the bottom select gate line SGSL, and connected to the corresponding bit line via a top select gate SGD controlled by the top select gate line SGDL. Each bit line and the corresponding NAND string (single or multiple) connected to that bit line via bit line contacts form a column in the memory cell array. Bit lines are shared by multiple NAND strings. Typically, bit lines extend on top of the NAND string in a direction perpendicular to the word line and are connected to one or more sense amplifiers. It should be understood that this disclosure utilizes only... Figure 1 and 2The example structure shown illustrates the NAND string structure. In practical applications, the charge trapping layer is not necessarily a floating gate, but can also be a trapping nitride layer, a non-conductive dielectric material, etc.

[0051] In practical applications, the memory array in a memory device has NAND strings (such as...) Figure 1 and Figure 2 A memory array in which multiple memory blocks are formed after appropriate layout as shown in the figure, with an exemplary structure as shown in the figure. Figure 3 As shown in the diagram, the memory array 300 is divided into multiple memory blocks BLOCK1-BLOCK. T A memory array, where T is a positive integer. Each memory block contains data via bit lines BL0-BL1. M-1 Access a set of NAND strings, and a set of public word lines WL0-WL N-1 Where M and N are both integers greater than 1. One end of the NAND string is connected to the corresponding bit line via the top select gate SGD (controlled by the top select gate line SGDL), and the other end is connected to the source line via the bottom select gate SGS (controlled by the bottom select gate line SGSL). Each memory block is divided into multiple pages. In some implementations, memory blocks are typically used as units for erase operations, and pages are typically used as units for programming operations. In some implementations, other units for erasing or programming may also be used. In the example, such as... Figure 3 The physical structure of the memory cells in the memory array shown does not limit the scope of this disclosure.

[0052] In this disclosure, Figure 3 The memory array shown can be arranged as a 3D quad-level cell (QLC) flash memory structure. It should be noted that other structural arrangements do not limit the scope of this disclosure.

[0053] For the structure of each storage block, such as Figure 4 The diagram shows a perspective view of a portion of an exemplary scheme of a three-dimensional memory array of a single memory block according to some embodiments of the present disclosure. References Figure 4 The storage block 400 includes multiple layers stacked on a substrate (not shown) and parallel to the surface of the substrate. Figure 4Four word lines (WL) on four layers are shown, denoted as WL0 to WL3. The memory block 400 also has multiple channels arranged perpendicular to the word lines. The intersections of word lines and channels form memory cells, such that a channel intersecting multiple word lines can also be referred to as a string of memory cells. Those skilled in the art will understand that the number of word lines and the number of strings of memory cells (e.g., channels) in the memory block 400 are not limited to specific values. For example, the memory block 400 may include 64 word lines and 64 memory cells formed by intersecting the 64 word lines with a single string of memory cells (channel). For another example, the number of strings of memory cells included in the memory block 400 may be on the order of hundreds of thousands, millions, or even larger. Word lines include millions of memory cells formed by intersecting, for example, millions of strings of memory cells. Memory cells in the memory block 400 may be single-level or multi-level memory cells. A single-level memory cell can be a single-level flash memory (SLC) capable of storing 1 bit; a multi-level memory cell can be a multi-level flash memory (MLC) capable of storing 2 bits, a triple-level flash memory (TLC) capable of storing 3 bits, a quadruple-level flash memory (QLC) capable of storing 4 bits, or a penta-level flash memory (PLC) capable of storing 5 bits. For example... Figure 4 As shown, memory block 400 also includes bit lines (BL), bit line selectors (BLS, also known as top select gate line SGDL), source lines (SL), and source select lines (SLS, also known as bottom select gate line SGSL). These circuit lines, together with word lines (WL), enable addressing of any memory cell in memory block 400.

[0054] In some implementations, memory block 400 may be logically divided into multiple memory sub-blocks. Multiple memory cells coupled to word lines within a memory sub-block may be referred to as memory cell pages or memory pages. In some implementations, memory block programming may be performed on a per-memory-page basis.

[0055] based on Figure 3 The memory array shown Figure 5 A schematic structural diagram of a memory system provided with read and write circuitry for parallel reading and / or programming of pages (or other cells) of a memory array, according to some embodiments of the present disclosure, is shown.

[0056] Memory system 50 includes memory device 501 and controller 502. Memory device 501 includes memory array 300 (two-dimensional or three-dimensional), control circuitry 5011, read / write circuitry 5012A and 5012B, row decoders 5013A and 5013B, and column decoders 5014A and 5014B. In some embodiments, access to memory array 300 via various control circuits is implemented symmetrically on opposite sides of memory array 300 to halve the access and circuitry density on each side. Read / write circuitry 5012A and 5012B includes multiple sensing blocks SB for parallel reading or programming of pages of memory array 300. Memory array 300 is addressable via word lines through row decoders 5013A and 5013B and via bit lines through column decoders 5014A and 5014B. In some implementations, the memory array 300, control circuitry 5011, read / write circuitry 5012A and 5012B, row decoders 5013A and 5013B, and column decoders 5014A and 5014B can be fabricated on-chip. Figure 5 The dashed box in the middle can also represent a chip. External signals and data are transmitted between the host and controller 502 via signal line 503, and between controller 502 and the chip via signal line 504. Control circuitry 5011 is configured to cooperate with read / write circuits 5012A and 5012B to perform memory operations on memory array 300. Control circuitry 5011 includes a state machine, an on-chip address decoder, and a power control module. The state machine is configured to provide chip-level control of memory operations; the on-chip address decoder is configured to provide an address interface between addresses used by the host or memory system controller and hardware addresses used by row decoders 5013A and 5013B and column decoders 5014A and 5014B; and the power control module is configured to provide power and voltage to word lines and bit lines during each memory operation device control.

[0057] The memory array in the memory system discussed above can be erased, programmed, and read. Since memory cells in a memory system can be arranged as single-cell flash memory or multi-cell flash memory, and multi-cell flash memory can be categorized as MLC, TLC, QLC, etc., for a memory page, at the end of a successful programming process (with verification), the threshold voltage of the programmed memory cell should be within one or more voltage distributions. In practical applications, different types of memory cells can have different data states. Specifically, Figures 6A to 6D Threshold voltage distribution curves for memory cells in SLC, MLC, TLC, and QLC are shown respectively.

[0058] like Figure 6AAs shown, SLC corresponds to two threshold voltage distributions: E and P, where threshold voltage distribution E corresponds to the erase data state; threshold voltage distribution P corresponds to the program data state. The threshold voltage corresponding to the erase data state of threshold voltage distribution E is less than the threshold voltage corresponding to the program data state of threshold voltage distribution P. Therefore, a memory cell with the threshold voltage in threshold voltage distribution E is in the erase data state; a memory cell with the threshold voltage in threshold voltage distribution P is in the program data state. In some embodiments, an SLC-type memory cell stores one bit of data. Specifically, an erased memory cell stores data 1, and a programmable memory cell stores data 0.

[0059] like Figure 6B As shown, the MLC corresponds to four threshold voltage distributions: E, P1, P2, and P3, with the threshold voltages increasing sequentially. Similarly, threshold voltage distribution E corresponds to the erased data state; threshold voltage distributions P1, P2, and P3 correspond to the programmed states. In some embodiments, the MLC-type memory cell stores two bits of data. Specifically, the erased memory cell stores data 11, the memory cell programmed to the P1 data state stores data 10, the memory cell programmed to the P2 data state stores data 01, and the memory cell programmed to the P3 data state stores data 00.

[0060] like Figure 6C As shown, TLC corresponds to eight threshold voltage distributions: E, S1, S2, S3, S4, S5, S6, and S7, with the threshold voltages increasing sequentially. Similarly, threshold voltage distribution E corresponds to the erased data state; threshold voltage distributions S1, S2, S3, S4, S5, S6, and S7 correspond to the programmed data states. In some embodiments, TLC-type memory cells store three bits of data. Specifically, erased memory cells can store data 111, memory cells programmed to the S1 data state store data 110, memory cells programmed to the S2 data state store data 101, memory cells programmed to the S3 data state store data 100, memory cells programmed to the S4 data state store data 011, memory cells programmed to the S5 data state store data 010, memory cells programmed to the S6 data state store data 001, and memory cells programmed to the S7 data state store data 000.

[0061] like Figure 6DAs shown, in a QLC, it corresponds to sixteen threshold voltage distributions: E, L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15, with the threshold voltages increasing sequentially. Similarly, threshold voltage distribution E corresponds to the erase data state; threshold voltage distributions L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14, and L15 correspond to the program data state. For data state N, data state N has a higher threshold voltage than data state N-1 and a lower threshold voltage than data state N+1. In some implementations, a QLC-type memory cell stores four bits of data. Specifically, the erased memory cell can store the data 1111, and the memory cells programmed into L1, L2, L3, L4, L5, L6, L7, L8, L9, L10, L11, L12, L13, L14 and L15 can store the data 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001 and 0000 respectively.

[0062] It should be noted that, regardless of the type of memory cell mentioned above, each threshold voltage distribution (data state) corresponds to a predetermined value for a set of data bits stored in the memory cell. The specific relationship between the data programmed into the memory cell and the threshold voltage level of the memory cell depends on the data encoding scheme used by the memory cell. For example, Gray code can be used as the encoding scheme.

[0063] In practical applications, for flash memory devices with multiple data states (e.g., NAND flash memory devices), in order to reduce coupling and interference between word lines when programming memory cells, in some implementations, multiple pass programming can be used for memory pages or blocks to achieve a tighter threshold voltage distribution. In some implementations, multiple pass programming may include two pass programming, three pass programming, etc. Two pass programming may include a first coarse programming and a fine programming; three pass programming may include a first coarse programming, a second coarse programming, and a fine programming. Here, the last pass of multiple pass programming is fine programming; according to some embodiments of this disclosure, the first coarse programming and the second coarse programming are collectively referred to as coarse programming, and may also be referred to as non-final programming.

[0064] In some implementations, both non-final programming and fine programming can be incremental step pulse programming (ISPP). Memory cells in a memory page are programmed several times, where the incremental step programming pulse Vpgm can be referenced. Figure 7 .

[0065] To consider programming speed and have a wide read window margin (RWM), in some implementations, during non-final programming passes (e.g., each coarse programming stage), programming voltage pulses with a large set step size (e.g., 0.5 volts (V)) are applied to selected word lines (e.g., the word lines of the memory cells selected to be programmed), allowing the memory cells coupled to the selected word lines to be quickly programmed to intermediate data states. In fine programming stages, performed after each coarse programming stage, programming voltage pulses with a small set step size (e.g., 0.2V) are applied to the selected word lines, allowing the memory cells coupled to the selected word lines to be accurately programmed to their final data states. That is, in some implementations, the programming voltage / pulse applied during the programming operation increases according to different set step sizes in each of the multiple programming passes, and a specific set step size can be determined based on the actual programming conditions set by the designer. It should be noted that intermediate data states are one or more data states before the programmed memory cells reach their final data states. For example, when programming a TLC-type memory cell, the final data state of a memory cell is S3, and the intermediate data states can be at least one of S1 and S2. However, other verifiable data states are also possible. The final data state is the data state that the user expects the programmed memory cell to be programmed into. For example, when programming the aforementioned TLC-type memory cell, the final data state is S3.

[0066] It should be understood that during the programming of a memory cell, in order to determine whether the programmed memory cell has been programmed to the target programmed data state, a verification operation can be added between the application of two programming voltage pulses (the process of applying programming voltage pulses is also called the programming operation) to determine whether the programmed memory cell has been programmed to the target data state. That is, programming operations and verification operations are performed alternately. The verification operation can be one or a set of verification voltage pulses, and the verification voltage pulses are... Figure 8 As shown in [the image]. Figure 8 In the diagram, 1001 and 1003 are incremental step programming pulses Vpgm; 1002 is the verification voltage pulse. Based on the preceding description, multiple traversal programming can include at least one coarse programming pass and one fine programming pass, and each pass includes at least one programming operation and at least one verification operation.

[0067] However, it was found that the aforementioned multiple-step programming method, which alternates between programming and verification operations, requires more verification operations, thus slowing down the programming process. In other words, during programming, using verification operations after each programming operation to increase the reliability of the programming results in some unnecessary verification operations, thereby increasing the programming time (tPROG) and reducing the programming speed.

[0068] To solve the above technical problems, such as Figure 9 As shown, some embodiments of this disclosure provide a memory device 501. The memory device 501 includes a memory array 300 having a plurality of memory blocks and control circuitry 5011 coupled to the memory array 300. Each memory block is arranged to include a plurality of memory sub-blocks. Each memory sub-block includes at least one memory cell.

[0069] Control circuit 5011 is configured to, when performing multiple traversal programming on a first memory block of a plurality of memory blocks, during a non-last traversal programming of memory cells in a first memory sub-block of the first memory block, determine a verification cycle count for verification operations following the programming of memory cells in the first memory sub-block of the first memory block to one or more first target programming states; and when programming memory cells in other memory sub-blocks (e.g., a second memory sub-block) of the first memory block to target programming states, using the same programming and verification conditions as for the first memory sub-block, at least not perform a verification operation corresponding to the last of the verification cycle (cycle) count during the non-last traversal programming of memory cells in the other memory sub-blocks. Note that the first memory block can be any one of the plurality of memory blocks; the first memory sub-block can be any one of the sub-blocks of the first memory block; the other memory sub-blocks can be memory sub-blocks of the first memory block other than the first memory sub-block. Note that the target programming state may not be the final target programming state after performing multiple traversal programming operations, but rather the target programming state corresponding to each programming operation in the multiple traversal programming operations. For example, the first target programming state is the target programming state after the first pass of the programming operation that has been performed multiple times.

[0070] It should be noted that the above-mentioned Figures 1 to 5 The memory device described herein is only used to illustrate the relationship between memory cell strings, memory blocks, memory sub-blocks, and word lines in a memory device, and is not intended to limit the scope of this disclosure. That is, the memory device described in this embodiment may have… Figures 1 to 5 The structure described herein may be another implementation structure.

[0071] Here, based on the foregoing description, memory cells in each sub-block of a memory block within a memory device are coupled to multiple word lines; and the memory cells of adjacent sub-blocks are coupled via word lines. Based on this, a programming operation may be applying a programming voltage (or programming pulse) to a selected word line among the multiple word lines; and a verification operation may be applying a verification voltage to a selected word line. In some embodiments, any pass of a multi-pass programming may include at least one programming cycle, and in a portion of the programming cycle within at least one programming cycle, the verification voltage and programming voltage / pulse are alternately applied to the selected word line. That is, typically, a programming cycle includes programming and verification operations. However, based on the methods described in some embodiments of this disclosure, some verification operations may be skipped. Therefore, the verification voltage and programming voltage / pulse are alternately applied to the selected word line only within a portion of the programming cycle. Therefore, the programming time (tPROG) can be reduced, and programming speed can be increased.

[0072] It should be understood that the multiple iterations mentioned here can refer to two-step, three-step, four-step, etc. "Not the last iteration" can refer to any rough iteration prior to fine-grained programming. That is, "not the last iteration" can refer to any rough iteration of programming at least once.

[0073] Based on this, when multiple traversal programming consists of two traversal programming passes (i.e., including one coarse programming pass and one fine programming pass), the non-last programming pass is a coarse programming pass. In this case, the verification cycle count determined during the non-last programming pass for performing the verification operation to program the memory cells in the first sub-block to the target programming state can be the verification cycle count determined during the coarse programming pass for performing the verification operation after programming the memory cells in the first sub-block to the target programming state. When multiple traversal programming includes multiple coarse programming passes, the non-last programming pass can be any of the multiple coarse programming passes. In this case, the verification cycle count determined during the non-last programming pass for performing the verification operation after programming the memory cells in the first sub-block to the target programming data state can refer to the verification cycle count determined during a certain coarse programming pass for performing the verification operation after programming the memory cells in the first sub-block to the target programming data state.

[0074] It is understandable that when multiple traversal programming includes multiple rounds of coarse programming, for each round of coarse programming, the verification loop count for performing the verification operation after programming the memory cells in the first memory subblock to the target programming data state can be determined.

[0075] For example, assuming multiple traversal programming includes two rounds of coarse programming and one round of fine programming, the non-last round of programming can be either of the two coarse programming rounds. For example, when the two coarse programming rounds are defined as a first coarse programming round and a second coarse programming round, the non-last round of programming can be either the first coarse programming round or the second coarse programming round. In this case, it is only possible to determine the verification cycle count for performing verification operations on memory cells in the first memory sub-block to be programmed to the target programming data state during the first programming round. It is also possible to determine the verification cycle count for performing verification operations during both the first and second coarse programming rounds after programming the memory cells in the first memory sub-block to the target programming data state. It is also possible to determine the verification cycle count for performing verification operations only during the second coarse programming round after programming the memory cells in the first memory sub-block to the target programming state. It should be understood that the determined verification cycle count for verification operations is only available if the non-last round of programming performed on other memory sub-blocks (other than the first memory sub-block) corresponds to the non-last round of programming performed on memory cells in the first memory sub-block. For example, suppose the multiple traversal programming performed on the first memory subblock is a three-pass traversal programming, and the verification cycle count when the verification operation is performed during the second coarse programming pass on the first memory subblock is determined. Then, when multiple traversal programming with a three-pass traversal programming pass is also performed on memory cells in memory subblocks other than the first memory subblock, the verification cycle count when the verification operation is performed during the second coarse programming pass on the first memory subblock can be determined only when the second coarse programming pass is performed, so as to at least reduce the last verification operation in the verification cycle count, thereby achieving the goal of saving programming time.

[0076] It should also be noted that the terms "first" and "second" are for ease of description only and are not intended to limit the scope of this disclosure. Similarly, the second memory cell described above or below can also be understood in this manner. Based on the foregoing description of memory cell types, the target programming data state may include one or more target programming data states.

[0077] In some implementations, when the target programming data state includes 1, it is only necessary to determine the verification loop count of the verification operations required after programming the memory cells in the first memory subblock to the target programming data state. In some implementations, the target programming data state can also be any verifiable programming data state in coarse programming. For example, the target programming data state can be any programming data state in the SLC, MLC, TLC, and QLC described above, except for the erase data state.

[0078] In some implementations, when the target programming state includes multiple states, the control circuit is also configured to determine, during non-final programming passes, a verification cycle count corresponding to the verification operation following the programming of memory cells in the first memory subblock to each target programming state.

[0079] It should be noted that, at this time, the target programming data state can also be any kind of verifiable programming data state in coarse programming. For example, besides the erase data state, the target data programming state can include multiple programming data states in the MLC, TLC, and QLC mentioned above. In this case, during non-final programming operations, the verification cycle count corresponding to the verification operation to be performed after programming the memory cells in the first memory sub-block to each programming state can be determined separately. For example, when the target data programming state includes two states, such as the two programming data states L1 and L2 in the QLC mentioned above. In this case, during non-final programming, the verification cycle count corresponding to the required verification operation must be determined to be 1 to program the memory cells in the first memory sub-block to L1; and the verification cycle count corresponding to the required verification operation must also be determined to be 2 to program the memory cells in the first memory sub-block to L2. It should be understood that the memory cells in the first memory sub-block programmed to L1 are different from the memory cells in the memory sub-block programmed to L2. Which memory cells need to be programmed to L1 and which memory cells need to be programmed to L2 are determined according to the host instructions mentioned above or below.

[0080] After programming the first sub-block, the programming of other sub-blocks within the same first sub-block uses the same programming and verification conditions as the first sub-block. When a memory cell in a sub-block is programmed to the target programming data state, no verification operation corresponding to at least the last verification cycle count is performed during the non-last programming pass of the memory cells in other sub-blocks. That is, the same programming and verification conditions as the first sub-block can be used to program the memory cells in other sub-blocks. When a memory cell in another sub-block is programmed to the target programming data state, no verification operation corresponding to at least the last verification cycle count is performed during the non-last programming pass of the memory cells in other sub-blocks. In other words, when programming the first sub-block using the same programming and verification conditions, during non-last programming passes, after the memory cells in other sub-blocks are programmed to the target programming data state, the verification operation corresponding to at least the last verification cycle count can be omitted.

[0081] In some implementations, when multiple traversal programming operations are performed on the first storage block of the storage block, during non-last programming passes of memory cells in the first sub-block of the first storage block, after programming the memory cells in the first sub-block of the first storage block to one or more first target programming states, a verification cycle count of m, where m is an integer, is determined for the verification operation. Furthermore, when memory cells in the second sub-block of the first storage block are programmed to one or more first target programming states n times using the same programming and verification conditions as the first sub-block of the first storage block, where n is an integer and greater than 1 and less than m, during the (n+1)th to mth programming passes of the memory cells in the second sub-block of the first storage block, a programming voltage is applied to the memory cells in the second sub-block of the first storage block using the same programming conditions as the first sub-block of the first storage block.

[0082] In some implementations, when a memory cell in a second sub-block of the first memory block is programmed to one or more first target programming states n times using the same programming and verification conditions as the first sub-block of the first memory block, where n is an integer and greater than 1 and less than m, after the (m+1)th programming pass of the memory cell in the second sub-block of the first memory block, the application of programming voltage to the memory cell in the second sub-block of the first memory block is prohibited.

[0083] In some implementations, preventing the application of programming voltage to memory cells in a second sub-block of the first memory block is achieved by increasing the bit line voltage applied to the bit lines coupled to the memory array. In some implementations, to prevent the application of programming voltage, the bit line voltage applied to the bit lines coupled to the memory array can be increased to, for example, 2.0V.

[0084] For example, when the target programming state includes 1, the verification loop count is determined to be 5 times. Then, under the same programming and verification conditions, programming memory cells in other memory sub-blocks (excluding the first memory sub-block) to the target programming data state can be performed only for the first 4 verification operations, omitting the last verification operation, thus saving programming time. When the target programming data state includes two states (e.g., L1 and L2), the determined verification loop count 1 is 6 times, and the determined verification loop count 2 is 7 times. In this case, under the same programming and verification conditions, the verification operation after programming memory cells in any sub-block of other memory sub-blocks to L1 can be performed only for the first 5 times, omitting the last verification operation. The verification operation after programming memory cells in any sub-block of other memory sub-blocks to L2 can be performed only for the first 6 times, without performing the last verification operation.

[0085] Based on the above description, the technical solution described above can be understood as follows: When performing multiple traversal programming on a memory block in a memory device, during non-last programming passes, the verification loop count required to perform a verification operation after programming a memory cell in a sub-block of the memory block to the target programming state is first determined. Then, when programming memory cells in other sub-blocks (e.g., a second sub-block) of the memory block to the same target programming data state using the same programming and verification conditions, during non-last programming passes of memory cells in other sub-blocks, at least the verification operation corresponding to the last verification loop count in the verification loop count is not performed. That is, when programming memory cells in other sub-blocks to the same target programming data state using the same programming and verification conditions, during non-last programming passes of memory cells in other sub-blocks, at least the verification operation corresponding to the last verification loop count in the verification loop count is skipped, thereby saving more tPROG. For RWM, this can be considered in the final fine programming. It should be understood that the situation described here is the same as the multiple traversal programming performed on the first sub-block and the multiple traversal programming performed on other sub-blocks of the same memory block. In other words, multiple traversal programming performed on the first sub-block is two traversal programming operations, and subsequent multiple traversal programming operations performed on other sub-blocks within the same memory block are also two traversal programming operations. That is, the same programming / verification conditions can refer to performing the same multiple traversal programming on memory cells in any sub-block of a memory block. Conditions include the initial programming voltage / pulse, the set step size, the verification voltage, the verification operation, and other relatively minor variations. It should be noted that in some descriptions, a sub-block is also described as a string of memories. For example, suppose a memory block of a memory device has six sub-blocks. These six sub-blocks can be six strings, such as string 0, string 1, string 2, string 3, string 4, and string 5.

[0086] It should be understood that when programming memory cells in a sub-block to a target programming state, after one programming operation and one verification operation, the threshold voltage of some memory cells will fall within the threshold voltage distribution corresponding to the target programming state; while the threshold voltage of other memory cells may require multiple programming and verification operations. Therefore, the verification cycle count can refer to the number of times it is necessary to program the last completed programming memory cell in the first sub-block to the target programming state.

[0087] In some implementations, after determining the verification cycle count required to perform the verification operation after programming the memory cells in the first sub-block of the memory block to each target programming state, the control circuit is further configured to, based on the verification cycle count corresponding to each target programming state, determine the verification cycle count required to perform the verification operation after programming the memory cells in other sub-blocks (e.g., the second sub-block) to the target programming state in a non-last programming pass.

[0088] In some implementations, the control circuitry includes an external interface through which the number of verification operations that need to be performed by memory cells in other memory subblocks during non-final programming passes is configured.

[0089] It should be noted that the external interface can refer to the above. Figure 5 Signal lines 504 and 503 are used to receive from the host the number of verification operations that need to be performed on memory cells in other memory subblocks during non-final programming passes. The current number of verification operations can be obtained based on the verification cycle count determined above.

[0090] In some implementations, when the verification strategy in multiple traversal programming employs Predicted Failure Bit Count (FBC) verification, Predicted FBC verification is performed during the programming process of a memory block. When a predetermined proportion of memory cells in a memory block have been programmed to the target programming data state, the remaining memory cells that have not yet been programmed to the target programming data state only need to undergo one more programming operation and do not require a verification operation.

[0091] The control circuit is also configured to determine, during non-last programming passes, a programming cycle count for performing programming operations to program memory cells in the first sub-block to the target programming state when multiple traversal programming is performed on the first memory block; and to at least not perform programming operations corresponding to the last programming cycle count when memory cells in other sub-blocks (e.g., the second sub-block) in the first memory block are programmed to the target programming state using the same programming and verification conditions as the first sub-block during non-last programming passes of the memory cells.

[0092] In some implementations, the process of predicting the FBC verification strategy may include: when multiple traversal programming is performed on a memory subblock, whether it is in the coarse programming stage or the fine programming stage, after several alternating programming and verification operations, a certain proportion (e.g., a preset proportion) of memory cells in the memory subblock has been programmed to the target programming data state, and only a portion of the remaining memory cells has not yet been programmed to the target programming data state. However, the intermediate data state of said portion of the unprogrammed remaining memory cells can be close to the target programming data state. Therefore, only said portion of the remaining memory cells needs to be programmed, and said portion of the remaining memory cells will inevitably be programmed to the target programming data state. Then, at this time, no further verification operation is required, saving more tPROG. It should be noted that the preset proportion of memory cells can be designed according to the actual memory device. For example, the preset proportion could be 90%, etc.

[0093] In some implementations, when the verification scheme (strategy) in the multiple traversal programming operation is predictive FBC verification, the control circuit is configured to: determine a programming cycle count for programming the memory cells in the first sub-block of the first memory block to a first target programming state during a non-last programming pass of the memory cells in the first sub-block of the first memory block when performing multiple traversal programming operations on memory cells in the first memory block; and when programming memory cells in the second sub-block of the first memory block to one or more first target programming states using the same programming and verification conditions as the first sub-block of the first memory block, at least during a non-last programming pass of the memory cells in the second sub-block of the first memory block, not perform a verification operation corresponding to the last verification cycle count in the verification cycle count.

[0094] For example, such as Figure 10 As shown, when performing a coarse programming operation on memory cells coupled to word line WL10 in a memory sub-block of a QLC type NAND flash memory device during multiple traversal programming, the verification strategy uses predictive FBC verification. In this coarse programming, after five alternating programming and verification operations, the memory cells are coupled to the WL10 word line. A certain percentage (e.g., 90%) of the memory cells have been programmed to the target programming data state, and only 10% of the memory cells remain unprogrammed to the target programming data state, while the intermediate programming data state of the remaining 10% of memory cells is close to the target programming data state. At this point, only one more programming operation is needed on the remaining 10% of memory cells. That is, in order to perform the sixth programming operation, the remaining 10% of memory cells must be programmed to the target programming data state. This is predictable, therefore no further verification operation is required.

[0095] In some implementations, the first memory block is programmed multiple times by programming memory cells in the first memory block to a first verification level (e.g., intermediate verification level) with a first ISPP having a first step length during a first programming pass, and programming memory cells to a second verification level (e.g., final verification level) with a second ISPP having a second step length during a final programming pass. The first step length is greater than the second step length.

[0096] In some implementations, predictive FBC verification is performed after the memory cells in the first memory block are programmed to a first verification level using a first ISPP and after the memory cells in the first memory block are programmed to a second verification level using a second ISPP.

[0097] Based on the above description, it can be seen that when predictive FBC verification is used, a verification operation is actually omitted. Then, by using the memory device provided by the embodiments of this disclosure, when the verification strategy in multiple traversal programming uses predictive FBC verification in the same memory block, it is only necessary to determine the verification loop count required after programming the memory cells in the first memory sub-block to the target programming data state. Furthermore, when programming memory cells in other memory sub-blocks (e.g., the second memory sub-block), the verification operation corresponding to the last verification loop count can also be omitted, thereby saving more tPROG.

[0098] When the verification strategy in multiple traversal programming employs predictive FBC verification, during the non-last programming pass of multiple traversal programming, if verification is passed and a certain programming data state is reached, the programming of memory cells coupled to a word line is completed, at which point most memory cells have been programmed to the programming data state. Only a small portion of memory cells remain unprogrammed to the programming data state. At this point, the final programming operation is performed on or not on this small portion of memory cells, and the threshold voltage distribution of the memory cells coupled to the word line has very small differences. Then, in this case, when performing multiple traversal programming on the first memory block, the programming cycle count required to program the memory cells in the first sub-block to the target programming state during the non-last programming pass can also be determined. Subsequently, when programming the memory cells in other sub-blocks (e.g., the second sub-block) in the first memory block to the target programming state using the same programming and verification conditions as the first sub-block, the other sub-blocks do not perform programming operations corresponding to the last programming cycle count during the non-last programming pass.

[0099] That is, when the verification strategy in multi-traversal programming adopts predictive FBC verification, within the same memory block, only the programming cycle count of the programming operations required to program the memory cells in the first memory sub-block to the target programming data state needs to be determined. When programming memory cells in other memory sub-blocks (e.g., the second memory sub-block), the programming operations corresponding to the last programming cycle count can also be omitted.

[0100] Based on the above description, when programming the first storage block, during non-final programming passes, when performing multiple traversal programming operations on the first storage block, based on the verification cycle count and programming cycle count of the first storage sub-block of the first storage block, at least one verification operation can be skipped when programming other storage sub-blocks (e.g., the second storage sub-block) within the first storage block. When using a predictive FBC verification scheme, at least one programming operation can also be skipped, resulting in significant savings in tPROG.

[0101] For RWM, it can be guaranteed during the fine programming phase, which not only speeds up programming but also ensures a wider RWM and guarantees the reliability of programming.

[0102] For example, consider a memory block in a memory device. The memory block has four sub-blocks (strings), named string 0, string 1, string 2, and string 3. Each sub-block includes 128 word lines. The memory block comprises 4 pages. The memory cells within the memory block are QLC (Quick Logic Controller) type memory cells. For QLC type memory cells, a multi-pass programming approach is used, including coarse programming and fine programming stages. Furthermore, in the coarse programming stage, the verification strategy employed is a predictive FCB (Fulfilled Keyboard) verification strategy. In this case, such as... Figure 11 The diagram illustrates the verification information required for each programming data state of the memory cells of string 0 coupled to word line WL10 during the coarse programming phase. After employing the programming method provided by some embodiments of this disclosure, the verification information required to program the memory cells of string 0 coupled to word line WL10 to each programming data state is determined. Thus, it is possible to... Figure 12 The diagram shows the verification information required to program the memory cells coupled to word line WL10 in strings 1, 2, and 3 to each programming data state. Figure 12 In this context, the X instruction can skip (not perform) verification operations. This saves programming time.

[0103] Embodiments of this disclosure provide a memory device in which, when a first memory block of the memory device undergoes multiple traversal programming, the number of verification operations required to program memory cells in a first memory sub-block of the first memory block to a specific target programming data state is determined during non-last programming passes. Then, when the same multiple traversal programming is performed on other memory sub-blocks of the same memory block using the same programming and verification conditions, the number of verification operations can be reduced when programming memory cells in other memory sub-blocks during non-last programming passes, based on the determined number of verification operations. In this way, read window margin is ensured, the time required for the programming process is reduced, and the programming (writing) speed of the memory device is improved.

[0104] Using the same or similar concepts as above, such as Figure 13 As shown, some embodiments of this disclosure also provide a method for programming a memory device 501. The memory device 501 includes a memory array having a plurality of memory blocks. Each memory block is arranged to include a memory array comprising a plurality of memory sub-blocks. Each memory sub-block includes at least one memory cell. Control circuitry is coupled to the memory array. The method includes:

[0105] S131: When performing multiple traversal programming on the first storage block of a plurality of storage blocks, determine the verification loop count of the verification operations required after programming the memory cells in the first storage sub-block of the first storage block to the target programming state during non-last programming passes.

[0106] S132: When memory cells in other sub-blocks (e.g., second sub-blocks) of the first memory block are programmed to the target programming state using the same programming and verification conditions as the first sub-block during a non-last pass of programming of memory cells, at least the verification operation corresponding to the last verification cycle count is not performed. The first memory block is any one of a plurality of memory blocks. The first sub-block is any one of the sub-blocks of the first memory block. Other sub-blocks (e.g., second sub-blocks) are the sub-blocks of the first memory block other than the first sub-block.

[0107] It should be noted that the execution subject of the method can refer to the control circuit. Based on this, for S131, that is: when the control circuit performs multiple traversal programming on the first memory block, during non-last programming, the verification loop count for performing the verification operation after programming the memory cells in the first memory sub-block to the target programming state is determined.

[0108] For S132, when the control circuit programs the memory cells in other memory sub-blocks in the first memory block to the target programming state using the same programming and verification conditions as the first memory sub-block in a non-last programming pass, at least the verification operation corresponding to the last verification cycle count is not performed.

[0109] In some implementations, the target programming state includes one or more.

[0110] In some implementations, when the target programming state includes multiple data states, the programming operation method further includes: determining a verification loop count corresponding to the verification operation, so as to program the memory cells in the first storage sub-block to each target programming state.

[0111] In some implementations, the programming verification method further includes configuring the number of verification operations that need to be performed by memory cells in other memory sub-blocks during non-last programming passes, based on a determined verification loop count corresponding to each target programming state.

[0112] In some implementations, when the verification strategy in multiple traversal programming is predictive FBC verification, predictive FBC verification is performed when, during the programming process of a memory block, a predetermined proportion of memory cells in a memory block have been programmed to the target programming data state. The remaining memory cells not yet programmed to the target programming data state only require one more programming operation and do not require another verification operation. The programming operation method further includes: when performing multiple traversal programming on a first memory block, determining a programming cycle count for programming memory cells in the first sub-block to the target programming state during non-last programming passes; and when, during non-last programming passes, memory cells in other sub-blocks of the first memory block are programmed to the target programming state using the same programming and verification conditions as the first sub-block, at least the programming operation corresponding to the last programming cycle count is not performed.

[0113] In some implementations, memory cells in each memory subblock are coupled to multiple word lines. Memory cells in adjacent memory subblocks are coupled via word lines. A programming operation applies a programming voltage / pulse to a selected word line among the multiple word lines. A verification operation applies a verification voltage to a selected word line. During a portion of a programming loop that iterates through the programming process multiple times, the verification voltage is alternately applied to the selected word line along with the programming voltage / pulse.

[0114] In some implementations, the programming voltage / pulse applied during the programming operation increases according to different set step sizes in each of the multiple traversal programming passes.

[0115] In some implementations, the first memory block is programmed multiple times by programming memory cells in the first memory block to a first verification level (e.g., intermediate verification level) with a first ISPP having a first step length during a first programming pass, and programming memory cells to a second verification level (e.g., final verification level) with a second ISPP having a second step length during a final programming pass. The first step length is greater than the second step length.

[0116] In some implementations, predictive FBC verification is performed after the memory cells in the first memory block are programmed to a first verification level using a first ISPP and after the memory cells in the first memory block are programmed to a second verification level using a second ISPP.

[0117] In some implementations, the memory array is a three-dimensional NAND memory array.

[0118] It should be noted that the method and the memory device described above may be the same or similar concepts, and the terms appearing in the method have been explained in detail in the memory device section and are applicable here as well, and will not be repeated here.

[0119] Based on the same or similar concepts as above, such as Figure 14 As shown, some embodiments of this disclosure also provide a memory system 50 including a memory device 501. The memory device 501 includes a memory array having a plurality of memory blocks. Each memory block is arranged to include a plurality of memory sub-blocks. Each memory sub-block includes at least one memory cell. Control circuitry is coupled to the memory array. The control circuitry is configured to determine, during a non-last programming pass, a verification cycle count for performing a verification operation to program a memory cell in a first memory sub-block of the first memory block to a target programming state; and when, during a non-last programming pass, memory cells in other memory sub-blocks (e.g., a second memory sub-block) of the first memory block are programmed to the target programming state using the same programming and verification conditions as the first memory sub-block, at least the verification operation corresponding to the last verification cycle count in the verification cycle count is not performed. The first memory block is any one of the plurality of memory blocks. The first memory sub-block is any one of the memory sub-blocks within the first memory block. The other memory sub-blocks are memory sub-blocks within the first memory block other than the first memory sub-block. Furthermore, the memory system 50 also includes a controller 502 coupled to the memory device 501 and configured to control the memory device 501.

[0120] It should be noted that the memory system 50 can be connected with... Figure 5The host communication described above. The host and / or memory system 50 may be included in various products, such as Internet of Things (IoT) devices, refrigerators, sensors, electric motors, mobile communication devices, automobiles, autonomous vehicles, etc. And the host and / or memory system 50 may be used to support the processing, communication, or control of these products. In some embodiments, the memory system 50 may be a discrete memory or memory component of the host device. In some other embodiments, the memory system 50 may also be part of an integrated circuit, such as part of a System on Chip (SOC). In this case, the memory system 50 is stacked or otherwise assembled with one or more components of the host. In other embodiments, the above-described memory system may be implemented and packaged in products such as memory cards and drives, as shown in Figures 15(A) and 15(B). Figure 15(A) shows a schematic diagram of an exemplary memory card having a memory system according to some aspects provided in this disclosure. Figure 15(B) shows a schematic diagram of an exemplary solid-state drive (SSD) having a memory system according to aspects of this disclosure. In one example shown in Figure 15(A), the memory system controller 502 and memory device 501 can be integrated into memory card 150. Memory card 150 may include PC cards (Personal Computer Memory Card International Association (PCMCIA) cards), CompactFlash (CF) cards, Smart Media (SM) cards, memory sticks, multimedia cards (e.g., Multimedia Card (MMC), Miniature Multimedia Card (RS-MMC), or Micro Multimedia Card (Micro MMC)), Secure Digital (SD) cards (SD, Mini SD, Micro SD, or Secure Digital High Capacity (SDHC)), Universal Flash Storage (UFS), etc. Memory card 150 may also include components for connecting memory card 150 to a host (e.g., Figure 5 The memory card connector 1501 is coupled to the host (e.g., in the host). In another example shown in FIG15(B), the controller 502 and multiple memory devices 501 can be integrated into the SSD 151. The SSD 151 may also include a connector for coupling the SSD 151 to the host (e.g., in the host). Figure 5 The SSD connector 1511 is coupled to the host in the memory card 150. In some implementations, the storage capacity and / or operating speed of the SSD 151 is greater than that of the memory card 150.

[0121] In some implementations, the host may include a processor and host random access memory (RAM), wherein the host RAM may include dynamic random access memory (DRAM), synchronous DRAM (SDRAM), or any other suitable volatile or non-volatile memory device. One or more communication interfaces may be provided on the memory system 50 to communicate with one or more components in the host. One or more components in the host may be a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Universal Flash Storage (UFS) interface, an embedded MultiMediaCard (eMMC™) interface, etc. The host may also include electronic devices, a memory card reader, or one or more other electronic devices external to the memory system 50.

[0122] In some implementations, controller 502 can receive instructions from a host and communicate with memory device 501. For example, controller 502 can transfer data to one or more memory cells, slices, sub-blocks, blocks, or pages of memory device 501 by executing write or erase commands. Controller 502 can also transfer data to the host by executing read commands. In hardware, controller 502 may include one or more controller units, circuits, or components configured to control access across memory device 501 and provide a translation layer between the host and memory system 50. Controller 502 may also include one or more input / output (I / O) circuits, wires, or interfaces for transferring data to and from memory device 501. Controller 502 may also include a memory management unit and an array control unit.

[0123] The memory management unit may include circuit hardware or firmware, such as multiple components or integrated circuits associated with various memory management functions, using NAND memory as an example of memory system operation or management functions. Those skilled in the art will understand that other forms of non-volatile memory may have the same or similar memory operation or management functions that can be implemented in this disclosure. NAND memory management functions may include wear leveling, such as garbage collection or recycling, error detection or correction, block retirement, or one or more other memory management functions. The memory management unit may process instructions from the host into commands recognizable by the memory system 50, for example, parsing or formatting instructions received from the host into commands related to the operation of the memory device 501. The memory management unit may also generate device commands for the array control unit or one or more other components of the memory system 50, such as various memory management commands for implementing processing functions.

[0124] The memory management unit can be configured to include a set of management tables for maintaining various information associated with one or more components of the memory system 50 (e.g., the memory array of memory device 501). For example, the management tables may contain information such as block age, block erase count, error history, or one or more error counts of one or more memory blocks coupled to the controller 502. Error counts may include operation error counts, read bit error counts, etc. In some embodiments, a bit error is an uncorrectable bit error when the detected error count exceeds a certain threshold. In some embodiments, the management tables may maintain counts of correctable or uncorrectable bit errors, etc. The management tables may also contain one or more logical-to-physical (L2P) tables containing one or more L2P pointers associated with physical addresses at the memory device 501 using logical addresses. In some embodiments, the management tables may contain unencrypted L2P tables and / or encrypted L2P tables. An unencrypted L2P table may include L2P pointers indicating unencrypted logical addresses and unencrypted physical addresses, and an encrypted L2P table may contain encrypted physical addresses and encrypted L2P pointers pointing to unencrypted logical addresses. In practical applications, the management table can be displayed at the memory management unit. That is, the management table can be stored in the RAM of the controller 502. In some embodiments, the management table may also be stored in the memory device 501. During operation, the memory management unit can read part or all of the cached management table from the RAM of the controller 502. The management table can also be read from the memory device 501.

[0125] The array control unit may include circuitry or components configured to control the execution of related memory operations. For example, the array control unit controls the writing of data to one or more memory cells of the memory system 50 coupled to the controller 502, and the reading or erasing of data from one or more memory cells. The array control unit may receive commands sent by the host or host commands generated internally by the memory management unit. Host commands may be commands associated with wear leveling, error detection, or correction, etc.

[0126] The array control unit may also include an error correction code (ECC) component, which may include an ECC engine or other circuitry for detecting or correcting associated errors. Associated errors may occur during the writing of data to one or more memory cells in the memory system 50 coupled to the controller 502, or during the reading of data from one or more memory cells. The controller 502 is configured to effectively detect and recover from error events (e.g., bit errors, operational errors, etc.) associated with various operations or data storage, while maintaining the integrity of data transferred between the host and the memory system 50 or the integrity of stored data. For example, a Redundant Array of Independent Disks (RAID) storage device may be used to remove and deactivate faulty memory resources, such as memory cells, memory arrays, memory pages, memory blocks, etc., to prevent future errors.

[0127] In the aforementioned memory system, in some embodiments, when the target programming state includes multiple data states, the control circuit is further configured to determine, during non-final programming passes, a verification cycle count corresponding to the verification operation to be performed when memory cells in the first memory sub-block are programmed to each target programming state.

[0128] In some implementations, the control circuitry is also configured to configure the number of verification operations to be performed on memory cells in other memory subblocks during non-final programming passes, based on a determined verification loop count corresponding to each target data programming state.

[0129] In some implementations, the verification strategy in multiple traversal programming is predictive FBC verification. Predictive FBC verification ensures that during the programming process of a memory block, when a predetermined proportion of memory cells in a memory block have been programmed to the target programming state, the remaining memory cells not yet programmed to the target programming state only require one more programming operation and do not require another verification operation. The control circuit is also configured to, during non-last traversal programming of the first memory block, determine the programming cycle count for programming memory cells in the first sub-block to the target programming data state during non-last programming cycles; and when, during non-last programming cycles, memory cells in other sub-blocks of the first memory block are programmed to the target programming state using the same programming and verification conditions as the first sub-block, at least the programming operation corresponding to the last programming cycle count is not performed.

[0130] In some implementations, memory cells in each memory subblock are coupled to multiple word lines. Memory cells in adjacent memory subblocks are coupled via word lines, and a programming operation is used to apply a programming voltage / pulse to a selected word line among the multiple word lines. A verification operation is used to apply a verification voltage to a selected word line. During a portion of a programming loop that iterates through the programming process multiple times, the verification voltage and programming voltage / pulse are alternately applied to the memory cells of the selected word line.

[0131] In some implementations, in each programming pass of the multiple traversal programming, the programming voltage / pulse applied during the programming operation is increased according to different preset step sizes.

[0132] In some implementations, the memory array is a three-dimensional NAND memory array; and the memory system is a three-dimensional NAND memory system.

[0133] It should be noted that the memory system includes the aforementioned memory device. Therefore, the two elements that appear in the memory system and have the same or similar technical features or use the same name have been explained in detail in the aforementioned memory device, and these two elements also apply here and will not be repeated.

[0134] The foregoing description of specific implementations can be readily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance presented herein, such adjustments and modifications are intended to be within the meaning and scope of equivalent variations of the disclosed implementations.

[0135] The breadth and scope of this disclosure should not be limited to any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents. Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, the subject matter described in this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adapted, modified, and rearranged in a manner consistent with the scope of this disclosure.

Claims

1. A memory device, comprising: A memory array comprising memory blocks, wherein each memory block comprises memory sub-blocks, and each memory sub-block comprises at least one memory cell; and A control circuit, coupled to the memory array, wherein the control circuit is configured to: When multiple traversal programming operations are performed on the first storage block of the storage block, during the non-last programming pass of the memory cells in the first storage sub-block of the first storage block, programming operations and verification operations are performed on the memory cells in the first storage sub-block of the first storage block to program to one or more first target programming states, and the number of verification operations required to successfully complete programming to the one or more first target programming states is counted and recorded as the verification loop count; and When the memory cell in the second storage sub-block of the first storage block is programmed to the one or more first target programming states using the same programming and verification conditions as the first storage sub-block of the first storage block, at least during the non-last programming pass of the memory cell in the second storage sub-block of the first storage block, the verification operation corresponding to the last verification cycle count in the verification cycle count is not performed. The first memory block is programmed with multiple iterations of programming, wherein the memory cells in the first memory block are programmed to a first verification level using a first incremental step pulse programming (ISPP) with a first step length during the first programming pass and to a second verification level using a second ISPP with a second step length during the last programming pass, wherein the first step length is greater than the second step length.

2. The memory device according to claim 1, wherein, Programming the memory cells in the first sub-block of the first memory block to one or more first target programming states includes: The memory cells in the first sub-block of the first memory block are programmed into a plurality of first target programming states.

3. The memory device according to claim 2, wherein, When the memory cells in the first sub-block of the first memory block are programmed to the plurality of first target programming states, the control circuit is further configured to: During the non-last pass programming of the memory cells in the first sub-block of the first storage block, determine the verification loop count for each corresponding verification operation after programming the memory cells in the first sub-block of the first storage block to each first target programming state.

4. The memory device according to claim 3, wherein, The control circuit is further configured to: During the non-last pass programming of the memory cells in the second storage sub-block of the first storage block, the number of verification operations to be performed on the memory cells in the second storage sub-block of the first storage block is set according to each verification cycle count in the verification cycle count determined corresponding to each of the first target programming states.

5. The memory device according to claim 1, wherein, The control circuit is configured as follows: When multiple traversal programming operations are performed on the second storage block of the storage block, during the non-last programming of the memory cells in the first storage sub-block of the second storage block, programming operations and verification operations are performed on the memory cells in the first storage sub-block of the second storage block to program to one or more second target programming states, and the number of verification operations required to successfully complete programming to the one or more second target programming states is counted and recorded as the second verification loop count. and When the memory cell in the second storage sub-block of the second storage block is programmed to the one or more second target programming states using the same programming and verification conditions as the first storage sub-block of the second storage block, at least during the non-last programming pass of the memory cell in the second storage sub-block of the second storage block, the verification operation corresponding to the last verification cycle count in the second verification cycle count is not performed.

6. The memory device according to claim 1, wherein, The memory array is a three-dimensional NAND memory array.

7. A memory device, comprising: A memory array comprising memory blocks, wherein each memory block comprises memory sub-blocks, and each memory sub-block comprises at least one memory cell; and A control circuit, coupled to the memory array, wherein the control circuit is configured to: When multiple traversal programming operations are performed on the first storage block of the storage block, during the non-last programming pass of the memory cells in the first storage sub-block of the first storage block, programming operations and verification operations are performed on the memory cells in the first storage sub-block of the first storage block to program to one or more first target programming states. The number of verification operations required to successfully complete programming to the one or more first target programming states is counted and denoted as m verification loop counts, where m is an integer. When the memory cell in the second storage sub-block of the first storage block is programmed to the one or more first target programming states n times using the same programming and verification conditions as the first storage sub-block of the first storage block, where n is an integer and n is greater than 1 and less than m, during the (n+1)th to the mth programming passes of the memory cell in the second storage sub-block of the first storage block, the programming voltage is applied to the memory cell in the second storage sub-block of the first storage block using the same programming conditions as the first storage sub-block of the first storage block.

8. The memory device according to claim 7, wherein, The control circuit is configured as follows: When the memory cell in the second storage sub-block of the first storage block is programmed to the one or more first target programming states n times using the same programming and verification conditions as the first storage sub-block of the first storage block, where n is an integer and n is greater than 1 and less than m, after the (m+1)th programming pass of the memory cell in the second storage sub-block of the first storage block, the programming voltage is prohibited from being applied to the memory cell in the second storage sub-block of the first storage block.

9. The memory device according to claim 8, wherein, This is achieved by increasing the bit line voltage applied to the bit lines coupled to the memory array, thereby preventing the application of the programming voltage to the memory cells in the second memory sub-block of the first memory block.

10. A method for programming a memory device, wherein, The memory device includes a memory array, the memory array includes memory blocks, each memory block includes memory sub-blocks, and each memory sub-block includes at least one memory cell, wherein the programming operation method includes: When multiple traversal programming operations are performed on the first storage block of the storage block, during the non-last programming of memory cells in the first sub-block of the first storage block, programming operations and verification operations are performed on memory cells in the first sub-block of the first storage block to program to one or more first target programming states, and the number of verification operations required to successfully complete programming to the one or more first target programming states is counted and recorded as the verification loop count; and When the memory cell in the second storage sub-block of the first storage block is programmed to the one or more first target programming states using the same programming and verification conditions as the first storage sub-block of the first storage block, at least during the non-last programming pass of the memory cell in the second storage sub-block of the first storage block, the verification operation corresponding to the last verification cycle count in the verification cycle count is not performed. The first memory block is programmed with multiple iterations of programming, wherein the memory cells in the first memory block are programmed to a first verification level using a first incremental step pulse programming (ISPP) with a first step length during the first programming pass and to a second verification level using a second ISPP with a second step length during the last programming pass, wherein the first step length is greater than the second step length.

11. The method according to claim 10, wherein, Programming the memory cells in the first sub-block of the first memory block to one or more first target programming states further includes: The memory cells in the first sub-block of the first memory block are programmed into a plurality of first target programming states.

12. The method according to claim 11, wherein, When programming the memory cells in the first sub-block of the first memory block to the plurality of first target programming states, the method further includes: During the non-last pass programming of the memory cells in the first sub-block of the first storage block, determine the verification loop count for each corresponding verification operation after programming the memory cells in the first sub-block of the first storage block to each first target programming state.

13. The method of claim 12, further comprising: During the non-last pass programming of the memory cells in the second storage sub-block of the first storage block, the number of verification operations to be performed on the memory cells in the second storage sub-block of the first storage block is set according to each verification cycle count in the verification cycle count determined corresponding to each of the first target programming states.

14. The method of claim 10, further comprising: When multiple traversal programming operations are performed on the second storage block of the storage block, during the non-last programming of the memory cells in the first storage sub-block of the second storage block, programming operations and verification operations are performed on the memory cells in the first storage sub-block of the second storage block to program to one or more second target programming states, and the number of verification operations required to successfully complete programming to the one or more second target programming states is counted and recorded as the second verification loop count. as well as When the memory cell in the second storage sub-block of the second storage block is programmed to the one or more second target programming states using the same programming and verification conditions as the first storage sub-block of the second storage block, at least during the non-last programming pass of the memory cell in the second storage sub-block of the second storage block, the verification operation corresponding to the last verification cycle count in the second verification cycle count is not performed.

15. A memory system comprising: A memory device, wherein the memory device comprises: A memory array comprising memory blocks, wherein each memory block comprises memory sub-blocks, and each memory sub-block comprises at least one memory cell; and A control circuit, coupled to the memory array, wherein the control circuit is configured to: When multiple traversal programming operations are performed on the first storage block of the storage block, during the non-last programming pass of the memory cells in the first storage sub-block of the first storage block, programming operations and verification operations are performed on the memory cells in the first storage sub-block of the first storage block to program to one or more first target programming states, and the number of verification operations required to successfully complete programming to the one or more first target programming states is counted and recorded as the verification loop count; and When the memory cells in the second sub-block of the first storage block are programmed to the one or more first target programming states using the same programming and verification conditions as the first sub-block of the first storage block, at least during the non-last programming pass of the memory cells in the second sub-block of the first storage block, the verification operation corresponding to the last verification cycle count in the verification cycle count is not performed; and A memory controller, coupled to and configured to control the memory device. The first memory block is programmed with multiple iterations of programming, wherein the memory cells in the first memory block are programmed to a first verification level using a first incremental step pulse programming (ISPP) with a first step length during the first programming pass and to a second verification level using a second ISPP with a second step length during the last programming pass, wherein the first step length is greater than the second step length.

16. The memory system according to claim 15, wherein, When the memory cells in the first sub-block of the first memory block are programmed to a plurality of first target programming states, the control circuit is further configured to: During the non-last pass programming of the memory cells in the first sub-block of the first storage block, determine the verification loop count for each corresponding verification operation after programming the memory cells in the first sub-block of the first storage block to each first target programming state.

17. The memory system according to claim 16, wherein, The control circuit is further configured to: During the non-last pass programming of the memory cells in the second storage sub-block of the first storage block, the number of verification operations to be performed on the memory cells in the second storage sub-block of the first storage block is set according to each verification cycle count in the verification cycle count determined corresponding to each of the first target programming states.

18. The memory system according to claim 15, wherein, The control circuit is configured as follows: When multiple traversal programming operations are performed on the second storage block of the storage block, during the non-last programming of the memory cells in the first storage sub-block of the second storage block, programming operations and verification operations are performed on the memory cells in the first storage sub-block of the second storage block to program to one or more second target programming states, and the number of verification operations required to successfully complete programming to the one or more second target programming states is counted and recorded as the second verification loop count. as well as When the memory cell in the second storage sub-block of the second storage block is programmed to the one or more second target programming states using the same programming and verification conditions as the first storage sub-block of the second storage block, at least during the non-last programming pass of the memory cell in the second storage sub-block of the second storage block, the verification operation corresponding to the last verification cycle count in the second verification cycle count is not performed.

19. The memory system according to claim 15, wherein, The memory array is a three-dimensional (3D) NAND memory array, and the memory device is a 3D NAND memory device.

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