Heterojunction solar cell and manufacturing method thereof, photovoltaic module and photovoltaic system

Abstract

This application relates to the field of solar cell technology, particularly heterojunction solar cells and their fabrication methods, photovoltaic modules, and photovoltaic systems. In the embodiments of this application, a polished backlight surface is employed, and a conductive transition layer and a metal layer are used instead of the transparent conductive layer used in related technologies. This reduces costs while increasing the overall short-circuit current, thereby improving the photoelectric conversion efficiency of the solar cell.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to heterojunction solar cells and manufacturing methods thereof, photovoltaic modules and photovoltaic systems. Background Art

[0002] In related technologies, heterojunction solar cells sequentially layer an intrinsic amorphous silicon layer, a doped layer, and a transparent conductive layer on both sides of the cell, forming a symmetrical structure with a high bifaciality. However, these heterojunction solar cells not only suffer from high costs due to the high amount of paste and transparent conductive materials used, but also have difficulty improving solar cell conversion efficiency due to low short-circuit current. Summary of the Invention

[0003] Based on this, it is necessary to provide a heterojunction solar cell and a manufacturing method thereof, a photovoltaic module and a photovoltaic system, so as to improve the conversion efficiency of the solar cell while reducing the cost.

[0004] According to one aspect of the present application, an embodiment of the present application provides a heterojunction solar cell, comprising:

[0005] The substrate has a backlight surface; the backlight surface is configured as a polished surface;

[0006] A first intrinsic amorphous silicon layer is provided on the backlight side;

[0007] A first doped layer is provided on a surface of the first intrinsic amorphous silicon layer facing away from the backlight surface;

[0008] A stacked structure comprising a conductive transition layer and a metal layer, wherein the conductive transition layer is disposed on a surface of the first doped layer facing away from the first intrinsic amorphous silicon layer, and the metal layer is disposed on a surface of the conductive transition layer facing away from the first doped layer; and

[0009] The first gate line electrode is located on a side of the stacked structure away from the first doped layer; at least one of the conductive transition layer and the metal layer is electrically connected to the first gate line electrode.

[0010] In one embodiment, the first gate line electrode is located on a surface of the metal layer facing away from the conductive transition layer;

[0011] The first gate line electrode is electrically connected to the metal layer.

[0012] In one embodiment, the first gate line electrode is located on a surface of the conductive transition layer facing away from the first doped layer;

[0013] At least a portion of the metal layer is located on a surface of the conductive transition layer facing away from the first doped layer;

[0014] The first gate line electrode is electrically connected to the conductive transition layer and the metal layer respectively.

[0015] In one embodiment, a portion of the metal layer is located on a surface of the conductive transition layer facing away from the first doped layer, and another portion covers at least a portion of the first gate line electrode.

[0016] In one embodiment, the orthographic projection of the first gate line electrode on the surface of the conductive transition layer facing away from the first doped layer is located within the orthographic projection of the metal layer on the surface of the conductive transition layer facing away from the first doped layer.

[0017] In one embodiment, the conductive transition layer includes at least one of a first transparent conductive layer and a tunneling layer.

[0018] In one embodiment, the conductive transition layer includes a first transparent conductive layer, and the thickness of the first transparent conductive layer is 5 nm-120 nm; or

[0019] The conductive transition layer includes a tunneling layer, and the thickness of the tunneling layer is 0.5nm-2nm; or

[0020] The conductive transition layer includes a first transparent conductive layer and a tunneling layer. The thickness of the first transparent conductive layer is 5nm-120nm, and the thickness of the tunneling layer is 0.5nm-2nm.

[0021] In one embodiment, the metal layer is a single-layer structure; or

[0022] The metal layer has a multi-layer structure.

[0023] In one embodiment, the thickness of the conductive transition layer is 0.5 nm to 122 nm; and / or

[0024] The thickness of the metal layer is 20nm-200nm.

[0025] In one embodiment, the heterojunction solar cell further includes an insulating layer;

[0026] The insulating layer covers at least the side surfaces of the heterojunction solar cell.

[0027] In one embodiment, the substrate has a light-receiving surface disposed opposite to the backlight surface;

[0028] The heterojunction solar cell further includes a second intrinsic amorphous silicon layer, a second doped layer, a second transparent conductive layer and a second gate electrode stacked in sequence on the light-receiving surface;

[0029] Wherein, the insulating layer also covers an edge region of a surface of the conductive transition layer on a side away from the first doped layer; and / or

[0030] The insulating layer also covers an edge region of a surface of the second transparent conductive layer that is away from the second doping layer.

[0031] According to another aspect of the present application, an embodiment of the present application provides a method for manufacturing a heterojunction solar cell, comprising:

[0032] Providing a substrate; the substrate has a backlight surface, and the backlight surface is configured as a polished surface;

[0033] forming a first intrinsic amorphous silicon layer and a first doped layer in sequence on the backlight surface;

[0034] forming a stacked structure and a first gate line electrode on a surface of the first doped layer away from the first intrinsic amorphous silicon layer; the first gate line electrode is located on a side of the stacked structure away from the first doped layer;

[0035] The stacked structure includes a conductive transition layer and a metal layer. The conductive transition layer is provided on a surface of the first doped layer facing away from the first intrinsic amorphous silicon layer. The metal layer is provided on a surface of the conductive transition layer facing away from the first doped layer.

[0036] At least one of the conductive transition layer and the metal layer is electrically connected to the first gate line electrode.

[0037] In one embodiment, a stacked structure and a first gate line electrode are formed on a surface of the first doped layer facing away from the first intrinsic amorphous silicon layer, including:

[0038] forming a conductive transition layer on a surface of the first doped layer on a side away from the first intrinsic amorphous silicon layer;

[0039] forming a metal layer and a first gate line electrode in sequence on a surface of the conductive transition layer facing away from the first doping layer;

[0040] Wherein, the first gate line electrode is electrically connected to the metal layer.

[0041] In one embodiment, before sequentially forming a metal layer and a first gate line electrode on a surface of the conductive transition layer facing away from the first doped layer, the method further includes:

[0042] An insulating layer is formed on a side surface of the heterojunction solar cell to at least cover the side surface of the heterojunction solar cell.

[0043] In one embodiment, a stacked structure and a first gate line electrode are formed on a surface of the first doped layer facing away from the first intrinsic amorphous silicon layer, including:

[0044] forming a conductive transition layer on a surface of the first doped layer on a side away from the first intrinsic amorphous silicon layer;

[0045] forming a first gate line electrode and a metal layer in sequence on a surface of the conductive transition layer facing away from the first doping layer;

[0046] At least a portion of the metal layer is located on a surface of the conductive transition layer facing away from the first doped layer; and the first gate line electrode is electrically connected to the conductive transition layer and the metal layer respectively.

[0047] In one embodiment, before sequentially forming the first gate line electrode and the metal layer on the surface of the conductive transition layer facing away from the first doped layer, the method further includes:

[0048] An insulating layer is formed on a side surface of the heterojunction solar cell to at least cover the side surface of the heterojunction solar cell.

[0049] In one embodiment, the conductive transition layer includes at least one of a first transparent conductive layer and a tunneling layer; and / or

[0050] The metal layer is formed by a predetermined process; the predetermined process includes a physical vapor deposition process or an electron beam evaporation process.

[0051] According to another aspect of the present application, an embodiment of the present application provides a photovoltaic assembly, comprising the heterojunction solar cell in any one of the above embodiments; or

[0052] A heterojunction solar cell manufactured by the method for manufacturing a heterojunction solar cell in any of the above embodiments.

[0053] According to another aspect of the present application, an embodiment of the present application provides a photovoltaic system, including the photovoltaic component in any of the above embodiments.

[0054] In the above-mentioned heterojunction solar cell and its manufacturing method, photovoltaic module and photovoltaic system, the heterojunction solar cell includes at least a substrate and a first intrinsic amorphous silicon layer, a first doped layer, a laminated structure and a first grid electrode arranged on the backlight side of the substrate, and the laminated structure includes a conductive transition layer and a metal layer. Compared with the method of only providing a transparent conductive layer in the related art, the conductive transition layer and the metal layer are used in the embodiment of the present application to replace the transparent conductive layer, which can reduce the amount of transparent conductive material used. When the metal layer is provided, since the metal layer and the transition conductive layer have a certain contact area, the path for collecting current can be increased, which not only reduces the number of the first grid electrodes provided, thereby reducing the amount of slurry material used, but also improves the short-circuit current. In addition, by setting the backlight side of the substrate to a polished surface, not only can the contact between the layers provided on the backlight side be better, improving the uniformity and film quality of each layer, but also can make the thickness of the conductive transition layer and the metal layer thinner, that is, can reduce the amount of related materials used, and can also reflect light incident on the back surface from the front, increase the light absorption of the substrate, thereby improving the short-circuit current.

[0055] Therefore, the heterojunction solar cell provided by the embodiment of the present application can improve the short-circuit current as a whole while reducing the cost, thereby improving the photoelectric conversion efficiency of the solar cell.

[0056] Additional aspects and advantages of the embodiments of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the embodiments of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0058] Figure 1 This is a schematic structural diagram of a heterojunction solar cell in one embodiment of the present application;

[0059] Figure 2 This is a schematic structural diagram of a heterojunction solar cell in another embodiment of the present application;

[0060] Figure 3 This is a schematic structural diagram of a heterojunction solar cell in another embodiment of the present application;

[0061] Figure 4 This is a schematic structural diagram of a heterojunction solar cell in another embodiment of the present application;

[0062] Figure 5 This is a schematic structural diagram of a heterojunction solar cell in another embodiment of the present application;

[0063] Figure 6 This is a schematic structural diagram of a heterojunction solar cell in another embodiment of the present application;

[0064] Figure 7 Schematic diagram of a process for manufacturing a heterojunction solar cell in one embodiment of the present application;

[0065] Figure 8 This is a flow chart of step S130 in one embodiment of the present application;

[0066] Figure 9 FIG. 1 is a flow chart of step S130 in another embodiment of the present application.

[0067] Description of reference numerals:

[0068] Substrate 100, backlight surface m1, light receiving surface m2;

[0069] a first intrinsic amorphous silicon layer 200 a and a second intrinsic amorphous silicon layer 200 b ;

[0070] a first doping layer 300a and a second doping layer 300b;

[0071] Laminated structure 400a, conductive transition layer 410a, first transparent conductive layer 411a, tunneling layer 412a, metal layer 420a, second transparent conductive layer 400b, insulating layer J;

[0072] A first gate line electrode 500a and a second gate line electrode 500b;

[0073] Steps S110, S120, S130, S131a, S132a, S131b, S132b. DETAILED DESCRIPTION

[0074] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0075] In the description of this application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0076] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0077] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. It is worth noting that in the following description and the attached claims, "electrical connection" between one feature and another feature not only includes one feature being in direct contact with another feature to form an electric energy transmission or current transmission channel, but also includes an intermediate feature between one feature and another feature, and the one feature, the other feature and the intermediate feature between them form an electric energy transmission channel or a current transmission channel to achieve electric energy transmission or transmission. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0078] In this application, unless otherwise expressly specified or limited, if a first feature is described as being "above" or "below" a second feature, or similar descriptions, this may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is described as being "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is described as being "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0079] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only embodiment.

[0080] Figure 1 A schematic structural diagram of a heterojunction solar cell in one embodiment of the present application is shown; for ease of explanation, only the content related to the embodiment of the present application is shown.

[0081] Please refer to Figure 1 The embodiment of the present application provides a heterojunction solar cell, including a substrate 100, a first intrinsic amorphous silicon layer 200a, a first doped layer 300a, a stacked structure 400a and a first gate line electrode 500a.

[0082] The substrate 100 can be selected based on actual needs. For example, the substrate 100 can be a silicon substrate. The doping type of the substrate 100 is not specifically limited. For example, the substrate 100 can be an N-type doped silicon substrate, or a P-type doped silicon substrate. In the embodiments of the present application, this is not specifically limited. In the embodiments of the present application, the substrate 100 can be an N-type single crystal silicon wafer.

[0083] The substrate 100 has a backlight surface m1, which is configured as a polished surface. Of course, the substrate 100 also has a light-receiving surface m2 arranged opposite to the backlight surface m1. It can be understood that the light-receiving surface m2 and the backlight surface m1 are relative. The light-receiving surface m2 specifically refers to the surface on the substrate 100 that is mainly irradiated by sunlight in a solar cell or a photovoltaic module. The light-receiving surface m2 is usually provided with a velvet structure, which can increase the light absorption area, increase the photocurrent, and help improve the efficiency of the heterojunction solar cell. In the embodiment of the present application, the backlight surface m1 can be formed into a polished surface through a polishing process.

[0084] The first intrinsic amorphous silicon layer 200a, the first doped layer 300a, the stacked structure 400a, and the first gate electrode 500a are disposed on the backlight surface m1 side of the substrate 100. Specifically, the first intrinsic amorphous silicon layer 200a is disposed on the backlight surface m1, the first doped layer 300a is disposed on the side of the first intrinsic amorphous silicon layer 200a facing away from the backlight surface m1, and the stacked structure 400a is disposed on the side of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a. Furthermore, the stacked structure 400a includes a conductive transition layer 410a and a metal layer 420a. The conductive transition layer 410a is disposed on the side of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a, and the metal layer 420a is disposed on the side of the conductive transition layer 410a facing away from the first doped layer 300a. The conductive transition layer 410a is a conductive transition structure that connects the first doped layer 300a and the metal layer 420a. The first gate electrode 500a is located on the side of the stacked structure 400a facing away from the first doped layer 300a. In other words, the first gate electrode 500a can be located on the side of the conductive transition layer 410a facing away from the first doped layer 300a, or on the side of the metal layer 420a facing away from the conductive transition layer 410a.

[0085] Of course, a second intrinsic amorphous silicon layer 200b, a second doped layer 300b, a second transparent conductive layer 400b and a second gate electrode 500b are sequentially stacked on the light-receiving surface m2 of the substrate 100 to achieve photoelectric conversion on the light-receiving surface m2 side.

[0086] The first doped layer 300a and the second doped layer 300b have different doping types. The first doped layer 300a can be an N-type doped semiconductor layer, and the second doped layer 300b can be a P-type doped semiconductor layer. Of course, the first doped layer 300a can also be a P-type doped semiconductor layer, and the second doped layer 300b can also be an N-type doped semiconductor layer. In the embodiment of the present application, the first doped layer 300a is one of a P-type amorphous silicon layer, a P-type microcrystalline silicon layer, or a P-type nanocrystalline silicon layer, and the second doped layer 300b is one of an N-type amorphous silicon layer, an N-type microcrystalline silicon layer, or an N-type nanocrystalline silicon layer. Flexible configurations can be made based on specific usage, and the embodiment of the present application does not impose specific limitations on this. The first intrinsic amorphous silicon layer 200a and the second intrinsic amorphous silicon layer 200b can achieve chemical passivation. When the substrate 100 is an N-type single crystal silicon wafer, the first doped layer 300a is a P-type doped semiconductor layer, and the second doped layer 300b is an N-type doped semiconductor layer, the first doped layer 300a can serve as an emitter, and the second doped layer 300b can achieve field passivation.

[0087] Compared to the related art approach of providing only a transparent conductive layer, the embodiments of the present application utilize a conductive transition layer 410a and a metal layer 420a in place of the transparent conductive layer, thereby reducing the amount of transparent conductive material used. In the case of the metal layer 420a, since the metal layer 420a is a layered structure composed of metallic materials and does not contain organic components, the metal layer 420a exhibits improved compactness, adhesion, and conductivity. Furthermore, the metal layer 420a and the transition conductive layer have a certain contact area, which increases the path for current collection. This not only reduces the number of first gateline electrodes 500a required, thereby reducing the amount of slurry material used, but also improves short-circuit current.

[0088] In addition, by setting the backlight surface m1 of the substrate 100 as a polished surface, not only can the contact between the layers set on the backlight surface m1 be better, the uniformity and film formation quality of each layer be improved, the thickness of the conductive transition layer 410a and the metal layer 420a can be made thinner, that is, the amount of related materials used can be reduced, and the light incident from the light-receiving surface m2 to the backlight surface m1 can be reflected, thereby increasing the light absorption of the substrate 100 and thereby increasing the short-circuit current.

[0089] It is understood that when the first doped layer 300a is a microcrystalline silicon layer or a nanocrystalline silicon layer, the crystallinity of the first doped layer 300a can be improved by setting the backlight surface m1 as a polished surface. When the first doped layer 300a is an emitter, setting the backlight surface m1 as a polished surface is more conducive to adjusting the emitter band gap.

[0090] Therefore, the heterojunction solar cell provided by the embodiment of the present application can improve the short-circuit current as a whole while reducing the cost, thereby improving the photoelectric conversion efficiency of the solar cell.

[0091] In some embodiments, please refer to Figure 1 The first gate electrode 500a is located on a surface of the metal layer 420a that faces away from the conductive transition layer 410a, and is electrically connected to the metal layer 420a. That is, the conductive transition layer 410a, the metal layer 420a, and the first gate electrode 500a are sequentially stacked and formed on a surface of the first doped layer 300a that faces away from the first intrinsic amorphous silicon layer 200a.

[0092] In this way, by directly disposing the first gate line electrode 500 a on the metal layer 420 a , it is not only beneficial to collect current but also can improve the reliability of the first gate line electrode 500 a .

[0093] Figure 2 A schematic structural diagram of a heterojunction solar cell in another embodiment of the present application is shown; for ease of explanation, only the content related to the embodiment of the present application is shown.

[0094] In some embodiments, please refer to Figure 2 The first gate electrode 500a is located on a surface of the conductive transition layer 410a that faces away from the first doped layer 300a. At least a portion of the metal layer 420a is located on a surface of the conductive transition layer 410a that faces away from the first doped layer 300a. The first gate electrode 500a is electrically connected to the conductive transition layer 410a and the metal layer 420a, respectively. In other words, at least a portion of the first gate electrode 500a and the metal layer 420a are both located on a surface of the conductive transition layer 410a that faces away from the first doped layer 300a.

[0095] Specifically, the metal layer 420a can be entirely located on the surface of the conductive transition layer 410a that is away from the first doped layer 300a, and the sidewall of the metal layer 420a is connected to the sidewall of the first gate electrode 500a. The metal layer 420a can also be partially located on the surface of the conductive transition layer 410a that is away from the first doped layer 300a, and the other part covers at least a portion of the first gate electrode 500a. It can be understood that the other part of the metal layer 420a can completely cover the first gate electrode 500a, or can at least cover the sidewall of the gate electrode, as long as the metal layer 420a can be electrically connected between the conductive transition layer 410a and the first gate electrode 500a, and the embodiment of the present application does not impose any specific restrictions on this. Figure 2For example, the other portion of the metal layer can completely cover the first gate electrode 500a. In this case, the orthographic projection of the first gate electrode 500a on the surface of the conductive transition layer 410a facing away from the first doped layer 300a is located within the orthographic projection of the metal layer 420a on the surface of the conductive transition layer 410a facing away from the first doped layer 300a. In other words, the conductive transition layer 410a, the first gate electrode 500a, and the metal layer 420a can be sequentially stacked on the surface of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a.

[0096] In this manner, electrically connecting the first gateline electrode 500a to the conductive transition layer 410a and the metal layer 420a, respectively, helps improve the reliability of the first gateline electrode 500a. By having the other portion of the metal layer 420a cover at least a portion of the first gateline electrode 500a, not only is the reliability of the first gateline electrode 500a further improved, but the contact area between the first gateline electrode 500a and the metal layer 420a is also further increased, further facilitating the first gateline electrode 500a to collect current passing through the metal layer 420a. It will be appreciated that when the metal layer 420a completely covers the exposed surface of the first gateline electrode 500a and the exposed surface of the conductive transition layer 410a facing away from the first doped layer 300a, the exposed surface of the first gateline electrode 500a is encased in the metal layer 420a, further increasing the contact area between the first gateline electrode 500a and the metal layer 420a. This not only facilitates current collection but also further improves the reliability of the first gateline electrode 500a.

[0097] It should be noted that the “exposed surface of the first gate line electrode 500a” refers to the surface of the first gate line electrode 500a excluding the surface where the first gate line electrode 500a contacts the conductive transition layer 410a, and the “exposed surface of the conductive transition layer 410a facing away from the first doped layer 300a” refers to the remaining portion of the surface of the conductive transition layer 410a facing away from the first doped layer 300a excluding the portion that contacts the first gate line electrode 500a.

[0098] Figure 3 A schematic structural diagram of a heterojunction solar cell in another embodiment of the present application is shown; Figure 4 A schematic structural diagram of a heterojunction solar cell in another embodiment of the present application is shown; Figure 5 A schematic structural diagram of a heterojunction solar cell in another embodiment of the present application is shown; Figure 6 A schematic structural diagram of a heterojunction solar cell in another embodiment of the present application is shown; for ease of explanation, only the content related to the embodiment of the present application is shown.

[0099] In some embodiments, the conductive transition layer 410a includes at least one of a first transparent conductive layer 411a and a tunneling layer 412a.

[0100] For example, Figure 1 and Figure 2 As shown, the conductive transition layer 410a may include a first transparent conductive layer 411a; Figure 3 and Figure 4 As shown, the conductive transition layer 410a may include a tunneling layer 412a; Figure 5 As shown, the conductive transition layer 410a may include a first transparent conductive layer 411a and a tunneling layer 412a. The first transparent conductive layer 411a is provided on a surface of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a. The tunneling layer 412a is provided on a surface of the first transparent conductive layer 411a facing away from the first doped layer 300a. The metal layer 420a is provided on a surface of the tunneling layer 412a facing away from the first transparent conductive layer 411a. Figure 6 As shown, Figure 5 The difference is that the first gate line electrode 500a is provided on the surface of the tunneling layer 412a away from the first transparent conductive layer 411a, a portion of the metal layer 420a is located on the surface of the tunneling layer 412a away from the first transparent conductive layer 411a, and the other portion covers the first gate line electrode 500a.

[0101] Of course, the tunneling layer 412a may be disposed on a surface of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a, the first transparent conductive layer 411a may be disposed on a surface of the tunneling layer 412a facing away from the first doped layer 300a, and the metal layer 420a may be disposed on a surface of the first transparent conductive layer 411a facing away from the tunneling layer 412a.

[0102] It is understood that when the conductive transition layer 410a includes the first transparent conductive layer 411a and the tunneling layer 412a, the configuration of the first gate line electrode 500a and the metal layer 420a may refer to the configurations illustrated in some of the aforementioned embodiments, which will not be described in detail here.

[0103] In some embodiments, the conductive transition layer 410a has a thickness of 0.5 nm to 122 nm. For example, the conductive transition layer 410a may have a thickness of 0.5 nm, 1 nm, 10 nm, 23 nm, 30 nm, 46 nm, 50 nm, 66 nm, 78 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 118 nm, or 122 nm.

[0104] In this way, by controlling the thickness of the conductive transition layer 410 a , the series resistance can be reduced while improving the interface contact and optical absorption.

[0105] In some embodiments, please refer to Figure 1 and Figure 2 When the conductive transition layer 410a includes a first transparent conductive layer 411a, the thickness of the first transparent conductive layer 411a is 5 nm to 120 nm. For example, the thickness of the first transparent conductive layer 411a can be 5 nm, 7 nm, 8 nm, 10 nm, 26 nm, 32 nm, 48 nm, 50 nm, 63 nm, 75 nm, 87 nm, 93 nm, 95 nm, 100 nm, 110 nm, 118 nm, or 120 nm.

[0106] In this way, by controlling the thickness of the first transparent conductive layer 411 a , it is possible to improve optical absorption and reduce series resistance while maintaining certain electrical and anti-reflection properties.

[0107] In some embodiments, please refer to Figure 3 and Figure 4 When the conductive transition layer 410a includes a tunneling layer 412a, the thickness of the tunneling layer 412a is 0.5 nm to 2 nm. For example, the thickness of the tunneling layer 412a can be 0.5 nm, 0.6 nm, 0.9 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, or 2 nm.

[0108] In this way, by controlling the thickness of the tunneling layer 412 a , it is possible to improve optical absorption and reduce series resistance while fully covering the surface of the first doped layer 300 a facing away from the first intrinsic amorphous silicon layer 200 a as much as possible.

[0109] In some embodiments, please refer to Figure 5 and Figure 6 The conductive transition layer 410a includes a first transparent conductive layer 411a and a tunneling layer 412a. The thickness of the first transparent conductive layer 411a is 5 nm to 120 nm, and the thickness of the tunneling layer 412a is 0.5 nm to 2 nm. For example, the thickness of the first transparent conductive layer 411a can be 5 nm, 7 nm, 8 nm, 10 nm, 26 nm, 32 nm, 48 nm, 50 nm, 63 nm, 75 nm, 87 nm, 93 nm, 95 nm, 100 nm, 110 nm, 118 nm, or 120 nm, and the thickness of the tunneling layer 412a can be 0.5 nm, 0.6 nm, 0.9 nm, 1 nm, 1.2 nm, 1.5 nm, 1.8 nm, or 2 nm. For the corresponding advantages, please refer to the contents of the aforementioned embodiments and will not be repeated here. With reference to the contents illustrated in the aforementioned embodiments, the object covered by the tunneling layer 412 a may be the first transparent conductive layer 411 a or the first doping layer 300 a .

[0110] It is understood that when the tunneling layer 412a is provided, the contact resistivity can be improved. When the tunneling layer 412a is provided between the first transparent conductive layer 411a and the metal layer 420a, the interface performance between the first transparent conductive layer 411a and the metal layer 420a can be further improved by the tunneling layer 412a.

[0111] It is understood that the material of the first transparent conductive layer 411a (i.e., TCO layer) is selected from one or more of indium tin oxide (ITO), tungsten-doped indium oxide (IWO), cesium-doped indium oxide (ICO), tin oxide, tungsten-doped zinc oxide (GZO), tungsten-aluminum-doped zinc oxide (GAZO), aluminum zinc oxide (AZO), and VTTO target. Correspondingly, the second transparent conductive layer 400b (i.e., TCO layer) can also be considered in this way. The materials of the first transparent conductive layer 411a and the second transparent conductive layer 400b can be the same or different. The material of the tunneling layer 412a is selected from one or more of aluminum oxide, silicon oxide, and titanium oxide. It can be selected according to the specific use case, and the embodiment of the present application does not impose specific restrictions on this.

[0112] In some embodiments, please refer to Figures 1 to 6 The thickness of the metal layer 420a is 20 nm to 200 nm. For example, the thickness of the metal layer 420a can be 20 nm, 22 nm, 30 nm, 35 nm, 40 nm, 45 nm, 55 nm, 58 nm, 60 nm, 65 nm, 70 nm, 73 nm, 80 nm, 90 nm, 100 nm, 110 nm, 130 nm, 140 nm, 150 nm, 170 nm, 175 nm, 180 nm, 190 nm, 200 nm, or 200 nm.

[0113] In this way, by controlling the thickness of the metal layer 420a, the conductive transition layer 410a can be covered as much as possible while increasing the path for collecting current. Combined with the content illustrated in some of the aforementioned embodiments, when the metal layer 420a cooperates with the conductive transition layer 410a to wrap the first gateline electrode 500a, the reliability of the first gateline electrode 500a can be further improved.

[0114] In some embodiments, the metal layer 420a has a single-layer structure; alternatively, the metal layer 420a has a multi-layer structure. For example, the material of the metal layer 420a can be one or more of copper, silver, aluminum, tin, nickel, or titanium. In the case of a multi-layer structure, the materials of each layer can be the same or different. The structure of the metal layer 420a can be configured according to the specific application and is not specifically limited here.

[0115] In some embodiments, please refer to Figures 1 to 6The heterojunction solar cell further includes an insulating layer J, which covers at least the side surfaces of the heterojunction solar cell. Thus, the insulating layer J acts as a gas and oxygen barrier on the side surfaces of the heterojunction solar cell, thereby improving the stability of the heterojunction solar cell.

[0116] It should be noted that the side surfaces of the heterojunction solar cell refer to the side surfaces of the substrate 100 and the side surfaces of the layers disposed on the backlight surface m1 and the light-receiving surface m2. The side surfaces of the substrate 100 are connected to the light-receiving surface m2 and the backlight surface m1. The side surfaces of the remaining layers can be understood in the same way and will not be further described.

[0117] It can be understood that the insulating layer J can be produced before forming the metal layer 420a. In this case, it can also improve the situation where the metal is deposited on the side of the heterojunction solar cell to form a recombination center when the metal layer 420a is produced, thereby improving the impact of the production of the metal layer 420a on the performance of the heterojunction solar cell.

[0118] In some embodiments, please refer to Figures 1 to 6 The insulating layer J also covers the edge region of the conductive transition layer 410a on the side facing away from the first doped layer 300a; and / or the insulating layer J also covers the edge region of the second transparent conductive layer 400b on the side facing away from the second doped layer 300b. This improves the reliability of the insulating layer J's adhesion.

[0119] It can be understood that the edge area of ​​the surface of the conductive transition layer 410a on the side facing away from the first doped layer 300a is the area connected to the side of the conductive transition layer 410a, and the edge area of ​​the surface of the second transparent conductive layer 400b on the side facing away from the second doped layer 300b is the area connected to the side of the second transparent conductive layer 400b.

[0120] In some embodiments, the material of the insulating layer J includes insulating materials such as silicon oxide, organic insulating materials, or inorganic insulating materials, etc. The material can be configured according to specific usage conditions, and the present embodiment does not impose any specific limitation thereto.

[0121] Figure 7 A schematic flow chart of a method for manufacturing a heterojunction solar cell in one embodiment of the present application is shown; for ease of explanation, only the content related to the embodiment of the present application is shown.

[0122] Based on the same invention concept, please refer to Figure 7 , and combined with reference Figures 1 to 6 The present invention also provides a method for manufacturing a heterojunction solar cell, comprising the following steps:

[0123] Step S110, providing a substrate 100; the substrate 100 has a backlight surface m1, and the backlight surface m1 is configured as a polished surface;

[0124] Step S120 , sequentially forming a first intrinsic amorphous silicon layer 200 a and a first doped layer 300 a on the backlight surface m1 ;

[0125] Step S130: forming a stacked structure 400a and a first gate electrode 500a on a surface of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a; the first gate electrode 500a is located on a side of the stacked structure 400a facing away from the first doped layer 300a; the stacked structure 400a includes a conductive transition layer 410a and a metal layer 420a, the conductive transition layer 410a being disposed on a surface of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a, and the metal layer 420a being disposed on a surface of the conductive transition layer 410a facing away from the first doped layer 300a; and at least one of the conductive transition layer 410a and the metal layer 420a being electrically connected to the first gate electrode 500a.

[0126] In step S110, the backlight surface m1 of the substrate 100 can be polished by a polishing process so that the backlight surface m1 is a polished surface. The polishing process can be a chemical polishing process or a physical polishing process. For example, the backlight surface m1 can be alkaline polished, and the alkaline polishing solution can be KOH. It can be selected according to the specific use situation, and the embodiment of the present application does not impose specific restrictions on this. Correspondingly, the substrate 100 also has a light-receiving surface m2 arranged opposite to the backlight surface m1, and the light-receiving surface m2 of the substrate 100 can be texturized by a texturizing process to form a velvet structure on the light-receiving surface m2.

[0127] Before providing the substrate 100, a step of pre-treating the substrate 100 may be included. The pre-treatment process includes cleaning and other processes to facilitate subsequent processes. The required pre-treatment process can be selected according to the usage, and the embodiments of the present application do not impose specific limitations on this.

[0128] In step S120, the first intrinsic amorphous silicon layer 200a can be formed on the backlight surface m1 while the second intrinsic amorphous silicon layer 200b can be formed on the light-receiving surface m2. The first doped layer 300a can be formed on the surface of the first intrinsic amorphous silicon layer 200a facing away from the backlight surface m1 while the second doped layer 300b can be formed on the surface of the second intrinsic amorphous silicon layer 200b facing away from the light-receiving surface m2. Of course, these operations can also be performed at different times, and this is not specifically limited here.

[0129] The first intrinsic amorphous silicon layer 200a and the second intrinsic amorphous silicon layer 200b can be deposited on corresponding surfaces by a chemical vapor deposition method (e.g., plasma-enhanced chemical vapor deposition, PECVD). The first doped layer 300a and the second doped layer 300b can be deposited on corresponding surfaces by a chemical vapor deposition method (e.g., plasma-enhanced chemical vapor deposition, PECVD). These can be configured according to specific usage scenarios and are not specifically limited in this embodiment of the present application.

[0130] In step S130, the conductive transition layer 410a is a transition structure that connects the first doped layer 300a and the metal layer 420a and is capable of conducting electricity. The conductive transition layer 410a may include at least one of a first transparent conductive layer 411a and a tunneling layer 412a. The first gate electrode 500a is located on the side of the stacked structure 400a facing away from the first doped layer 300a. In other words, the first gate electrode 500a may be located on the side of the conductive transition layer 410a facing away from the first doped layer 300a, or on the side of the metal layer 420a facing away from the conductive transition layer 410a.

[0131] The advantages of the heterojunction solar cell illustrated in some of the above embodiments are also possessed by the heterojunction solar cell obtained by the method for manufacturing the heterojunction solar cell, which will not be described in detail here. In addition, the implementation methods of the relevant layers can also refer to the methods illustrated in some of the above embodiments, which will not be described in detail here.

[0132] Figure 8 A flow chart of step S130 in an embodiment of the present application is shown; for ease of explanation, only the content related to the embodiment of the present application is illustrated.

[0133] In some embodiments, please refer to Figure 8 , and combined with reference Figure 1 、 Figure 3 and Figure 5 Step S130 includes the following steps:

[0134] Step S131a, forming a conductive transition layer 410a on a surface of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a;

[0135] Step S132a: forming a metal layer 420a and a first gate line electrode 500a in sequence on a surface of the conductive transition layer 410a facing away from the first doped layer 300a; wherein the first gate line electrode 500a is electrically connected to the metal layer 420a.

[0136] In step S131a, when the conductive transition layer 410a includes a first transparent conductive layer 411a, a second transparent conductive layer 400b may be formed simultaneously with the formation of the first transparent conductive layer 411a on a surface of the second doped layer 300b facing away from the second intrinsic amorphous silicon layer 200b. Of course, the first transparent conductive layer 411a and the second transparent conductive layer 400b may not be formed simultaneously. The materials of the first transparent conductive layer 411a and the second transparent conductive layer 400b may be the same or different. As illustrated in some of the aforementioned embodiments, since the metal layer 420a is also formed on the backlight surface m1, the thickness of the first transparent conductive layer 411a may be less than the thickness of the second transparent conductive layer 400b. The first transparent conductive layer 411a and the second transparent conductive layer 400b can be formed on the surface of the corresponding layer by a physical vapor deposition method (for example, magnetron sputtering (Physical Vapor Deposition, PVD). It can be set according to the specific use case, and the embodiment of the present application does not impose specific restrictions on this. When the conductive transition layer 410a includes a tunneling layer 412a, it can be formed on the surface of the corresponding layer by atomic layer deposition (Atomic Layer Deposition, ALD).

[0137] In step S132a, the following may be formed: Figure 1 、 Figure 3 and Figure 5 The stacked structure 400a and the first gate line electrode 500a are shown in a coordinated structure.

[0138] Figure 9 A flow chart of step S130 in another embodiment of the present application is shown; for ease of explanation, only the content related to the embodiment of the present application is shown.

[0139] In some embodiments, please refer to Figure 9 , and combined with reference Figure 2 、 Figure 4 and Figure 6 Step S130 includes the following steps:

[0140] Step S131b: forming a conductive transition layer 410a on a surface of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a;

[0141] Step S132b: forming a first gate line electrode 500a and a metal layer 420a in sequence on a surface of the conductive transition layer 410a facing away from the first doped layer 300a; wherein at least a portion of the metal layer 420a is located on a surface of the conductive transition layer 410a facing away from the first doped layer 300a; and the first gate line electrode 500a is electrically connected to the conductive transition layer 410a and the metal layer 420a, respectively.

[0142] In step S131b, reference may be made to the situations illustrated in some of the aforementioned embodiments, which will not be described in detail here.

[0143] In step S132b, the structure and configuration of the metal layer 420a may refer to the contents illustrated in some of the aforementioned embodiments, and will not be repeated here.

[0144] Thus, the metal layer 420a can be manufactured using different manufacturing methods according to the structure of the stacked structure 400a. The implementation and advantages of different metal layers 420a and first gate line electrodes 500a can be referred to the contents shown in the above embodiments and will not be repeated here.

[0145] In the manufacturing method of the stacked structure 400a illustrated above, the metal layer 420a can be formed by a preset process, which includes a physical vapor deposition process or an electron beam evaporation process. In the case where the heterojunction solar cell also includes an insulating layer J provided on the side of the heterojunction solar cell, the insulating layer J can be formed on the side of the heterojunction solar cell before forming the metal layer 420a to at least cover the side of the heterojunction solar cell. The insulating layer J can be generated simultaneously when the conductive transition layer 410a is manufactured, or it can be formed separately using an edge printing process or a smearing process. It can be selected according to the specific usage and is not specifically limited here. Other implementations and advantages of the insulating layer J can refer to the contents illustrated in some of the aforementioned embodiments and will not be repeated here.

[0146] It should be noted that, in combination with the situations illustrated in some of the above embodiments, the first gate line electrode 500a and the second gate line electrode 500b can be formed in corresponding steps and on corresponding layers by screen printing, laser transfer or electroplating.

[0147] In this way, the desired heterojunction solar cell can be obtained through the implementation methods illustrated in some of the above embodiments.

[0148] The performance of the heterojunction solar cell provided by the embodiments of the present application is described below based on the contents illustrated in some of the above embodiments and related comparative examples.

[0149] In Comparative Examples 1 to 4 of the comparative examples of the present application, both the light-receiving surface and the backlight surface of the substrate are subjected to a velvet treatment to form a velvet structure, and the first grid line electrode provided on the backlight side includes 12 first main grid line electrodes and 164 first auxiliary grid line electrodes. The line width of the first main grid line electrode is 100 μm, and the line height is 18 μm. The line width of the first auxiliary grid line electrode is 40 μm, and the line height is 15 μm. The second grid line electrode 500b provided on the light-receiving surface m2 side includes 12 second main grid line electrodes and 74 second auxiliary grid line electrodes. The line width of the second main grid line electrode is 100 μm, and the line height is 18 μm. The line width of the second auxiliary grid line electrode is 40 μm, and the line height is 15 μm. The thickness of the second transparent conductive layer (using an ITO layer) located on the light-receiving side is 75 nm.

[0150] In comparative example 1, the transparent conductive layer on the backlight side is an ITO layer formed by a PVD process, and has a thickness of 80 nm.

[0151] In Comparative Example 2, a first transparent conductive layer, a first gate electrode, and a metal layer were sequentially formed, with the metal layer overlying the first gate electrode. The first transparent conductive layer located on the backlight side was an 80 nm thick ITO layer produced using a PVD process. The metal layer was a 100 nm thick silver layer produced using vapor deposition on the side of the first transparent conductive layer facing away from the first doped layer. No insulating layer was provided.

[0152] In Comparative Example 3, compared to Comparative Example 2, an insulating layer J is provided.

[0153] In Examples 1 to 8 of the present application, the backlight surface m1 of the substrate 100 is a polished surface, and the side surface of the heterojunction solar cell is formed with an insulating layer J. The metal layer 420a is a silver layer formed by evaporation and has a thickness of 100 nm.

[0154] Among them, in embodiment 1, adopt Figure 2 The structure shown, the parameters of the first gate line electrode 500a and the second gate line electrode 500b are the same as those of the aforementioned comparative example. The conductive transition layer 410a on the backlight side m1 is a first transparent conductive layer 411a, which is an ITO layer formed by PVD process and has a thickness of 80nm.

[0155] In Example 2, the Figure 4 The conductive transition layer 410a on the backlight side m1 is a tunneling layer 412a, which is a silicon oxide layer formed by ALD process and has a thickness of 1.5nm.

[0156] In Example 3, the Figure 6 In the structure shown, the parameters of the first gateline electrode 500a and the second gateline electrode 500b are the same as those in the aforementioned comparative example. The conductive transition layer 410a located on the backlight side m1 includes a first transparent conductive layer 411a and a tunneling layer 412a. The first transparent conductive layer 411a is an 80nm thick ITO layer formed using a PVD process. The tunneling layer 412a is a 1.5nm thick silicon oxide layer formed using an ALD process.

[0157] In Example 4, the Figure 6 The structure shown is based on the third embodiment, but the number of first sub-gate line electrodes located on the backlight surface m1 side is reduced to 82.

[0158] In Example 5, the Figure 5 In the structure shown, the parameters of the first gateline electrode 500a and the second gateline electrode 500b are the same as those in the aforementioned comparative example. The conductive transition layer 410a located on the backlight side m1 includes a first transparent conductive layer 411a and a tunneling layer 412a. The first transparent conductive layer 411a is an 80nm thick ITO layer formed using a PVD process. The tunneling layer 412a is a 1.5nm thick silicon oxide layer formed using an ALD process.

[0159] In Example 6, the Figure 1 The structure shown, the parameters of the first gate line electrode 500a and the second gate line electrode 500b are the same as those of the above comparative example. The conductive transition layer 410a on the backlight side m1 is a first transparent conductive layer 411a, which is an ITO layer formed by PVD process and has a thickness of 10nm.

[0160] In Example 7, the Figure 5 In the structure shown, the parameters of the first gateline electrode 500a and the second gateline electrode 500b are the same as those of the aforementioned comparative example. The conductive transition layer 410a located on the backlight side m1 comprises a first transparent conductive layer 411a and a tunneling layer 412a. The first transparent conductive layer 411a is a 10nm thick ITO layer formed using a PVD process. The tunneling layer 412a is a 1.5nm thick silicon oxide layer formed using an ALD process.

[0161] Relevant tests were conducted on the heterojunction solar cells in the above comparative examples and embodiments, and the experimental results shown in Table 1 were obtained.

[0162] Table 1

[0163]

[0164] As can be seen from Table 1, compared with Comparative Example 1, the optical loss at the interface between the metal layer 420a and the first transparent conductive layer 411a is larger in Comparative Example 2, and the short-circuit current is reduced by 0.15A. However, the lack of protection on the side leads to leakage, and the parallel resistance is significantly reduced. The series resistance is slightly reduced, and the efficiency is reduced by 0.13%. In Comparative Example 3, after the insulating layer J is added, the parallel resistance is not significantly reduced, and the efficiency is only reduced by 0.05%, which is mainly due to the reduction in short-circuit current. Example 1 is similar to Comparative Example 3. Since the backlight surface m1 is set as a polished surface, the multiple reflection absorption loss at the interface can be reduced, and the short-circuit current is higher. In addition, because the backlight surface m1 is a polished surface, the metal layer 420a obtained by the same evaporation process is thicker, and since the polished surface is smoother, the carrier transmission path is shorter, resulting in a lower series resistance and an efficiency increase of 0.06%. In Example 2, only a 1.5nm silicon oxide layer is used, which can improve the potential barrier between the metal layer 420a and the substrate 100 to a certain extent, and can also ensure a certain short-circuit current. The series resistance increases to a certain extent, and there may be damage that causes the efficiency to decrease to a certain extent, but overall it can meet certain efficiency requirements while reducing costs. In Example 3, the interface absorption optical loss is smaller, the contact resistance and series resistance are also slightly better, and the efficiency is improved by 0.1% compared to Comparative Example 1. In Example 4, when the back sub-grid is reduced by half, the efficiency is still 0.04% higher than that of Comparative Example 1. In Example 5, similar to Example 3, the metal layer 420a is below the first gate electrode 500a, and the results are similar. In Example 6, the thickness of the first transparent conductive layer 411a is thinned to 10nm, the parasitic absorption of the first transparent conductive layer 411a is reduced, and the anti-reflection performance also deteriorates. The short-circuit current is basically the same, the convergence effect is mainly borne by the metal layer 420a, and the series resistance is the same, which can effectively reduce the use of ITO. In Example 7, a tunneling layer 412a is added on the basis of Example 6, which improves the interface contact and optical absorption effect and has a higher efficiency.

[0165] Thus, the heterojunction solar cell provided by the embodiment of the present application reduces costs while improving solar cell conversion efficiency. Furthermore, through the interaction of the first transparent conductive layer 411a, the tunneling layer 412a, the metal layer 420a, and the insulating layer J, even better effects are achieved.

[0166] Based on the same inventive concept, an embodiment of the present application provides a photovoltaic module, including the heterojunction solar cell in any of the above embodiments; or, including the heterojunction solar cell manufactured by the manufacturing method of the heterojunction solar cell in any of the above embodiments.

[0167] Furthermore, a plurality of heterojunction solar cells can be provided, and the heterojunction solar cells can be electrically connected in the form of a whole piece or multiple slices to form a plurality of cell strings, and the plurality of cell strings are electrically connected in series and / or in parallel. The photovoltaic module may further include an encapsulation layer and a cover plate, the encapsulation layer being used to cover the surface of the cell string, and the cover plate being used to cover the surface of the encapsulation layer away from the cell string. Specifically, in some embodiments, the plurality of cell strings can be electrically connected via a conductive tape. The encapsulation layer covers the surface of the solar cell. For example, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene co-elastomer film, or a polyethylene terephthalate film. The cover plate can be a cover plate with a light-transmitting function such as a glass cover plate or a plastic cover plate.

[0168] The advantages possessed by the heterojunction solar cell in any of the above embodiments, or the advantages possessed by the heterojunction solar cell manufactured by the method for manufacturing the heterojunction solar cell in any of the above embodiments, are also possessed by the photovoltaic module and will not be described in detail here.

[0169] Based on the same inventive concept, the embodiment of the present application provides a photovoltaic system, including the photovoltaic module in any of the above embodiments. The advantages of the above photovoltaic modules are also possessed by the photovoltaic system, which will not be repeated here.

[0170] It is understood that photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water-surface power stations, etc., and can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understood that the application scenarios of photovoltaic systems are not limited to this, that is, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array can be an array combination of multiple photovoltaic modules. For example, multiple photovoltaic modules can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box. The junction box can converge the current generated by the photovoltaic array. The converged current flows through the inverter to be converted into the alternating current required by the mains power grid and then connected to the mains power network to achieve solar power supply.

[0171] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0172] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A heterojunction solar cell, characterized in that: include: A substrate having a backlight surface; the backlight surface is configured as a polished surface; A first intrinsic amorphous silicon layer is provided on the backlight surface; A first doped layer is provided on a surface of the first intrinsic amorphous silicon layer facing away from the backlight surface; A stacked structure comprising a conductive transition layer and a metal layer, wherein the conductive transition layer is provided on a surface of the first doped layer facing away from the first intrinsic amorphous silicon layer, and the metal layer is provided on a surface of the conductive transition layer facing away from the first doped layer; and a first gate line electrode, located on a side of the stacked structure away from the first doped layer; at least one of the conductive transition layer and the metal layer is electrically connected to the first gate line electrode; The heterojunction solar cell further includes an insulating layer; The insulating layer covers the side surfaces of the heterojunction solar cell; The insulating layer also covers an edge region of a surface of the conductive transition layer that is away from the first doping layer.

2. The heterojunction solar cell according to claim 1, wherein: The first gate line electrode is located on a surface of the metal layer facing away from the conductive transition layer; The first gate line electrode is electrically connected to the metal layer.

3. The heterojunction solar cell according to claim 1, wherein: The first gate line electrode is located on a surface of the conductive transition layer facing away from the first doping layer; At least a portion of the metal layer is located on a surface of the conductive transition layer facing away from the first doping layer; The first gate line electrode is electrically connected to the conductive transition layer and the metal layer respectively.

4. The heterojunction solar cell according to claim 3, characterized in that: A portion of the metal layer is located on a surface of the conductive transition layer facing away from the first doping layer, and another portion covers at least a portion of the first gate line electrode.

5. The heterojunction solar cell according to claim 4, characterized in that: The orthographic projection of the first gate line electrode on the surface of the conductive transition layer facing away from the first doping layer is located within the orthographic projection of the metal layer on the surface of the conductive transition layer facing away from the first doping layer.

6. The heterojunction solar cell according to any one of claims 1 to 5, characterized in that: The conductive transition layer includes at least one of a first transparent conductive layer and a tunneling layer.

7. The heterojunction solar cell according to claim 6, characterized in that: The conductive transition layer includes a first transparent conductive layer, and the thickness of the first transparent conductive layer is 5nm-120nm; or The conductive transition layer includes a tunneling layer, and the thickness of the tunneling layer is 0.5 nm to 2 nm; or The conductive transition layer includes a first transparent conductive layer and a tunneling layer. The thickness of the first transparent conductive layer is 5 nm to 120 nm, and the thickness of the tunneling layer is 0.5 nm to 2 nm.

8. The heterojunction solar cell according to any one of claims 1 to 5, characterized in that: The metal layer is a single-layer structure; or The metal layer is a multi-layer structure.

9. The heterojunction solar cell according to any one of claims 1 to 5, characterized in that: The thickness of the conductive transition layer is 0.5 nm to 122 nm; and / or The thickness of the metal layer is 20nm-200nm.

10. The heterojunction solar cell according to claim 1, characterized in that: The substrate has a light-receiving surface arranged opposite to the backlight surface; The heterojunction solar cell further includes a second intrinsic amorphous silicon layer, a second doped layer, a second transparent conductive layer and a second gate electrode stacked in sequence on the light-receiving surface; The insulating layer further covers an edge region of a surface of the second transparent conductive layer on a side facing away from the second doping layer.

11. A method for manufacturing a heterojunction solar cell, characterized in that: include: providing a substrate; The substrate has a backlight surface, and the backlight surface is configured as a polished surface; forming a first intrinsic amorphous silicon layer and a first doping layer in sequence on the backlight surface; forming a stacked structure and a first gate line electrode on a surface of the first doped layer on a side away from the first intrinsic amorphous silicon layer; The first gate line electrode is located on a side of the stacked structure away from the first doped layer; The stacked structure includes a conductive transition layer and a metal layer, wherein the conductive transition layer is provided on a surface of the first doped layer facing away from the first intrinsic amorphous silicon layer, and the metal layer is provided on a surface of the conductive transition layer facing away from the first doped layer. At least one of the conductive transition layer and the metal layer is electrically connected to the first gate line electrode; The stacked structure and the first gate line electrode are formed on a surface of the first doped layer facing away from the first intrinsic amorphous silicon layer, comprising: forming the conductive transition layer on a surface of the first doped layer facing away from the first intrinsic amorphous silicon layer; forming the metal layer and the first gate line electrode on a surface of the conductive transition layer facing away from the first doping layer; Before forming the metal layer and the first gate line electrode on the surface of the conductive transition layer facing away from the first doping layer, the method further includes: An insulating layer is formed on a side surface of the heterojunction solar cell and an edge region of a surface of the conductive transition layer facing away from the first doping layer.

12. The method for manufacturing a heterojunction solar cell according to claim 11, wherein: The forming of the metal layer and the first gate line electrode on a surface of the conductive transition layer facing away from the first doping layer comprises: forming the metal layer and the first gate line electrode in sequence on a surface of the conductive transition layer facing away from the first doping layer; Wherein, the first gate line electrode is electrically connected to the metal layer.

13. The method for manufacturing a heterojunction solar cell according to claim 11, wherein: The forming of the metal layer and the first gate line electrode on a surface of the conductive transition layer facing away from the first doping layer comprises: forming the first gate line electrode and the metal layer in sequence on a surface of the conductive transition layer facing away from the first doping layer; At least a portion of the metal layer is located on a surface of the conductive transition layer facing away from the first doped layer; and the first gate line electrode is electrically connected to the conductive transition layer and the metal layer respectively.

14. The method for manufacturing a heterojunction solar cell according to any one of claims 11 to 13, characterized in that: The conductive transition layer includes at least one of a first transparent conductive layer and a tunneling layer; and / or The metal layer is formed by a preset process; the preset process includes a physical vapor deposition process or an electron beam evaporation process.

15. A photovoltaic module, characterized in that: A heterojunction solar cell comprising the heterojunction solar cell according to any one of claims 1 to 10; or A heterojunction solar cell manufactured by the method for manufacturing a heterojunction solar cell according to any one of claims 11 to 14.

16. A photovoltaic system, characterized in that: Comprising the photovoltaic module according to claim 15.

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