Latch bit cell via write mask

Abstract

The write-masked latch bit cell of the SRAM includes a write mask circuit that causes the value of the write data node to be a first value in response to the assertion of a first write mask signal and causes the value of the write data node to have a second value in response to the assertion of a second write mask signal. A transmission gate supplies the data on the write data node to an internal node of the bit cell in response to the write word line signal being asserted. When the first write mask signal and the second write mask signal are deasserted, a keeper circuit maintains the value of the first node independent of the value of the write word line signal.

Description

BACKGROUND OF THE INVENTION

[0001] This application relates to SRAM and SRAM bit cells. Selectively writing to bit cells in SRAM allows for more efficient overall operation of the SRAM. It is desirable to continue to improve the area impact of masked writes to SRAM cells to help provide improved system performance. SUMMARY OF THE INVENTION

[0002] Accordingly, in one embodiment, an apparatus includes a latched bit cell that is written to with a mask, the latched bit cell that is written to with a mask including a write portion. The write portion includes a write mask circuit that causes a value of a write data node to be a first value in response to an assertion of a first write mask signal and causes the value of the write data node to have a second value in response to an assertion of a second write mask signal. A transmission gate is coupled to the write data node and supplies the value on the write data node to a first node in response to a write word line signal being asserted. A keeper circuit is configured to maintain the value of the first node independent of the value of the write word line signal when the first write mask signal and the second write mask signal are deasserted.

[0003] In another embodiment, a method includes setting a write data node in a latched bit cell that is written to with a mask to a first value in response to an assertion of a first write mask signal and setting the write data node to a second value in response to an assertion of a second write mask signal. The method includes coupling the write data node to a first node in response to a write word line signal being asserted. When the first write mask signal and the second write mask signal are deasserted, data on the first node is maintained by a keeper circuit independent of the value of the write word line signal.

[0004] In another embodiment, a method includes writing to a latched bit cell that is written to with a mask in response to a write word line (WWL) signal and an active low write word line (WWLX) signal being asserted in combination with either a first write mask signal or a second write mask signal being asserted. The state of the latched bit cell that is written to with a mask is maintained when the WWL signal and the WWLX signal are asserted and the first write mask signal and the second write mask signal are deasserted. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present invention can be better understood by reference to the accompanying drawings, and many of its objects, features, and advantages will be apparent to those skilled in the art.

[0006] Figure 1 An embodiment of a latched bit cell according to an embodiment is shown.

[0007] Figure 2Shows an exemplary layout of a latch bit cell.

[0008] Figure 3 Shows how different threshold voltages can be used in the read and write portions of a latch bit cell.

[0009] Figure 4 Shows a column of 32 latch bit cells.

[0010] Figure 5 Shows a high-level block diagram of two columns each having 64 rows of latch bit cells.

[0011] Figure 6 Shows an implementation of a masked latch bit cell.

[0012] Figure 7 Shows the layout of a masked latch bit cell.

[0013] Figure 8 Shows another implementation of a masked latch bit cell.

[0014] Figure 9 Shows an implementation of a pulse generator that generates WRZERO or WRONEX pulses.

[0015] Figure 10 Shows Figure 8 the layout of the masked latch bit cell.

[0016] Figure 11 Shows Figure 1 the implementation of a column formed by the latch bit cells.

[0017] Figure 12A Shows a conventional standard cell architecture where each transistor finger has two fins.

[0018] Figure 12B Shows a hybrid standard cell architecture of alternating cells where each transistor finger has two fins and each transistor finger has one fin.

[0019] Figure 12C Shows a high-level block diagram of a fin field-effect transistor where each transistor finger has one fin and each transistor finger has two fins.

[0020] Figure 13 Shows an implementation of an array of latch bit cells using a hybrid standard cell library.

[0021] Figure 14 Shows an implementation of an array of latch bit cells using a hybrid standard cell library, which provides a ratio better than Figure 13Embodiments with more balanced performance.

[0022] Figure 15 FIG. shows a high-level block diagram of an embodiment of a latch bit cell array.

[0023] Figure 16 FIG. shows a high-level block diagram of an embodiment of a latch bit cell array using masked-written bit cells.

[0024] Like or identical items are denoted by the same reference numerals in the different figures. DETAILED DESCRIPTION

[0025] In newer technology nodes, eight-transistor (8T) static random access memory (SRAM) arrays do not scale well in terms of area. However, circuits built with standard cell design rules continue to scale relatively well in newer technology nodes. Building an SRAM array with standard cell design rules allows for a smaller area, even with more transistors. Figure 1 FIG. shows an SRAM bit cell implemented as a latch bit cell 100 with separate read and write ports. Note that the latch bit cell 100 uses 12 transistors per bit compared to the 8 transistors of an 8T SRAM bit cell, but still uses less area in some manufacturing technologies due to the use of standard cell design rules. A significant difference between the latch-type bit cell and classical 6T / 8T SRAM bit cells is that the latch bit cell disables feedback during writes. In contrast, in 6T / 8T bit cells, the transmission gate must fight the pull-up to perform a write. The latch bit cell does not have such contention during writes.

[0026] Implemented using standard cell design rules Figure 1 The method means that the overhead required for using a custom SRAM macro disappears, thus reducing the area. For example, using standard cell layout rules allows for 0-contact poly pitch (CPP) (the distance between transistors in the horizontal direction) adjacent to standard cell logic. More traditional SRAM methods have boundary cells and edge cells required for lithography purposes. Since standard cell design rules scale well, implementing an SRAM cell based on the latch bit cell 100 and standard cell design rules allows the SRAM design to scale in area similarly to standard architectures in the future.

[0027] Figure 1 The latch bit cells shown in FIG. spread the local inverter that would normally be present in a latch over more cells. Figure 1The latch bit cell shown removes the local inverters that are conventionally used on the inputs to the latch, which inputs include the write bit line (WBL), write word line (WWL), active low write word line (WWLX), read word line (RWL), and active low read word line (RWLX). In more conventional latch arrays, CMOS combinational stages are used between the latches. The latch bit cell 100 uses a tri-state output for the RBL 101. The use of a tri-state driver in the latch bit cell allows the outputs (read bit lines) of several cells (e.g., 16) to be combined together using a tri-state output driver to avoid any additional combinational stages for the output data (such as NOR / NANDing).

[0028] Figure 2 A bar layout of the latch bit cell 100 showing 7 transistors in the horizontal direction is shown. The boxes show the source / drain connections of the transistors. The gate regions of the transistors are shown as vertical lines, with the same markings as the Figure 1 transistors in. The long vertical line 201 indicates a shared gate connection, e.g., through the transistors PFBO and NFBO and the transistors PINV and NINV. In the case where there are blanks in the boxes, there are Figure 1 unnamed nodes in, but any unrecognized source / drain connections as well as gate connections can be easily seen in Figure 1 . This layout includes dummy cell (DUM) transistors. Dummy transistors are transistors that are formed but not connected. The use of dummy transistors provides an effective way to provide isolation between other transistors. The use of dummy transistors also provides the advantage of being able to vary the type of transistors used in terms of the threshold voltage (Vt). In an embodiment, the write part (transistors PPG, NPG, PINV, NINV, NFB1, NFB0, PFB0, and PFB1) of the latch does not require high performance, but the read part (transistors PRP1, PRP0, NRP0, and NRP1) of the latch requires high performance. Note that the first letter of the transistor name refers to the type of transistor (N or P), and the remaining letters refer to its function (PG: transmission gate, INV: inverter, FB: feedback, RP: read port)

[0029] Referring to Figure 3 , which allows the use of lower Vt (such as ultra-low Vt (ulvt)) transistors to implement the read part 301 of the latch bit cell 100 including the transistors PRP0, PRP1, NRP0, and NRP1, thus providing the required high performance, while implementing with higher threshold voltage transistors (such as low Vt (lvt) transistors) Figure 3The write section 303 of the latch bit cell 100 on the left side of the virtual transistor in []. The higher Vt transistors provide lower performance but also cause less leakage, and the lower Vt transistors are utilized only when performance is required. Thus, the layout option allows different threshold voltages to be utilized on the read and write ports with different performance requirements, allowing the leakage current to be reduced compared to having to use the lower Vt devices in all devices to meet the performance requirements of only a portion of the bit cell. The transistors in the read and write ports share the diffusion between adjacent cells, where the xtor (transistor) load may be halved compared to an unoptimized design.

[0030] Referring back to Figure 1 , the operation of the latch bit cell 100 will now be described. The data of the cell to be written to the write bit line WBL 102 (also referred to herein as write data (WD)) is supplied to the transmission gate 103 formed by transistors NPG and PPG. The gates of those transistors are coupled to the write word line (WWL) and the write word line X (WWLX), where "X" indicates that the signal is active low. When WWL and WWLX are asserted, the data on the WBL is passed as data "D" into the inverter 104 formed by transistors PINV and NINV. When WWL and WWLX are asserted, transistors NFB1 and PFB1 are turned off. The gates of NFB0 and PFB0 in the feedback section of the bit latch cell 100 receive the output D_X (the inverted value of "D") from the inverter. The gates of PRP1 and NRP1 in the read section 106 of the latch also receive D_X. When WWL and WWLX are de-asserted, the transmission gate 103 is turned off and transistors NFB1 and PFB1 are turned on, allowing D_X to turn on one of transistors NFB0 or PFB0 to supply "D" as a feedback signal. Transistors NFB1, NFB0, PFB0, and PFB1 act as a holding circuit 108 and, together with the inverter formed by transistors PINV and NINV, ensure that the data on node D is maintained when WWL and WWLX are de-asserted. In this way, the value of D is maintained in the write section of the latch bit cell 100 and is available when the latch is read. In the latch bit cell 100, the PMOS transistors PINV, PFB1, and PRP1 are coupled to the supply voltage (VDD) at their sources. The NMOS transistors NINV, NFB1, and NRP1 are coupled to the second supply voltage (ground) at their sources.

[0031] To read the latch bit cell, the read word line (RWL) and RWLX assertion respectively turn on NRP0 and PRP0. Remember, "X" indicates an active low signal. The assertion of RWL and RWLX allows the value of D_X to determine the value of the output signal read bit line (RBL) 101, which is also referred to herein as read data (RD). When RWL and RWLX are de-asserted, RBL is set to high impedance to allow other SRAM cells to drive RBL when other SRAM cells are selected for reading.

[0032] Figure 4 An embodiment is shown in which a group of 32 latch bit cells are formed in two groups of latch bit cells (bits <31:16> and bits <15:0>). Each group of latch bit cells supplies bits to a multiplexer 401, which selects a bit from bits <31:16> or selects a bit from bits <15:0> and supplies the selected bit on rdData 403. In Figure 4 the embodiment, the tri-state drivers on the read side of the latch bit cells allow 16 bits (only one bit active at a time) to drive the same RBL supplied to the multiplexer 401. Thus, only one RWL / RWLX is turned on at a time in each group [31:16] and [15:0] to ensure that multiple latch bit cells do not drive RBL simultaneously, which would otherwise cause a high current situation. It is also important to ensure that one of the RWL / RWLX signals is active, such that one of the bit cells in the bit cell drives a high or low logic level onto RBL. De-asserting all RWL / RWLX pairs will result in a floating node on RBL, which can cause high current draw in downstream CMOS gates that receive an intermediate signal between VDD and VSS.

[0033] Figure 5 A block diagram of an embodiment is shown having 64 rows of bit cells and two columns, and multiplexer 501 selects one bit from 64 rows and two columns. Although not shown in Figure 5 for ease of illustration, Figure 5 the embodiment shown in

[0034] also requires a write column multiplexer function. One way to achieve this is to supply a WWL / WWLX pair to the even physical columns and supply another WWL / WWLX pair to the odd physical columns. In this way, every other cell can be written. Another way to implement the write multiplexer function is to use a write mask as further described herein. Figure 6In another embodiment shown, the latch bit cell 600 includes a write mask. The write mask utilizes signals Write One X (WRONEX) and Write Zero (WRZERO), where "X" indicates that the signal is active low. The write mask circuit is formed by transistors PWD 601 and NWD 603, where WD represents write data. When WRONEX is asserted (active low), the write data (WD) node is pulled high by transistor PWD, and when WRZERO is asserted, the WD node is pulled low by transistor NWD. The write mask allows the write word line for a row of cells to be asserted without changing the state in all cells in the unit. For example, by asserting the word line and using the write mask, it can be ensured that only those cells of interest are written, thereby changing only one byte or a few bits on the word line. In addition to transistors PWD and NWD for determining the value of WD, the write-masked latch bit cell 600 also includes transistors NFB2 and PFB2 used in the keeper circuit 605. Those transistors are used to ensure that the feedback function of the keeper circuit continues to work, so that the latch bit cell maintains its state even when WWL and WWLX are asserted. If WWLX is asserted, NFB1 is turned off, and if WWL is asserted, PFB1 is turned off. Transistors NFB2 and PFB2 ensure that if the bit has a write mask that actually blocks the writing of the latch bit cell, then when WWL and WWLX are asserted, the keeper circuit keeps driving "D" with the correct value from the node between NFB0 and PFB0. Note that when WRONEX and WRZERO are de-asserted, WD will float. By incorporating the PWD and NWD transistors into the bit cell itself, the capacitance on the intermediate node WD is kept low enough to avoid cell stability issues when WWL / WWLX is asserted. In Figure 6 the keeper stack (KSTK) nodes PKSTK 602 and NKSTK 604 are marked.

[0035] Figure 7 is shown Figure 6 a simplified diagram of the layout of the write-masked latch bit cell 600 shown. Note that compared to Figure 2 the layout shown, Figure 6 the solution increases the size of the cell by four transistors and includes additional dummy cells. Thus, compared to Figure 1 the layout of the latch bit cell 100 shown Figure 2 (7CPP), the write-masked latch bit cell 600 ( Figure 6 ) shows an increase from 3CPP to 10CPP.

[0036] Figure 8 is shown compared to Figure 6A more efficient implementation of the write-masked latch bit cell 800 as compared to the write-masked latch bit cell 600. Note that the additional transistors NFB2 and PFB2 coupled to the keeper stack nodes in the write-masked latch bit cell 600 replace NFB1 and PFB1 in the write-masked latch bit cell 800. When WWL and WWLX are asserted (see Figure 1 and Figure 6 ), the write-masked latch bit cell 800 does not disable the keeper circuit 805 by turning off NFB1 and PFB1. Instead, the write-masked latch bit cell 800 disables the keeper only in response to WRONEX or WRZERO being asserted. This ensures that the latch bit cell 800 maintains its state when the latch bit cell 800 is masked. Note that WWL and WWLX are coupled only to the transmission gate transistors PPG and NPG in the write-masked latch bit cell 800. When WRONEX is asserted (active low), the transistor NFB2 turns off, and when WRZERO is asserted, the transistor PFB2 turns off. Assuming WWLX and WWL are asserted, when WRONEX is asserted, the node WD goes high and the node D goes high, and when WRZERO is asserted (active low), the node WD goes low and the node D goes low. When the respective mask lines (WRONEX and WRZERO) are de-asserted, both NFB2 and PFB2 turn on and the keeper circuit maintains the value of the node D according to the value of D_X provided by the inverter formed by the transistors PINV and NINV. D_X turns on the transistor NFB0 to maintain a low value of the node D or turns on PFB0 to maintain a high value of the node D. The write mask circuit is formed by the transistors PWD 801 and NWD 803 and is similar to the Figure 6 shown implementation. The read side of the write-masked latch bit cell 800 formed by the transistors PRP1, PRP0, NRP0, and NRP1 is the same as that in the previous latch bit cell implementations 100 and 600 shown in Figure 1 and Figure 6 .

[0037] Whenever WRONEX or WRZERO is asserted, each bit cell in the columns coupled to WRONEX and WRZERO disables its keeper circuit because asserting WRONEX turns off NFB2, preventing D_X from being pulled to VSS through NFB0 and NFB2, and asserting WRZERO turns off PFB2, preventing D_X from being pulled to BDD through PFB0 and PBF2. Thus, node D will float in response to the assertion of WRONEX or WRZERO. If the assertion of WRONEX or WRZERO is long enough, the cells along the column can change state because at least a portion of the keeper circuit is disconnected due to the assertion of WRONEX or WRZERO disabling NFB1 or PFB1. Therefore, WRONEX and WRZERO should be asserted as pulsed writes. Thus, those signals should be asserted as self-timed pulses that are several inverter delays long (e.g., 50 ps). For example, 9 inverters can be used to generate the pulses. The number of inverters depends on the technology used. Figure 9 An embodiment is shown where pulse circuit 901 is for WRZERO and pulse circuit 903 is for WRONEX. Note that Figure 9 an odd number of inverters are used in each of the pulse circuits of the pulse circuits shown. In Figure 9 , it is assumed that the inputs (write zero and write one) to the logic gates are active high. Many other pulse generator circuits that provide suitable pulse widths for WRONEX and WRZERO are known to those skilled in the art. The pulse should be long enough to write one cell but short enough so that other cells along the column do not lose their state due to node D floating during the pulse, and thus there is a relatively small area penalty for the additional write mask capability compared to the Figure 6 written-mask latch bit cell shown.

[0038] Figure 10 An example layout of the Figure 8 circuit is shown. Note that the latch bit cell 800 requires only one dummy transistor. Figure 10 The layout of the latch bit cell 800 shown has only one additional CPP compared to the Figure 2 baseline latch bit cell 100 shown.

[0039] Figure 11 An example is shown of Figure 1The latch array columns of the latch shown. Note that the term "single standard cell row" refers to the physical row of an integrated circuit rather than the logical row of an SRAM. In a standard design with non-mixed standard cell library rules, all devices typically have the same number of fins. In a traditional standard cell architecture, the devices in all rows have the same height. In the field of fin field effect transistors, this generally also means that each finger has the same number of fins. Figure 12A A traditional standard cell architecture of PFETs and NFETs is shown where each finger has 2 fins. Each standard cell is uniform in a row and has P and N transistors.

[0040] A hybrid standard cell architecture utilizes alternating high-performance standard cell rows and high-density (but lower performance) standard cell rows. For example, in one embodiment, this means that each transistor finger of the high-performance cell has two fins, and each transistor finger of the lower performance cell has one fin. As Figure 12B shown, this results in alternating higher and shorter cell rows and shorter rows. The advantage of the hybrid standard cell architecture is smaller area and reduced power, but the shorter cell height results in reduced performance compared to the larger two-fin cells. Figure 12C An exemplary device with one fin per transistor finger 1201 and two fins per transistor finger 1203 is shown.

[0041] Figure 13 Shifting from a traditional standard cell library to a hybrid standard cell library approach to build a standard cell latch array can result in unbalanced performance between adjacent bits. For example, the bit cells in column 1301 are formed from "fast" standard cells, e.g., each finger has two fins. In the illustrated embodiment, the logical SRAM column 1301 is in the physical fast row of the hybrid row architecture. The bit cells in column 1303 are "slow" cells, e.g., each finger has one fin. Thus, reading Rddata[1] 1302 from one of the bit cells in column 1301 occurs faster than reading Rddata[0] 1304 from column 1302. Thus, adjacent bits are read at different timings (one fast and one slow), which is undesirable.

[0042] To provide more balanced performance between fast and slow cells, Figure 14The embodiments shown use a set of bit cells from one column, such as the bit cells in column 1401 (fast physical row) or 1403 (slow physical row), but use the multiplexer circuits from another row. For example, the slow multiplexer 1407 selects one bit from 32 fast bit cells. The 32 fast bit cells are fast bit cell 1404 (bits <15:0>, only one of which is shown) and fast bit cell 1406 (bits <31:16>, only one of which is shown). The fast multiplexer 1415 selects one bit from 32 slow bit cells. The 32 slow bit cells are slow bit cell 1409 (bits <15:0>, only one of which is shown) and slow bit cell 1411 (bits <31:16>, only one of which is shown). Similarly, fast bit cells 1421 and 1423 use slow multiplexer 1425, while slow bit cells 1427 and 1429 use fast multiplexer 1431. The read data (Rddata[1]) supplied by the fast multiplexer 1435 has a fast multiplexer (2 fins) but has slow bit cells (1 fin), and the read data (Rddata[0]) has a slow multiplexer (1 fin) but has fast bit cells (2 fins). Thus, one logical SRAM column has fast bit cells and slow multiplexer stages, while the adjacent SRAM logical column has slow bit cells and fast multiplexer stages. This provides an improved performance balance compared to an array where every other bit has significantly different timings: fast and slow.

[0043] Figure 15 A high-level block diagram of the bit cell array is shown. Although Figure 14 is shown Figure 1 The latch bit cells are used as the bit cells in columns 1401 and 1403, but in other embodiments, other bit cells may be used. Figure 16 is shown where Figure 6 The masked write latch bit cell 600 or Figure 8 The masked write latch bit cell 800 of Figure 16 is shown. The mask signals WRONEX and WRZERO signals assigned to the bit cells are shown.

[0044] Thus, the masked write SRAM bit cells have been described. The description of the present invention set forth herein is illustrative and is not intended to limit the scope of the present invention set forth in the following claims. Variations and modifications may be made to the embodiments disclosed herein based on the description set forth herein without departing from the scope of the present invention set forth in the following claims.

Claims

1. A device, comprising: A write-masked latch bit cell, the write-masked latch bit cell including a write portion of the write-masked latch bit cell, the write portion including, A write mask circuit that causes a value of a write data node of the write portion to be a first value in response to an assertion of a first write mask signal and causes the value of the write data node to have a second value in response to an assertion of a second write mask signal; A transmission gate coupled to the write data node, the transmission gate supplying the value of the write data node to a first node of the write portion in response to a write word line signal being asserted; And A keeper circuit configured to maintain a value of data on the first node independent of a value of the write word line signal when the first write mask signal and the second write mask signal are de-asserted.

2. The device according to claim 1, wherein the write data node floats in response to the first write mask signal and the second write mask signal being de-asserted.

3. The device according to claim 2, wherein the write mask circuit further includes: A first write data transistor coupled between a first power source node and the write data node, the first write data transistor having a gate coupled to the first write mask signal; And A second write data transistor coupled between the write data node and a second power source node, the second write data transistor having a gate coupled to the second write mask signal.

4. The device according to claim 3, further comprising: An inverter coupled to the first node to supply inverted data; And wherein the keeper circuit further includes: A keeper stack including a first keeper transistor, a second keeper transistor, a third keeper transistor, and a fourth keeper transistor; wherein the first keeper transistor has a first gate coupled to the first write mask signal, and the first keeper transistor has a first current-carrying terminal coupled between the second power source node and the second keeper transistor; wherein the second keeper transistor has a second gate coupled to the inverted data, and the second keeper transistor has a second current-carrying terminal coupled between the first keeper transistor and the first node; wherein the third keeper transistor has a third gate coupled to the inverted data, and the third keeper transistor has a third current-carrying terminal coupled between the first node and the fourth keeper transistor; and wherein the fourth keeper transistor has a fourth gate coupled to the second write mask signal, and the fourth keeper transistor has a fourth current-carrying terminal coupled between the third keeper transistor and the first power source node.

5. The device according to claim 3, further comprising: An inverter coupled to the first node to supply inverted data; And The keeper circuit further includes: A keeper stack including a first keeper transistor, a second keeper transistor, a third keeper transistor, and a fourth keeper transistor; Wherein the first keeper transistor has a first gate coupled to an active low write word line signal, and the first keeper transistor has a first current carrying terminal coupled between the second power source node and the second keeper transistor; Wherein the second keeper transistor has a second gate coupled to the inverted data, and the second keeper transistor has a second current carrying terminal coupled between the first keeper transistor and the first node; Wherein the third keeper transistor has a third gate coupled to the inverted data, and the third keeper transistor has a third current carrying terminal coupled between the first node and the fourth keeper transistor; Wherein the fourth keeper transistor has a fourth gate coupled to a second write word line signal, and the fourth keeper transistor has a fourth current carrying terminal coupled between the third keeper transistor and the first power source node; and Wherein the write word line signal includes the second write word line signal and the active low write word line signal.

6. The apparatus according to claim 5, wherein the keeper circuit further includes: A fifth keeper transistor coupled between the second power source node and a first keeper node located between the first keeper transistor and the second keeper transistor, the fifth keeper transistor having a fifth gate coupled to the first write mask signal; and A sixth keeper transistor coupled between the first power source node and a second keeper node located between the third keeper transistor and the fourth keeper transistor, the sixth keeper transistor having a sixth gate coupled to the second write mask signal.

7. The apparatus according to claim 1, further comprising: A first pulse generator for generating the first write mask signal; and A second pulse generator for generating the second write mask signal.

8. The apparatus according to claim 1, further comprising: A read portion of the write masked latch bit cell, the read portion of the write masked latch bit cell being coupled to receive a read word line signal and supplying output data at an output node of the read portion of the write masked latch bit cell in response to an assertion of the read word line signal, the output data corresponding to the data at the first node.

9. The apparatus according to claim 8, wherein the read portion of the write masked latch bit cell is configured to cause the output node to be high impedance in response to the read word line signal being deasserted.

10. A method, comprising: Setting a write data node in a write masked latch bit cell to a first value in response to an assertion of a first write mask signal; Setting the write data node to a second value in response to an assertion of a second write mask signal; Coupling the write data node to a first node in response to a write word line signal being asserted; and When the first write mask signal and the second write mask signal are de-asserted, maintaining the value of the data on the first node independently of the value of the write word line signal using a keeper circuit.

11. The method according to claim 10, further comprising: Causing the write data node to float in response to the first write mask signal and the second write mask signal being de-asserted.

12. The method according to claim 10, further comprising: Supplying the first write mask signal to a gate of a first write data transistor; In response to the assertion of the first write mask signal, setting the write data node to the first value by coupling a first power source node to the first node via the first write data transistor; Supplying the second write mask signal to a gate of a second write data transistor; And In response to the assertion of the second write mask signal, setting the write data node to the second value by coupling a second power source node to the first node via the second write data transistor.

13. The method according to claim 10, further comprising: Inverting the data on the first node and supplying the inverted data to the keeper circuit; Enabling the keeper circuit in response to the first write mask signal and the second write mask signal being de-asserted; And Disabling the keeper circuit in response to the first write mask signal and the second write mask signal being asserted.

14. The method according to claim 13, further comprising: Supplying the first write mask signal to a first gate of a first keeper transistor and enabling the first keeper transistor in response to the first write mask signal being de-asserted; Supplying the inverted data to a second gate of a second keeper transistor; Supplying the inverted data to a third gate of a third keeper transistor; And Supplying the second write mask signal to a fourth gate of a fourth keeper transistor and enabling the fourth keeper transistor in response to the second write mask signal being de-asserted.

15. The method according to claim 13, further comprising: Supplying an active-low write word line signal to a first gate of a first keeper transistor; Supplying the inverted data to a second gate of a second keeper transistor; Supplying the inverted data to a third gate of a third keeper transistor; Supplying a second write word line signal to a fourth gate of a fourth keeper transistor, the write word line signal including the second write word line signal and the active-low write word line signal; Supplying the first write mask signal to a first gate of a fifth keeper transistor and enabling the fifth keeper transistor in response to the first write mask signal being de-asserted; And Supply the second write mask signal to a sixth gate of a sixth keeper transistor and enable the sixth keeper transistor in response to de-assertion of the second write mask signal.

16. The method according to claim 10, further comprising: Generating the first write mask signal as a first pulse; And Generating the second write mask signal as a second pulse.

17. The method according to claim 16, Wherein the first pulse is short enough to keep the data on the first node unchanged in state when the first pulse write mask signal is asserted and the write word line signal is not asserted.

18. The method according to claim 16, Wherein the second pulse is short enough to keep the data on the first node unchanged in state when the first pulse write mask signal is asserted and the write word line signal is not asserted.

19. The method according to claim 10, further comprising: Supplying output data on an output node of a read portion of the write-masked latch bit cell in response to assertion of a read word line signal; And Causing the output node to be in a high impedance state in response to de-assertion of the read word line signal.

20. A method, comprising: Writing to a write-masked latch bit cell in response to assertion of a write word line (WWL) signal and an active low write word line (WWLX) signal in combination with assertion of either a first write mask signal or a second write mask signal; And Maintaining a state of the write-masked latch bit cell when the write word line signal and the active low write word line signal are asserted and the first write mask signal and the second write mask signal are de-asserted.

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