A multi-display working method

Abstract

The application provides a multi-screen working method, comprising the following steps: S1, starting the multi-screen; S2, after starting the multi-screen, displaying vehicle information or / and entertainment information on the multi-screen. The application can guarantee the safe driving of the driver, avoid using the instrument screen in the multi-screen as an entertainment screen during driving, and cause driving influence.

Description

Technical Field

[0001] This invention relates to the field of automotive technology, and in particular to a method for operating multi-screen displays. Background Technology

[0002] As people's living standards improve, more and more people are placing greater emphasis on the entertainment features of cars. The central control screen, in particular, needs to display the car's current status, such as speed, coolant temperature, RPM, and fuel level, while also meeting people's entertainment needs, such as watching videos and listening to music. Therefore, multi-screen displays have emerged on the market. However, displaying entertainment information on the instrument panel while driving could potentially lead to accidents. Summary of the Invention

[0003] This invention aims to at least solve the technical problems existing in the prior art, and in particular, it innovatively proposes a multi-screen working method.

[0004] To achieve the above-mentioned objectives of the present invention, the present invention provides a multi-screen working method, comprising the following steps:

[0005] S1, multi-screen startup;

[0006] S2, after the multi-screen system is activated, displays vehicle information and / or entertainment information on the multi-screen system.

[0007] In a preferred embodiment of the present invention, the vehicle information includes one or any combination of vehicle speed, engine speed, engine coolant temperature, vehicle interior and exterior temperature, lighting status, and remaining fuel level, and the lighting status includes one or any combination of high beam headlights, low beam headlights, and turn signals.

[0008] In a preferred embodiment of the present invention, step S1 includes activating one or any combination of a first liquid crystal display screen, a second liquid crystal display screen, and a third liquid crystal display screen.

[0009] In a preferred embodiment of the present invention, step S2 further includes the following step:

[0010] S21, The vehicle controller determines whether it has received an entertainment information playback trigger signal:

[0011] If the vehicle controller receives an entertainment information playback trigger signal, proceed to the next step;

[0012] If the vehicle controller does not receive an entertainment information playback trigger signal, proceed to step S21;

[0013] S22, displaying entertainment information on the first LCD screen and / or the third LCD screen.

[0014] In a preferred embodiment of the present invention, step S22 includes the following steps before displaying entertainment information on the first liquid crystal display screen or / and the third liquid crystal display screen:

[0015] S221, The vehicle controller determines whether the entertainment information playback trigger signal is triggered by the first LCD screen or the third LCD screen:

[0016] If the entertainment information playback trigger signal is triggered by the first LCD screen, proceed to the next step;

[0017] If the entertainment information playback trigger signal is triggered by the third LCD screen, then step S225 is executed;

[0018] S222, the on-board controller determines the vehicle status:

[0019] If the vehicle is in motion, proceed to the next step;

[0020] If the vehicle is in a parked state, proceed to step S224;

[0021] S223, the vehicle controller determines whether there is someone sitting in the passenger seat:

[0022] If there is someone in the passenger seat, entertainment information will be displayed on the third LCD screen; this entertainment information may be movies, TV series, or anime.

[0023] If there is no one in the passenger seat, a prompt will be issued asking you to park the vehicle and watch entertainment information.

[0024] S224, the vehicle controller determines whether there is someone sitting in the passenger seat:

[0025] If there is someone in the front passenger seat, entertainment information will be displayed simultaneously on the first and third LCD screens;

[0026] If there is no one in the passenger seat, entertainment information will be displayed on the first LCD screen;

[0027] S225, the on-board controller determines the vehicle status:

[0028] If the vehicle is in motion, entertainment information will be displayed on the third LCD screen;

[0029] If the vehicle is parked, proceed to the next step;

[0030] S226, The vehicle controller determines whether someone is sitting in the driver's seat:

[0031] If there is someone in the driver's seat, entertainment information will be displayed simultaneously on the first LCD screen and the third LCD screen;

[0032] If no one is in the driver's seat, entertainment information will be displayed on the third LCD screen.

[0033] In a preferred embodiment of the present invention, step S223 or / and S225 further includes: in order to ensure safer driving for the driver, when entertainment information is displayed on the third LCD screen, audio information of the entertainment information is received through Bluetooth headphones.

[0034] In a preferred embodiment of the present invention, the method for calculating the first level signal in step S11 is as follows:

[0035]

[0036] Wherein, P1 represents the voltage value of the wake-up terminal PTD5 of the input controller U6, which is the first level signal;

[0037] This indicates the cutoff voltage of transistor Q1;

[0038] This indicates the preset voltage first adjustment threshold.

[0039] The calculation method for the second level signal in step S11 is as follows:

[0040]

[0041] Wherein, P2 represents the voltage value of the wake-up terminal PTD5 of the input controller U6, which is the second level signal;

[0042] V +3.3V_MCU This indicates the voltage of the +3.3V power supply to the MCU.

[0043] This indicates the preset voltage first adjustment threshold.

[0044]

[0045] In a preferred embodiment of the present invention, the multi-screen includes a multi-screen body, and a PCB board with the same number of liquid crystal displays is disposed in the multi-screen body. Each PCB board is provided with a power module, a wake-up module, a voltage sampling module, a CAN communication module, a controller module, a deserializer module and a screen backlight module.

[0046] The power module is connected to one or any combination of the wake-up module, voltage sampling module, CAN communication module, controller module, deserializer module and screen backlight module, respectively, to provide appropriate power or voltage signals to one or any combination of the wake-up module, voltage sampling module, CAN communication module, controller module, deserializer module and screen backlight module.

[0047] The controller module is connected to one or any combination of the wake-up module, voltage sampling module, CAN communication module, and deserializer module;

[0048] The controller module enables signal acquisition and control of one or any combination of the wake-up module, voltage sampling module, CAN communication module, deserializer module, and screen backlight module.

[0049] In a preferred embodiment of the present invention, the power supply module includes one or any combination of a first voltage conversion module, a second voltage conversion module, a third voltage conversion module, a fourth voltage conversion module, a fifth voltage conversion module, a sixth voltage conversion module, a seventh voltage conversion module, an eighth voltage conversion module, a ninth voltage conversion module, a tenth voltage conversion module, an eleventh voltage conversion module, a twelfth voltage conversion module, a thirteenth voltage conversion module, and a fourteenth voltage conversion module;

[0050] The power input terminal of the first voltage conversion module is connected to the power output terminal of interface J3. The power output terminal of the first voltage conversion module is connected to the power input terminals of the second and twelfth voltage conversion modules respectively. The power output terminal of the second voltage conversion module is connected to the power input terminals of the third and fourth voltage conversion modules respectively. The power output terminal of the fourth voltage conversion module is connected to the power input terminals of the fifth, sixth, seventh, and eighth voltage conversion modules respectively. The power output terminal of the fifth voltage conversion module is connected to the power input terminal of the ninth voltage conversion module. The power output terminal of the sixth voltage conversion module is connected to the power input terminals of the tenth and eleventh voltage conversion modules respectively. The power output terminal of the twelfth voltage conversion module is connected to the power input terminals of the thirteenth and fourteenth voltage conversion modules respectively.

[0051] In a preferred embodiment of the present invention, the multi-screen body includes a housing, on which a plurality of liquid crystal displays are horizontally spaced. The housing extends to the left and right and both ends are curved forward to form an arc shape. Separating decorative parts are provided between adjacent liquid crystal displays and near both ends of the housing. The housing includes a bracket and a glass cover plate located on the front side of the bracket, and the glass cover plate covers all the liquid crystal displays and the separating decorative parts. Decorative patterns are provided on the glass cover plate corresponding to the separating decorative parts. A decorative backlight module is installed on the bracket corresponding to each decorative pattern. The bracket is provided with a through hole for exposing the decorative backlight module. The back of the bracket is provided with a rear shell that bulges backward in the middle. The rear shell is provided with a plurality of data interaction holes for connecting to the car host for each liquid crystal display and decorative backlight module.

[0052] In a preferred embodiment of the present invention, the bracket is offset backward at the part corresponding to the liquid crystal display screen to form a mounting groove for mounting the liquid crystal display screen. A PCB board is mounted on the back of the mounting groove, and the mounting groove is provided with wiring holes for data transmission between the liquid crystal display screen and the PCB board.

[0053] The bracket has a rearwardly extending positioning pin on its back, and the rear shell has a positioning hole corresponding to the positioning pin for it to pass through. The rear shell is installed on the bracket by bolts. This allows the rear shell to be pre-positioned using the positioning pin and positioning hole before being fixed with bolts, improving installation efficiency.

[0054] In a preferred embodiment of the present invention, the upper part of the back of the bracket is provided with a row of multiple rearwardly extending fixing lugs symmetrically arranged along the vertical center line, and the rear shell is provided with a clearance hole for each fixing lug to extend out, and the fixing lugs are fixed to the car body by bolts.

[0055] The lower back of the bracket also features a row of bracket fixing claws for securing it to the vehicle body. The rear housing also has corresponding clearance holes for each bracket fixing claw to extend from it. The provided locking lugs allow the bracket to be fixed to the vehicle body, while the bracket fixing claws allow the bracket to be directly secured to the vehicle body. The use of two different fixing methods improves stability and ensures the support stability of the bracket.

[0056] Multiple fixing lugs are evenly distributed on the rear side of each LCD screen, with the fixing lugs on the rear side of the central LCD screen having greater length and support strength than the other fixing lugs; each LCD screen has a bracket fixing claw on its rear side. Because the central section requires higher support strength, reinforcing the fixing lugs in the central section improves support stability.

[0057] In a preferred embodiment of the present invention, the rear shell has a row of symmetrically arranged holes along the vertical center line near its top for inserting clips from the vehicle body. The holes face upwards. The rear shell has end-mounting claws on both ends for fixing it to the vehicle body. This allows the rear shell to be fixed to the vehicle body, and the end-mounting claws secure both ends of the rear shell to the vehicle body, achieving two different fixing methods and improving stability.

[0058] In a preferred embodiment of the present invention, the rear shell end mounting claw is fixed directly behind the partition decorative parts located at both ends, and the insertion hole is positioned to avoid the liquid crystal display screen located in the middle.

[0059] In a preferred embodiment of the present invention, the bracket extends out of the rear shell on all four sides, and the back of the left and right ends of the bracket is provided with end connection components located outside the rear shell, the end connection components being used to connect to the vehicle body.

[0060] In a preferred embodiment of the present invention, the end connection assembly includes an upper connecting lug and a lower snap-fit ​​lug arranged at an interval, both extending rearward. The upper connecting lug is fixed to the vehicle body by bolts, and the lower snap-fit ​​lug has a positioning hole for a positioning pin of the vehicle body to be inserted. This allows the two ends of the bracket to be fixed to the vehicle body by bolts.

[0061] In a preferred embodiment of the present invention, the upper connecting lug is also provided with a positioning hole for the insertion of a positioning pin of the vehicle body. The upper connecting lug is vertically arranged, and a downwardly extending limiting notch is provided on the bottom side of the upper connecting lug. Positioning can be pre-established through the positioning hole of the upper connecting lug, and then connected by bolts. The limiting notch can stably hook onto the vehicle body, and is engaged by the clips on the vehicle body into the locking holes on the two locking lugs.

[0062] In a preferred embodiment of the present invention, the top two ends of the bracket are bent downward to form an irregular hexagon; the upper edge of the bracket is provided with upward protruding ribs for securing it to the vehicle body, thereby improving the stability of the multi-display assembly. The front side of the bracket, near the top, has a positioning rib for positioning the top edge of the glass cover, facilitating glass cover fixing and improving installation efficiency.

[0063] The front of the bracket is tilted upwards to face the human body, which is a reasonable design. The left and right ends of the bracket are tilted backwards, flush with the outer contour of the car dashboard.

[0064] In a preferred embodiment of the present invention, both the PCB board and the decorative backlight module are fixed to the bracket with bolts for easy installation and fixation. The partition decorative portions located at both ends of the housing are larger than the other partition decorative portions, and the liquid crystal display screens are all larger than the partition decorative portions.

[0065] In summary, by adopting the above technical solution, the present invention can ensure the driver's safe driving and prevent the instrument panel in the multi-screen setup from being used as an entertainment screen during driving, thus avoiding any impact on driving.

[0066] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0067] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0068] Figure 1 This is a schematic block diagram illustrating the connection of the present invention.

[0069] Figure 2 This is a schematic block diagram of the power module circuit connection of the present invention.

[0070] Figure 3 This is a schematic diagram of the circuit connection of the wake-up module of the present invention.

[0071] Figure 4 This is a schematic diagram of the circuit connection of the voltage sampling module of the present invention.

[0072] Figure 5 This is a schematic diagram of the circuit connection of the voltage sampling module of the present invention.

[0073] Figure 6 This is a schematic diagram of the circuit connection of the CAN communication module of the present invention.

[0074] Figure 7 This is a schematic diagram of the circuit connection of the deserializer module of the present invention.

[0075] Figure 8 This is a schematic diagram of the circuit connection of the deserializer module of the present invention.

[0076] Figure 9 This is a schematic diagram of the circuit connection of the deserializer module of the present invention.

[0077] Figure 10 This is a schematic diagram of the circuit connection of the J2 module of the TFT screen interface of the present invention.

[0078] Figure 11 This is a schematic diagram of the circuit connection of the controller module of the present invention.

[0079] Figure 12 This is a schematic diagram of the circuit connection of the controller module of the present invention.

[0080] Figure 13 This is a schematic diagram of the circuit connection of the controller module of the present invention.

[0081] Figure 14 This is a schematic diagram of the circuit connection of the screen backlight module of the present invention.

[0082] Figure 15 This is an exploded view of the present invention.

[0083] Figure 16 This is a front view of the present invention.

[0084] Figure 17 yes Figure 16 Enlarged diagram of point D in the middle.

[0085] Figure 18 yes Figure 16 The left view.

[0086] Figure 19 yes Figure 16 Rear view.

[0087] Figure 20 This is a front view of the bracket.

[0088] Figure 21 This is the rear view of the bracket.

[0089] Figure 22 This is a schematic diagram of the back of the bracket.

[0090] Figure 23 yes Figure 15 Enlarged diagram of point C in the middle.

[0091] Figure 24 This is a flowchart illustrating the process of this invention. Detailed Implementation

[0092] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0093] This invention provides a method for multi-screen operation, such as... Figure 24 As shown, it includes the following steps:

[0094] S1, multi-screen startup;

[0095] After the S2 multi-screen system is activated, vehicle information is displayed on the multi-screen display.

[0096] In a preferred embodiment of the present invention, the vehicle information includes one or any combination of vehicle speed, engine speed, engine coolant temperature, vehicle interior and exterior temperature, lighting status, and remaining fuel level. The lighting status includes one or any combination of high beam headlights, low beam headlights, and turn signals. This vehicle information is preferably displayed on the left LCD screen.

[0097] In a preferred embodiment of the present invention, step S1 includes activating one or any combination of a first liquid crystal display screen, a second liquid crystal display screen, and a third liquid crystal display screen.

[0098] In a preferred embodiment of the present invention, step S2 further includes the following step:

[0099] S21, The vehicle controller determines whether it has received an entertainment information playback trigger signal:

[0100] If the vehicle controller receives an entertainment information playback trigger signal, proceed to the next step;

[0101] If the vehicle controller does not receive an entertainment information playback trigger signal, proceed to step S21;

[0102] S22, displaying entertainment information on the first LCD screen and / or the third LCD screen.

[0103] In a preferred embodiment of the present invention, step S22 includes the following steps before displaying entertainment information on the first liquid crystal display screen or / and the third liquid crystal display screen:

[0104] S221, The vehicle controller determines whether the entertainment information playback trigger signal is triggered by the first LCD screen or the third LCD screen:

[0105] If the entertainment information playback trigger signal is triggered by the first LCD screen, proceed to the next step;

[0106] If the entertainment information playback trigger signal is triggered by the third LCD screen, then step S225 is executed;

[0107] S222, the on-board controller determines the vehicle status:

[0108] If the vehicle is in motion, proceed to the next step;

[0109] If the vehicle is in a parked state, proceed to step S224;

[0110] S223, the vehicle controller determines whether there is someone sitting in the passenger seat:

[0111] If there is someone in the passenger seat, entertainment information will be displayed on the third LCD screen; this entertainment information may be movies, TV series, or anime.

[0112] If there is no one in the passenger seat, a prompt will be issued asking you to park the vehicle and watch entertainment information.

[0113] S224, the vehicle controller determines whether there is someone sitting in the passenger seat:

[0114] If there is someone in the front passenger seat, entertainment information will be displayed simultaneously on the first and third LCD screens;

[0115] If there is no one in the passenger seat, entertainment information will be displayed on the first LCD screen;

[0116] S225, the on-board controller determines the vehicle status:

[0117] If the vehicle is in motion, entertainment information will be displayed on the third LCD screen;

[0118] If the vehicle is parked, proceed to the next step;

[0119] S226, The vehicle controller determines whether someone is sitting in the driver's seat:

[0120] If there is someone in the driver's seat, entertainment information will be displayed simultaneously on the first LCD screen and the third LCD screen;

[0121] If no one is in the driver's seat, entertainment information will be displayed on the third LCD screen. This operation helps prevent interference with the driver's driving, allows for easy viewing of vehicle information on the left LCD screen, and enables timely action.

[0122] In a preferred embodiment of the present invention, step S223 or / and S225 further includes: in order to ensure safer driving for the driver, when entertainment information is displayed on the third LCD screen, audio information of the entertainment information is received through Bluetooth headphones.

[0123] In a preferred embodiment of the present invention, the method for activating the first liquid crystal display screen includes the following steps:

[0124] S11, the controller U6 on the first PCB board determines whether the wake-up terminal PTD5 of the controller U6 on the first PCB board receives a first level signal or a second level signal:

[0125] If the wake-up terminal PTD5 of the controller U6 on the first PCB board receives the first level signal, the controller U6 on the first PCB board will wake up; proceed to the next step.

[0126] If the wake-up terminal PTD5 of the controller U6 on the first PCB board receives the second level signal, the controller U6 on the first PCB board will be in sleep mode, and the process will return to step S11.

[0127] S12, the control terminal PTD16 of the controller U6 on the first PCB board inputs an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the first PCB board; at this time, the power supply +VBATT input to the DC-DC buck converter U2 on the first PCB board is converted into a stable power supply +3.3VSW through the DC-DC buck converter U2 on the first PCB board for output; proceed to the next step;

[0128] S13, the control terminal PTC15 of the controller U6 on the first PCB board inputs a conduction level to the base of the transistor Q4 on the first PCB board, and the transistor Q4 on the first PCB board is in the conducting state. At this time, the gate voltage of the field-effect transistor Q5 on the first PCB board is pulled low, and the field-effect transistor Q5 on the first PCB board is in the conducting state. The power supply +3.3VSW on the source of the field-effect transistor Q5 on the first PCB board is output as power supply +3.3V_TFT through the drain of the field-effect transistor Q5 on the first PCB board.

[0129] S14, the controller U6 on the first PCB board sends the power-on screen to the first LCD screen through the deserialization chip U1 on the first PCB board, and displays the power-on screen on the first LCD screen;

[0130] S15, the control terminal PTD16 of the controller U6 on the first PCB board does not input an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the first PCB board; at this time, the DC-DC buck converter U2 on the first PCB board does not work, reducing energy consumption.

[0131] In a preferred embodiment of the present invention, the method for activating the second liquid crystal display screen includes the following steps:

[0132] S11, the controller U6 on the second PCB board determines whether the wake-up terminal PTD5 of the controller U6 on the second PCB board receives the first level signal or the second level signal:

[0133] If the wake-up terminal PTD5 of the controller U6 on the second PCB board receives the first level signal, the controller U6 on the second PCB board will wake up and proceed to the next step.

[0134] If the wake-up terminal PTD5 of the controller U6 on the second PCB board receives the second level signal, then the controller U6 on the second PCB board is in sleep mode, and the process returns to step S11.

[0135] S12, the control terminal PTD16 of the controller U6 on the second PCB board inputs an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the second PCB board; at this time, the power supply +VBATT input to the DC-DC buck converter U2 on the second PCB board is converted into a stable power supply +3.3VSW through the DC-DC buck converter U2 on the second PCB board for output; proceed to the next step;

[0136] S13, the control terminal PTC15 of the controller U6 on the second PCB board inputs a conduction level to the base of the transistor Q4 on the second PCB board, and the transistor Q4 on the second PCB board is in the conducting state. At this time, the gate voltage of the field-effect transistor Q5 on the second PCB board is pulled low, and the field-effect transistor Q5 on the second PCB board is in the conducting state. The power supply +3.3VSW on the source of the field-effect transistor Q5 on the second PCB board is output as +3.3V_TFT through the drain of the field-effect transistor Q5 on the second PCB board.

[0137] S14, the controller U6 on the second PCB board sends the power-on screen to the second LCD screen through the deserialization chip U1 on the second PCB board, and displays the power-on screen on the second LCD screen;

[0138] S15, the control terminal PTD16 of the controller U6 on the second PCB board does not input an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the second PCB board; at this time, the DC-DC buck converter U2 on the second PCB board does not work, reducing energy consumption;

[0139] The method for activating or / and a third LCD screen includes the following steps:

[0140] S11, the controller U6 on the third PCB board determines whether the wake-up terminal PTD5 of the controller U6 on the third PCB board receives the first level signal or the second level signal:

[0141] If the wake-up terminal PTD5 of the controller U6 on the third PCB board receives the first level signal, the controller U6 on the third PCB board will wake up and proceed to the next step.

[0142] If the wake-up terminal PTD5 of the controller U6 on the third PCB board receives the second level signal, the controller U6 on the third PCB board will enter sleep mode and return to step S11.

[0143] S12, the control terminal PTD16 of the controller U6 on the third PCB board inputs an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the third PCB board; at this time, the power supply +VBATT input to the DC-DC buck converter U2 on the third PCB board is converted into a stable power supply +3.3VSW through the DC-DC buck converter U2 on the third PCB board for output; proceed to the next step;

[0144] S13, the control terminal PTC15 of the controller U6 on the third PCB board inputs a conduction level to the base of the transistor Q4 on the third PCB board, and the transistor Q4 on the third PCB board is in the conducting state. At this time, the gate voltage of the field-effect transistor Q5 on the third PCB board is pulled low, and the field-effect transistor Q5 on the third PCB board is in the conducting state. The power supply +3.3VSW on the source of the field-effect transistor Q5 on the third PCB board is output as +3.3V_TFT through the drain of the field-effect transistor Q5 on the third PCB board.

[0145] S14, the controller U6 on the third PCB board sends the power-on screen to the third LCD screen through the deserialization chip U1 on the third PCB board, and displays the power-on screen on the third LCD screen;

[0146] S15, the control terminal PTD16 of the controller U6 on the third PCB board does not input an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the third PCB board; at this time, the DC-DC buck converter U2 on the third PCB board does not work, reducing energy consumption.

[0147] In a preferred embodiment of the present invention, the method for calculating the first level signal in step S11 is as follows:

[0148]

[0149] Wherein, P1 represents the voltage value of the wake-up terminal PTD5 of the input controller U6, which is the first level signal;

[0150] This indicates the cutoff voltage of transistor Q1;

[0151] This indicates the preset voltage first adjustment threshold.

[0152] The calculation method for the second level signal in step S11 is as follows:

[0153]

[0154] Wherein, P2 represents the voltage value of the wake-up terminal PTD5 of the input controller U6, which is the second level signal;

[0155] V +3.3V_MCU This indicates the voltage of the +3.3V power supply to the MCU.

[0156] This indicates the preset voltage first adjustment threshold.

[0157]

[0158] In a preferred embodiment of the present invention, the multi-screen unit includes a multi-screen body, and a PCB board 4 is disposed within the multi-screen body in a number equal to the number of liquid crystal displays A. In this embodiment, the number of liquid crystal displays is three. Figure 16 As shown, from left to right, the three LCD screens are the first LCD screen (left LCD screen), the second LCD screen (middle LCD screen), and the third LCD screen (right LCD screen). The three LCD screens are identical in all parameters except for their length and width, which may differ. In this invention, the three LCD screens have the same width, and correspondingly, from right to left, they are the first PCB board, the second PCB board, and the third PCB board, as shown below. Figure 21 As shown; the circuits on the first PCB board are connected to the first LCD screen, the circuits on the second PCB board are connected to the second LCD screen, and the circuits on the third PCB board are connected to the third LCD screen. A power module, a wake-up module, a voltage sampling module, a CAN communication module, a controller module, a deserializer module, and a screen backlight module are all provided on the first, second, and third PCB boards. Figures 1-24 As shown.

[0159] The power module is connected to one or any combination of the wake-up module, voltage sampling module, CAN communication module, controller module, deserializer module and screen backlight module, respectively, to provide appropriate power or voltage signals to one or any combination of the wake-up module, voltage sampling module, CAN communication module, controller module, deserializer module and screen backlight module.

[0160] The controller module is connected to one or any combination of the wake-up module, voltage sampling module, CAN communication module, and deserializer module;

[0161] The controller module enables signal acquisition and control of one or any combination of the wake-up module, voltage sampling module, CAN communication module, deserializer module, and screen backlight module.

[0162] In a preferred embodiment of the present invention, the power supply module includes one or any combination of a first voltage conversion module, a second voltage conversion module, a third voltage conversion module, a fourth voltage conversion module, a fifth voltage conversion module, a sixth voltage conversion module, a seventh voltage conversion module, an eighth voltage conversion module, a ninth voltage conversion module, a tenth voltage conversion module, an eleventh voltage conversion module, a twelfth voltage conversion module, a thirteenth voltage conversion module, and a fourteenth voltage conversion module; such as Figure 2 As shown.

[0163] The power input terminal of the first voltage conversion module is connected to the power output terminal of interface J3. The power output terminal of the first voltage conversion module is connected to the power input terminals of the second and twelfth voltage conversion modules respectively. The power output terminal of the second voltage conversion module is connected to the power input terminals of the third and fourth voltage conversion modules respectively. The power output terminal of the fourth voltage conversion module is connected to the power input terminals of the fifth, sixth, seventh, and eighth voltage conversion modules respectively. The power output terminal of the fifth voltage conversion module is connected to the power input terminal of the ninth voltage conversion module. The power output terminal of the sixth voltage conversion module is connected to the power input terminals of the tenth and eleventh voltage conversion modules respectively. The power output terminal of the twelfth voltage conversion module is connected to the power input terminals of the thirteenth and fourteenth voltage conversion modules respectively.

[0164] In a preferred embodiment of the present invention, the first voltage conversion module includes: a power output terminal of interface J3 connected to a first terminal of capacitor C64, a second terminal of capacitor C64 connected to a first terminal of capacitor C65, a second terminal of capacitor C65 connected to power ground, and a power output terminal of interface J3 outputting a battery. The battery power output from interface J3 is connected to the power output terminal of the vehicle battery, and the battery power output from interface J3 is converted into a stable battery power output after passing through capacitors C64 and C65 connected in series.

[0165] In a preferred embodiment of the present invention, the second voltage conversion module includes: the drain of a field-effect transistor Q17 is connected to a power supply BATTERY; the gate of the field-effect transistor Q17 is connected to the first terminal of a resistor R99, the first terminal of a resistor R100, the positive terminal of a diode D8, and the first terminal of a capacitor C91; the second terminal of a resistor R99 is connected to a power supply ground; the source of the field-effect transistor Q17 is connected to the second terminal of a resistor R100, the negative terminal of a diode D8, and the second terminal of a capacitor C91; the source of the field-effect transistor Q17 is also connected to the first terminal of a capacitor C117; the second terminal of a capacitor C117 is connected to a power supply ground; the source of the field-effect transistor Q17 is connected to the first terminal of an inductor L3; the second terminal of an inductor L3 is connected to the first terminals of capacitors C70 and C62; the second terminals of capacitors C70 and C62 are connected to a power supply ground; and the second terminal of an inductor L3 outputs a power supply +VBATT. The power supply BATTERY outputs voltage through the body diode of MOSFET Q17. MOSFET Q17 not only provides reverse connection protection for subsequent circuits but also has virtually no voltage drop, ensuring that its input voltage equals its output voltage. The output voltage is then divided by resistors R99 and R100 to provide the gate of MOSFET Q17 with a conduction level, turning MOSFET Q17 on. At this time, the source of MOSFET Q17 outputs a continuous voltage. This voltage is filtered by a π-type filter circuit consisting of capacitors C117 and C70 and inductor L3, outputting power supply +VBATT. Power supply +VBATT provides power to the screen backlight module, the three-phase pre-drive module, and the motor drive module.

[0166] In a preferred embodiment of the present invention, the fourth voltage conversion module includes: a first terminal of resistor R115 connected to the power supply +VBATT; a second terminal of resistor R115 connected to the first terminals of capacitors C53, C58, and C54; the second terminals of capacitors C53, C58, and C54 connected to the power supply ground; a second terminal of resistor R115 connected to the power supply terminal VIN of DC-DC buck converter U2; the bootstrap capacitor terminal BOOT of DC-DC buck converter U2 connected to the first terminal of resistor R52; and resistor R52... The second terminal is connected to the first terminal of capacitor C48. The second terminal of capacitor C48 is connected to the output terminal SW of DC-DC buck converter U2. The output terminal SW of DC-DC buck converter U2 is connected to the first terminal of inductor L6. The second terminal of inductor L6 is connected to the first terminals of capacitors C49, C50, C51, and C52. The second terminals of capacitors C49, C50, C51, and C52 are connected to the power supply ground. The second terminal of inductor L6 outputs +3.3VSW. The second terminal is connected to the first terminal of resistor R62. The second terminal of resistor R62 is connected to the first terminal of resistor R61. The second terminal of resistor R61 is connected to the first terminal of resistor R63 and the feedback terminal FB of DC-DC buck converter U2. The second terminal of resistor R63 is connected to the power supply ground. The enable terminal EN of DC-DC buck converter U2 is connected to the control terminal PTD16 of controller U6. The enable terminal EN of DC-DC buck converter U2 is connected to the first terminal of resistor R11. The second terminal of resistor R11 is connected to the power supply ground. The clock frequency terminal RT / CLK of DC-DC buck converter U2 is... The first terminal of resistor R51 is connected to the power supply ground. The second terminal of resistor R51 is connected to the power supply ground. The heat dissipation terminal EPGND of DC-DC buck converter U2 is in contact with the heat dissipation pad of DC-DC buck converter U2. The power supply ground terminal GND of DC-DC buck converter U2 is connected to the power supply ground. The soft start terminal SOFT-START of DC-DC buck converter U2 is connected to the first terminal of capacitor C56 and the first terminal of capacitor C92 respectively. The second terminal of capacitor C92 is connected to the first terminal of resistor R101. The second terminals of resistor R101 and capacitor C56 are connected to the power supply ground respectively.When a +3.3VSW power supply is required, the control terminal PTD16 of controller U6 inputs a high level to the enable terminal EN of DC-DC buck converter U2, enabling DC-DC buck converter U2 to operate and convert the input power supply +VBATT into a stable +3.3VSW power supply for output. Alternatively, a resistor R65 can be connected to the second terminal of inductor L6, with resistor R65 outputting a +3.3V_MCU power supply to power the controller module. To prevent DC-DC buck converter U2 from outputting power, the control terminal PTD16 of controller U6 inputs a low level to the enable terminal EN of DC-DC buck converter U2, disabling it and preventing power output from DC-DC buck converter U2.

[0167] In a preferred embodiment of the present invention, the fifth voltage conversion module includes: a first terminal of capacitor C69 connected to a power supply +3.3VSW, a second terminal of capacitor C69 connected to power supply ground, a first terminal of resistor R74 connected to a power supply +3.3VSW, a second terminal of resistor R74 connected to the enable terminal EN of positive voltage regulator U4, a second terminal of resistor R74 connected to a first terminal of resistor R72, a second terminal of resistor R72 connected to power supply ground, a power input terminal VIN of positive voltage regulator U4 connected to a power supply +3.3VSW, an output terminal VOUT of positive voltage regulator U4 connected to a first terminal of resistor R75, a second terminal of resistor R75 connected to the adjustment terminal ADJ of positive voltage regulator U4, a second terminal of resistor R75 connected to a first terminal of resistor R76, a second terminal of resistor R76 connected to power supply ground, a power output terminal VOUT of positive voltage regulator U4 connected to a first terminal of capacitor C68, a second terminal of capacitor C68 connected to power supply ground, and a power output terminal VOUT of positive voltage regulator U4 outputting a power supply +1.8VSW. The input power supply +3.3VSW is converted into a stable power supply +1.8VSW by the positive voltage regulator U4 for output.

[0168] In a preferred embodiment of the present invention, the sixth voltage conversion module includes: a first terminal of capacitor C24 connected to the +3.3VSW power supply, a second terminal of capacitor C24 connected to power ground, a first terminal of resistor R26 connected to the +3.3VSW power supply, a second terminal of resistor R26 connected to the enable terminal EN of positive voltage regulator U10, a second terminal of resistor R26 connected to the first terminal of resistor R31, a second terminal of resistor R31 connected to power ground, and the power input terminal VIN of positive voltage regulator U10 connected to the +3.3VSW power supply. The positive voltage regulator U10's power output terminal VOUT is connected to the first terminal of resistor R30. The second terminal of resistor R30 is connected to the adjustment terminal ADJ of the positive voltage regulator U10. The second terminal of resistor R30 is connected to the first terminal of resistor R27, and the second terminal of resistor R27 is connected to the power ground. The positive voltage regulator U10's power output terminal VOUT is connected to the first terminal of capacitor C29, and the second terminal of capacitor C29 is connected to the power ground. The positive voltage regulator U10 outputs a power supply of +1.0VSW. The input power supply +3.3VSW is converted into a stable power supply +1.0VSW for output by the positive voltage regulator U10.

[0169] In a preferred embodiment of the present invention, the seventh voltage conversion module includes: a first terminal of inductor L8 connected to a power supply +3.3VSW; a second terminal of inductor L8 connected to the first terminals of capacitors C36, C37, C38, and C35; and the second terminals of capacitors C36, C37, C38, and C35 connected to power ground. The second terminal of inductor L8 outputs power supply VDDIO. The input power supply +3.3VSW is filtered by an L-shaped filter circuit composed of capacitor C38 and inductor L8, outputting a stable power supply VDDIO to power the deserializer module.

[0170] In a preferred embodiment of the present invention, the eighth voltage conversion module includes: the source of field-effect transistor Q5 is connected to the power supply +3.3VSW; the drain of field-effect transistor Q5 is connected to the first terminal of resistor R81; the second terminal of resistor R81 is connected to the power supply ground; the drain of field-effect transistor Q5 outputs power supply +3.3V_TFT; the first terminal of capacitor C45 and the first terminal of resistor R80 are connected to the power supply +3.3VSW; the second terminal of capacitor C45 and the second terminal of resistor R80 are connected to the gate of field-effect transistor Q5; the gate of field-effect transistor Q5 is connected to the first terminal of resistor R79; the second terminal of resistor R79 is connected to the collector of transistor Q4; the emitter of transistor Q4 is connected to the power supply ground; the base of transistor Q4 is connected to the first terminal of resistor R78; the second terminal of resistor R78 is connected to the power supply ground; the base of transistor Q4 is connected to the first terminal of resistor R77; and the second terminal of resistor R77 is connected to the control terminal PTC15 of controller U6. When the control terminal PTC15 of controller U6 inputs a cutoff level to the base of transistor Q4, transistor Q4 is in the cutoff state. At this time, the gate potential of MOSFET Q5 is equal to that of the source potential of MOSFET Q5, and there is no power output from the drain of MOSFET Q5. When the control terminal PTC15 of controller U6 inputs a conduction level to the base of transistor Q4, transistor Q4 is in the conduction state. At this time, the gate voltage of MOSFET Q5 is pulled low, and MOSFET Q5 is in the conduction state. The drain of MOSFET Q5 outputs a power supply of +3.3V_TFT, which provides a power supply of +3.3V_TFT to the TFT screen interface J2 module.

[0171] In a preferred embodiment of the present invention, the ninth voltage conversion module includes: a first terminal of inductor L1 connected to a power supply +1.8VSW; a second terminal of inductor L1 connected to the first terminals of capacitors C19, C20, C21, C22, C27, and C28; and the second terminals of capacitors C19, C20, C21, C22, C27, and C28 connected to power ground. The second terminal of inductor L1 outputs power supply VDD18. The input power supply +1.8VSW is filtered by an L-shaped filter circuit composed of inductor L1 and capacitor C61, outputting a stable power supply VDD18 to power the deserializer module.

[0172] In a preferred embodiment of the present invention, the tenth voltage conversion module includes: a first terminal of inductor L2 connected to a power supply +1.0VSW; a second terminal of inductor L2 connected to the first terminals of capacitors C23, C26, C97, and C25; and the second terminals of capacitors C23, C26, C97, and C25 connected to power ground. The second terminal of inductor L2 outputs power supply VDDA. The input power supply +1.0VSW is filtered by an L-shaped filter circuit composed of inductor L2 and capacitor C23, outputting a stable power supply VDDA to provide analog power to the controller module.

[0173] In a preferred embodiment of the present invention, the eleventh voltage conversion module includes: a first terminal of inductor L14 connected to a power supply +1.0VSW; a second terminal of inductor L14 connected to the first terminals of capacitors C13, C14, C15, and C18; and the second terminals of capacitors C13, C14, C15, and C18 connected to power ground. The second terminal of inductor L14 outputs power supply VDDD. The input power supply +1.0VSW is filtered by an L-shaped filter circuit composed of inductor L14 and capacitor C18, outputting a stable power supply VDDD to provide digital power to the controller module. The digital power supply terminal VDDD of controller U6 is connected to power supply VDDD.

[0174] In a preferred embodiment of the present invention, the twelfth voltage conversion module includes: the positive terminal of diode D13 is connected to the power supply BATTERY; the negative terminal of diode D13 is connected to the first terminal of capacitor C113 and the first terminal of capacitor C114; the second terminals of capacitor C113 and the second terminal of capacitor C114 are connected to the power supply ground; and the negative terminal of diode D13 outputs power supply +VBAT2. After passing through diode D13, the power supply BATTERY is filtered by capacitors C113 and C114 to obtain a stable power supply +VBAT2 output. Diode D13 serves to prevent reverse connection, protecting the safety of subsequent circuits.

[0175] In a preferred embodiment of the present invention, the thirteenth voltage conversion module includes: the power supply terminal VIN of the linear regulator U5 is connected to the power supply +VBAT2; the power supply output terminal VOUT of the linear regulator U5 is connected to the first terminal of capacitor C115; the second terminal of capacitor C115 is connected to the power supply ground; the power supply output terminal VOUT of the linear regulator U5 outputs a power supply +3.3V_MCU; the power supply terminal VIN of the linear regulator U5 is connected to the first terminal of resistor R33; the second terminal of resistor R33 is connected to the enable terminal EN of the linear regulator U5; and the power supply ground terminal GND of the linear regulator U5 is connected to the power supply ground. The input power supply +VBAT2 is converted into a stable power supply +3.3V_MCU using the linear regulator U5, providing power to the controller module and a wake-up signal to the wake-up module.

[0176] The thirteenth voltage conversion module can also be connected as follows: the power supply terminal VIN of the linear regulator U5 is connected to the power supply +VBAT2; the power output terminal VOUT of the linear regulator U5 is connected to the first terminal of capacitor C115; the second terminal of capacitor C115 is connected to the power supply ground; the power output terminal VOUT of the linear regulator U5 outputs power supply +3.3V_MCU; the enable terminal EN of the linear regulator U5 is connected to the first terminal of resistor R143, the first terminal of resistor R165, and the first terminal of capacitor C116; the second terminal of resistor R165 and the second terminal of capacitor C116 are connected to the power supply ground; the second terminal of resistor R143 is connected to the negative terminal of diode D3; and the power supply ground terminal GND of the linear regulator U5 is connected to the power supply ground. The wake-up level signal is output through the negative terminal of diode D3, which makes the enable terminal EN of linear regulator U5 high. Linear regulator U5 works and converts the input power supply +VBAT2 into a stable power supply +3.3V_MCU, providing power to the controller module and a wake-up signal to the wake-up module.

[0177] In a preferred embodiment of the present invention, the fourteenth voltage conversion module includes: a first terminal of capacitor C123 connected to power supply +VBAT2, a second terminal of capacitor C123 connected to power ground, a power supply terminal VIN and an enable terminal EN of linear regulator U9 connected to power supply +VBAT2, a power output terminal VOUT of linear regulator U9 outputting power supply VCC_5V, a power output terminal VOUT of linear regulator U9 connected to the first terminal of capacitor C124, a second terminal of capacitor C124 connected to power ground, and a power ground terminal GND of linear regulator U9 connected to power ground. The input power supply +VBAT2 is converted into a stable power supply VCC_5V by linear regulator U9 to provide power to the CAN communication module.

[0178] In a preferred embodiment of the present invention, such as Figure 3As shown, the wake-up module includes: the first terminal of resistor R58 is connected to the +3.3V power supply MCU; the second terminal of resistor R58 is connected to the collector of transistor Q1; the collector of transistor Q1 is connected to the first terminal of resistor R132; the second terminal of resistor R132 is connected to the wake-up terminal PTD5 of controller U6; the emitter of transistor Q1 is connected to power ground; the base of transistor Q1 is connected to the first terminal of capacitor C61 and the first terminal of resistor R56; the second terminals of capacitor C61 and resistor R56 are both connected to power ground; and the base of transistor Q1 is connected to the first terminal of resistor R73. The first terminal is connected, the second terminal of resistor R73 is connected to the negative terminal of diode D3, the positive terminal of diode D3 is connected to the wake-up terminal of interface J3, the positive terminal of diode D3 is connected to the first terminal of capacitor C66, the second terminal of capacitor C66 is connected to power ground, the second terminal of resistor R73 is connected to the first terminal of resistor R59, the second terminal of resistor R59 is connected to the first terminal of resistor R60 and the first terminal of capacitor C59, the second terminals of resistor R60 and capacitor C59 are both connected to power ground, and the second terminal of resistor R59 is connected to the wake-up signal monitoring terminal PTC1 of controller U6. The wake-up signal is output through the wake-up terminal of interface J3 (this wake-up signal can be the ignition signal or other wake-up signals, such as the wake-up signal sent from the vehicle control). When it is the ignition signal, the voltage is divided by resistors R73 and R56 to provide a conduction level for transistor Q1. At this time, transistor Q1 conducts, and the level of the wake-up terminal PTD5 of the input controller U6 is low, thus waking up the controller U6. When the base of transistor Q1 is at the cutoff level, transistor Q1 is in the cutoff state, and the level of the wake-up terminal PTD5 of the input controller U6 is high. In addition, after the wake-up signal is output from the wake-up terminal of interface J3, the wake-up signal can be protected against reverse connection by diode D3. Then, the voltage is divided by resistors R59 and R60, and the wake-up signal monitoring terminal PTC1 of the controller U6 collects whether the ignition signal is abnormal.

[0179] In a preferred embodiment of the present invention, such as Figure 4 and 5As shown, the voltage sampling module includes: the emitter of transistor Q2 is connected to the power supply BATTERY; the collector of transistor Q2 is connected to the first end of resistor R67; the second end of resistor R67 is connected to the first end of resistor R68 and the first end of capacitor C67; the second end of resistor R68 and the second end of capacitor C67 are both connected to the power supply ground; the second end of resistor R68 is connected to the voltage sampling terminal PTC0 of controller U6; the first end of resistor R71 is connected to the power supply BATTERY; the second end of resistor R71 is connected to the base of transistor Q2; the second end of resistor R71 is connected to the first end of resistor R66; the second end of resistor R66 is connected to the collector of transistor Q3; the emitter of transistor Q3 is connected to the power supply ground; the base of transistor Q3 is connected to the first end of resistor R70; the second end of resistor R70 is connected to the power supply ground; the base of transistor Q3 is connected to the first end of resistor R69; and the second end of resistor R69 is connected to the voltage sampling control terminal PTC16 of controller U6.

[0180] The emitter of transistor Q16 is connected to the power supply +VBATT. The collector of transistor Q16 is connected to the first terminal of resistor R217. The second terminal of resistor R217 is connected to the first terminal of resistor R216 and the first terminal of capacitor C141. The second terminals of resistor R216 and capacitor C141 are both connected to the power supply ground. The second terminal of resistor R217 is connected to the voltage sampling terminal PTB3 of controller U6. The first terminal of resistor R218 is connected to the power supply +VBATT. The second terminal of resistor R218 is connected to the base of transistor Q16. The second terminal of resistor R218 is connected to the first terminal of resistor R215. The second terminal of resistor R215 is connected to the second terminal of resistor R66. When the voltage sampling control terminal PTC16 of controller U6 inputs a cutoff level to the base of transistor Q3, transistor Q3 is in the cutoff state. At this time, the base potential of transistor Q2 is equal to the emitter potential of transistor Q2, and there is no voltage output from the collector of transistor Q2. Similarly, the base potential of transistor Q16 is equal to the emitter potential of transistor Q16, and there is no voltage output from the collector of transistor Q16. When it is necessary to sample the voltages of power supply BATTERY and power supply +VBATT, the voltage sampling control terminal PTC16 of controller U6 inputs a conduction level to the base of transistor Q3. When transistor Q3 is in the conducting state, the voltage of transistor Q2 is pulled low. The collector output voltage of transistor Q2, through the voltage divider circuit composed of resistors R67 and R68, ensures the voltage safety of the voltage sampling terminal PTC0 of the input controller U6, thus realizing the voltage acquisition of the power supply BATTERY. At the same time, the voltage of transistor Q16 is pulled low. The collector output voltage of transistor Q16, through the voltage divider circuit composed of resistors R217 and R216, ensures the voltage safety of the voltage sampling terminal PTB3 of the input controller U6, thus realizing the voltage acquisition of the power supply +VBATT.

[0181] In a preferred embodiment of the present invention, such as Figure 6 As shown, the CAN communication module includes: the NC terminal of the communication chip U3 is connected to the +3.3V_MCU power supply; the first terminal of capacitor C142 is connected to the +3.3V_MCU power supply; the second terminal of capacitor C142 is connected to the power supply ground; the first terminals of capacitors C107 and C108 are connected to the VCC_5V power supply; the second terminals of capacitors C107 and C108 are connected to the power supply ground; and the VCC terminal of the communication chip U3 is connected to the VCC_5V power supply.

[0182] The data terminal CANH of communication chip U3 is connected to the first terminal of resistor R148, the second terminal of resistor R148 is connected to the first terminal of capacitor C63, the data terminal CANH of communication chip U3 is connected to the first terminal of resistor R152, the second terminal of resistor R152 is connected to the first terminal of capacitor C10, the second terminal of capacitor C10 is connected to power ground, the second terminal of resistor R152 is connected to the high-level data terminal of interface J3, and the second terminal of resistor R152 is connected to the first terminal of electrostatic protection diode D1.

[0183] The data terminal CANL of communication chip U3 is connected to the first terminal of resistor R149. The second terminal of resistor R149 is connected to the first terminal of capacitor C63. The second terminal of capacitor C63 is connected to the power supply ground. The data terminal CANL of communication chip U3 is connected to the first terminal of resistor R153. The second terminal of resistor R153 is connected to the first terminal of capacitor C60. The second terminal of capacitor C60 is connected to the power supply ground. The second terminal of resistor R153 is connected to the low-level data terminal of interface J3. The second terminal of resistor R153 is connected to the second terminal of electrostatic discharge protection diode D1. The common terminal of electrostatic discharge protection diode D1 is connected to the power supply ground.

[0184] The standby mode selection terminal STB-IN of communication chip U3 is connected to the control terminal PTE10 of controller U6. The data transmission terminal TXD-IN of communication chip U3 is connected to the first terminal of resistor R154, and the second terminal of resistor R154 is connected to the data receiving terminal PTE5 of controller U6. The data receiving terminal RXD-OUT of communication chip U3 is connected to the first terminal of resistor R155, and the second terminal of resistor R155 is connected to the data transmission terminal PTE4 of controller U6. It connects to the vehicle controller module or other modules via interface J3, enabling communication between controller U6 and the vehicle controller module or other modules using communication chip U3.

[0185] In a preferred embodiment of the present invention, such as Figures 7-10As shown, the deserializer module includes: the negative differential signal terminal SIOB- of the deserializer chip U1 is connected to the first terminal of capacitor C7; the second terminal of capacitor C7 is connected to the first terminal of resistor R161; the second terminal of resistor R161 is connected to power ground; the positive differential signal terminal SIOB+ of the deserializer chip U1 is connected to the first terminal of capacitor C12; the second terminal of capacitor C12 is connected to the first terminal of resistor R47; the second terminal of resistor R47 is connected to power ground; the first terminal of resistor R47 is connected to the first terminal of electrostatic discharge protection diode ESD5; the second terminal of electrostatic discharge protection diode ESD5 is connected to power ground; the first terminal of electrostatic discharge protection diode ESD5 is connected to the video signal data terminal RF of interface J4; and the power ground terminal GND of interface J4 is connected to power ground. By connecting interface J4 to a video cable, video data transmitted from interface J4 can be played on the screen.

[0186] The power supply terminal VDD18 of the deserializer chip U1 is connected to power supply VDD18. The first terminal of resistor R28 is connected to power supply VDDIO, and the second terminal of resistor R28 is connected to the data terminal SDA_RX of the deserializer chip U1. The first terminal of resistor R29 is connected to power supply VDDIO, and the second terminal of resistor R29 is connected to the serial clock signal terminal SCL_TX of the deserializer chip U1. The first terminal of resistor R123 is connected to the first terminal of resistor R7, and the second terminal of resistor R7 is connected to the clock terminal PTA0 of controller U6. The first terminal of resistor R121 is connected to the power supply +3.3V_MCU, and the second terminal of resistor R123 is connected to the serial clock signal terminal SCL_TX of the deserializer chip U1. TX is connected; the first end of resistor R122 is connected to the first end of resistor R8; the second end of resistor R8 is connected to the data terminal PTA1 of controller U6 and the first end of resistor R120; the second end of resistor R120 is connected to the power supply +3.3V_MCU; the second end of resistor R122 is connected to the data terminal SDA_RX of deserialization chip U1; the first end of resistor R116 is connected to the data terminal PTA2 of controller U6; the second end of resistor R116 is connected to the data terminal SDA_RX of deserialization chip U1; the first end of resistor R117 is connected to the serial clock signal terminal PTA3 of controller U6; the second end of resistor R117 is connected to the serial clock signal terminal SCL_TX of deserialization chip U1.

[0187] The power supply terminal VDDA of the deserializer chip U1 is connected to the power supply VDDA. The first terminal of the resistor R102 is connected to the power supply VDDIO. The second terminal of the resistor R102 is connected to the twisted pair / coaxial cable mode selection terminal CXTP / GPIO09 of the deserializer chip U1. The twisted pair / coaxial cable mode selection terminal CXTP / GPIO09 of the deserializer chip U1 is connected to the first terminal of the resistor R96. The second terminal of the resistor R96 is connected to the power supply ground.

[0188] The first end of resistor R35 is connected to the power supply VDDIO, and the second end of resistor R35 is connected to the LOCK terminal of deserialization chip U1. The first end of resistor R32 is connected to the PTE9 terminal of controller U6, and the second end of resistor R32 is connected to the LOCK terminal of deserialization chip U1. The first end of resistor R40 is connected to the PTD15 terminal of controller U6, and the second end of resistor R40 is connected to the ERRORB terminal of deserialization chip U1. The first end of resistor R34 is connected to the power supply VDDIO, and the second end of resistor R34 is connected to the ERRORB terminal of deserialization chip U1.

[0189] The first terminal X1 / SOC of the crystal oscillator of the deserializer chip U1 is connected to the first terminal of capacitor C16, and the second terminal of capacitor C16 is connected to the power supply ground. The first terminal X1 / SOC of the crystal oscillator of the deserializer chip U1 is connected to the first terminal of crystal oscillator Y2, and the ground terminal GND of crystal oscillator Y2 is connected to the power supply ground. The second terminal of crystal oscillator Y2 is connected to the second terminal X2 of the crystal oscillator of the deserializer chip U1 and the first terminal of capacitor C17, and the second terminal of capacitor C17 is connected to the power supply ground; thus providing a clock oscillation signal for the deserializer chip U1.

[0190] The transmit reset terminal TXRES of the deserializer chip U1 is connected to the first terminal of resistor R49, and the second terminal of resistor R49 is connected to the power supply ground. The I2C mode selection terminal GPIO01 / I2CSEL of the deserializer chip U1 is connected to the first terminal of resistor R46, and the second terminal of resistor R46 is connected to the power supply VDDIO. The differential signal terminal SIOA+ of the deserializer chip U1 is connected to the first terminal of capacitor C8, and the second terminal of capacitor C8 is connected to the first terminal of resistor R44, and the second terminal of resistor R44 is connected to the power supply ground. The differential signal terminal SIOA- of the deserializer chip U1 is connected to the first terminal of capacitor C11, and the second terminal of capacitor C11 is connected to the first terminal of resistor R43, and the second terminal of resistor R43 is connected to the power supply ground. The power-off mode selection terminal PWDNB of the deserializer chip U1 is connected to the first terminal of resistor R21, and the second terminal of resistor R21 is connected to the power supply ground. The power-off mode selection terminal PWDNB of the deserializer chip U1 is connected to the first terminal of resistor R48, and the second terminal of resistor R48 is connected to the control terminal PTC9 of controller U6.

[0191] The address pins SD / ADD0 / GPIO11 of the deserializer chip U1 are connected to the power supply VDDIO. The address pins SD / ADD0 / GPIO11 of the deserializer chip U1 are also connected to the first terminal of resistor R23, and the second terminal of resistor R23 is connected to ground. The address pins SCK / ADD1 / GPIO12 of the deserializer chip U1 are connected to the power supply VDDIO. The address pins SCK / ADD1 / GPIO12 of the deserializer chip U1 are also connected to the first terminal of resistor R24, and the second terminal of resistor R24 ​​is connected to ground. The address pins WS / ADD2 / GPIO13 of the deserializer chip U1 are connected to the first terminal of resistor R42, and the second terminal of resistor R42 is connected to ground. The address pins WS / ADD2 / GPIO13 of the deserializer chip U1 are connected to the power supply VDDIO; the interrupt signal pins SDIR / GPIO06 of the deserializer chip U1 are connected to the first end of resistor R118, and the second end of resistor R118 is connected to the interrupt signal pin PTC5 of the controller U6; or the interrupt signal pins SDIR / GPIO06 of the deserializer chip U1 are connected to the first end of resistor R124, the second end of resistor R124 is connected to the interrupt signal pin of the TFT screen interface J2 and the first end of resistor R15, and the second end of resistor R15 is connected to the +3.3V_TFT power supply; providing the address code for the deserializer chip U1.

[0192] The data terminal TXOUT_B0- of the deserialization chip U1 is connected to the first negative data terminal of the TFT screen interface J2; the data terminal TXOUT_B0+ of the deserialization chip U1 is connected to the first positive data terminal of the TFT screen interface J2; the data terminal TXOUT_B1- of the deserialization chip U1 is connected to the second negative data terminal of the TFT screen interface J2; the data terminal TXOUT_B0+ of the deserialization chip U1 is connected to the second positive data terminal of the TFT screen interface J2; and the clock terminal TXCLK_OUTB- of the deserialization chip U1 is connected to the first negative clock terminal of the TFT screen interface J2. The clock terminal TXCLK_OUTB+ of the deserialization chip U1 is connected to the first positive clock terminal of the TFT screen interface J2; the data terminal TXOUT_B2- of the deserialization chip U1 is connected to the third negative data terminal of the TFT screen interface J2; the data terminal TXOUT_B2+ of the deserialization chip U1 is connected to the third positive data terminal of the TFT screen interface J2; the data terminal TXOUT_B3- of the deserialization chip U1 is connected to the fourth negative data terminal of the TFT screen interface J2; and the data terminal TXOUT_B3+ of the deserialization chip U1 is connected to the fourth positive data terminal of the TFT screen interface J2.

[0193] The data terminal TXOUT_A0- of the deserializer chip U1 is connected to the fifth negative data terminal of the TFT screen interface J2; the data terminal TXOUT_A0+ of the deserializer chip U1 is connected to the fifth positive data terminal of the TFT screen interface J2; the data terminal TXOUT_A1- of the deserializer chip U1 is connected to the sixth negative data terminal of the TFT screen interface J2; the data terminal TXOUT_A1+ of the deserializer chip U1 is connected to the sixth positive data terminal of the TFT screen interface J2; and the clock terminal TXCLK_OUTA- of the deserializer chip U1 is connected to the second negative clock terminal of the TFT screen interface J2. The clock terminal TXCLK_OUTA+ of the deserialization chip U1 is connected to the second clock positive terminal of the TFT screen interface J2; the data terminal TXOUT_A2- of the deserialization chip U1 is connected to the seventh data negative terminal of the TFT screen interface J2; the data terminal TXOUT_A2+ of the deserialization chip U1 is connected to the seventh data positive terminal of the TFT screen interface J2; the data terminal TXOUT_A3- of the deserialization chip U1 is connected to the eighth data negative terminal of the TFT screen interface J2; and the data terminal TXOUT_A3+ of the deserialization chip U1 is connected to the eighth data positive terminal of the TFT screen interface J2.

[0194] The TFT screen enable control terminal GPIO02 of the deserializer chip U1 is connected to the first end of resistor R36, and the second end of resistor R36 is connected to the TFT screen enable detection terminal PTE7 of controller U6. The TFT screen enable control terminal GPIO02 of the deserializer chip U1 is connected to the first end of resistor R37, and the second end of resistor R37 is connected to the first end of resistor R130. The second end of resistor R130 is connected to the backlight enable control terminal PTC8 of controller U6. The backlight enable terminal EN of backlight chip U7 is enabled by the TFT screen enable control terminal GPIO02 of the deserializer chip U1 and / or the backlight enable control terminal PTC8 of controller U6. The TFT screen enable detection terminal PTE7 of controller U6 detects whether a control signal is sent to the backlight enable terminal EN of backlight chip U7.

[0195] The PWM adjustment terminal WSIR / GPIO08 of the deserializer chip U1 is connected to the first terminal of resistor R38, and the second terminal of resistor R38 is connected to the PWM detection terminal PTC3 of controller U6. The PWM adjustment terminal WSIR / GPIO08 of the deserializer chip U1 is connected to the first terminal of resistor R39, the second terminal of resistor R39 is connected to the first terminal of resistor R129, the second terminal of resistor R129 is connected to the backlight adjustment terminal PTB2 of controller U6, the first terminal of resistor R129 is connected to the first terminal of capacitor C93, and the second terminal of capacitor C93 is connected to the power supply ground. A PWM signal is input to the backlight adjustment terminal PWM of backlight chip U7 through the PWM adjustment terminal WSIR / GPIO08 of deserializer chip U1 and / or the backlight adjustment terminal PTB2 of controller U6. The PWM detection terminal PTC3 of controller U6 detects whether a PWM signal is input to the backlight adjustment terminal PWM of backlight chip U7.

[0196] The power supply terminal VDDD of the deserialization chip U1 is connected to the power supply VDDD, and the power supply terminal EPGND of the deserialization chip U1 is connected to the power ground. It is connected to the TFT screen via the TFT screen interface J2 to display data on the screen.

[0197] In a preferred embodiment of the present invention, such as Figure 15As shown, the screen backlight module includes: the power supply terminal VCC of the backlight chip U7 is connected to the first terminal of capacitor C87, the second terminal of capacitor C87 is connected to power ground; the power supply terminal VCC of the backlight chip U7 is connected to the first terminal of resistor R98, the second terminal of resistor R98 is connected to power supply VBATT; the second terminal of resistor R98 is connected to the first terminal of capacitor C71, the second terminal of capacitor C71 is connected to power ground; the first terminal of capacitor C71 is connected to the first terminals of capacitors C81, C82, and C83; the second terminals of capacitors C81, C82, and C83 are all connected to power ground; the first terminal of capacitor C71 is connected to the first terminal of inductor L4, the second terminal of inductor L4 is connected to the anode of diode D5, the cathode of diode D5 is connected to the first terminal of resistor R86, the second terminal of resistor R86 is connected to the voltage protection terminal OVP of the backlight chip U7, the second terminal of resistor R86 is connected to the first terminal of resistor R87, the second terminal of resistor R87 is connected to power ground, and the diode... The negative terminal of diode D5 is connected to the first terminals of capacitors C85, C84, C86, and C80. The second terminals of capacitors C85, C84, C86, and C80 are all connected to the power supply ground. The negative terminal of diode D5 is connected to the first terminal of resistor R9. The second terminal of resistor R9 outputs the power supply TFT_BL+. The second terminal of inductor L4 is connected to the drain of MOSFET Q18. The gate of MOSFET Q18 is connected to the gate of resistor R89. The first terminal is connected, the second terminal of resistor R89 ​​is connected to the driving voltage terminal DRV of backlight chip U7, the source of field-effect transistor Q18 is connected to the first terminal of resistor R88, the second terminal of resistor R88 is connected to the current sampling terminal SEN of backlight chip U7, the source of field-effect transistor Q18 is connected to the first terminal of resistor R97, the second terminal of resistor R97 is connected to the power supply ground, the second terminal of resistor R97 is connected to the first terminal of capacitor C88, and the second terminal of capacitor C88 is connected to the current sampling terminal SEN of backlight chip U7.

[0198] The backlight adjustment terminal PWM of the backlight chip U7 is connected to the first terminal of resistor R90. The second terminal of resistor R90 is connected to the first terminal of resistor R129. The second terminal of resistor R129 is connected to the backlight adjustment terminal PTB2 of controller U6. The backlight enable terminal EN of the backlight chip U7 is connected to the first terminal of resistor R91. The second terminal of resistor R91 is connected to the first terminal of resistor R130. The second terminal of resistor R130 is connected to the backlight enable terminal PTC8 of controller U6. The compensation terminal VC of the backlight chip U7 is connected to the first terminal of resistor R93. The second terminal of resistor R93 is connected to the first terminal of capacitor C89. The second terminal of capacitor C89 is connected to the power supply ground.

[0199] The STATUS pin of the backlight chip U7 is connected to the PTA13 pin of the controller U6. The STATUS pin of the backlight chip U7 is connected to the first terminal of the resistor R94. The second terminal of the resistor R94 is connected to the +3.3VSW power supply. The RISET pin of the backlight chip U7 is connected to the first terminal of the resistor R92. The second terminal of the resistor R92 is connected to the power supply ground. The RT pin of the backlight chip U7 is connected to the first terminal of the resistor R95. The second terminal of the resistor R95 is connected to the power supply ground. The GREG pin of the backlight chip U7 is connected to the first terminal of the capacitor C90. The second terminal of the capacitor C90 is connected to the power supply ground. The GND pin of the backlight chip U7 is connected to the power supply ground.

[0200] The first backlight activation terminal LED1 of backlight chip U7 is connected to the first terminal of resistor R2. The second terminal of resistor R2 is connected to the first backlight activation terminal of TFT screen interface J2. The first backlight activation terminal of TFT screen interface J2 is connected to the first terminal of capacitor C1. The second terminal of capacitor C1 is connected to the power supply TFT_BL+. The second backlight activation terminal LED2 of backlight chip U7 is connected to the first terminal of resistor R3. The second terminal of resistor R3 is connected to the second backlight activation terminal of TFT screen interface J2. The second backlight activation terminal of TFT screen interface J2 is connected to the first terminal of capacitor C2. The second terminal of capacitor C2 is connected to the power supply TFT_BL+. The third backlight activation terminal LED3 of backlight chip U7 is connected to the first terminal of resistor R4. One end of the resistor R4 is connected to the third backlight activation terminal of the TFT screen interface J2. The third backlight activation terminal of the TFT screen interface J2 is connected to the first end of the capacitor C3, and the second end of the capacitor C3 is connected to the power supply TFT_BL+. The fourth backlight activation terminal LED4 of the backlight chip U7 is connected to the first end of the resistor R5. The second end of the resistor R5 is connected to the fourth backlight activation terminal of the TFT screen interface J2. The fourth backlight activation terminal of the TFT screen interface J2 is connected to the first end of the capacitor C4, and the second end of the capacitor C4 is connected to the power supply TFT_BL+. The second ends of capacitors C1, C2, C3, and C4 are connected to the power supply terminal of the TFT screen interface J2. The input power supply VBATT is converted to power the LEDs via the LED beads connected to the TFT screen interface J2, providing backlight.

[0201] In a preferred embodiment of the present invention, such as Figures 11-13As shown, the controller module also includes: the power supply terminal VDD of controller U6 is connected to the analog power supply terminal VDDA of controller U6; the power supply terminal VDD of controller U6 is connected to the first terminal of capacitor C79, the first terminal of capacitor C72, and the first terminal of capacitor C78 respectively; the second terminals of capacitor C79, C72, and C78 are all connected to power ground; the power supply terminal VDD of controller U6 is connected to the +3.3V_MCU power supply; the reference voltage terminal VREFH of controller U6 is connected to the first terminal of capacitor C74, the first terminal of capacitor C75, and the first terminal of capacitor C76; the second terminals of capacitor C74, C75, and C76 are all connected to power ground; the reference voltage terminal VREFH of controller U6 is connected to the first terminal of resistor R85; the second terminal of resistor R85 is connected to the +3.3V_MCU power supply.

[0202] The data terminal PTA4 of controller U6 is connected to the data terminal of interface J5. PTA4 is also connected to the first terminal of resistor R113. The second terminal of resistor R113 is connected to the power supply terminal of interface J5. The second terminal of resistor R113 is connected to the first terminal of resistor R111. The first terminal of resistor R111 is connected to the +3.3V power supply (MCU). Resistor R111 is connected to the first terminal of capacitor C94. The second terminal of capacitor C94 is connected to ground. The second terminal of resistor R111 is connected to the reset terminal PTA5 of controller U6. The second terminal of resistor R111 is connected to the first terminal of resistor R110. The second terminal of resistor R110 is connected to the reset terminal of interface J5. The clock terminal of interface J5 is connected to the clock terminal PTC4 of controller U6. The clock terminal of interface J5 is connected to the first terminal of resistor R112. The second terminal of resistor R112 is connected to ground. The ground terminal of interface J5 is connected to ground. The test function is achieved by connecting to interface J5 via a data cable.

[0203] The crystal oscillator terminal PTB7 of controller U6 is connected to the first terminal of resistor R114 and the first terminal of crystal oscillator Y1. The crystal oscillator terminal PTB7 of controller U6 is connected to the first terminal of capacitor C95. The second terminal of capacitor C95 is connected to the power supply ground. The second terminal of resistor R114 and the second terminal of crystal oscillator Y1 are both connected to the crystal oscillator terminal PTB6 of controller U6. The second terminal of resistor R114 is connected to the first terminal of capacitor C96. The second terminal of capacitor C96 is connected to the power supply ground.

[0204] The temperature monitoring terminal PTB1 of controller U6 is connected to the first terminal of capacitor C55, the second terminal of capacitor C55 is connected to the power supply ground, the temperature monitoring terminal PTB1 of controller U6 is connected to the first terminal of resistor R19, the second terminal of resistor R19 is connected to the temperature monitoring terminal of TFT screen interface J2, the temperature monitoring terminal of TFT screen interface J2 is connected to the first terminal of resistor R18, and the second terminal of resistor R18 is connected to the power supply +3.3V_TFT.

[0205] The interrupt terminal PTA11 of controller U6 is connected to the first terminal of resistor R6, and the second terminal of resistor R6 is connected to the interrupt signal terminal of TFT screen interface J2.

[0206] The clock terminal PTA0 of controller U6 is connected to the first terminal of resistor R7, and the second terminal of resistor R7 is connected to the clock terminal of TFT screen interface J2.

[0207] The data terminal PTA1 of controller U6 is connected to the first terminal of resistor R8, and the second terminal of resistor R8 is connected to the TFT screen data terminal of TFT screen interface J2.

[0208] The TFT screen reset terminal PTE0 of controller U6 is connected to the first terminal of resistor R20 and the first terminal of resistor R10 respectively. The second terminal of resistor R10 is connected to the first terminal. The second terminal of resistor R20 is connected to the TFT screen reset terminal of TFT screen interface J2.

[0209] The TFT screen read / write protection terminal PTE1 of controller U6 is connected to the first terminal of resistor R22, and the second terminal of resistor R22 is connected to the read / write protection terminal of TFT screen interface J2.

[0210] The TFT screen fault status terminal PTA12 of controller U6 is connected to the first terminal of resistor R16, the second terminal of resistor R16 is connected to the fault status terminal of TFT screen interface J2, the second terminal of resistor R16 is connected to the first terminal of resistor R17, and the second terminal of resistor R17 is connected to the power supply +3.3V_TFT.

[0211] The TFT screen reset terminal PTC17 of controller U6 is connected to the first terminal of resistor R12, the second terminal of resistor R12 is connected to the reset terminal of TFT screen interface J2, the second terminal of resistor R12 is connected to the first terminal of resistor R13, and the second terminal of resistor R13 is connected to the power ground.

[0212] The A-phase position detection terminal PTD1 of controller U6 is connected to the first terminal of resistor R103. The second terminal of resistor R103 is connected to the first position detection terminal of interface J1. The second terminal of resistor R103 is connected to the first terminal of resistor R146 and the first terminal of capacitor C104. The second terminal of capacitor C104 is connected to power ground. The second terminal of resistor R146 is connected to power supply PWR_SOR. The first terminal of resistor R103 is connected to the first terminal of resistor R108. The second terminal of resistor R108 is connected to power ground. The B-phase position detection terminal PTD0 of controller U6 is connected to the first terminals of resistor R104 and resistor R107 respectively. The second terminal of resistor R104 is connected to the second position detection terminal of interface J1. The second terminal of resistor 104 is connected to the first terminal of resistor R147 and the first terminal of capacitor C105. The second terminal of capacitor C105 is connected to the power supply ground. The second terminal of resistor R147 is connected to the power supply PWR_SOR. The second terminal of resistor R107 is connected to the power supply ground. The C-phase position detection terminal PTE11 of controller U6 is connected to the first terminal of resistor R105 and the first terminal of resistor R106 respectively. The second terminal of resistor R105 is connected to the third position detection terminal of interface J1. The second terminal of resistor R105 is connected to the first terminal of resistor R83 and the first terminal of capacitor C9. The second terminal of capacitor C9 is connected to the power supply ground. The second terminal of resistor R83 is connected to the power supply PWR_SOR. The second terminal of resistor R106 is connected to the power supply ground.

[0213] The A-phase voltage detection terminal PTA7 of controller U6 is connected to the first terminal of resistor R173, the second terminal of resistor R173 is connected to the A-phase terminal of drive motor of interface J1, the A-phase voltage detection terminal PTA7 of controller U6 is connected to the first terminal of resistor R84, the second terminal of resistor R84 is connected to power ground, the A-phase voltage detection terminal PTA7 of controller U6 is connected to the first terminal of capacitor C128, and the second terminal of capacitor C128 is connected to power ground.

[0214] The B-phase voltage detection terminal PTA6 of controller U6 is connected to the first terminal of resistor R175, the second terminal of resistor R175 is connected to the B-phase terminal of the drive motor of interface J1, the B-phase voltage detection terminal PTA6 of controller U6 is connected to the first terminal of resistor R174, the second terminal of resistor R174 is connected to the power supply ground, the B-phase voltage detection terminal PTA6 of controller U6 is connected to the first terminal of capacitor C127, and the second terminal of capacitor C127 is connected to the power supply ground.

[0215] The C-phase voltage detection terminal PTC14 of controller U6 is connected to the first terminal of resistor R177. The second terminal of resistor R177 is connected to the C-phase terminal of the drive motor of interface J1. The C-phase voltage detection terminal PTC14 of controller U6 is connected to the first terminal of resistor R176. The second terminal of resistor R176 is connected to the power supply ground. The C-phase voltage detection terminal PTC14 of controller U6 is connected to the first terminal of capacitor C73. The second terminal of capacitor C73 is connected to the power supply ground.

[0216] In a preferred embodiment of the present invention, the TFT screen interface module further includes: the first power supply terminal of the TFT screen interface J2 is connected to the first terminal of capacitor C5 and the first terminal of capacitor C6, the second terminals of capacitor C5 and capacitor C6 are connected to the power ground, the second power supply terminal of the TFT screen interface J2 is connected to the first terminal of resistor R14, and the second terminal of resistor R14 is connected to the power supply +3.3V_TFT.

[0217] The third power supply terminal of the TFT screen interface J2 is connected to the first terminal of resistor R184, and the second terminal of resistor R184 is connected to the +3.3V_TFT power supply.

[0218] like Figures 15-23 The diagram illustrates a multi-screen unit comprising a shell extending horizontally, with both ends of the shell curved forward to form an arc shape for better viewing. Three LCD screens A are horizontally spaced on the shell, arranged from left to right as an instrument display, a central control screen, and an entertainment display. Adjacent LCD screens A are separated by decorative partitions B, as are those near both ends of the shell. The decorative partitions B near the ends of the shell are larger than the other decorative partitions B, and all LCD screens A are larger than the decorative partitions B.

[0219] The housing includes a bracket 1 and a glass cover 3 located on the front side of the bracket 1, which covers all the LCD screens A and the partition decorative parts B. The bracket 1 is offset backwards at the part corresponding to the LCD screen A, forming a mounting groove 1a for mounting the LCD screen A. The back of the bracket 1 is provided with several crisscrossing reinforcing ribs to improve the support strength of the bracket 1. A PCB board 4 is bolted to the back of each mounting groove 1a, and the mounting groove 1a is provided with wiring holes for data transmission between the LCD screen A and the PCB board 4.

[0220] A decorative pattern is provided on the glass cover plate 3 corresponding to the decorative section B. In this embodiment, the decorative pattern is a starry sky pattern. A decorative backlight module 5 is bolted to the back of the bracket 1 for each decorative pattern. The bracket 1 has a through hole 1b for exposing the decorative backlight module 5. The decorative pattern is illuminated by the backlight module 5, and the color of the light is adjusted by the decorative backlight module 5 to form ambient lighting and enrich the lighting effect inside the vehicle.

[0221] The back of the bracket 1 has a rear shell 2 that bulges backward from the center, and all the PCB boards 4 and decorative backlight modules 5 are covered by the rear shell 2. The rear shell 2 has multiple data interaction holes for connecting to the car host for each PCB board 4 and decorative backlight module 5.

[0222] The back of bracket 1 has a row of multiple rearwardly extending fixing lugs 1c symmetrically arranged along the vertical center line near the top. The fixing lugs 1c are fixed to the vehicle body with bolts. The rear cover 2 has a clearance hole for each fixing lug 1c to extend from it. The fixing lugs 1c have mounting holes and positioning holes. The mounting holes allow bolts to pass through and be fixed to the vehicle body. The positioning holes allow positioning pins from the vehicle body to pass through, enabling pre-positioning before fixing with bolts.

[0223] The lower part of the back of bracket 1 is also provided with a row of bracket fixing claws 1d, which are used to clamp onto the car body. The rear shell 2 also has a relief hole for each bracket fixing claw 1d to extend out. The provided locking lugs allow bracket 1 to be fixed onto the car body, and the provided bracket fixing claws 1d can directly clamp bracket 1 onto the car body. The use of two different fixing methods improves the fixing stability and also ensures the support stability of bracket 1.

[0224] Each LCD screen A has a pair of fixed lugs 1c on its rear side, which can individually support each LCD screen A and meet the support strength requirements for each LCD screen A. Furthermore, the fixed lugs 1c on the rear side of the central LCD screen A are longer and stronger than the other fixed lugs 1c. Because the support strength requirement is higher in the central section, strengthening the fixed lugs 1c in the central section improves support stability.

[0225] The rear cover 2 has a row of symmetrically arranged insertion holes 2b along the vertical center line near its top for inserting clips from the vehicle body. The insertion holes 2b face upwards, allowing the rear cover 2 to be fixed to the vehicle body. The back of the rear cover 2 has end mounting claws 2a at both ends for fixing it to the vehicle body. These end mounting claws 2a also secure both ends of the rear cover 2 to the vehicle body, achieving two different fixing methods and improving stability.

[0226] The rear end is fixed to the rear of the decorative partition B located at both ends, with the mounting claw 2a positioned to avoid the LCD screen A located in the middle.

[0227] The bracket 1 extends beyond the rear shell 2 on all four sides, and end connecting components 6 located outside the rear shell 2 are provided on the back of both ends of the bracket 1. The end connecting components 6 are used to connect to the vehicle body. Specifically, the end connecting components 6 include upper connecting ears 6a and lower snap-fit ​​ears 6b arranged at intervals. Both upper connecting ears 6a and lower snap-fit ​​ears 6b extend rearward and are vertically arranged. Both upper connecting ears 6a and lower snap-fit ​​ears 6b are provided with positioning holes for the insertion of positioning pins from the vehicle body. The upper connecting ear 6a is also provided with a mounting hole, which is fixed to the vehicle body by bolts passing through the mounting hole. The bottom side of the upper connecting ear 6a is provided with a downwardly extending limiting notch 6a. The limiting notch 6a can be stably hooked onto the vehicle body and is snapped into the snap-fit ​​holes on the two snap-fit ​​ears by the clips of the vehicle body.

[0228] The top two ends of the bracket 1 are bent downwards to form an irregular hexagon. Decorative ribs 1g protrude upwards from the upper edge of the bracket 1, and a positioning rib 1f protrudes forward from the top of the front side of the bracket 1 to position the top edge of the glass cover 3, facilitating the fixing of the glass cover 3 and improving installation efficiency. The decorative ribs 1g and the positioning rib 1f are coated with different colors of high-gloss paint to enhance the aesthetic appeal of the bracket 1.

[0229] The front of bracket 1 is tilted upwards to face the human body, which is a reasonable arrangement. The left and right ends of bracket 1 are tilted backwards to form a slope 1h, which is flush with the outer contour of the car dashboard.

[0230] The bracket 1 has a rearwardly extending positioning pin 1e on its back, and the rear shell 2 has a positioning hole corresponding to the positioning pin 1e for it to pass through. The rear shell 2 is installed on the bracket 1 by bolts. The rear shell 2 can be pre-positioned by the positioning pin 1e and the positioning hole, and then fixed by bolts, which improves installation efficiency.

[0231] The back of the bracket 1 and the perimeter of the rear shell 2 are provided with an edge positioning structure 7. Specifically, the edge positioning structure 7 includes a first limiting protrusion 7a located horizontally on the back of the bracket 1 along the perimeter of the rear shell 2, positioned outside the rear shell 2. A second limiting protrusion 7b is provided on the back of the bracket 1 corresponding to the inner side of the rear shell 2, and the first limiting protrusion 7a and the second limiting protrusion 7b form an edge groove in the rear shell 2 to accommodate the edge of the rear shell 2. The first limiting protrusion 7a and the second limiting protrusion 7b are provided to position the edge of the rear shell 2.

[0232] Multiple clearance notches 2d are recessed at intervals along the bottom edge of the rear shell 2. A boss 7d is provided on the back of the bracket 1 corresponding to the clearance notches 2d along the bottom edge of the rear shell 2. Multiple first bottom locking teeth 7f are arranged at intervals along the horizontal direction along the edge of the clearance notches 2d. The boss 7d is provided with a first bottom locking groove 7c for the first bottom locking teeth 7f to engage. The first bottom locking teeth 7f are symmetrically arranged along the vertical center line of the rear shell 2.

[0233] The portion of the bottom edge of the rear shell 2 without the clearance notch 2d has symmetrically arranged forward-extending second bottom teeth 7e along its vertical center line. The back of the bracket 1 has a second bottom groove 7g corresponding to the second bottom teeth 7e for them to engage. The arrangement of the first bottom teeth 7f, the second bottom teeth 7e, the first bottom groove 7c, and the second bottom groove 7g further improves the positioning and fixation between the rear shell 2 and the bracket 1, avoids misalignment during installation, and improves assembly efficiency.

[0234] A ring of raised dots 2c is provided at intervals along the edge of the back cover 2. The raised dots 2c allow the edge of the back cover 2 to form a gap with the back of the bracket 1, which facilitates heat dissipation.

[0235] The beneficial effects of the above structure are as follows: the forward curve at both ends of the housing conforms to ergonomics and improves the viewing experience. Multiple LCD screens are used to display different content, such as a car instrument panel (first LCD screen), a central control screen (second LCD screen), or an entertainment screen (third LCD screen). The transition areas between the LCD screens are further enhanced by decorative partitions, improving the overall aesthetics of the display assembly and increasing viewing interest. The decorative backlight modules and patterns illuminate the decorative patterns, enhancing the interior lighting atmosphere and providing a richer lighting experience. The glass cover improves the overall integrity of the LCD screens and the decorative partitions, ensuring a harmonious transition. The mounting grooves and through holes allow for the positioning and fixing of the LCD screens and decorative backlight modules, improving assembly efficiency. The rear cover protects all the LCD screens and decorative backlight modules.

[0236] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A multi-screen working method, characterized in that, Includes the following steps: S1, multi-screen startup; S2, after the multi-screen system is started, vehicle information is displayed on the multi-screen system. Step S2 also includes the following steps: S21, The vehicle controller determines whether it has received an entertainment information playback trigger signal: If the vehicle controller receives an entertainment information playback trigger signal, proceed to the next step; If the vehicle controller does not receive an entertainment information playback trigger signal, proceed to step S21; S22, Displaying entertainment information on the first LCD screen and / or the third LCD screen; Before displaying the entertainment information on the first LCD screen and / or the third LCD screen, the following steps are included: S221, The vehicle controller determines whether the entertainment information playback trigger signal is triggered by the first LCD screen or the third LCD screen: If the entertainment information playback trigger signal is triggered by the first LCD screen, proceed to the next step; If the entertainment information playback trigger signal is triggered by the third LCD screen, then step S225 is executed; S222, the on-board controller determines the vehicle status: If the vehicle is in motion, proceed to the next step; If the vehicle is in a parked state, proceed to step S224; S223, the vehicle controller determines whether there is someone sitting in the passenger seat: If there is someone in the passenger seat, entertainment information will be displayed on the third LCD screen; this entertainment information may be movies, TV series, or anime; while entertainment information is displayed on the third LCD screen, the audio information of the entertainment information will be received through Bluetooth headphones. If there is no one in the passenger seat, a prompt will be issued asking you to park the vehicle and watch entertainment information. S224, the vehicle controller determines whether there is someone sitting in the passenger seat: If there is someone in the front passenger seat, entertainment information will be displayed simultaneously on the first and third LCD screens; If there is no one in the passenger seat, entertainment information will be displayed on the first LCD screen; S225, the on-board controller determines the vehicle status: If the vehicle is in motion, entertainment information is displayed on the third LCD screen; while entertainment information is displayed on the third LCD screen, audio information of the entertainment information is received through Bluetooth headphones. If the vehicle is parked, proceed to the next step; S226, The vehicle controller determines whether someone is sitting in the driver's seat: If there is someone in the driver's seat, entertainment information will be displayed simultaneously on the first LCD screen and the third LCD screen; If no one is in the driver's seat, entertainment information will be displayed on the third LCD screen.

2. The multi-screen working method according to claim 1, characterized in that, Vehicle information includes vehicle speed, engine speed, engine coolant temperature, interior and exterior temperatures, light status, and fuel level, or any combination thereof. Light status includes high beams, low beams, and turn signals, or any combination thereof.

3. The multi-screen working method according to claim 1, characterized in that, Step S1 includes activating one or any combination of the first liquid crystal display screen, the second liquid crystal display screen, and the third liquid crystal display screen.

4. The multi-screen working method according to claim 1, characterized in that, The method for starting the first LCD screen includes the following steps: S11, the controller U6 on the first PCB board determines whether the wake-up terminal PTD5 of the controller U6 on the first PCB board receives a first level signal or a second level signal: If the wake-up terminal PTD5 of the controller U6 on the first PCB board receives the first level signal, the controller U6 on the first PCB board will wake up; proceed to the next step. If the wake-up terminal PTD5 of the controller U6 on the first PCB board receives the second level signal, the controller U6 on the first PCB board will be in sleep mode, and the process will return to step S11. S12, the control terminal PTD16 of the controller U6 on the first PCB board inputs an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the first PCB board; at this time, the power supply +VBATT input to the DC-DC buck converter U2 on the first PCB board is converted into a stable power supply +3.3VSW through the DC-DC buck converter U2 on the first PCB board for output; proceed to the next step; S13, the control terminal PTC15 of the controller U6 on the first PCB board inputs a conduction level to the base of the transistor Q4 on the first PCB board, and the transistor Q4 on the first PCB board is in the conducting state. At this time, the gate voltage of the field-effect transistor Q5 on the first PCB board is pulled low, and the field-effect transistor Q5 on the first PCB board is in the conducting state. The power supply +3.3VSW on the source of the field-effect transistor Q5 on the first PCB board is output as power supply +3.3V_TFT through the drain of the field-effect transistor Q5 on the first PCB board. S14, the controller U6 on the first PCB board sends the power-on screen to the first LCD screen through the deserialization chip U1 on the first PCB board, and displays the power-on screen on the first LCD screen; S15, the control terminal PTD16 of the controller U6 on the first PCB board does not input an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the first PCB board; at this time, the DC-DC buck converter U2 on the first PCB board does not work, reducing energy consumption.

5. The multi-screen working method according to claim 1, characterized in that, The method for starting the second LCD screen includes the following steps: S11, the controller U6 on the second PCB board determines whether the wake-up terminal PTD5 of the controller U6 on the second PCB board receives the first level signal or the second level signal: If the wake-up terminal PTD5 of the controller U6 on the second PCB board receives the first level signal, the controller U6 on the second PCB board will wake up and proceed to the next step. If the wake-up terminal PTD5 of the controller U6 on the second PCB board receives the second level signal, then the controller U6 on the second PCB board is in sleep mode, and the process returns to step S11. S12, the control terminal PTD16 of the controller U6 on the second PCB board inputs an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the second PCB board; at this time, the power supply +VBATT input to the DC-DC buck converter U2 on the second PCB board is converted into a stable power supply +3.3VSW through the DC-DC buck converter U2 on the second PCB board for output; proceed to the next step; S13, the control terminal PTC15 of the controller U6 on the second PCB board inputs a conduction level to the base of the transistor Q4 on the second PCB board, and the transistor Q4 on the second PCB board is in the conducting state. At this time, the gate voltage of the field-effect transistor Q5 on the second PCB board is pulled low, and the field-effect transistor Q5 on the second PCB board is in the conducting state. The power supply +3.3VSW on the source of the field-effect transistor Q5 on the second PCB board is output as +3.3V_TFT through the drain of the field-effect transistor Q5 on the second PCB board. S14, the controller U6 on the second PCB board sends the power-on screen to the second LCD screen through the deserialization chip U1 on the second PCB board, and displays the power-on screen on the second LCD screen; S15, the control terminal PTD16 of the controller U6 on the second PCB board does not input an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the second PCB board; at this time, the DC-DC buck converter U2 on the second PCB board does not work, reducing energy consumption.

6. The multi-screen working method according to claim 1, characterized in that, The method for starting the third LCD screen includes the following steps: S11, the controller U6 on the third PCB board determines whether the wake-up terminal PTD5 of the controller U6 on the third PCB board receives the first level signal or the second level signal: If the wake-up terminal PTD5 of the controller U6 on the third PCB board receives the first level signal, the controller U6 on the third PCB board will wake up and proceed to the next step. If the wake-up terminal PTD5 of the controller U6 on the third PCB board receives the second level signal, the controller U6 on the third PCB board will enter sleep mode and return to step S11. S12, the control terminal PTD16 of the controller U6 on the third PCB board inputs an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the third PCB board; at this time, the power supply +VBATT input to the DC-DC buck converter U2 on the third PCB board is converted into a stable power supply +3.3VSW through the DC-DC buck converter U2 on the third PCB board for output; proceed to the next step; S13, the control terminal PTC15 of the controller U6 on the third PCB board inputs a conduction level to the base of the transistor Q4 on the third PCB board, and the transistor Q4 on the third PCB board is in the conducting state. At this time, the gate voltage of the field-effect transistor Q5 on the third PCB board is pulled low, and the field-effect transistor Q5 on the third PCB board is in the conducting state. The power supply +3.3VSW on the source of the field-effect transistor Q5 on the third PCB board is output as +3.3V_TFT through the drain of the field-effect transistor Q5 on the third PCB board. S14, the controller U6 on the third PCB board sends the power-on screen to the third LCD screen through the deserialization chip U1 on the third PCB board, and displays the power-on screen on the third LCD screen; S15, the control terminal PTD16 of the controller U6 on the third PCB board does not input an enable signal to the enable terminal EN of the DC-DC buck converter U2 on the third PCB board; at this time, the DC-DC buck converter U2 on the third PCB board does not work, reducing energy consumption.

7. The multi-screen working method according to claim 4, characterized in that, The calculation method for the first level signal in step S11 is as follows: ， in, This indicates the voltage value of the wake-up terminal PTD5 of the input controller U6, which is the first level signal; This indicates the cutoff voltage of transistor Q1; This indicates the preset voltage first adjustment threshold. >0; The calculation method for the second level signal in step S11 is as follows: ， in, This indicates the voltage value of the wake-up terminal PTD5 of the input controller U6, which is the second level signal; This indicates the voltage of the +3.3V power supply to the MCU. This indicates the preset voltage first adjustment threshold. >0; ＜ 。 8. A multi-screen working method according to claim 1, characterized in that, The multi-screen unit includes a multi-screen body, and a PCB board (4) with the same number of liquid crystal displays is provided in the multi-screen body. Each PCB board (4) is provided with a power module, a wake-up module, a voltage sampling module, a CAN communication module, a controller module, a deserializer module and a screen backlight module. The power module is connected to one or any combination of the wake-up module, voltage sampling module, CAN communication module, controller module, deserializer module and screen backlight module, which are the wake-up module, voltage sampling module, CAN communication module, controller module, deserializer module and screen backlight module. The controller module is connected to the wake-up module, voltage sampling module, CAN communication module, and deserializer module, respectively. The controller module performs signal acquisition and control of the wake-up module, voltage sampling module, CAN communication module, deserializer module, and screen backlight module.

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