A power switch circuit, an electrically programmed fuse memory and an electronic device

Abstract

The embodiment of the application provides a power switch circuit, an electrically programmable fuse memory and an electronic device, and is applied to the technical field of data storage. The electrically programmable fuse memory comprises a power switch circuit and a storage cell array. The power switch circuit comprises a driving circuit, a protection circuit and a programming circuit. The driving circuit comprises a control voltage circuit and a first transistor; the protection circuit protects a second transistor. The control voltage circuit is used for receiving a control signal and a power supply voltage, and generating a control voltage to control the first transistor to output a first voltage to the programming circuit. The programming circuit is used for receiving a programming voltage, and outputting the programming voltage to a storage cell of the storage cell array according to the input first voltage, so as to realize programming of the storage cell. Meanwhile, the control voltage circuit also generates a coupling voltage that turns on the first transistor, thereby causing misprogramming. The second transistor of the protection circuit is used for outputting a second voltage to control the programming circuit not to be affected by the coupling voltage and misprogram.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, in particular to a power switch circuit, an electrically programmed fuse memory and an electronic device. BACKGROUND

[0002] An electrically programmed fuse (EFUSE) memory (also known as one-time programmable memory) is a kind of memory based on electromigration and thermal rupture phenomenon for data storage, which can permanently save programmed information.

[0003] The electrically programmed fuse memory includes a programming circuit and a storage cell array. The programming circuit is configured to output a programming voltage to a storage cell in the storage cell array, and program the storage cell, so as to store data into the storage cell. The programming circuit includes a driving circuit and a programming circuit. The driving circuit is configured to output a control voltage to the programming circuit under the control of a control signal. The programming circuit is configured to output the programming voltage to the storage cell in the storage cell array under the control of the control voltage provided by the driving circuit, so as to program the storage cell.

[0004] In the above-mentioned electrically programmed fuse memory, the driving circuit and the programming circuit usually adopt a double power supply design, that is, the driving circuit inputs a supply voltage, and the programming circuit inputs a programming voltage. This double power supply design has strict requirements on the power-on and power-off sequence of the programming circuit and the driving circuit. When power-on, the driving circuit is required to be powered on before the programming circuit. When power-off, the programming circuit is required to be powered off before the driving circuit. The power-on of the driving circuit refers to that the driving circuit inputs the supply voltage. The power-off of the driving circuit refers to that the driving circuit loses the input supply voltage. The power-on of the programming circuit refers to that the programming circuit inputs the programming voltage. The power-off of the programming circuit refers to that the programming circuit loses the input programming voltage.

[0005] Otherwise, when power-on, if the programming circuit is powered on before the driving circuit, or when power-off, if the driving circuit is powered off before the programming circuit, the internal devices of the driving circuit will generate a floating signal. Due to the capacitive coupling effect, a coupling voltage is generated. The driving circuit will control the programming circuit to output the programming voltage to the storage cell array through the coupling voltage, resulting in an error programming of the storage cell array. SUMMARY

[0006] Embodiments of the present application provide a power switch circuit, an electrically programmed fuse memory and an electronic device, which are used to avoid the capacitive coupling effect in the electrically programmed fuse memory.

[0007] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a power switch circuit is provided for coupling to a memory cell in an array of memory cells to output a program voltage to the memory cell for programming the memory cell. The power switch circuit includes a driving circuit, a programming circuit, and a protection circuit. The driving circuit is powered by a supply voltage, and the programming circuit is powered by the program voltage. The driving circuit includes a control voltage circuit and a first transistor. The protection circuit includes a comparison circuit and a second transistor. An output terminal of the control voltage circuit is coupled to a gate of the first transistor. A first pole of the first transistor is coupled to a control terminal of the programming circuit at a coupling point. A first pole of the second transistor is coupled at the coupling point. The control terminal of the comparison circuit is configured to input the supply voltage. An output terminal of the comparison circuit is coupled to a gate of the second transistor. An output terminal of the programming circuit is coupled to the memory cell for outputting the program voltage. The second transistor has a driving capability greater than a driving capability of the first transistor.

[0009] In the embodiments, when the supply voltage is powered down before the program voltage, or the supply voltage is powered up after the program voltage, the control voltage circuit of the driving circuit generates a coupling voltage. The coupling voltage is transmitted to the programming circuit, causing the programming circuit to be misprogrammed. In the embodiments, the first transistor is used to isolate the coupling voltage generated by the control voltage circuit. When the coupling voltage is lower than a threshold voltage of the first transistor, the first transistor is not turned on. For the case that the coupling voltage is higher than the threshold voltage of the first transistor, the first transistor outputs a first voltage through the first pole to the coupling point, which controls the programming circuit to output the program voltage to the memory cell. In this case, the second transistor is used for processing, specifically, the comparison circuit receives the supply voltage and determines the size of the supply voltage. When the supply voltage is lower than a certain value, the second transistor is turned on by the comparison circuit, so that a second voltage is input through the first pole of the second transistor, which is used to control the programming circuit not to program. In the case that the first transistor and the second transistor are both turned on, the first pole of the second transistor outputs the second voltage at the coupling point, which plays a decisive role in controlling the programming circuit not to output the program voltage to the memory cell. The embodiments solve the problem of misprogramming of the programming circuit caused by the supply voltage being powered down before the program voltage, or the supply voltage being powered up after the program voltage, and also solve the problem of the sequence limitation of the power-on and power-off of the program voltage and the supply voltage.

[0010] In a possible implementation, the control voltage circuit is configured to receive the supply voltage, and when the supply voltage is greater than or equal to a preset value, input a control signal, generate a control voltage according to the control signal, and output the control voltage to the gate of the first transistor. The first transistor is further configured to output a first voltage through the first pole of the first transistor to the control terminal of the programming circuit when the first transistor is turned on due to the gate being controlled by the control voltage.

[0011] The embodiment of the present application controls the voltage circuit to input a control signal when the supply voltage reaches the preset value, generates a control voltage according to the input control signal, and outputs the generated control voltage to the gate of the first transistor, so as to realize the conduction of the first transistor. When the first transistor is turned on, the programming circuit outputs a programming voltage to the storage unit. During the programming stage, only different control signals need to be inputted to realize the control of the programming circuit to program or not to program, which is simple and convenient to operate and has strong stability.

[0012] In a possible implementation, the comparison circuit is further configured to control the second transistor to be turned off when the supply voltage is greater than or equal to the preset value.

[0013] The embodiment of the present application judges whether the supply voltage reaches the preset value through the comparison circuit. When the supply voltage does not reach the preset value, there is a risk of the first transistor being turned on by the coupling voltage and causing misprogramming. At this time, the comparison circuit controls the second transistor to continuously output the second voltage, so as to maintain the programming circuit to output a voltage insufficient for programming the storage unit by the second voltage. When the supply voltage reaches the preset value, the influence of the capacitive coupling effect is reduced, and the coupling voltage is reduced or disappears. At this time, in order to meet the subsequent normal programming, the second transistor needs to no longer output the second voltage. The comparison circuit judges that the supply voltage reaches the preset value, outputs the third voltage to the second transistor, and controls the second transistor to be turned off by the third voltage.

[0014] In some possible implementations, the comparison circuit includes a sixth transistor, a seventh transistor and a Schmitt trigger; the gate of the sixth transistor is used as an input end of the comparison circuit to input the supply voltage; the first pole of the sixth transistor and the first pole of the seventh transistor are coupled to the input end of the Schmitt trigger; the second pole of the sixth transistor is grounded; and the output end of the Schmitt trigger is coupled to the gate of the second transistor as an output end of the comparison circuit.

[0015] The comparison circuit in the embodiment of the application comprises a sixth transistor, a seventh transistor and a Schmitt trigger; a gate of the sixth transistor is configured to input a supply voltage; a first pole of the sixth transistor and a first pole of the seventh transistor are coupled to an input end of the Schmitt trigger; a second pole of the sixth transistor is grounded; a second pole of the seventh transistor is configured to input a fifth voltage; when the supply voltage is less than a preset value, the first pole of the seventh transistor is configured to output the fifth voltage to the input end of the Schmitt trigger; the fifth voltage is configured to control the first pole of the second transistor to output a second voltage through the Schmitt trigger; when the supply voltage is greater than or equal to the preset value, the sixth transistor is turned on due to the gate being subjected to the supply voltage; the first pole of the sixth transistor is configured to output a sixth voltage to the input end of the Schmitt trigger; the sixth voltage is configured to control the second transistor to be turned off through the Schmitt trigger. The fifth voltage and the sixth voltage are voltages representing opposite levels; the third voltage and the fourth voltage are voltages representing opposite levels.

[0016] In some possible implementation manners, the comparison circuit further comprises an eighth transistor; a gate of the eighth transistor is configured to input a programming voltage; the programming voltage is configured to control the eighth transistor to be turned on; a first pole of the eighth transistor is coupled to a second pole of the sixth transistor, and a second pole of the eighth transistor is grounded.

[0017] In the embodiment of the application, the programming voltage is input to the gate of the eighth transistor, and the eighth transistor is controlled to be turned on by the programming voltage. When the programming voltage is not powered on, the sixth transistor cannot provide the third voltage to the Schmitt trigger, regardless of whether the sixth transistor is turned on or not, because the eighth transistor is not turned on, so that it is ensured that the programming circuit always outputs a low voltage that is insufficient to program the storage unit to the storage unit in the case that the programming voltage is not powered on.

[0018] In some possible implementation manners, the comparison circuit further comprises a ninth transistor; a first pole of the ninth transistor is coupled to a second pole of the eighth transistor, and a second pole of the ninth transistor is grounded; a gate of the ninth transistor is connected in parallel to a gate of the sixth transistor, and is configured to input the supply voltage as an input end of the comparison circuit. In the embodiment of the application, the ninth transistor is configured to divide the voltage input to the gate of the sixth transistor, so that the threshold value of the supply voltage for turning on the sixth transistor is improved.

[0019] In some possible implementation manners, the comparison circuit further comprises a first resistor; an input end of the first resistor is configured to input the supply voltage; an output end of the first resistor is coupled to the gate of the sixth transistor, and is configured to output the supply voltage. In the embodiment of the application, the first resistor is configured to limit the current input, so that the sixth transistor and the ninth transistor are protected, and damage of the sixth transistor and the ninth transistor caused by excessive current is avoided.

[0020] In some possible implementation, the programming circuit includes a third transistor and a programming power switch circuit; a control terminal of the programming power switch circuit is a control terminal of the programming circuit, and is coupled to the coupling point together with the first electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor; an output terminal of the programming power switch circuit is an output terminal of the programming circuit, and is configured to be coupled to the storage unit to output the programming voltage to the storage unit; and a driving capability of the third transistor is equal to or less than a driving capability of the first transistor.

[0021] In the embodiment, the first electrode of the third transistor outputs the seventh voltage to the programming power switch circuit, and the seventh voltage controls the programming power switch circuit to output a voltage insufficient for programming the storage unit. When the first transistor is turned on, the current output by the first electrode of the third transistor is led through the first electrode of the first transistor, so that the first electrode of the first transistor outputs the first voltage to the programming power switch circuit, and the first voltage controls the programming power switch circuit to output the programming voltage to the storage unit.

[0022] In some possible implementation, the programming power switch circuit includes an odd number of inverter components; each inverter component includes one NMOS transistor and one PMOS transistor; a gate of the PMOS transistor and a gate of the NMOS transistor of the inverter component are coupled to serve as a control terminal of the inverter component; a drain of the PMOS transistor and a drain of the NMOS transistor of the inverter component are coupled to serve as an output terminal of the inverter component; a source of the PMOS transistor of the inverter component is configured to input the programming voltage; when the programming power switch circuit includes a single inverter component: the control terminal of the single inverter component is a control terminal of the programming power switch circuit, and is coupled to the coupling point together with the first electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor; the output terminal of the single inverter component is an output terminal of the programming power switch circuit, and is configured to be coupled to the storage unit to output the programming voltage to the storage unit; when the programming power switch circuit includes a plurality of inverter components: the output terminal of a front-stage inverter component and the control terminal of a rear-stage inverter component are coupled; the control terminal of the first-stage inverter component is a control terminal of the programming power switch circuit, and is coupled to the coupling point together with the first electrode of the first transistor, the first electrode of the second transistor, and the first electrode of the third transistor; and the output terminal of the last-stage inverter component is an output terminal of the programming power switch circuit, and is configured to be coupled to the storage unit to output the programming voltage to the storage unit.

[0023] The embodiment of the present application forms a programming power switch circuit through odd number of inverter components. When a high voltage is input to the control end of the programming power switch circuit, the programming power switch circuit outputs a low voltage to the storage unit to prevent programming of the storage unit. When a low voltage is input to the control end of the programming power switch circuit, the programming power switch circuit outputs a programming voltage to the storage unit to program the storage unit. The odd number of inverter components have the same effect on the control logic, but the multiple inverter components can increase a certain time delay, and the output is corrected in real time through the time delay, so that when the single inverter component outputs, the output of the inverter component is repeatedly inverted, and the inversion speed is too fast, and the output is not stable.

[0024] In some possible implementation, the second pole of the third transistor is used to input the programming voltage.

[0025] In the embodiment of the present application, the second pole of the third transistor is used to output a high voltage to control the programming power switch circuit to output a low voltage to the storage unit. The high voltage can be provided by an additional voltage device, or can be provided by the programming voltage. Providing the high voltage by the programming voltage can reduce the setting of additional power devices, and at the same time can ensure the synchronization of the high voltage and the programming voltage, and increase the stability of the system.

[0026] In some possible implementation, the control voltage circuit includes a first inverter, a NAND gate, and an inverter group; the inverter group includes an odd number of second inverters; the input end of the first inverter is used to receive a first control signal, and the output end of the first inverter is coupled with the first input end of the NAND gate; the second input end of the NAND gate is used to receive a second control signal; the output end of the NAND gate is connected with the input end of the inverter group; and the output end of the inverter group, as the output end of the control voltage circuit, is coupled with the gate of the first transistor, and is used to output the control voltage.

[0027] In the embodiment of the present application, when the supply voltage reaches a preset value to start programming, the control voltage circuit inputs a control signal, generates a control voltage according to the input control signal, and outputs the generated control voltage to the gate of the first transistor, so as to realize the conduction of the first transistor. When the first transistor is turned on, the programming circuit outputs a programming voltage to the storage unit. During the programming stage, only different control signals need to be input to realize the control of the programming circuit to program or not to program, which is simple and convenient to operate, and has strong stability. The control signal includes a first control signal and a second control signal, and the first control signal, the second control signal, and the first inverter, the NAND gate, and the inverter group jointly control whether the control voltage circuit outputs the control voltage to the gate of the first transistor, so as to realize the control of the programming.

[0028] In some possible implementation manners, the driving circuit further includes a fourth transistor, a first electrode of the fourth transistor is coupled with a second electrode of the first transistor, a second electrode of the fourth transistor is grounded, and a gate electrode of the fourth transistor is configured to input a programming voltage; and the programming voltage is configured to turn on the fourth transistor.

[0029] In the embodiment of the application, the fourth transistor is turned on by the programming voltage. The fourth transistor is ensured to be turned on only when the programming voltage is powered on, so that the second electrode of the first transistor is grounded.

[0030] In some possible implementation manners, the driving circuit further includes a fifth transistor, a gate electrode of the fifth transistor is coupled with the gate electrode of the first transistor in parallel and configured to be coupled with an output terminal of the control voltage circuit, a first electrode of the fifth transistor is coupled with the second electrode of the fourth transistor, and a second electrode of the fifth transistor is grounded.

[0031] In the embodiment of the application, the fifth transistor is used to divide the voltage of the first transistor, so as to improve the isolation capability of the first transistor to the coupling voltage.

[0032] In some possible implementation manners, the second electrode of the second transistor is configured to input the programming voltage.

[0033] In the embodiment of the application, the high voltage is output to the programming circuit through the second electrode of the second transistor, so as to control the programming power switch circuit to output the low voltage that is insufficient to program the storage unit to the storage unit. The high voltage can be provided by an additional voltage device or by the programming voltage. The high voltage provided by the programming voltage can reduce the setting of the additional power device, and can ensure the synchronization of the high voltage and the programming voltage powered on, and increase the stability of the system.

[0034] In a second aspect, an electrically programmable fuse memory is provided, which includes the power switch circuit and the storage unit array as described in the first aspect, and the power switch circuit is configured to input a power supply voltage, a control signal and a programming voltage, and output the programming voltage to the storage unit in the coupled storage unit array according to the control signal; and the programming voltage is configured to program the storage unit.

[0035] In a third aspect, an electronic device is provided, which includes the power switch circuit and an interface circuit as described in the first aspect, and the power switch circuit is configured to input a power supply voltage, a control signal and a programming voltage, and output the programming voltage to the storage unit in the coupled storage unit array through the interface circuit according to the control signal; and the programming voltage is configured to program the storage unit.

[0036] The technical effects of the second aspect and the third aspect are described with reference to the description of the first aspect, and thus will not be described again. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A structure schematic diagram of an electrically programmed fuse memory provided by an embodiment of the present application is shown in FIG. 1.

[0038] Figure 2 A structure schematic diagram of another electrically programmed fuse memory provided by an embodiment of the present application is shown in FIG. 2.

[0039] Figure 3 A structure schematic diagram of a power switch circuit provided by an embodiment of the present application is shown in FIG. 3.

[0040] Figure 4 A structure schematic diagram of another power switch circuit provided by an embodiment of the present application is shown in FIG. 4.

[0041] Figure 5 A structure schematic diagram of a programming circuit provided by an embodiment of the present application is shown in FIG. 5.

[0042] Figure 6 A structure schematic diagram of another electrically programmed fuse memory provided by an embodiment of the present application is shown in FIG. 6.

[0043] Figure 7 A structure schematic diagram of a Schmitt trigger provided by an embodiment of the present application is shown in FIG. 7.

[0044] Figure 8 A comparison schematic diagram of voltage changes of each part in a power-on stage and a programming stage provided by an embodiment of the present application is shown in FIG. 8.

[0045] Figure 9 A comparison schematic diagram of voltage changes of each part in a power-on stage and a programming stage provided by an embodiment of the present application is shown in FIG. 9.

[0046] Figure 10 A comparison schematic diagram of voltage changes of each part in a power-down stage provided by an embodiment of the present application is shown in FIG. 10.

[0047] Figure 11 A comparison schematic diagram of voltage changes of each part in a power-down stage provided by an embodiment of the present application is shown in FIG. 11.

[0048] Figure 12 A structure schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 12. DETAILED DESCRIPTION

[0049] It should be noted that the terms "first", "second", etc. involved in the embodiments of the present application are only used for distinguishing the same type of features, and cannot be understood as indicating relative importance, quantity, sequence, etc.

[0050] The term "exemplary" or "for example" is used herein to mean an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the exemplary or for example embodiments are presented so as to enable a clear and concise disclosure of the disclosure.

[0051] The term "coupled" or "connected" should be construed broadly in the context of the embodiments described herein, for example, it can refer to a direct connection, or an indirect connection via an electronic device, for example, a connection via a resistor, inductor, capacitor or other electronic device.

[0052] First, some basic concepts of the embodiments of the present application are explained:

[0053] The driving capability refers to the size of the load capacity, the influencing factor is the size of the load of the subsequent device, and the performance mainly includes the size of the voltage requirement and the size of the current requirement. Taking the voltage requirement as an example, if the voltage required by the subsequent device for normal operation is 5V, the driving capability of the current device refers to: the voltage output by the current device meets the requirement that after the subsequent device is connected, under the influence of the load of the subsequent device, the voltage remains stable or the voltage will not be reduced to below 5V due to the load of the subsequent device. Taking the current requirement as an example, if the current required by the subsequent device for normal operation is 5A, the driving capability of the current device refers to: the current output by the current device meets the requirement that after the subsequent device is connected, under the influence of the load of the subsequent device, the current remains stable or the current will not be reduced to below 5A due to the load of the subsequent device. The size of the driving capability of the electronic device can be selected and adjusted according to the properties and parameters of the device.

[0054] Electrically programmable fuse (EFUSE) memory, also known as one-time programmable memory, is a type of memory that stores data based on electromigration and thermal breakdown phenomena, and can permanently save programmed information. The birth of EFUSE is based on a discovery that electron migration (EM) characteristics can be used to generate smaller fuse structures, i.e. EM fuses, compared with older laser fuse technology. EM fuses can be programmed on a chip, whether in the wafer probing phase or in the packaging phase. A 10-mA direct current pulse lasting 200 microseconds provided by the on-chip voltage of the I / O circuit alone is enough to program a single EM fuse. Unlike static random access memory (SRAM) arrays used by most field programmable gate arrays (FPGAs), only one EM fuse in the EFUSE memory can be programmed at a time, which is the reason for the limited range of configuration capabilities of this method. However, when combined with increasingly mature built-in self-test (BIST) engines, these EM fuses become powerful tools that can reduce the cost of testing and self-repairing, which is required for complex chip designs.

[0055] As shown in Figure 1 , an embodiment of the present application provides an electrically programmable fuse memory 1, which includes a power switch circuit 10, a storage unit array 20, a row decoding circuit 30, a column decoding circuit 40, a control circuit 50, and a sense amplifier 60. The power switch circuit 10 is configured to provide a programming voltage to the storage unit array 20, and program storage units 210 in the storage unit array 20 by the programming voltage, so as to store data into the storage units 210; the control circuit 50 is configured to control the row decoding circuit 30 and the column decoding circuit 40 to decode a physical address in a read / write command, so as to determine a corresponding storage unit 210; and the sense amplifier 60 is configured to read data stored in the storage unit 210.

[0056] In some possible embodiments, as shown in Figure 2 , the power switch circuit 10 includes a driving circuit 110 and a programming circuit 120; the programming circuit 120 is configured to receive a programming voltage; the programming voltage is configured to be output to the storage units 210, so as to program the storage units 210; the driving circuit 110 is configured to receive a control signal and a power supply voltage, and generate a control voltage according to the control signal; the control voltage is configured to control the programming circuit 120 to output the programming voltage to the storage units 210 of the storage unit array 20; and the power supply voltage is configured to supply power for the driving circuit 110.

[0057] Exemplarily, the control signals include a first control signal and a second control signal. As shown in Figure 3 The driving circuit 110 includes a control voltage circuit 111. The control voltage circuit 111 includes a first inverter 1111, a NAND gate 1112, and an inverter group 1113. The inverter group 1113 includes an odd number of second inverters. When there are multiple second inverters, the multiple second inverters are connected in series. The input end of the first inverter 1111 is configured to receive the first control signal. The output end of the first inverter 1111 is coupled to the first input end of the NAND gate 1112. The second input end of the NAND gate 1112 is configured to receive the second control signal. The output end of the NAND gate 1112 is connected to the input end of the inverter group 1113. The output end of the inverter group 1113 is configured to output a control voltage to the programming circuit 120. When the first control signal is a low voltage and the second control signal is a high voltage, the control voltage circuit 111 outputs the control voltage through the output end of the inverter group 1113. At this time, the control voltage is a high voltage. When the first control signal and the second control signal are in other cases, the control voltage circuit 111 outputs a low voltage through the output end of the inverter group 1113.

[0058] As shown in Figure 3 The programming circuit 120 includes a programming power switch circuit 121. The programming power switch circuit 121 includes an even number of cascaded inverter components 1211. The control end of the first inverter component 1211 is configured to receive the control voltage of the programming circuit 120. The output end of the last inverter component 1211 is configured to output a programming voltage or a low voltage. The output end of the inverter component 1211 of the previous stage is coupled to the control end of the inverter component 1211 of the next stage. For a single inverter component 1211, the first pole of the inverter component 1211 is configured to input the programming voltage, and the second pole is configured to input the low voltage. The inverter component 1211 is configured to output the low voltage when the control end of the inverter component 1211 inputs the high voltage, and output the programming voltage when the control end of the inverter component 1211 inputs the low voltage. The control voltage circuit 111 outputs the control voltage as a high voltage to the programming circuit 120. After the programming circuit 120 receives the control voltage as a high voltage, the programming circuit 120 outputs the programming voltage as a high voltage to the storage unit 210 through the coupled inverter components 1211.

[0059] The even number of cascaded inverter components 1211 are equivalent to no inverter components 1211 in terms of the logic of the output signal. However, the even number of inverter components 1211 can form an oscillator to make the output voltage signal reach a steady state and avoid voltage competition. Figure 3In the embodiment, the inverter assembly 1211 functions to output a programming voltage as a high voltage when receiving a control voltage output by the control voltage circuit 111 as a high voltage. For an odd number of inverter assemblies 1211, the single inverter assembly 1211 and the multiple odd number of inverter assemblies 1211 are set to be consistent in the logic of the output signal, but the multiple inverter assemblies 1211 can increase a certain time delay, correct the output in real time through the time delay, and avoid the case where the single inverter assembly 1211 outputs, the inversion speed is too fast when the output of the inverter assembly 1211 repeatedly inverts, and the output has no steady state.

[0060] Exemplarily, in the process of working operation of the electrically programmable fuse memory 1 based on Figure 2 and Figure 3 , the process can be divided into the following three stages: power-on stage, programming stage and power-off stage. In the power-on stage, it is divided into two power-on processes: driving power-on and programming power-on. The process of inputting the supply voltage by the driving circuit 110 is driving power-on, and the process of inputting the programming voltage by the programming circuit 120 is programming power-on. In the programming stage, the driving power-on and the programming power-on have been completed, the supply voltage reaches the preset value, the driving circuit 110 starts to receive the control signal, and generates the control voltage according to the control signal, and controls the programming circuit to output the programming voltage to the storage unit 210 of the storage unit array 20 to realize the programming of the storage unit 210. Among them, the preset value is the minimum voltage value required for the driving circuit 110 to work normally. After the programming is completed, the power-off stage is entered. In the power-off stage, it is also divided into two power-off processes: driving power-off and programming power-off. The process of losing the input supply voltage by the driving circuit 110 is driving power-off, and the process of losing the programming voltage by the programming circuit 120 is programming power-off.

[0061] And in the process of working operation of the electrically programmable fuse memory 1 based on Figure 2 and Figure 3The power switch circuit 10 of the electrically programmable fuse memory 1 has strict requirements for the sequence of power-on and power-off between the driving circuit 110 and the programming circuit 120 during the programming of the storage unit 210. In the power-on stage before starting the programming, the driving circuit 110 needs to be powered on before the programming circuit 120, that is, the driving power-on is earlier than the programming power-on; in the power-off stage after ending the programming, the driving circuit 110 needs to be powered off after the programming circuit 120, that is, the driving power-off is later than the programming power-off. Otherwise, in the power-on stage, if the programming circuit 120 is powered on before the driving circuit 110, or in the power-off stage, if the driving circuit 110 is powered off before the programming circuit 120, when the driving circuit 110 is powered on, the internal devices of the driving circuit 110 will generate floating signals, and due to the capacitive coupling effect, a coupling voltage will be generated in the driving circuit 110 and output to the programming circuit 120. Under the control of the coupling voltage, the programming circuit 120 will output the programming voltage to the storage unit array 20, causing the storage unit 210 in the storage unit array 20 to be programmed incorrectly.

[0062] To this end, as shown in Figure 4 the embodiment of the present application provides another electrically programmable fuse memory 1, which comprises a power switch circuit 10 and a storage unit array 20. The power switch circuit 10 comprises a driving circuit 110, a programming circuit 120 and a protection circuit 130. The protection circuit 130 is coupled at a coupling point 140 between the output end of the driving circuit 110 and the control end of the programming circuit 120. Among them, the input end of the programming circuit 120 is used to input the programming voltage; the output end of the programming circuit 120 is coupled to the storage unit 210 in the storage unit array 20, and is used to output the programming voltage. The driving circuit 110 comprises a control voltage circuit 111 and a first transistor 112; the protection circuit 130 comprises a comparison circuit 131 and a second transistor 132.

[0063] The control end of the control voltage circuit 111 is used to receive a control signal; the input end of the control voltage circuit 111 is used to input a supply voltage; the output end of the control voltage circuit 111 is coupled to the gate of the first transistor 112, and outputs a coupling voltage or a control voltage generated according to the control signal; the coupling voltage and the control voltage control the first transistor 112 to output a first voltage to the coupling point 140; the first voltage is used to control the programming circuit 120 to output the programming voltage to the storage unit 210. The input end of the comparison circuit 131 is used to input the supply voltage; the output end of the comparison circuit 131 is coupled to the gate of the second transistor 132, and is used to output a fourth voltage when the supply voltage is less than a preset value; the fourth voltage is used to control the first electrode of the second transistor 132 to output a second voltage.

[0064] The first terminal of the first transistor 112 in the driving circuit 110 and the first terminal of the second transistor 132 in the protection circuit 130 are coupled together to the terminal of the programming circuit 120. The driving capability of the second transistor 132 is greater than that of the first transistor 112. When the first terminal of the first transistor 112 outputs a first voltage to the coupling point 140, the programming circuit 120 outputs a programming voltage to the memory cell 210. When the first terminal of the first transistor 112 outputs a first voltage to the coupling point 140, and the first terminal of the second transistor 132 outputs a second voltage to the coupling point 140, because the driving capability of the second transistor 132 is greater than that of the first transistor 112, the second voltage output from the first terminal of the second transistor 132 at the coupling point 140 pulls up the voltage at the coupling point 140, and the programming circuit 120 outputs a low voltage to the memory cell 210 that is insufficient to program the memory cell 210.

[0065] For example, such as Figure 4 As shown, during the power-on phase, when the programming power-on precedes the driving power-on, the control voltage circuit 111 inputs the supply voltage. The supply voltage gradually increases until it reaches a preset value and then stabilizes.

[0066] Before the supply voltage increases to a preset value, as the supply voltage increases, the control voltage circuit 111 generates a floating signal and a coupling voltage under the capacitive coupling effect caused by the programming voltage. The control voltage circuit 111 outputs the generated coupling voltage to the gate of the first transistor 112. The first transistor 112 is turned on due to the coupling voltage at its gate, and the first transistor 112 outputs a first voltage to the coupling point 140 through its first electrode. The first electrode of the second transistor 132 outputs a second voltage to the coupling point 140. The first voltage and the second voltage work together to obtain the voltage at the coupling point 140, and the voltage at the coupling point 140 controls the programming circuit 120 to output a low voltage to the memory cell 210.

[0067] After the supply voltage reaches the preset value, the supply voltage tends to stabilize. At this time, the floating signal inside the control voltage circuit 111 disappears, and the control voltage circuit 111 stops outputting the coupling voltage to the first transistor 112. The first transistor 112 is turned off, and the first electrode of the first transistor 112 does not output the first voltage to the coupling point 140. The programming circuit 120 outputs a low voltage to the storage cell 210.

[0068] The embodiments of this application are as follows: Figure 4In the electrically programmable fuse memory 1 shown, the first transistor 112 in the drive circuit 110 performs preliminary interference filtering on the coupling voltage. Specifically, when the coupling voltage input to the gate of the first transistor 112 exceeds a certain value, the first transistor 112 will conduct, leading to misprogramming. Therefore, for coupling voltages that do not reach the threshold voltage of the first transistor 112, interference filtering can be achieved through the first transistor 112. However, the coupling voltage is uncontrollable, and the first transistor 112 cannot guarantee complete isolation of the coupling voltage. Furthermore, the first transistor 112 cannot be a transistor that requires excessively high voltage to conduct, because to ensure subsequent normal programming operations, it is also necessary to ensure that the control voltage can stably turn on the first transistor 112. Based on this situation, a protection circuit 130 is set up. The comparison circuit 131 of the protection circuit 130 judges whether the power supply voltage has reached the preset value. When the power supply voltage has not reached the preset value, the first electrode of the second transistor 132 outputs a second voltage to the coupling point 140. The voltage at the coupling point obtained by the combined action of the second voltage and the first voltage controls the programming circuit 120 to output a low voltage to the storage unit 210.

[0069] The design of protection circuit 130 is based on the relationship between supply voltage and coupling voltage. Figure 8 A schematic diagram of the power-on and programming stages when the first transistor 112 is set in the drive circuit 110; Figure 9 This diagram illustrates the power-on and programming stages when a protection circuit 130 is added in addition to the first transistor 112.

[0070] like Figure 8 As shown: When the power supply voltage is initially powered on, the control voltage circuit 111 generates a coupling voltage and outputs it to the gate of the first transistor 112. During the growth phase after the power supply voltage is powered on, the coupling voltage increases with the power supply voltage. At time t1, the coupling voltage reaches a level that can turn on the first transistor 112, at which point the first transistor 112 is turned on, and the programming circuit 120 performs misprogramming and outputs a programming voltage. As the power supply voltage continues to increase, the coupling voltage begins to decrease, the first transistor 112 turns off, and the programming circuit 120 begins to output a low voltage. When the power supply voltage reaches a preset value at time t2 and tends to stabilize, the coupling voltage disappears, the first transistor 112 remains off, and the programming circuit 120 continues to output a low voltage. Then, at time t3, a control signal is input to the control voltage circuit 111, which generates a control voltage and outputs it to the gate of the first transistor 112, and the programming circuit 120 begins to output a programming voltage.

[0071] After using the protection circuit provided in the embodiments of this application, such as Figure 9As shown, before reaching the t1 moment, the coupling circuit reaches a degree that can turn on the first transistor 112, at this time, the first transistor 112 is turned on, but the second voltage output by the second transistor 132 in the protection circuit 130 controls the low voltage output by the programming circuit 120. Before the t1 moment, the coupling voltage disappears. Then at the t2 moment, the supply voltage reaches the preset value that meets the normal work, at this moment, the second transistor 132 no longer outputs the second voltage to the programming circuit 120. Then at the t3 moment, the control voltage circuit 111 generates the control voltage through the input control signal, and turns on the first transistor 112 through the control voltage, so as to control the programming circuit 120 to program. The embodiment of the application avoids the problem that the floating signal generated by the control voltage circuit 111 in combination with the capacitive coupling effect causes the programming circuit 120 to be misprogrammed in the process of the supply voltage increasing.

[0072] In addition, Figure 10 A schematic diagram of a power-off stage when the first transistor 112 is arranged in the driving circuit 110; Figure 11 A schematic diagram of a power-off stage when the protection circuit 130 is further arranged on the basis of the first transistor 112. As Figure 10 As shown, when the supply voltage drops to about 0.249V, the programming circuit 120 stops outputting the programming voltage. After the protection circuit 130 is arranged, as Figure 11 As shown, when the supply voltage drops to 0.603V, the programming circuit 120 has already stopped outputting the programming voltage. Therefore, in addition to avoiding the misprogramming of the programming circuit 120 in the power-on stage, the embodiment of the application can also make the programming circuit 120 respond more quickly to stop programming in the power-off stage.

[0073] In some possible implementation manners, when the supply voltage reaches the preset value and enters the programming stage. As Figure 4 As shown, the comparison circuit 131 is configured to output a third voltage to the gate of the second transistor 132 when the received supply voltage is greater than or equal to the preset value, and the third voltage is used to control the second transistor 132 to be turned off, that is, in the programming stage, the second transistor 132 does not control the programming circuit 120. The control voltage circuit 111 is configured to receive the control signal and output the control voltage generated according to the control signal to the gate of the first transistor 112. The first transistor 112 is turned on due to the gate being controlled by the control voltage, so as to output the first voltage to the coupling point 140 through the first pole of the first transistor 112, and the programming circuit 120 outputs the programming voltage to the storage unit 210 through the first voltage.

[0074] In some possible implementation manners, as Figure 5As shown, the programming circuit 120 comprises a programming power switch circuit 121 and a third transistor 122. The control end of the programming power switch circuit 121 is coupled with the first electrode of the first transistor 112, the first electrode of the second transistor 132 and the first electrode of the third transistor 122; the driving capability of the third transistor 122 is equal to or less than the driving capability of the first transistor; the first electrode of the third transistor 122 is used to output a seventh voltage; the seventh voltage is used to control the programming power switch circuit 121 to output a low voltage to the storage unit 210; the programming power switch circuit 121 is used to input a programming voltage through the input end of the programming power switch circuit 121 and output the programming voltage to the storage unit 210 through the output end of the programming power switch circuit 121; if the control end of the programming power switch circuit 121 inputs the first voltage, a low voltage insufficient to program the storage unit 210 is output to the storage unit 210; if the control end of the programming power switch circuit 121 inputs the seventh voltage, the programming voltage is output to the storage unit 210.

[0075] Exemplarily, the first transistor 112 is an NMOS tube, the drain of the first transistor 112 is used as the first electrode to output the first voltage and the source is used as the second electrode. The second transistor 132 is a PMOS tube, the drain of the second transistor 132 is used as the first electrode to output the second voltage and the source is used as the second electrode to receive the high voltage. The third transistor 122 is a PMOS tube, the drain of the third transistor 122 is used as the first electrode to output the seventh voltage and the source is used as the second electrode to receive the high voltage. The programming power switch circuit 121 comprises an odd number of inverter components 1211; for a single inverter component 1211, it comprises an NMOS tube and a PMOS tube; the gate of the PMOS tube and the gate of the NMOS tube of the inverter component 1211 are coupled to serve as the control end of the inverter component 1211; the drain of the PMOS tube and the drain of the NMOS tube of the inverter component 1211 are coupled to serve as the output end of the inverter component 1211; the source of the PMOS tube of the inverter component 1211 serves as the first input end of the inverter component 1211 to input the programming voltage; the source of the NMOS tube of the inverter component 1211 serves as the second input end of the inverter component 1211 to input the low voltage; when there are multiple inverter components 1211, the multiple inverter components 1211 are cascaded through the output end of the previous inverter component 1211 and the control end of the next inverter component 1211.

[0076] Before driving power-up: the supply voltage is 0. The low voltage is continuously input to the gate of the third transistor 122 which is a PMOS tube, so that the third transistor 122 remains on, and the high voltage is input to the second pole of the third transistor 122, so that the first pole of the on third transistor 122 outputs the seventh voltage which is high voltage to the coupling point 140. For the single inverter component 1211, when the control end inputs high voltage, the output end outputs low voltage, and when the control end inputs low voltage, the output end outputs programming voltage. The programming power switch circuit 121 continuously outputs low voltage to the storage unit 210 through the seventh voltage which is high voltage and the odd number of inverter components 1211.

[0077] After programming power-up and before driving power-up: the control voltage circuit 111 generates the coupling voltage and outputs the coupling voltage to the gate of the first transistor 112. The first transistor 112 which is an NMOS tube presents the on state after receiving the coupling voltage which is high voltage. Because the driving ability of the third transistor 122 is less than or equal to the driving ability of the first transistor 112, the first transistor 112 drags the current output by the first pole of the third transistor to the second pole of the first transistor 112, at this time the second pole of the first transistor 112 is grounded, and the first pole of the third transistor 122 does not provide the seventh voltage to the programming power switch circuit 121, but provides the first voltage which is low voltage to the programming power switch circuit 121 through the first pole of the first transistor 112. If the first voltage which is low voltage is directly input to the programming power switch circuit 121, it will cause the programming power switch circuit 121 to misprogram and output the programming voltage. But at this time, because the supply voltage is lower than the preset value, after the comparison circuit of the protection circuit 130 inputs the supply voltage which is lower than the preset value, it inputs the fourth voltage which is low voltage to the gate of the second transistor 132 through the output end; the fourth voltage which is low voltage makes the second transistor 132 which is a PMOS tube on. The high voltage is input to the second pole of the second transistor 132, so that the first pole of the on second transistor 132 outputs the second voltage which is high voltage to the coupling point 140. At this time, because the driving ability of the second transistor 132 is greater than the driving ability of the first transistor 112, the second voltage which is high voltage output by the first pole of the second transistor 132 dominates over the first voltage which is low voltage at the coupling point 140. Further, when the first voltage and the second voltage are both output to the coupling point 140, the second voltage pulls up the voltage at the coupling point 140; so that the control end of the programming power switch circuit 121 inputs high voltage through the coupling point 140, and outputs low voltage, not high voltage, from the output end to the storage unit 210.

[0078] When the power supply voltage is stable, the comparison circuit 131 inputs the power supply voltage which is greater than or equal to the preset value, and outputs the third voltage which is high voltage to the gate of the second transistor 132. The second transistor 132 is a PMOS transistor, and is turned off due to the high voltage received by the gate. The second transistor 132 no longer outputs the second voltage to the coupling point 140. Due to the stable power supply voltage, the influence of the capacitive coupling effect is reduced or eliminated, so that the coupling voltage in the control voltage circuit 111 is reduced, the voltage of the gate of the first transistor 112 is low voltage, the first transistor 112 which is an NMOS transistor is turned off, and the seventh voltage is directly output from the first electrode of the third transistor 122 to the programming power supply switch circuit 121. The seventh voltage controls the programming power supply switch circuit 121 to output low voltage to the storage unit 210.

[0079] When the programming stage starts, the control signal is input to the control voltage circuit 111. When programming is needed, the control voltage circuit 111 generates the control voltage according to the control signal. The control voltage which is high voltage turns on the first transistor 112, so that the current output from the first electrode of the third transistor 122 is led away through the first electrode of the first transistor 112. The first electrode of the first transistor 112 outputs the first voltage which is low voltage. The first voltage controls the programming power supply switch circuit 121 to output the programming voltage to the storage unit 210. When programming is not needed, the control voltage circuit 111 does not generate the control voltage according to the control signal, so that the first transistor 112 is not turned on due to the low voltage input to the gate. At this time, the first electrode of the third transistor 122 outputs the seventh voltage to the coupling point 140. The seventh voltage controls the programming power supply switch circuit 121 to output low voltage to the storage unit 210.

[0080] For example, the seventh voltage input to the second electrode of the third transistor 122 can be provided by the programming voltage. The programming voltage is input to the second electrode of the turned-on third transistor 122, so that the first electrode of the third transistor 122 continuously outputs the seventh voltage to the coupling point 140.

[0081] The seventh voltage is generated by using the programming voltage, and no additional power supply is needed. At the same time, the function of the seventh voltage is to control the programming circuit 120 to output low voltage instead of the programming voltage to the storage unit 210 after the programming voltage is powered on. Therefore, the seventh voltage and the programming voltage have synchronism by using the programming voltage to generate the seventh voltage, and the stability of the circuit is improved.

[0082] In some possible implementation manners, as shown in Figure 5 The driving circuit 110 further includes a fourth transistor 113. The first electrode of the fourth transistor 113 is coupled with the second electrode of the first transistor. The second electrode of the fourth transistor is grounded. The gate of the fourth transistor is used to input the programming voltage. The programming voltage is used to turn on the fourth transistor.

[0083] Exemplarily, the fourth transistor 113 is an NMOS transistor. When the gate of the fourth transistor 113 inputs a programming voltage, the gate is a high voltage, at this time, the fourth transistor 113 is turned on.

[0084] The embodiment of the present application sets the fourth transistor 113, which realizes that only when the programming power-on is completed, that is, the input is the programming voltage, the fourth transistor 113 can be turned on to ground, so that the first transistor 112 can pull down the voltage at the coupling point 140 by turning on the ground and output the first voltage. Without the input of the programming voltage, the fourth transistor 113 is not turned on, so whether the first transistor 112 is turned on or not, the voltage at the coupling point 140 will not be pulled down, thereby ensuring that the programming power switch circuit 121 always outputs a low voltage without the programming voltage.

[0085] In some possible implementation manners, as shown in Figure 5 The driving circuit 110 further includes a fifth transistor 114. The gate of the fifth transistor 114 is connected in parallel with the gate of the first transistor 112, and receives the coupling voltage or the control voltage together. The first electrode of the fifth transistor 114 is connected with the second electrode of the fourth transistor 113, and the second electrode of the fifth transistor 114 is grounded.

[0086] Exemplarily, the fifth transistor 114 is an NMOS transistor. The fourth transistor 113 realizes the turn-off or turn-on between the first transistor 112 and the fifth transistor 114. The fifth transistor 114 is set to realize voltage division. When the coupling voltage is generated, the coupling voltage needs to reach a certain threshold value to turn on the first transistor 112. Therefore, the first transistor 112 can filter the coupling voltage below a certain threshold value. For the case that the coupling voltage is higher than a certain threshold value to turn on the first transistor 112, the second voltage output by the second transistor 132 is needed to eliminate the influence of the coupling voltage. The fifth transistor 114 is set to divide the voltage, which can increase the threshold value.

[0087] In some possible implementation manners, as shown in Figure 6As shown, the comparison circuit 131 includes a sixth transistor 1311, a Schmitt trigger 1312 and a seventh transistor 1313. The first pole of the sixth transistor 1311 and the first pole of the seventh transistor 1313 are commonly coupled to the input end of the Schmitt trigger 1312; the second pole of the sixth transistor 1311 is grounded; the gate of the sixth transistor 1311 is used as the control end of the comparison circuit 131, for inputting the supply voltage. When the supply voltage is less than the preset value, the first pole of the seventh transistor 1313 is used to output the fifth voltage to the input end of the Schmitt trigger 1312; the fifth voltage is used to control the Schmitt trigger 1312 to output the fourth voltage; when the supply voltage is greater than or equal to the preset value, the sixth transistor 1311 is turned on due to the gate being subjected to the supply voltage; the first pole of the sixth transistor 1311 is used to output the sixth voltage to the input end of the Schmitt trigger 1312; the sixth voltage is used to control the Schmitt trigger 1312 to output the third voltage.

[0088] Exemplarily, as Figure 7As shown, it is a Schmitt trigger 1312 composed of MOS tubes, which includes a first PMOS tube 13121, a second PMOS tube 13122, a third PMOS tube 13123, a first NMOS tube 13124, a second NMOS tube 13125, and a third NMOS tube 13126; wherein the gate of the first PMOS tube 13121, the gate of the second PMOS tube 13122, the gate of the first NMOS tube 13124, and the gate of the second NMOS tube 13125 are connected in parallel as the control end of the Schmitt trigger 1312; the drain of the second PMOS tube 13122 and the drain of the first NMOS tube 13124 are connected in parallel as the output end of the Schmitt trigger 1312; the drain of the first PMOS tube 13121 and the source of the second PMOS tube 13122 are connected with the source of the third PMOS tube 13123; the source of the first NMOS tube 13124 and the drain of the second NMOS tube 13125 are connected with the source of the third NMOS tube 13126; the gate of the third PMOS tube 13123 is connected with the gate of the third NMOS tube 13126; the source of the first PMOS tube 13121 and the drain of the third NMOS tube 13126 are respectively used as the positive voltage connection end of the Schmitt trigger 1312 for receiving a high voltage signal; the source of the second NMOS tube 13125 and the drain of the third PMOS tube 13123 are respectively used as the negative voltage connection end of the Schmitt trigger 1312 for receiving a low voltage signal. Compared with a general trigger, the Schmitt trigger 1312 has two stable states, and the Schmitt trigger 1312 adopts a potential trigger mode, and its state is maintained by the input signal potential; for input signals with two different change directions of negative direction decrease and positive direction increase, the Schmitt trigger 1312 has different threshold voltages, which are respectively called positive threshold voltage and negative threshold voltage. The positive threshold voltage and the negative threshold voltage are determined by the voltage corresponding to the voltage input by the positive voltage connection end and the negative voltage connection end of the Schmitt trigger 1312. In the process of rising from low voltage to high voltage of the voltage input by the control end, when the input voltage reaches the voltage value of the positive threshold voltage, the circuit state of the Schmitt trigger 1312 changes, so as to output low voltage. In the process of reducing from high voltage to low voltage of the voltage input by the control end, when the input voltage reaches the voltage value of the negative threshold voltage, the circuit state of the Schmitt trigger 1312 changes, so as to output high voltage.

[0089] Exemplarily, as Figure 6As shown, the sixth transistor 1311 is an NMOS transistor, and the seventh transistor 1313 is a PMOS transistor. A low voltage is continuously input to the gate of the seventh transistor 1313, so that the seventh transistor as a PMOS transistor is always turned on. A high voltage is input to the source of the seventh transistor 1313 as the second electrode, so that the seventh transistor 1313 outputs the fifth voltage as a high voltage to the input terminal of the Schmitt trigger 1312. When the supply voltage does not reach the preset value, the sixth transistor 1311 as an NMOS transistor is not turned on due to the low voltage at the gate. At this time, after the input terminal of the Schmitt trigger 1312 receives the fifth voltage as a high voltage, the fourth voltage as a low voltage is output to the gate of the second transistor 132 through the output terminal. The second transistor 132 is a PMOS transistor, and is turned on due to the fourth voltage as a low voltage at the gate, so that the second voltage is output through the first electrode of the second transistor 132. When the supply voltage reaches the preset value, the gate of the sixth transistor 1311 is provided with a high voltage, so that the sixth transistor 1311 is turned on. The sixth transistor 1311 after being turned on draws the current output from the first electrode of the seventh transistor 1313 from the input terminal of the Schmitt trigger 1312 to the second electrode of the sixth transistor 1311 grounded, and at this time the sixth voltage as a low voltage is output from the first electrode of the sixth transistor 1311 to the input terminal of the Schmitt trigger 1312. After the input terminal of the Schmitt trigger 1312 receives the sixth voltage as a low voltage, the third voltage as a high voltage is output to the gate of the second transistor 132, and the second transistor 132 as a PMOS transistor is turned off due to the third voltage as a high voltage input at the gate.

[0090] For example, the fifth voltage input to the source of the second electrode of the seventh transistor 1313 can be provided by a programming voltage. The fifth voltage input to the second electrode of the seventh transistor 1313 by using the programming voltage reduces the additional power supply settings. At the same time, the synchronization between the fifth voltage output from the first electrode of the seventh transistor 1313 and the programming voltage can be ensured, thereby improving the stability of the system.

[0091] In some possible implementations, as Figure 6 As shown, the comparison circuit 131 further includes an eighth transistor 1314; the first electrode of the eighth transistor 1314 is coupled with the second electrode of the sixth transistor 1311, and the second electrode of the eighth transistor 1314 is grounded; the eighth transistor 1314 is turned on due to the programming voltage input at the gate.

[0092] Exemplarily, the eighth transistor 1314 is an NMOS transistor. When the programming voltage is powered on, a high voltage is input to the gate of the eighth transistor 1314, so that the eighth transistor 1314 is turned on, thereby grounding the second electrode of the sixth transistor 1311 through the eighth transistor 1314. When the programming voltage is powered off, the eighth transistor 1314 is turned off. By the eighth transistor 1314, it can be ensured that the second electrode of the sixth transistor 1311 can be grounded only when the programming voltage is powered on, thereby outputting the first voltage as a low voltage through the first electrode.

[0093] In some possible implementation manners, as shown in Figure 6 The comparison circuit 131 further includes a ninth transistor 1315. The first electrode of the ninth transistor 1315 is coupled with the second electrode of the eighth transistor 1314, and the second electrode of the ninth transistor 1315 is grounded; and the gate of the ninth transistor 1315 is connected in parallel with the gate of the sixth transistor 1311.

[0094] Exemplarily, the ninth transistor 1315 is an NMOS transistor, which is used for voltage division and increasing the threshold value of the supply voltage for turning on the sixth transistor 1311.

[0095] In some possible implementation manners, as shown in Figure 6 The comparison circuit 131 further includes a first resistor 1316. The input end of the first resistor 1316 is configured to input the supply voltage, and the output end of the first resistor 1316 is configured to output the supply voltage to the gate of the sixth transistor 1311.

[0096] The current of the supply voltage is generally large, and the first resistor 1316 can be used to limit the current, thereby protecting the sixth transistor 1311 and the ninth transistor 1315 from being damaged by excessive current.

[0097] It should be noted that the above-mentioned description of different voltage signals as high voltage or low voltage in the above-mentioned embodiments is only an actual example. In actual application, only the number of the second inverters of the inverter group 1113 in the control voltage circuit 111 and the number of the inverter group 1211 in the programming circuit 120 need to be changed, and the specific PMOS transistor or NMOS transistor of the first transistor 112, the second transistor 132 and the third transistor 122 needs to be adjusted adaptively, so that different implementation manners such as low-voltage control or high-voltage control can be implemented.

[0098] As shown in Figure 12As shown, the embodiment of the present application further provides an electronic device 2, which comprises the power switch circuit 201 and the interface circuit 202 as described in the above embodiment; the power switch circuit 201 is configured to input a power supply voltage, a control signal and a programming voltage, and output the programming voltage to a storage unit in a storage unit array coupled through the interface circuit 202 according to the control signal; and the programming voltage is configured to program the storage unit.

[0099] Exemplarily, the electronic device 2 can be a handheld terminal, a computer, a dedicated programming device, etc.

[0100] Those skilled in the art can understand that the modules and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software manner depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0101] Those skilled in the art can clearly understand that, for the convenience and brevity of the description, the specific working processes of the above-described system, device and module can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0102] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be realized by other ways. For example, the device embodiments described above are merely schematic, for example, the division of the modules is only a logical function division, and actual implementation can have another division manner, for example, a plurality of modules or components can be combined or integrated into another device, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed ones can be indirect coupling or communication connection through some interfaces, devices or modules, which can be electrical, mechanical or other forms.

[0103] The modules described as separate components can or can not be physically separated, and the components displayed as modules can or can not be physical modules, i.e., they can be located in one device or distributed to multiple devices. Part or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment.

[0104] In addition, each functional module in each embodiment of the present application can be integrated in one device, or each module can be physically present alone, or two or more modules can be integrated in one device.

[0105] The above merely provides the specific implementation of the present application, but the protection scope of the present application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A power switching circuit, characterized by, The power switch circuit is used for coupling to a memory cell in a memory cell array to output a programming voltage to the memory cell, the programming voltage being used for programming the memory cell; The power switch circuit comprises a driving circuit, a programming circuit and a protection circuit; the driving circuit is powered by a supply voltage, and the programming circuit is powered by the programming voltage; the driving circuit comprises a control voltage circuit and a first transistor; the protection circuit comprises a comparison circuit and a second transistor; An output terminal of the control voltage circuit is coupled to a gate of the first transistor; a first pole of the first transistor is coupled to a control terminal of the programming circuit as an output terminal of the driving circuit at a coupling point; a first pole of the second transistor is coupled at the coupling point; a control terminal of the comparison circuit is used for inputting the supply voltage, and an output terminal of the comparison circuit is coupled to a gate of the second transistor; An output terminal of the programming circuit is coupled to the memory cell for outputting the programming voltage; A driving capability of the second transistor is greater than a driving capability of the first transistor.

2. The circuit of claim 1, wherein, The comparison circuit comprises a sixth transistor, a seventh transistor and a Schmitt trigger; A gate of the sixth transistor is used as an input terminal of the comparison circuit for inputting the supply voltage; a first pole of the sixth transistor and a first pole of the seventh transistor are commonly coupled to an input terminal of the Schmitt trigger; a second pole of the sixth transistor is grounded; An output terminal of the Schmitt trigger is coupled to the gate of the second transistor as an output terminal of the comparison circuit.

3. The circuit of claim 2, wherein, The comparison circuit further comprises an eighth transistor; A gate of the eighth transistor is used for inputting the programming voltage; the programming voltage is used for controlling the eighth transistor to be turned on; a first pole of the eighth transistor is coupled to a second pole of the sixth transistor, and a second pole of the eighth transistor is grounded.

4. The circuit of claim 3, wherein, The comparison circuit further comprises a ninth transistor; A first pole of the ninth transistor is coupled to a second pole of the eighth transistor, and a second pole of the ninth transistor is grounded; a gate of the ninth transistor is connected in parallel with a gate of the sixth transistor as an input terminal of the comparison circuit for inputting the supply voltage.

5. The circuit of any one of claims 2-4, wherein, The comparison circuit further comprises a first resistor; An input terminal of the first resistor is used for inputting the supply voltage; an output terminal of the first resistor is coupled to the gate of the sixth transistor for outputting the supply voltage.

6. The circuit of claim 1, wherein, The programming circuit comprises a third transistor and a programming power switch circuit; A control terminal of the programming power switch circuit is used as the control terminal of the programming circuit, and is commonly coupled to the first pole of the first transistor, the first pole of the second transistor and the first pole of the third transistor at the coupling point; an output terminal of the programming power switch circuit is used as the output terminal of the programming circuit, and is used for coupling to the memory cell to output the programming voltage to the memory cell; A driving capability of the third transistor is equal to or less than a driving capability of the first transistor.

7. The circuit of claim 6, wherein, The programming power switch circuit comprises an odd number of inverter components; The single inverter component includes an NMOS tube and a PMOS tube; the gate of the PMOS tube and the gate of the NMOS tube of the inverter component are coupled to serve as the control end of the inverter component; the drain of the PMOS tube and the drain of the NMOS tube of the inverter component are coupled to serve as the output end of the inverter component; and the source of the PMOS tube of the inverter component is used for inputting the programming voltage; When the programming power switch circuit includes a single inverter component, the control end of the single inverter component serves as the control end of the programming power switch circuit and is coupled to the first pole of the first transistor, the first pole of the second transistor and the first pole of the third transistor at the coupling point; and the output end of the single inverter component serves as the output end of the programming power switch circuit and is used for coupling to the storage unit to output the programming voltage to the storage unit. When the programming power switch circuit includes multiple inverter components, the output end of a front-stage inverter component is coupled to the control end of a rear-stage inverter component; the control end of a first-stage inverter component serves as the control end of the programming power switch circuit and is coupled to the first pole of the first transistor, the first pole of the second transistor and the first pole of the third transistor at the coupling point; and the output end of a last-stage inverter component serves as the output end of the programming power switch circuit and is used for coupling to the storage unit to output the programming voltage to the storage unit.

8. The circuit of claim 6 or 7, characterized in that, The second pole of the third transistor is used for inputting the programming voltage.

9. The circuit of claim 1, wherein, The control voltage circuit includes a first inverter, an NAND gate and an inverter group; the inverter group includes an odd number of second inverters; The input end of the first inverter is used for receiving a first control signal, the output end of the first inverter is coupled to the first input end of the NAND gate; the second input end of the NAND gate is used for receiving a second control signal; the output end of the NAND gate is connected to the input end of the inverter group; and the output end of the inverter group, as the output end of the control voltage circuit, is coupled to the gate of the first transistor to output a control voltage.

10. The circuit of any one of claims 1-4, wherein, The driving circuit further includes a fourth transistor, the first pole of the fourth transistor is coupled to the second pole of the first transistor, the second pole of the fourth transistor is grounded, and the gate of the fourth transistor is used for inputting the programming voltage; The programming voltage is used for turning on the fourth transistor.

11. The circuit of claim 10, wherein, The driving circuit further includes a fifth transistor; the gate of the fifth transistor is connected in parallel to the gate of the first transistor and is used for coupling to the output end of the control voltage circuit; the first pole of the fifth transistor is coupled to the second pole of the fourth transistor, and the second pole of the fifth transistor is grounded.

12. The circuit of any one of claims 1-4, wherein, The second pole of the second transistor is used for inputting the programming voltage.

13. An electrically programmable fuse, comprising: The electrically programmed fuse memory comprises the power switch circuit according to any one of claims 1-12, a storage cell array; the power switch circuit is used for inputting a supply voltage, a control signal and a programming voltage, and outputting the programming voltage to a storage cell in the coupled storage cell array according to the control signal; The programming voltage is used for programming the storage cell.

14. An electronic device, comprising: The electronic device comprises the power switch circuit according to any one of claims 1-12; the power switch circuit is used for inputting a supply voltage, a control signal and a programming voltage, and outputting the programming voltage to a storage cell in the coupled storage cell array according to the control signal; The programming voltage is used for programming the storage cell.

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