Method and system for solid state drive based redundant array of independent disks

Abstract

Methods and systems for a solid state drive based redundant array of independent disks are provided. An operation is received at a file system (FS) of a RAID system from an application. A memory mapping module of the RAID system receives at least one FS logical block address (LBA) from the operation. The memory mapping module uses the at least one FS LBA to create a mapping from a virtual memory of the application to a RAID array in a system memory of the RAID system.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to solid state drives (SSDs), and more particularly, to a redundant array of independent disks (RAID) system for compute express link (CXL) SSDs. BACKGROUND

[0002] Big data applications handle extremely large data sets. SSDs are widely used as a hardware feature in cloud infrastructure for big data services. SSDs are well suited for big data applications as they provide fast storage performance and are efficient and cost effective. Specifically, input / output (I / O) intensive operations are accelerated by using SSD architecture. RAID systems based on SSDs protect data by distributing redundant data blocks across multiple SSDs. Mirroring is a concept in RAID where data is written to two separate drives simultaneously. Striping is a concept in RAID where data is evenly split across two or more drives. SUMMARY

[0003] Embodiments enable software RAID in a system equipped with multiple CXL SSDs. Applications can access data transparently to memory operations, regardless of RAID configuration.

[0004] According to embodiments, a method of a RAID system is provided. An operation can be received at a file system (FS) of the RAID system from an application. A memory mapping module of the RAID system can receive at least a FS logical block address (LBA) from the FS according to the operation. The memory mapping module can create a mapping from virtual memory of the application to a RAID array in system memory of the RAID system using at least the FS LBA.

[0005] According to embodiments, a RAID system is provided that can include a FS configured to receive an operation from an application. The RAID system can also include a memory mapping module configured to receive at least a FS LBA from the FS according to the operation and create a mapping from virtual memory of the application to a RAID array in system memory of the RAID system using at least the FS LBA.

[0006] According to embodiments, a memory mapping module of a RAID system is provided that can include a memory and a controller. The controller can be configured to receive at least a FS LBA from a FS of the RAID system according to an operation received at the FS. The controller can also be configured to create a mapping from virtual memory of an application to a RAID array in system memory of the RAID system using at least the FS LBA. The RAID array includes SSDs with cache coherency protocol. BRIEF DESCRIPTION OF DRAWINGS

[0007] The above and other aspects, features and advantages of certain embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a diagram illustrating a CXL SSD-based RAID system with a RAID 0 array according to an embodiment;

[0009] Figure 2 is a diagram illustrating a CXL SSD-based RAID system with a RAID 0 array according to an embodiment;

[0010] Figure 3 is a diagram illustrating a CXL SSD-based RAID system with a RAID array in a serial mode according to an embodiment;

[0011] Figure 4 is a diagram illustrating a CXL SSD-based RAID system with a RAID array in a parallel mode according to an embodiment;

[0012] Figure 5 is a flowchart illustrating a method of operating a CXL SSD-based RAID system with a RAID 0 array according to an embodiment;

[0013] Figure 6 is a flowchart illustrating a method of operating a CXL SSD-based RAID system with a RAID array according to an embodiment;

[0014] Figure 7 is a block diagram of an electronic device in a network environment according to one embodiment; and

[0015] Figure 8 is a diagram illustrating a storage system according to an embodiment. DETAILED DESCRIPTION

[0016] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that the same elements will be designated by the same reference numerals regardless of whether they are shown in different drawings. In the following description, specific details (such as detailed configuration and components) are provided only to help understanding of the embodiments of the present disclosure. Therefore, it will be apparent that various changes in the embodiments described herein can be made by those skilled in the art to which the present disclosure pertains without departing from the scope of the present disclosure. In addition, descriptions of well-known functions and configurations are omitted for clarity and conciseness. The terms described below are terms defined in consideration of functions in the present disclosure, and can vary according to users, user's intentions, or habits. Therefore, the definition of the terms should be determined based on the contents throughout the present specification.

[0017] The present disclosure can have various modifications and various embodiments, and some embodiments thereof will be described in detail with reference to the accompanying drawings. However, it should be understood that the present disclosure is not limited to these embodiments but includes all modifications, equivalents, and substitutes within the scope of the present disclosure.

[0018] Although terms including ordinal numbers (such as first, second, etc.) can be used to describe various elements, the structural elements are not limited by the terms. The terms are used only to distinguish one element from another element. For example, a first structural element can be referred to as a second structural element without departing from the scope of the present disclosure. Similarly, a second structural element can also be referred to as a first structural element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0019] The terms used herein are only used to describe various embodiments of the present disclosure and are not intended to limit the present disclosure. The singular form includes the plural form unless the context clearly indicates otherwise. In the present disclosure, it should be understood that the term "include" or "have" indicates the presence of features, numbers, steps, operations, structural elements, components, or combinations thereof, and does not exclude the presence or possibility of adding one or more other features, numbers, steps, operations, structural elements, components, or combinations thereof.

[0020] Unless defined differently, all terms used herein have the same meanings as those understood by those skilled in the art to which the present disclosure belongs. Unless clearly defined in the present disclosure, terms such as those defined in a general dictionary will be interpreted as having the same meanings as those in the context of related technology, and will not be interpreted as having ideal or excessively formal meanings.

[0021] According to one embodiment, the electronic device can be one of various types of electronic devices that utilize storage devices. The electronic device can use any suitable storage standard such as Peripheral Component Interconnect Express (PCIe), Non-Volatile Memory Express (NVMe), NVMe over Fabrics (NVMeoF), Advanced eXtensible Interface (AXI), Ultra Path Interconnect (UPI), Ethernet, Transmission Control Protocol / Internet Protocol (TCP / IP), Remote Direct Memory Access (RDMA), RDMA over Converged Ethernet (ROCE), Fibre Channel (FC), InfiniBand (IB), Serial Advanced Technology Attachment (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Internet Wide Area RDMA Protocol (iWARP), etc., or any combination thereof. In some embodiments, the interconnect interface can be implemented with one or more memory semantics and / or memory consistency interfaces and / or protocols including one or more Compute Express Link (CXL) protocols such as CXL.mem, CXL.io, and / or CXL.cache, Gen-Z, Coherent Accelerator Processor Interface (CAPI), Cache Coherent Interconnect for Accelerators (CCIX), etc., or any combination thereof. Any storage device can be implemented with one or more of any type of memory device interface including Double Data Rate (DDR), DDR2, DDR3, DDR4, DDR5, Low Power DDR (LPDDR X), Open Memory Interface (OMI), NVlink, High Bandwidth Memory (HBM), HBM2, HBM3, etc. The electronic device can include, for example, a portable communication device (e.g., a smartphone), a computer, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance. However, the electronic device is not limited to those described above.

[0022] The terminology used in the disclosure is not intended to limit the disclosure, but is intended to encompass various alterations, equivalents, or alternatives of the corresponding embodiments. In describing the drawings, like reference numerals can be used to refer to like or associated elements. The singular form of a noun that corresponds to a plural form of the noun, unless the relevant context clearly dictates otherwise. As used herein, each of such phrases as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C," can include all possible combinations of the items enumerated together in the phrases. As used herein, terms such as "1st", "2nd", "first", and "second" can be used to distinguish elements with like reference numerals from each other, without otherwise implying an order (e.g., importance or sequence). It is intended that if an element (e.g., first element) is claimed to be "coupled" or "connected" to another element (e.g., second element), it can be directly coupled or connected to the other element or it can be indirectly coupled or connected to the other element through a third element.

[0023] As used herein, the term "module" can include a unit implemented in hardware, software, firmware, or combination thereof, and can interchangeably be used with other terms, e.g., "logic", "logic block", "component", or "circuitry". A module can be a single integral component, or a minimum unit or part thereof, adapted to perform one or more functions. For example, according to an embodiment, a module can be implemented in a form of an application-specific integrated circuit (ASIC), a co-processor, or a field-programmable gate array (FPGA).

[0024] The RAID module has been designed for traditional block devices. However, the traditional RAID module does not accommodate CXL SSDs. CXL is a cache-coherent interconnect and / or protocol for processors, memory expansion, and accelerators, CXL maintains memory coherency between central processing unit (CPU) memory space and memory attached on a device. CXL SSDs can provide data via I / O operations and memory operations.

[0025] Embodiments of the disclosure enable software RAID in a system equipped with multiple CXL SSDs. Additionally, applications are able to access data transparently using memory operations regardless of the RAID configuration.

[0026] Figure 1is a diagram illustrating an SSD-based RAID system with a RAID array. A file system (FS) 102 can receive an operation (e.g., a R / W (read / write) operation or other operation, hereinafter, a R / W operation will be described as an example) from an application 104 (e.g., through a function readOwriteO) and a virtual-to-physical (V2P) memory mapping module 106 (or a memory mapping module 106) can obtain a (at least one) FS logical block address (LBA) related to the R / W operation from the FS 102. Using the FS LBA, the V2P memory mapping module 106 can map a virtual memory 108 of the application 104 to a system memory 110 (e.g., a dynamic random access memory (DRAM)), where the virtual memory 108 is communicated with the application 104 through a function mmapO.

[0027] A RAID module 112 can convert the FS LBA to a device identifier (ID) and a device LBA. The device ID can be an ID of one of the SSDs in a RAID array 114. The SSDs in the RAID array 114 can include, but are not limited to, SSD-0 116, SSD-1 118, and SSD-2 120. The RAID array can include SSDs with cache coherency protocols. The RAID module 112 can provide data striping and data replication for each R / W operation to one or more of the SSDs in the RAID array 114 via NVMe over Peripheral Component Interconnect Express (PCIe). The FS 102 can use the device ID and the device LBA to read data from the corresponding SSD of the RAID array 114 into a page cache of the system memory 110 mapped by the V2P memory mapping module 106 via direct memory access (DMA).

[0028] Figure 2is a diagram illustrating a CXL SSD based RAID system with a RAID 0 array according to embodiments. RAID 0 is a standard RAID class that involves single striping. FS 202 can receive R / W operations from application 204, and V2P memory mapping module 206 (or memory mapping module 206) can obtain FS LBAs related to the R / W operations from FS 202. RAID 0 module 212 can use RAID information to convert the FS LBAs to CXL SSD IDs and LBAs in CXL SSDs. A CXL SSD ID can be an ID of one of the CXL SSDs in RAID 0 array 214. The CXL SSDs in RAID 0 array 214 can include, but are not limited to, CXL SSD-0 216, CXL SSD-1 218, and CXL SSD-2 220. The CXL SSD IDs and LBAs in CXL SSDs can be provided to V2P memory mapping module 206.

[0029] V2P memory mapping module 206 can create a direct mapping from virtual memory 208 to system memory 210 based on the FS LBAs from FS 202 and the CXL SSD IDs and LBAs in CXL SSDs from RAID 0 module 212. Specifically, V2P memory mapping module 206 can obtain a base address of the CXL SSDs and convert the LBAs to an offset in memory. V2P memory mapping module 206 can determine a physical address in system memory 210 by adding the offset to the base address. Thus, V2P memory mapping module 206 can create a mapping between virtual memory 208 (e.g., user virtual addresses 222) of application 204 and system memory 210, which includes DRAM 224 and RAID 0 array 214 of CXL SSDs (e.g., device memory or CXL memory). Specifically, V2P memory mapping module 206 can compute the physical addresses to which the CXL SSDs are exposed.

[0030] In mapping virtual memory 208 and system memory 210, page module 226 (or page 226) can map a page global directory (PGD), a page upper directory (PUD), a page middle directory (PMD), and a page table entry directory (PTE) through control register (CR) 228 (e.g., CR3). CR 228 can enable translation of addresses by locating the page directory and page table for the current operation.

[0031] In a CXL SSD based RAID system with RAID arrays at RAID 1 and above, a V2P memory mapping module can select devices for mapping between mirror storage devices and sub-mirror storage devices. The selection policy used can include, for example, round-robin, random, fixed, or storage devices with least mapping, which will evenly distribute system load. A data replication manager (DRM) can support serial and parallel modes. Data integrity can be checked in the memory mapping module.

[0032] Figure 3 is a diagram illustrating a CXL SSD based RAID system with RAID arrays in serial mode according to an embodiment. The RAID arrays can be any standard RAID level above RAID 0 (e.g., RAID 1-6). For example, the RAID arrays can be RAID 1 arrays involving single or multiple mirroring. In serial mode, data can be replicated after updating data in one of the CXL SSDs.

[0033] FS 302 can receive R / W operations from application 304, and V2P memory mapping module 306 (or memory mapping module 306) can obtain FS LBAs related to the R / W operations from FS 302. V2P memory mapping module 306 can translate the FS LBAs to absolute physical addresses in system memory 310. The base address can be the start address of a mirror storage device or a sub-mirror storage device. Data integrity can be checked by memory comparison. V2P memory mapping module 306 can create a direct mapping between the application’s virtual memory 308 (e.g., user virtual addresses 322) and system memory 310, which includes DRAM 324 and RAID arrays 314 of CXL SSDs (e.g., device memory or CXL memory) in system memory 310. The CXL SSDs in RAID arrays 314 of system memory 310 can include, but are not limited to, CXL SSD-0 316, CXL SSD-1 318, and CXL SSD-2 320.

[0034] In mapping virtual memory 308 to system memory 310, page module 326 (or page 326) can map PGD, PUD, PMD, and PTE to system memory 310 through control register (CR) 328 (e.g., CR3). CR 328 can enable translation of addresses by locating the page directory and page table for the current operation.

[0035] The DRM 330 can periodically check if the CXL pages are dirty due to updates. Specifically, when the application 304 writes data, the CPU can set a dirty bit in the PTE through hardware logic. The DRM 330 can check all PTEs pointing to the mirror storage or sub-mirror storage. If the page is dirty, the page ID can be recorded and then the dirty bit can be cleared to avoid frequent updates to the sub-mirror storage. The DRM 330 communicates with the RAID module 312 and writes the data via the RAID module 312 if the detected data is dirty. The DRM 330 also checks if the recorded page remains clean. If the recorded page is clean, the data can be copied into the sub-mirror CXL SSD. If the recorded page is dirty, the dirty bit can be cleared. The DRM 330 can perform the copying via the CXL.io protocol or the CXL.mem protocol. The DRM 330 can copy data from the mirror storage to the sub-mirror storage or vice versa. For example, the copying strategy can be one of memory-to-memory copy, memory-to-block copy, block-to-block copy (R / W data via CXL.io), or device-to-device direct copy.

[0036] Figure 4 FIG. 1 is a diagram illustrating a CXL SSD-based RAID system with a RAID array in a parallel mode, according to an embodiment. The RAID array can be any standard RAID level above RAID 0 (e.g., RAID 1-6). For example, the RAID array can be a RAID 1 array involving a single mirror or multiple mirrors. In the parallel mode, writes to the reserved CXL RAID mirror region are copied and dispatched to the CXL SSDs that make up the RAID 1 configuration simultaneously.

[0037] The FS 402 can receive R / W operations from the application 404, and the V2P memory mapping module 406 (or the memory mapping module 406) can obtain the FS LBAs related to the R / W operations from the FS 402. The V2P memory mapping module 406 can translate the FS LBAs to absolute physical addresses in the system memory 410. The base address can be the start address of the mirror storage or the sub-mirror storage. Data integrity can be checked through memory comparison. The V2P memory mapping module 406 can create a direct mapping between the virtual memory 408 (e.g., user virtual addresses 422) of the application 404 and the system memory 410, which includes the DRAM 424 and the RAID array 414 (e.g., device memory or CXL memory). The CXL SSDs in the RAID array 414 of the system memory 410 can include, but are not limited to, CXL SSD-0 416, CXL SSD-1 418, and CXL SSD-2 420.

[0038] In mapping the virtual memory 408 to the system memory 410, the page module 426 (or page 426) can map the PGD, PUD, PMD, and PTE to the system memory 410 through a control register (CR) 428 (e.g., CR3). The CR 428 can enable translation of addresses by locating the page directory and page table for the current operation.

[0039] When the V2P memory mapping module 406 creates the mapping between the virtual memory 408 and the system memory 410, write protection can be set for the CXL pages. Specifically, the write protection can be set so that if the application 404 attempts to write to the RAID array 414 (e.g., CXL memory), the data will first be written to the CXL RAID mirror region 432 protected in the DRAM 424. Thus, for each write operation, the data can first be written to the CXL RAID mirror region 432. After the page update (write) in the CXL RAID mirror region 332 is completed, the page can be copied and dispatched to the CXL SSDs that make up the RAID configuration simultaneously. The CXL.io protocol can be used for the data copy.

[0040] The DRM 430 can check if the CXL RAID mirror region 432 has valid pages. If the valid pages are dirty, the DRM can write back to the mirror storage and the sub-mirror storage simultaneously. The DRM 430 communicates with the RAID module 412 and if the detected data is dirty, the DRM 430 can write the data via the RAID module 412. The DRM 430 can clear the dirty bit after the write back. If the page is clean, the PTE pointing to the page can be changed to map directly to the CLX memory and the page is write protected.

[0041] Thus, the disclosed embodiments result in a flexible data layout and mapping algorithm, efficient data mapping that meets different performance requirements, and improved garbage collection efficiency.

[0042] Figure 5is a flowchart illustrating a method of operating a CXL-SSD based RAID system with a RAID 0 array according to an embodiment. At 502, a file system of the RAID system can receive an R / W operation from an application. At 504, a RAID module can receive a FS LBA corresponding to the R / W operation from the file system and translate the FS LBA to a SSD LBA and a SSD ID in the RAID array. At 506, a memory mapping module can receive the file system LBA, the SSD ID, and the SSD LBA. At 508, the memory mapping module can obtain a base address of the SSD using the SSD ID. At 510, the memory mapping module can translate the SSD LBA to an offset. At 512, the memory mapping module can determine a physical address in system memory by adding the offset to the base address. Thus, the memory mapping module can create a direct mapping from the application’s virtual memory to the RAID array in system memory.

[0043] Figure 6 is a flowchart illustrating operating a CXL-SSD based RAID system with a RAID array in serial or parallel mode. The RAID array can be any standard RAID level above RAID 0 (e.g., RAID 1-6). At 602, a file system of the RAID system can receive an R / W operation from an application. At 604, a memory mapping module can receive a FS LBA corresponding to the R / W operation from the FS and can translate the FS LBA to an absolute physical address in system memory of the RAID system. The absolute physical address includes a base address of a SSD in the RAID array.

[0044] At 606, data can be written to a mirror storage device and a sub-mirror storage device in the RAID array in serial or parallel mode based on the absolute physical address. In serial mode, a SSD corresponding to the mirror storage device or the sub-mirror storage device can be selected according to a RAID array distribution policy. Data can be written to the SSD and replication can be performed by copying data from the SSD to the other one of the mirror storage device or the sub-mirror storage device. In parallel mode, write protection can be set so that data is first written to a RAID mirror region in DRAM of the system memory and data can be written to the mirror storage device and the sub-mirror storage device in the SSDs of the RAID array simultaneously.

[0045] Figure 7 is a block diagram illustrating an electronic device 701 in a network environment 700 according to an embodiment. Referring to Figure 7The electronic device 701 in the network environment 700 can communicate with an electronic device 702 via a first network 798 (e.g., a short-range wireless communication network), or an electronic device 704 or a server 708 via a second network (or a network) 799 (e.g., a long-range wireless communication network). The electronic device 701 can communicate with the electronic device 704 via the network 799. The electronic device 701 can include a processor 720, a memory 730, an input device 750, a sound output device 755, a display device 760, an audio module 770, a sensor module 776, an interface 777, a haptic module 779, a camera module 780, a power management module 788, a battery 789, a communication module 790, a subscriber identification module (SIM) 796, and / or an antenna module 797. In an embodiment, at least one (e.g., the display device 760 and / or the camera module 780) of the components can be omitted from the electronic device 701, or one or more other components can be added in the electronic device 701. In an embodiment, some of the components can be implemented as single integrated circuit (IC) or multiple ICs. The sensor module 776 (e.g., a fingerprint sensor, an iris sensor, and / or an illuminance sensor) can be embedded in the display device 760 (e.g., a display).

[0046] The processor 720 can execute, for example, software (e.g., a program 740) to control at least one other component (e.g., a hardware or software component) of the electronic device 701 coupled with the processor 720 and can perform various data processing or computation. The processor can correspond to a high-performance CPU (HCPU), or a combination of an HCPU, an embedded CPU, and / or a neural CPU of an SSD. As at least part of the data processing or computation, the processor 720 can load a command or data received from a host or another component (e.g., the sensor module 776 and / or the communication module 790) to a volatile memory 732, process the command or the data stored in the volatile memory 732, and store the resulting data in a non-volatile memory 734. The processor 720 can include a main processor 721 (e.g., a CPU or an application processor (AP)) and an auxiliary processor 723 (e.g., a graphics processor (GPU), an image signal processor (ISP), a sensor hub processor, and / or a communication processor (CP)) that is operable independently from, or in conjunction with, the main processor 721. Additionally or alternatively, the auxiliary processor 723 can be suitable for use in a functionally less complex use case than the main processor 721, or for consumption of less power than the main processor 721. The auxiliary processor 723 can be implemented as separate from, or as part of, the main processor 721.

[0047] The auxiliary processor 723 can control at least some of the functions or states of at least one component (e.g., the display device 760, the sensor module 776, and / or the communication module 790) among the components of the electronic device 701, instead of the main processor 721 while the main processor 721 is in an inactive (e.g., sleep) state, or together with the main processor 721 while the main processor 721 is in an active state (e.g., executing an application). According to an embodiment, the auxiliary processor 723 (e.g., an image signal processor or a communication processor) can be implemented as part of another component functionally related to the auxiliary processor 723 (e.g., the camera module 780 or the communication module 790).

[0048] The memory 730 can store various data used by at least one component (e.g., the processor 720 or the sensor module 776) of the electronic device 701. The various data can include, for example, software (e.g., the program 740) and input data or output data for a command related to the software. The memory 730 can include the volatile memory 732 or the non-volatile memory 734.

[0049] The program 740 can be stored in the memory 730 as software, and can include, for example, the operating system (OS) 742, middleware 744, and / or an application 746.

[0050] The input device 750 can receive a command and / or data, which is to be used by another component (e.g., the processor 720) of the electronic device 701, from the outside (e.g., a user) of the electronic device 701. The input device 750 can include, for example, a microphone, a mouse, or a keyboard.

[0051] The sound output device 755 can output sound signals to the outside of the electronic device 701. The sound output device 755 can include, for example, a speaker and / or a receiver. The speaker can be used for general purposes, such as playing multimedia or recording, and the receiver can be used for receiving an incoming call. According to an embodiment, the receiver can be implemented as part of the speaker or a separate component from the speaker.

[0052] The display device 760 can visually provide information to the outside (e.g., a user) of the electronic device 701. The display device 760 can include, for example, a display, a hologram device, or a projector and a control circuitry to control a corresponding one of the display, the hologram device, and the projector. According to an embodiment, the display device 760 can include a touch circuitry adapted to detect a touch or a sensor circuitry (e.g., a pressure sensor) adapted to measure the intensity of force incurred by the touch.

[0053] The audio module 770 can convert a sound into an electrical signal and vice versa. According to an embodiment, the audio module 770 can obtain the sound via the input device 750, or output the sound via the sound output device 755 or a headphone of the external electronic device 702 connected with the electronic device 701 directly (e.g., wiredly) or wirelessly.

[0054] The sensor module 776 can detect an operational state (e.g., power or temperature) of the electronic device 701 or an environmental state (e.g., a state of a user) external to the electronic device 701, and then generate an electrical signal or data value corresponding to the detected state. The sensor module 776 can include, for example, a gesture sensor, a gyro sensor, an atmospheric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, and / or an illuminance sensor.

[0055] The interface 777 can support one or more designated protocols to be used for the electronic device 701 to be directly (e.g., wiredly) or wirelessly connected with the external electronic device 702. According to an embodiment, the interface 777 can include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, a secure digital (SD) card interface, and / or an audio interface.

[0056] The connection terminal 778 can include a connector through which the electronic device 701 can be physically connected with the external electronic device 702. According to an embodiment, the connection terminal 778 can include, for example, a HDMI connector, a USB connector, a SD card connector, and / or an audio connector (e.g., a headphone connector).

[0057] The haptic module 779 can convert an electrical signal into a mechanical stimulus (e.g., a vibration or movement) or an electrical stimulus that can be recognized by a user via tactile or kinesthetic sensation. According to an embodiment, the haptic module 779 can include, for example, a motor, a piezoelectric element, and / or an electrical stimuluser.

[0058] The camera module 780 can capture a still image or moving images. According to an embodiment, the camera module 780 can include one or more lenses, image sensors, image signal processors, and / or flashes.

[0059] The power management module 788 can manage power supplied to the electronic device 701. The power management module 788 can be implemented as at least part of, for example, a power management integrated circuit (PMIC).

[0060] The battery 789 can supply power to at least one component of the electronic device 701. According to an embodiment, the battery 789 can include, for example, a primary cell which is not rechargeable, a secondary cell which is rechargeable, or a fuel cell.

[0061] Communication module 790 can support the establishment of a direct (e.g., wired) or wireless communication channel between electronic device 701 and external electronic devices (e.g., electronic device 702, electronic device 704, or server 708), and perform communication via the established communication channel. Communication module 790 may include one or more communication processors that can operate independently of processor 720 (e.g., AP) and support direct (e.g., wired) or wireless communication. According to one embodiment, communication module 790 may include wireless communication module 792 (e.g., cellular communication module, short-range wireless communication module, and / or Global Navigation Satellite System (GNSS) communication module) and / or wired communication module 794 (e.g., local area network (LAN) communication module and / or power line communication (PLC) module). A corresponding one of these communication modules can communicate via a first network 798 (e.g., a short-range communication network such as Bluetooth). TM The communication module 792 can communicate with external electronic devices using Wi-Fi Direct and / or Infrared Data Association (IrDA) standards and / or a second network 799 (e.g., a long-range communication network such as a cellular network, the Internet, and / or a computer network such as a LAN or a wide area network (WAN)). These various types of communication modules can be implemented as a single component (e.g., a single IC) or as multiple components that are separate from each other (e.g., multiple ICs). The wireless communication module 792 can use user information (e.g., International Mobile Subscriber Identity (IMSI)) stored in the user identification module 796 to identify and authenticate electronic devices 701 in the communication network (e.g., a first network 798 or a second network 799).

[0062] Antenna module 797 can transmit or receive signals or power to or from the outside of electronic device 701 (e.g., external electronic device). According to one embodiment, antenna module 797 may include one or more antennas, and thus at least one antenna suitable for a communication scheme used in a communication network (such as a first network 798 or a second network 799) may be selected, for example, by communication module 790 (e.g., wireless communication module 792). Signals or power can then be transmitted or received between communication module 790 and external electronic device via the selected at least one antenna.

[0063] At least some of the above components can be combined with each other and communicate signals (e.g., commands or data) between at least some of the above components via a peripheral communication scheme (e.g., bus, general purpose input and output (GPIO), serial peripheral interface (SPI) or mobile industrial processor interface (MIPI)).

[0064] According to an embodiment, commands and / or data can be transmitted or received between the electronic device 701 and the external electronic device 704 via the server 708 coupled with the second network 799. Each of the electronic devices 702 and 704 can be a device of a same type as or different from the electronic device 701. All or some of operations performed by the electronic device 701 can be performed at one or more of the external electronic devices 702, 704, and 708. For example, if the electronic device 701 is to perform a function or a service automatically, the electronic device 701, instead of performing or in addition to performing the function or the service, can request one or more of the external electronic devices to perform at least part of the function or the service. The external electronic device(s) that receive the request can perform at least part of the function or the service requested or an additional function or an additional service related to the request and transmit the result of the performance to the electronic device 701. The electronic device 701 can provide the result, with or without further processing of the result, as at least part of a reply to the request. To that end, cloud computing, distributed computing, or client-server computing technology can be used, for example.

[0065] One embodiment can be implemented as software (e.g., the program 740) including one or more instructions that are readable by a machine (e.g., the electronic device 701) and are stored in a storage medium (e.g., the internal memory 736 or the external memory 738). For example, the processor(s) of the electronic device 701 can invoke at least one of the one or more instructions stored in the storage medium, and execute the at least one instruction with or without using one or more other components under the control of the processor(s). Therefore, the machine can be operated to perform at least one function by the invoked at least one instruction. The one or more instructions can include a code generated by a compiler or a code executable by an interpreter. The machine-readable storage medium can be provided in the form of a non-transitory storage medium. The term "non-transitory" indicates that the storage medium is a tangible device and does not include a signal (e.g., an electromagnetic wave), but this term does not differentiate a case where data is semi-permanently stored in the storage medium and a case where data is temporarily stored in the storage medium.

[0066] According to an embodiment, the disclosed method can be included and provided in a computer program product. The computer program product can be traded as a product between a seller and a buyer. The computer program product can be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or be distributed online via an application store (e.g., Google Play Store TM) online distribution (e.g., download or upload), or directly between two user devices (e.g., smartphones). If distributed online, at least part of the computer program product can be temporarily generated or at least temporarily stored in a machine-readable storage medium such as a server of a manufacturer, a server of an application store, or a memory of a relay server.

[0067] According to an embodiment, each of the above-described components (e.g., a module or a program) can include a single entity or multiple entities. One or more of the above-described components can be omitted, or one or more other components can be added. Additionally or alternatively, a plurality of components (e.g., modules or programs) can be integrated into a single component. In such a case, the integrated component can still perform one or more functions of each of the plurality of components before the integration. Operations performed by the module, the program, or the other components can be executed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations can be executed in a different order or omitted, or one or more other operations can be added.

[0068] Figure 8 A diagram of a storage system 800 is shown, in accordance with an embodiment. The storage system 800 includes a host 802 and a storage device 804. Although one host and one storage device are depicted, the storage system 800 can include multiple hosts and / or multiple storage devices (such as a RAID array). The storage device 804 can be an SSD, a universal flash storage (UFS) device, etc. The storage device 804 includes a controller 806 and a storage medium 808 connected to the controller 806. The controller 806 can be an SSD controller, a UFS controller, etc. The storage medium 808 can include volatile memory, non-volatile memory, or both, and can include one or more flash memory chips (or other storage medium). The controller 806 can include one or more processors, one or more error correction circuits, one or more field programmable gate arrays (FPGAs), one or more host interfaces, one or more flash bus interfaces, etc., or a combination thereof. The controller 806 can be configured to facilitate transfer of data / commands between the host 802 and the storage medium 808. The host 802 sends data / commands to the storage device 804 for receipt by the controller 806 and processing in connection with the storage medium 808. As described herein, methods, processes, and algorithms can be implemented on a storage device controller, such as the controller 806. An arbiter, a command extractor, and a command processor can be implemented in the controller 806 of the storage device 804, and a processor and a buffer can be implemented in the host 802.

[0069] Although specific embodiments of the disclosure have been described in the detailed description of the disclosure, the disclosure can be modified in various forms without departing from the scope of the disclosure. Accordingly, the scope of the disclosure should not be determined only based on the described embodiments, but should be determined based on the appended claims and their equivalents.

Claims

1. A method of a redundant array of independent disks (RAID) system, comprising: receiving an operation at a file system (FS) of the RAID system from an application; receiving at least one FS logical block address (LBA) from the FS at a memory mapping module of the RAID system in accordance with the operation; creating, by the memory mapping module, a mapping from a virtual memory of the application to a RAID array in system memory of the RAID system using the at least one FS LBA, wherein the mapping is further created using a storage device identifier (ID) and a storage device LBA from a RAID module of the RAID system in the case that the RAID array is a RAID 0 class array.

2. The method of claim 1, wherein, the RAID array comprises storage devices having a cache coherency protocol.

3. The method of claim 2, wherein, in the case that the RAID array is a RAID 0 class array, the method further comprises: converting the FS LBA to the storage device ID and the storage device LBA at a RAID module of the RAID system; and receiving the storage device ID and the storage device LBA at the memory mapping module, wherein the mapping is created using the FS LBA, the storage device ID, and the storage device LBA.

4. The method of claim 3, wherein, the step of creating the mapping comprises: obtaining an address of the storage device in the RAID array using the storage device ID; converting the storage device LBA to an offset; and determining a physical address in the system memory by adding the offset to the address.

5. The method of claim 2, wherein, in the case that the RAID array is any standard RAID class array above a RAID 0 class array, the step of creating the mapping comprises: converting, by the memory mapping module, the FS LBA to a physical address in the system memory, wherein the physical address comprises the address of the SSD in the RAID array.

6. The method of claim 5, wherein, the step of creating the mapping further comprises: selecting, by the memory mapping module, the storage device corresponding to the first storage device or the second storage device in accordance with a RAID array distribution policy.

7. The method of claim 6, wherein, the RAID system operates in a serial mode, and further comprises: writing data into the storage devices of the RAID array; and performing replication in the RAID array by copying the data from the storage devices to the first storage device or the second storage device.

8. The method of claim 7, further comprising: determining, by the data replication manager, that a page of a storage device of the RAID array is dirty due to an update; recording a page ID of the dirty page; and clearing a dirty bit of the page and replicating data of the page. the RAID array operates in a parallel mode, and the step of creating the mapping further comprises:

9. The method of claim 5, wherein, setting, by the memory mapping module, a write protection such that data is first written to a portion of a dynamic random access memory (DRAM) of the system memory.

10. The method of claim 9, further comprising: determining, by the data replication manager, that a page of the portion of the DRAM is dirty; writing data of the page to the first storage device and the second storage device in the storage devices of the RAID array; and clearing a dirty bit of the page.

11. A redundant array of independent disks (RAID) system, comprising: ​ ​ a file system (FS) configured to receive an operation from an application; a memory mapping module configured to: receive at least one FS logical block address (LBA) from the FS according to the operation; and create a mapping from a virtual memory of the application to a RAID array in system memory of a RAID system using the at least one FS LBA, wherein the mapping is further created using a storage device identifier (ID) and a storage device LBA from a RAID module of the RAID system in a case where the RAID array is a RAID 0 class array.

12. The RAID system of claim 11, wherein, the RAID array includes storage devices having a cache coherency protocol.

13. The RAID system of claim 12, wherein, in a case where the RAID array is a RAID 0 class array, the RAID system further includes: a RAID module configured to translate the FS LBA to the storage device ID and the storage device LBA in the RAID array, wherein the memory mapping module is further configured to receive the storage device ID and the storage device LBA, and wherein the mapping is created using the FS LBA, the storage device ID, and the storage device LBA.

14. The RAID system of claim 13, wherein, in creating the mapping, the memory mapping module is further configured to: obtain an address of a storage device in the RAID array using the storage device ID; translate the storage device LBA to an offset; and determine a physical address in the system memory by adding the offset to the address.

15. The RAID system of claim 14, wherein, the RAID array operates in a parallel mode, and in creating the mapping, the memory mapping module is further configured to: set a write protection such that data is first written to a portion of a dynamic random access memory (DRAM) of the system memory.

16. The RAID system of claim 15, further comprising a data replication manager configured to: determine that a page of the portion of the DRAM is dirty; write data of the page to a first storage device and a second storage device of the storage devices of the RAID array; and clear a dirty bit of the page.

17. The RAID system of claim 12, wherein, in a case where the RAID array is any standard RAID class array above a RAID 0 class array, in creating the mapping, the memory mapping module is further configured to: translate the FS LBA to a physical address in the system memory, wherein the physical address includes an address of a storage device in the RAID array; and select a storage device corresponding to the first storage device or the second storage device according to a RAID array distribution policy.

18. The RAID system of claim 17, wherein, the RAID system operates in a serial mode, and further comprising a page module configured to: write data to the storage devices of the RAID array; and perform replication in the RAID array by copying the data from the storage devices to the first storage device or the second storage device.

19. The RAID system of claim 18, further comprising a data replication manager configured to: determine that a page of the storage devices of the RAID array is dirty due to an update; record a page ID of the dirty page; and clear a dirty bit of the page and replicate data of the page.

20. The RAID system of claim 19, wherein the data replication manager is further configured to: determine that the page is dirty due to an update; and clear the dirty bit of the page and replicate the data of the page.

20. A storage device of a Redundant Array of Independent Disks (RAID) system, the storage device comprising: a memory; and a controller in communication with the memory and configured to: receive, from a file system (FS) of the RAID system, at least one FS logical block address (LBA) in accordance with an operation received at the FS; and create a mapping from a virtual memory of an application to a RAID array in a system memory of the RAID system using the at least one FS LBA, wherein the RAID array comprises the storage device having a cache coherency protocol, wherein, in a case where the RAID array is a RAID 0 class array, the mapping is further created using a storage device identifier (ID) and a storage device LBA from a RAID module of the RAID system. ​

Images