Quantum state driven signal generator, device, and quantum computer system

Abstract

Quantum state drive signal generator, device, and quantum computer system. The present application discloses a quantum state drive signal generator, comprising a plurality of pulse signal output module groups, each of which comprises a first clock module configured to distribute a plurality of mutually synchronized working clock signals based on a received clock source signal and a second pulse signal; a control module configured to receive task data and a trigger signal and forward the task data and the trigger signal based on the working clock signal; and a plurality of signal output modules, each of which is configured to respond to the trigger signal and output a plurality of pulse signals for carrying quantum state encoding information of quantum bits based on the received task data and the working clock signal; wherein the control modules of the plurality of pulse signal output module groups are synchronously connected in communication. The present application improves the synchronization accuracy of the pulse signal used to drive the quantum state.

Description

Technical Field

[0001] The present application relates to the quantum field, and in particular to a quantum state driven signal generator, device, and quantum computer system. Background Art

[0002] The quantum processor is the core component for performing quantum computing. It integrates multiple qubits. To ensure the proper operation of the qubits, they require a variety of drive signals, including a frequency drive signal that drives the qubit's operating frequency and a microwave drive signal that drives and reads the qubit's quantum state. The microwave drive signal achieves its drive effect through resonance with the qubit, so its frequency is close to that of the qubit, typically in the gigahertz (GHz) range. Frequency conversion technology is used to convert the intermediate frequency signal carrying the qubit's quantum state drive encoding information into a microwave drive signal that is applied to the qubit. Therefore, a dedicated quantum measurement and control system is required, within which a pulse signal source module is installed to output the intermediate frequency signal.

[0003] With the development of quantum technology, the number of qubits integrated on quantum processors is increasing, and the quantum computing tasks performed on quantum processors are becoming more and more complex. The corresponding number of pulse signal source modules that need to be integrated in the quantum measurement and control system is also increasing. As a result, the clocks of multiple pulse signal source modules are difficult to synchronize, making the multiple intermediate frequency signals output by the pulse signal source modules asynchronous, and thus making the microwave driving signal finally applied to the quantum processor asynchronous, reducing the computing accuracy of the quantum processor.

[0004] Therefore, how to improve the clock synchronization of multiple pulse signal source modules in a quantum measurement and control system has become a technical problem that needs to be solved urgently in this field.

[0005] It should be noted that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Summary of the Invention

[0006] The purpose of this application is to provide a quantum state driving signal generator, device, and quantum computer system, which improves the synchronization accuracy of the pulse signal used to drive the quantum state.

[0007] The technical solution of this application is as follows:

[0008] One aspect of the present application provides a quantum state drive signal generator, comprising a plurality of pulse signal output module groups, each of which comprises:

[0009] A first clock module is configured to distribute a plurality of mutually synchronized working clock signals based on a received clock source signal and a second pulse signal; wherein the second pulse signal is used to align the plurality of working clock signals;

[0010] a control module configured to receive task data and a trigger signal and forward the task data and the trigger signal according to the working clock signal;

[0011] a plurality of signal output modules, each of the signal output modules being configured to respond to the trigger signal and output multiple pulse signals for carrying quantum state encoding information of qubits according to the received task data and the working clock signal;

[0012] Among them, the control modules of the plurality of pulse signal output module groups are synchronously connected for communication.

[0013] The quantum state driving signal generator as described above preferably further comprises a board body, and the plurality of pulse signal output module groups are integrated on the board body.

[0014] As described above, in the quantum state driving signal generator, preferably, the control modules of the plurality of pulse signal output module groups are communicatively connected via a GPIO interface.

[0015] In the quantum state driving signal generator as described above, preferably, the control modules of the plurality of pulse signal output module groups are communicatively connected via LVDS interfaces.

[0016] As described above, for the quantum state driving signal generator, preferably, the control module of each of the pulse signal output module groups is specifically configured to synchronize the working clock signal according to the LVDS protocol.

[0017] As described above, the quantum state driving signal generator, preferably, the control module of each of the pulse signal output module groups is specifically configured to synchronously forward the trigger signal to the signal output module of each of the pulse signal output module groups according to the LVDS protocol.

[0018] As described above, in the quantum state driving signal generator, preferably, the pulse signal output module group further includes a memory, which is communicatively connected to the control module and is used to store the task data.

[0019] As described above, in the quantum state driving signal generator, preferably, the pulse signal output module group further includes a second clock module, which is configured to output a clock signal for the operation of the memory.

[0020] The quantum state driving signal generator as described above preferably further includes a power supply module, which is configured to provide a power supply signal for the first clock module, the control module, and the signal output module of each of the pulse signal output module groups.

[0021] As for the quantum state driving signal generator as described above, preferably, the control module includes FPGA, MCU, MPU or DSP.

[0022] In the quantum state driving signal generator as described above, preferably, the signal output module includes a DAC.

[0023] On the other hand, the present application provides a quantum driving device, including a backplane, and a plurality of quantum state driving signal generators as described above, wherein the plurality of quantum state driving signal generators are integrated on the backplane.

[0024] On the other hand, the present application provides a quantum control system, including a central control system and multiple quantum drive devices as described above, wherein the central control system is configured to control the multiple quantum drive devices to output pulse signals for driving the quantum state of quantum bits.

[0025] On the other hand, the present application provides a quantum computer system, comprising the above-mentioned quantum control system and a quantum processor, wherein the quantum processor performs quantum computing based on a pulse signal output by the quantum control system.

[0026] Compared with the prior art, this application has the following effects:

[0027] The present application provides a quantum state drive signal generator, comprising multiple pulse signal output module groups, each of which comprises a first clock module, a control module, and multiple signal output modules; wherein the first clock module is configured to distribute multiple mutually synchronized working clock signals based on a received clock source signal and a second pulse signal, and the second pulse signal is used to align the multiple working clock signals; the control module is configured to receive task data and forward the task data and a trigger signal based on the working clock signal; each of the signal output modules is configured to respond to the trigger signal and output multiple pulse signals for carrying quantum state encoding information of quantum bits based on the received task data and the working clock signal; in addition, the multiple control modules are communicatively connected. The present application receives a clock source signal through a first clock module and divides it into multiple working clock signals to ensure that the multiple working clock signals are of the same source, and uses a second pulse signal to align the multiple working clock signals, ensuring that the synchronization accuracy between the multiple working clock signals of the control module and the signal output module distributed to a pulse signal output module group is very high; and the control modules on the multiple pulse signal output module groups communicate and are synchronously connected with each other, and the multiple control modules ensure the synchronization of the working clock signals and the synchronization of the trigger signals forwarded to each signal output module through a communication protocol, thereby ensuring that the synchronization accuracy of the pulse signals for driving the quantum state output by all multiple signal output modules on the multiple pulse signal output module groups based on the task data and trigger signals received from the control module is very high, thereby improving the computing accuracy of the quantum processor.

[0028] The quantum driving device, quantum control system and quantum computer system proposed in this application belong to the same application concept as the quantum state driving signal generator, and therefore have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of a quantum measurement and control system constructed using prior art is provided for the embodiments of this application;

[0030] Figure 2 A schematic diagram of a quantum state drive signal generator provided in an embodiment of the present application Figure 1 ;

[0031] Figure 3 A schematic diagram of a quantum state drive signal generator provided in an embodiment of the present application Figure 2 ;

[0032] Figure 4 A schematic diagram of a quantum drive device provided in an embodiment of the present application.

[0033] Description of reference numerals:

[0034] 1-Pulse signal output module group, 11-First clock module, 12-Control module, 13-Signal output module, 14-Memory, 15-Second clock module, 16-Third clock module. DETAILED DESCRIPTION

[0035] The following detailed description is illustrative only and is not intended to limit the application or uses of the embodiments and / or embodiments. In addition, there is no intention to be bound by any express or implied information presented in the previous "Background Technology" or "Summary of the Invention" section or "Detailed Description of the Invention" section.

[0036] To make the purpose, technical solutions, and advantages of the embodiments of the present application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals are used throughout the text to refer to similar components. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it is obvious that in various cases, one or more embodiments can be practiced without these specific details, and the various embodiments can be combined and referenced with each other without contradiction.

[0037] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Typically, a quantum processor is equipped with multiple qubits and data transmission lines. Each qubit includes a detector and a qubit device coupled to each other. The qubit device can be an artificial superconducting qubit constructed using a superconducting Josephson junction and a ground capacitor, and the detector can be a resonant cavity. The qubit device is provided with a first control signal line and a second control signal line, and the detector coupled to the qubit device is provided with a third control signal line. The first control signal line is used to transmit a quantum state control signal for controlling the quantum state information of the qubit device, the second control signal line is used to transmit a frequency control signal for controlling the frequency parameters of the qubit device, and the third control signal line is used to transmit both a measurement signal for measuring and reading the detector and an output signal returned by the detector, thereby indirectly reading and measuring the state of the qubit device. Therefore, the quantum control system used for controlling and measuring qubits in the quantum processor needs to generate and output three control signals, which are provided to the first through third control signal lines, respectively, to control and measure the qubits in the quantum processor.

[0039] like Figure 1 The prior art shown uses commercial instruments to build a quantum measurement and control system. As is well known, a quantum processor has multiple qubits, and quantum computing tasks can be performed by a single qubit or by multiple qubits working together. To ensure the normal operation of each qubit, it is necessary to provide the qubit with multiple drive signals, such as frequency drive signals that drive a single qubit or multiple qubits to perform gate operations. Specifically, it includes a single-bit gate frequency drive signal that drives a single qubit to perform a gate operation, which is provided by a DC signal source, and a multi-bit gate frequency drive signal that is provided by a pulse signal source. In addition, when the qubit performs quantum computing, it is also necessary to control the qubit to the target quantum state. Specifically, this is done by outputting a quantum state drive signal from a microwave signal source. When the quantum processor completes the quantum computing, it is also necessary to measure and process the operation results of the quantum processor using signal acquisition equipment and signal processing equipment to obtain the computing results.

[0040] Multiple signal sources are typically independent commercial signal sources. Furthermore, when a quantum processor has a large number of qubits and multiple drive signals of the same type are required to perform quantum computations, a single signal source cannot meet the required number of drive signals, requiring the coordinated provision of multiple signal sources of the same type. It is conceivable that when multiple independent commercial signal sources collaborate to provide quantum state drive signals for a quantum processor to perform quantum computations, errors in the clocks between the signal sources could make it difficult to ensure the synchronization of the output quantum state drive signals, directly impacting the quantum processor's drive performance and, in turn, the accuracy of the quantum processor's quantum computations.

[0041] like Figure 2As shown, the present application provides a quantum state drive signal generator, comprising a plurality of pulse signal output module groups 1, each of the pulse signal output module groups 1 comprising: a first clock module 11, configured to distribute a plurality of mutually synchronized working clock signals based on a received clock source signal and a second pulse signal; wherein the second pulse signal is used to align the plurality of working clock signals; a control module 12, configured to receive task data and a trigger signal and forward the task data and the trigger signal based on the working clock signal; a plurality of signal output modules 13, each of the signal output modules 13 being configured to respond to the trigger signal and output a plurality of pulse signals for carrying quantum state encoding information of quantum bits based on the received task data and the working clock signal; wherein the control modules 12 of the plurality of pulse signal output module groups 1 are synchronously connected for communication.

[0042] The first clock module 11 receives the clock source signal and distributes multiple working clock signals. The multiple working clock signals are aligned through the second pulse signal to ensure that the working clock signals distributed to the control module 12 and the signal output module 13 are synchronized with each other. The control module 12 receives the task data and trigger signal and forwards it to the signal output module 13. The trigger signal ensures that the triggering between the multiple signal output modules 13 is also synchronized, thereby ensuring that the multiple pulse signals for carrying quantum state encoding information output by the multiple signal output modules 13 according to the task parameters are highly synchronized. Among them, the quantum state encoding information includes the driving information of the quantum state of the qubit.

[0043] A first clock module 11, a control module 12, and multiple signal output modules 13 are used to form a pulse signal output module group 1 to provide quantum state drive signals for several quantum bits. It is understandable that the driving capacity of a control module 12 is limited, that is, the number of signal output modules 13 integrated in a pulse signal output module group 1 is also limited, and the number of pulse signals output by a corresponding pulse signal output module group 1 for driving the quantum state of the quantum bit is also limited. It can provide a highly synchronized pulse signal carrying quantum state encoding information for a limited number of quantum bits. However, with the development of quantum computing, the number of quantum bits integrated on the quantum processor has increased exponentially, and the number of required quantum state drive signals has increased accordingly. One pulse signal output module group 1 cannot meet the demand, and multiple pulse signal output module groups 1 need to be used.

[0044] During implementation of the present application, the control modules 12 of the plurality of pulse signal output module groups 1 are communicatively connected to each other so that synchronization can be achieved between the plurality of control modules 12, such as synchronization of the working clock signal, synchronization of forwarding task data and trigger signals, to ensure that all signal output modules 13 are synchronized, thereby ensuring that all pulse signals output to the quantum processor for driving the quantum state of the qubits are synchronized.

[0045] In addition, the pulse signal that drives the quantum state of the qubit on the quantum processor is usually a sinusoidal wave signal. By adjusting the amplitude, pulse width, phase and other parameters of the sinusoidal wave signal, the quantum state of the qubit reaches the preset value and quantum calculation is performed.

[0046] The present application receives a clock source signal through a first clock module 11 and divides it into multiple working clock signals to ensure that the multiple working clock signals are of the same source, and uses a second pulse signal to align the multiple working clock signals to ensure that the synchronization accuracy between the multiple working clock signals distributed to the control module 12 and the signal output module 13 of a pulse signal output module group 1 is very high; and the control modules 12 on the multiple pulse signal output module groups 1 communicate and are synchronously connected with each other, and the multiple control modules 12 ensure the synchronization of the working clock signals and the synchronization of the trigger signals forwarded to each signal output module 13 through a communication protocol, thereby ensuring that the synchronization accuracy of the pulse signals for driving the quantum state output by all multiple signal output modules 13 on the multiple pulse signal output module groups 1 based on the task data and trigger signals received from the control module 12 is very high, thereby improving the computing accuracy of the quantum processor.

[0047] As one implementation of an embodiment of the present application, the quantum state drive signal generator further includes a board body, onto which the plurality of pulse signal output module groups 1 are integrated. Specifically, the first clock module 11, control module 12, and plurality of signal output modules 13 of each pulse signal output module group 1 are integrated circuits. The board body integrates all functional modules onto a single board, resulting in a compact size, high integration, and ease of expansion.

[0048] As an implementation method of an embodiment of the present application, the control modules 12 of the plurality of pulse signal output module groups 1 are communicatively connected via a GPIO interface. The control modules 12 of different pulse signal output module groups 1 are communicatively connected via a GPIO interface, which has low loss, a small package size, simple wiring, and is easy to integrate.

[0049] As one implementation of an embodiment of the present application, the control modules 12 of the plurality of pulse signal output module groups 1 are communicatively connected via an LVDS interface. The control modules 12 of different pulse signal output module groups 1 are communicatively connected via an LVDS interface, which provides stable communication performance and a high information transmission rate, facilitates accurate acquisition of configuration information and operating status, and ensures stable performance of the entire quantum state drive signal generator.

[0050] As an implementation method of an embodiment of the present application, the control module 12 of each of the pulse signal output module groups 1 is specifically configured to synchronize the working clock signal according to the LVDS protocol. The first clock module 11 in each pulse signal output module group 1 ensures that the distributed multiple working clock signals are synchronized with each other based on the received clock source signal and the second pulse signal. The working clock signals between the multiple pulse signal output module groups 1 obtain the configuration information of each working clock signal according to the LVDS protocol through each control module 12 to ensure that the pulse signals output by the multiple pulse signal output module groups 1 are synchronized.

[0051] As an implementation method of an embodiment of the present application, the control module 12 of each of the pulse signal output module groups 1 is specifically configured to synchronously forward the trigger signal to the signal output module 13 of each of the pulse signal output module groups 1 according to the LVDS protocol. The control module 12 in each pulse signal output module group 1 will forward the received task data and trigger signal to the signal output module 13 in the module group to ensure the synchronization of the pulse signals output by each signal output module 13 in the module group. The configuration information of each trigger signal is obtained between the multiple pulse signal output module groups 1 through each control module 12 according to the LVDS protocol to ensure the synchronization of the pulse signals output by the multiple pulse signal output module groups 1.

[0052] like Figure 3As shown, as an implementation method of the embodiment of the present application, the pulse signal output module group 1 also includes a memory 14, which is communicatively connected to the control module 12 for storing the task data. The task data specifically includes the signal waveform parameters of the pulse signal, the signal waveform timing, etc., wherein the signal waveform parameters are specifically the waveform parameters of the pulse signal output by the signal output module 13, such as pulse amplitude, pulse width, phase, etc.; the signal waveform timing is the application time of the pulse signal. When the quantum processor performs a quantum computing task, the multiple driving signals applied to the quantum bit are in time sequence, and the driving signals need to be applied strictly in accordance with the preset time sequence to ensure the driving effect and accuracy of the quantum bit. For quantum computing tasks, the memory occupied by the corresponding task data is usually relatively large. After being received by the control module 12, it is stored in the memory 14 and read from the memory 14 when it needs to be forwarded, saving the memory consumption of the control module 12. In this embodiment, the memory 14 is preferably DDR, and the number of DDRs can be multiple. In other embodiments, other devices with similar data storage functions can also be selected, without limitation.

[0053] like Figure 3 As shown, as an implementation method of an embodiment of the present application, the pulse signal output module group 1 also includes a second clock module 15, which is configured to output a clock signal for the operation of the memory 14. Specifically, the second clock module 15 may include a crystal oscillator and is connected to the memory 14 through a phase-locked loop circuit to provide a stable high-frequency clock signal for the memory 14. In addition, each pulse signal output module group 1 also includes a third clock module 16, which is configured to output a clock signal for configuring the control module 12. Before the control module 12 works, it is also necessary to configure its built-in parameters, such as the clock signal. The built-in clock parameters of the control module 12 are configured through the third clock module 16 to ensure the normal operation of the control module 12.

[0054] It should be noted that the operating clock signal distributed by the first clock module 11 to the control module 12 is the clock signal used by the control module 12 to control the coordinated output of pulse waveforms by multiple signal output modules 13. The control module 12 is actively configured, configuring the operating clock signal of the signal output modules 13. However, when the third clock module 16 is used to configure the built-in clock of the control module 12, the control module 12 is passively configured. Configuring the built-in clock parameters and operating clock parameters of the control module 12 through the first and third clock modules 11, 16 ensures stable clock performance when the control module 12 executes quantum computing tasks. Furthermore, both the second and third clock modules 15, 16 can utilize crystal oscillators for ease of integration.

[0055] As an implementation method of an embodiment of the present application, the quantum state drive signal generator also includes a plurality of signal connectors, each of which is configured to receive the clock source signal and / or the second pulse signal, and / or output the pulse signal. The clock source signal and the second pulse signal are both externally transmitted signals, and the pulse signal generated by the signal output module 13 also needs to be output to the quantum processor. A signal connector is used to receive and / or output signals, which is convenient for cable connection and disassembly. In this embodiment, the signal connector is preferably an SSMA radio frequency connector, which is fixed on the board body and has a small size, stable structure and performance. In other embodiments, other devices with similar functions can also be selected, and there is no limitation here.

[0056] As an implementation of an embodiment of the present application, the quantum state drive signal generator further includes a power supply module, which is configured to provide a power supply signal for the first clock module 11, the control module 12, and the signal output module 13 of each of the pulse signal output module groups 1. The first clock module 11, the first control module 12, and the plurality of signal output modules 13 are all active devices, and the power supply module is provided to provide a power supply signal for each functional module.

[0057] As one implementation of the present application, the control module 12 includes an FPGA, an MCU, an MPU, or a DSP. The control module 12 is a device with data forwarding and processing functions, and can generally be an FPGA (Field Programmable Gate Array), an MCU (Microcontroller Unit), an MPU (Microprocessor Unit), or a DSP (Digital Signal Processor). In this embodiment, the control module 12 is preferably an FPGA. In other embodiments, other devices with similar data processing functions can also be used, without limitation.

[0058] As an implementation method of an embodiment of the present application, the signal output module 13 includes a DAC. The signal output module 13 is a device that outputs a pulse signal according to the task data, and a DAC (Digital to Analog Converter) can generally be selected. In this embodiment, the pulse signal is used to drive the sinusoidal wave signal of the quantum state of the qubit by adjusting the parameters such as the pulse amplitude, pulse width, and phase of the sinusoidal wave signal; therefore, in this embodiment, a DAC with a sampling rate of about 3GHz is preferably used as the signal output module 13 to ensure high accuracy of the output pulse signal, thereby ensuring the driving accuracy of the quantum state of the qubit.

[0059] As described above, in this embodiment, the control module 12 is preferably FPGA, and the signal output module 13 is preferably DAC. The control module 12 and the multiple signal output modules 13 communicate through the JESD204B interface, and the task data transmission efficiency is high. It also reduces the board layout space of the board body, reduces the pin and package size of the device, and is conducive to integration.

[0060] like Figure 4 As shown, based on the same application concept, an embodiment of the present application further provides a quantum drive device, comprising a backplane and a plurality of quantum state drive signal generators as described above, wherein the plurality of quantum state drive signal generators are integrated on the backplane. Each module of the quantum state drive signal generator can be an integrated device integrated on a board body; and the plurality of board bodies can be integrated on a backplane, so that multiple quantum state drive signal generators are integrated on a backplane, facilitating expansion and providing drive signals for quantum state encoding for multi-bit quantum processors.

[0061] Based on the same application concept, embodiments of the present application also provide a quantum control system comprising a central control system and multiple aforementioned quantum drive devices. The central control system is configured to control the multiple quantum drive devices to output pulse signals for driving the quantum states of qubits. With the development of quantum technology, the number of qubits on quantum processors is increasing, requiring more quantum drive devices as signal sources to provide quantum state drive signals for the qubits. As the number of quantum drive devices increases, the central control system is used to control the multiple quantum drive devices, i.e., to control the multiple quantum state drive signal generators on the quantum drive devices through a backplane, thereby ensuring the stability of clock synchronization and trigger synchronization of the entire control system.

[0062] Based on the same application concept, an embodiment of the present application further provides a quantum computer system, comprising the above-mentioned quantum control system and a quantum processor, wherein the quantum processor performs quantum computing based on a pulse signal output by the quantum control system.

[0063] The above describes in detail the structure, features and effects of the present application based on the embodiments shown in the drawings. The above is only a preferred embodiment of the present application, but the present application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of the present application, or modifications to equivalent embodiments with equivalent changes, which still do not exceed the spirit covered by the description and drawings, should be within the scope of protection of the present application.

Claims

1. A quantum state drive signal generator, characterized in that: It includes multiple pulse signal output module groups, each of which includes: A first clock module is configured to distribute a plurality of mutually synchronized working clock signals based on a received clock source signal and a second pulse signal; wherein the second pulse signal is used to align the plurality of working clock signals; a control module configured to receive task data and a trigger signal and forward the task data and the trigger signal according to the working clock signal; a plurality of signal output modules, each of the signal output modules being configured to respond to the trigger signal and output multiple pulse signals for carrying quantum state encoding information of qubits according to the received task data and the working clock signal; Among them, the control modules of multiple pulse signal output module groups are synchronously connected through LVDS interface communication, and the working clock signal is synchronized according to the LVDS protocol, and the control module of each pulse signal output module group synchronously forwards the trigger signal to the signal output module of each pulse signal output module group according to the LVDS protocol.

2. The quantum state driving signal generator according to claim 1, characterized in that: It also includes a board main body, and a plurality of the pulse signal output module groups are integrated on the board main body.

3. The quantum state driving signal generator according to claim 1, characterized in that: The control modules of the plurality of pulse signal output module groups are communicatively connected via a GPIO interface.

4. The quantum state driving signal generator according to claim 1, characterized in that: The pulse signal output module group further includes a memory, which is communicatively connected to the control module and is used to store the task data.

5. The quantum state driving signal generator according to claim 4, characterized in that: The pulse signal output module group further includes a second clock module configured to output a clock signal for the memory to operate.

6. The quantum state driving signal generator according to claim 1, characterized in that: It also includes a power supply module, which is configured to provide a power supply signal for the first clock module, the control module, and the signal output module of each pulse signal output module group to operate.

7. The quantum state driving signal generator according to claim 1, characterized in that: The control module includes FPGA, MCU, MPU or DSP.

8. The quantum state driving signal generator according to claim 1, characterized in that: The signal output module includes a DAC.

9. A quantum drive device, characterized in that: It comprises a backplane, and a plurality of quantum state drive signal generators according to any one of claims 1 to 8, wherein the plurality of quantum state drive signal generators are integrated on the backplane.

10. A quantum control system, characterized in that: The device comprises a central control system and a plurality of quantum driving devices according to claim 9, wherein the central control system is configured to control the plurality of quantum driving devices to output pulse signals for driving the quantum state of a quantum bit.

11. A quantum computer system, characterized in that: The invention comprises the quantum control system according to claim 10 and a quantum processor, wherein the quantum processor performs quantum calculation based on the pulse signal output by the quantum control system.

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