Display panel, driving method thereof and display device

Abstract

The application discloses a display panel and a driving method thereof, and a display device. A display area of the display panel comprises a plurality of sub-pixels arranged in an array. The sub-pixel comprises a pixel driving circuit and a light emitting element. The pixel driving circuit comprises a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit are located in different rows of sub-pixels. Control ends of threshold compensation modules of the first pixel driving circuit and the second pixel driving circuit are electrically connected to a same first scanning signal end. In the display of the nth frame of display picture, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit. In the display of the (n+1)th frame of display picture, the data writing stage of the second pixel driving circuit is earlier than the data writing stage of the first pixel driving circuit. n is an integer greater than or equal to 1. The above technical scheme improves the display quality of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and its driving method, and a display device. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for the display quality of display panels. When multiple rows of sub-pixels are displayed simultaneously using the control signal output by the same shift circuit, the different start times of writing data to the multiple rows of sub-pixels can easily lead to differences in display brightness, thereby affecting the display effect of the display panel and reducing display quality. Summary of the Invention

[0003] This invention provides a display panel, a driving method thereof, and a display device to improve the display quality of the display panel.

[0004] In a first aspect, embodiments of the present invention provide a display panel, the display panel including a display area, the display area including a plurality of sub-pixels arranged in an array, the sub-pixels including a pixel driving circuit and a light-emitting element, the pixel driving circuit being used to drive the light-emitting element to emit light;

[0005] The pixel driving circuit includes a threshold compensation module, and the control terminal of the threshold compensation module is electrically connected to the first scanning signal terminal.

[0006] The pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit are located in the sub-pixels in different rows. The control terminals of the threshold compensation modules of the first pixel driving circuit and the second pixel driving circuit are electrically connected to the same first scanning signal terminal.

[0007] When the nth frame is displayed, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit.

[0008] When the screen is displayed in the (n+1)th frame, the data writing phase of the second pixel driving circuit is earlier than the data writing phase of the first pixel driving circuit.

[0009] Where n is an integer greater than or equal to 1.

[0010] Secondly, embodiments of the present invention provide a driving method for a display panel, executed by the display panel described in the first aspect, the driving method comprising:

[0011] When the nth frame is displayed, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit.

[0012] When the screen is displayed in the (n+1)th frame, the data writing phase of the second pixel driving circuit is earlier than the data writing phase of the first pixel driving circuit.

[0013] Where n is an integer greater than or equal to 1.

[0014] Thirdly, embodiments of the present invention provide a display device, including the display panel described in the first aspect.

[0015] The solution provided by this invention includes a pixel driving circuit comprising a first pixel driving circuit and a second pixel driving circuit, located in sub-pixels of different rows. The control terminals of the threshold compensation modules of both the first and second pixel driving circuits are electrically connected to the same first scan signal terminal. This allows the first scan signal provided by the first scan signal terminal to simultaneously control the on / off state of the threshold compensation modules in both the first and second pixel driving circuits. When the nth frame is displayed, the data writing phase of the first pixel driving circuit precedes the data writing phase of the second pixel driving circuit, resulting in a longer threshold compensation time after the first pixel driving circuit writes its data signal. Similarly, when the (n+1)th frame is displayed, the data writing phase of the second pixel driving circuit precedes the data writing phase of the first pixel driving circuit, again resulting in a longer threshold compensation time after the second pixel driving circuit writes its data signal, where n is an integer greater than or equal to 1. This ensures that the total threshold compensation time of the first pixel driving circuit and the total threshold compensation time of the second pixel driving circuit are the same in two adjacent display frames, thereby eliminating the difference in display brightness between the sub-pixels corresponding to the first pixel driving circuit and the sub-pixels corresponding to the second pixel driving circuit, and improving the display effect of the display panel.

[0016] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, although the drawings described below are some specific embodiments of the present invention, those skilled in the art can extend and extend the basic concepts of the device structure, driving method and manufacturing method disclosed and indicated by various embodiments of the present invention to other structures and drawings. Undoubtedly, these should all be within the scope of the claims of the present invention.

[0018] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention;

[0019] Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0020] Figure 3 A driving timing diagram of a pixel driving circuit provided in an embodiment of the present invention;

[0021] Figure 4 A driving timing diagram for a display panel provided in an embodiment of the present invention;

[0022] Figure 5 A schematic diagram of another pixel driving circuit is provided for an embodiment of the present invention;

[0023] Figure 6 A schematic diagram of yet another pixel driving circuit is provided for embodiments of the present invention;

[0024] Figure 7 A schematic diagram of yet another pixel driving circuit is provided for embodiments of the present invention;

[0025] Figure 8 A schematic diagram of yet another pixel driving circuit is provided for embodiments of the present invention;

[0026] Figure 9 A schematic diagram of yet another pixel driving circuit is provided for embodiments of the present invention;

[0027] Figure 10 A schematic diagram of another pixel driving circuit is provided for embodiments of the present invention.

[0028] Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention;

[0029] Figure 12 This is a driving timing diagram for another display panel provided in an embodiment of the present invention;

[0030] Figure 13 A flowchart illustrating a driving method for a display panel provided in an embodiment of the present invention;

[0031] Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this invention. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the basic concepts disclosed and indicated in the embodiments of this invention, all other embodiments obtained by those skilled in the art are within the scope of protection of this invention.

[0033] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of a pixel driving circuit provided in an embodiment of the present invention, in conjunction with reference to the reference. Figure 1 and Figure 2 As shown, the display panel 100 includes a display area AA, which includes multiple sub-pixels P arranged in an array. Each sub-pixel P includes a pixel driving circuit 10 and a light-emitting element 20. The pixel driving circuit 10 drives the light-emitting element 20 to emit light. The pixel driving circuit 10 includes a threshold compensation module 11, the control terminal of which is electrically connected to the first scanning signal terminal S1. The pixel driving circuit 10 includes a first pixel driving circuit and a second pixel driving circuit, which are located in sub-pixels P in different rows. The control terminals of the threshold compensation modules 11 of both the first and second pixel driving circuits are electrically connected to the same first scanning signal terminal S1. When the nth frame of the display is displayed, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit. When the (n+1)th frame of the display is displayed, the data writing stage of the second pixel driving circuit is earlier than the data writing stage of the first pixel driving circuit. Here, n is an integer greater than or equal to 1.

[0034] The light-emitting element 20 may include one or more of the following: red, green, blue, white, yellow, cyan, and magenta light-emitting elements, without limitation herein. The light-emitting element may be a light-emitting diode, including but not limited to organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (Mini LEDs), or micro light-emitting diodes (Micro LEDs).

[0035] The specific circuit structures of the first pixel driving circuit and the second pixel driving circuit can be the same or different. Preferably, the circuit structures of the first pixel driving circuit and the second pixel driving circuit are the same. (Reference) Figure 2As shown, the threshold compensation module 11 in the pixel driving circuit 10 is turned on or off under the control of the first scan signal provided by the first scan signal terminal S1. When the first scan signal provided by the first scan signal terminal S1 controls the threshold compensation module 11 to be turned on, the threshold compensation module 11 can perform threshold compensation on the gate of the write driving module 12.

[0036] Understandably, since the first pixel driving circuit and the second pixel driving circuit are located in sub-pixels P in different rows, and the sub-pixels P are displayed row by row, the start time of the data writing phase of the first pixel driving circuit and the second pixel driving circuit in the same frame of display is different. This leads to different durations of threshold compensation by the threshold compensation module 11 of the first pixel driving circuit and the second pixel driving circuit. As a result, the brightness of the light-emitting element 20 driven by the first pixel driving circuit and the brightness of the light-emitting element 20 driven by the second pixel driving circuit may differ, thereby affecting the display effect of the display panel 100 and reducing the display quality. Thus, when the nth frame is displayed, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit. This results in the threshold compensation time after the first pixel driving circuit writes the data signal being displayed being longer than that after the second pixel driving circuit writes the data signal being displayed. Similarly, when the (n+1)th frame is displayed, the data writing stage of the second pixel driving circuit is earlier than the data writing stage of the first pixel driving circuit. This results in the threshold compensation time after the second pixel driving circuit writes the data signal being longer than that after the first pixel driving circuit writes the data signal being displayed. By swapping the order of the data writing stages of the first and second pixel driving circuits in two adjacent frames, the total threshold compensation time of the first and second pixel driving circuits can be made the same, eliminating the difference in display brightness between the sub-pixel P corresponding to the first pixel driving circuit and the sub-pixel P corresponding to the second pixel driving circuit, thereby improving the display effect of the display panel 100.

[0037] In this embodiment, the pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit, located in sub-pixels of different rows. The control terminals of the threshold compensation modules of both the first and second pixel driving circuits are electrically connected to the same first scan signal terminal. This allows the first scan signal provided by the first scan signal terminal to simultaneously control the on / off state of the threshold compensation modules in both the first and second pixel driving circuits. When the nth frame is displayed, the data writing phase of the first pixel driving circuit is earlier than that of the second pixel driving circuit, resulting in a longer threshold compensation time after the first pixel driving circuit writes the data signal. Similarly, when the (n+1)th frame is displayed, the data writing phase of the second pixel driving circuit is earlier than that of the first pixel driving circuit, resulting in a longer threshold compensation time after the first pixel driving circuit writes the data signal.

[0038] The threshold compensation time after the second pixel driving circuit writes the data signal is greater than the threshold compensation time after the first pixel driving circuit writes the data signal, where n is an integer greater than or equal to 1. This ensures that the total threshold compensation time of the first pixel driving circuit and the total threshold compensation time of the second pixel driving circuit are the same in two adjacent display frames, thereby eliminating the brightness difference between the sub-pixels corresponding to the first and second pixel driving circuits and improving the display effect of the display panel.

[0039] Optionally, the first pixel driving circuit and the second pixel driving circuit are located in the sub-pixels P of two adjacent rows.

[0040] Specifically, since the threshold compensation modules of the first pixel driving circuit and the second pixel driving circuit are both electrically connected to the same first scanning signal terminal S1, by setting the first pixel driving circuit and the second pixel driving circuit to be located in the sub-pixels P of two adjacent rows, the wiring can be simplified, which is beneficial to the narrow bezel design of the display panel 100.

[0041] Optionally, the first pixel driving circuit is located in the sub-pixel P in the 2m-1 row, and the second pixel driving circuit is located in the sub-pixel P in the 2m row, or the second pixel driving circuit is located in the sub-pixel P in the 2m-1 row, and the first pixel driving circuit is located in the sub-pixel P in the 2m row, where m is an integer greater than or equal to 1.

[0042] Specifically, the first pixel driving circuit and the second pixel driving circuit are located in the sub-pixels P of two adjacent rows. The first pixel driving circuit can be located in the sub-pixels P of the odd-numbered rows and the second pixel driving circuit can be located in the sub-pixels P of the even-numbered rows, or the first pixel driving circuit can be located in the sub-pixels P of the even-numbered rows and the second pixel driving circuit can be located in the sub-pixels P of the odd-numbered rows. This embodiment of the invention does not impose a specific limitation on this and can be set according to the actual situation.

[0043] Optional, continue to refer to Figure 2 As shown, the pixel driving circuit 10 also includes a driving module 12 and a data writing module 13; the first end of the driving module 12 is electrically connected to the first power supply voltage terminal PVDD, the second end of the driving module 12 is electrically connected to the first electrode of the light-emitting element 20, the second electrode of the light-emitting element 20 is electrically connected to the second power supply voltage terminal PVEE, and the control terminal of the driving module 12 is electrically connected to the first node N1. The driving module 12 is used to control the light-emitting element 20 to emit light during the light-emitting stage; the first end of the data writing module 13 is electrically connected to the data signal terminal Data, the second end of the data writing module 13 is electrically connected to the first end of the driving module 12, and the control terminal of the data writing module 13 is electrically connected to the second scan signal terminal S2. The data writing module 13 is used to write data signals to the first node N1 during the data writing stage; the first end of the threshold compensation module 11 is electrically connected to the second end of the driving module 12, and the second end of the threshold compensation module 11 is electrically connected to the first node N1. The threshold compensation module 11 is used to perform threshold compensation on the driving module 12 during the threshold compensation stage.

[0044] Specifically, the first power supply voltage terminal PVDD can provide a positive voltage signal, and the second power supply voltage terminal can provide a negative voltage signal. During the data writing stage, the data writing module 13 is turned on under the control of the second scan signal provided by the second scan signal terminal S2, so that the data signal Vdata provided by the data signal terminal Data is written to the first node N1 through the turned-on drive module 12 and threshold compensation module 11. Due to the presence of the threshold compensation module 11, the voltage written to the first node N1 is Vdata-Vth, where Vth is the threshold voltage of the drive module 12. Then, during the light emission stage, a current loop is formed between the first power supply voltage terminal PVDD and the second power supply voltage terminal PVEE. Under the influence of the potentials of the first power supply voltage terminal PVDD and the first node N1, a driving current is generated and provided to the light-emitting element 20, driving the light-emitting element 20 to emit light, thereby realizing the image display of the display panel 100.

[0045] Optional, continue to refer to Figure 2As shown, the pixel driving circuit 10 further includes: a first initialization module 14, the first terminal of which is electrically connected to the first reference signal terminal Vref1, the second terminal of which is electrically connected to the first node N1, and the control terminal of which is electrically connected to the third scanning signal terminal S3; a second initialization module 15, the first terminal of which is electrically connected to the second reference signal terminal Vref2, the second terminal of which is electrically connected to the first electrode of the light-emitting element 20, and the control terminal of which is electrically connected to the fourth scanning signal terminal S4; and a first light-emitting control module 16, the first terminal of which is electrically connected to the first electrode of the light-emitting element 20. The first light-emitting control module 16 is electrically connected to the first power supply voltage terminal PVDD, and the second terminal of the first light-emitting control module 16 is electrically connected to the first terminal of the driving module 12. The control terminal of the first light-emitting control module 16 is electrically connected to the enable signal terminal Emit. The second light-emitting control module 17 is electrically connected to the second terminal of the driving module 12, and the second terminal of the second light-emitting control module 17 is electrically connected to the first electrode of the light-emitting element 20. The control terminal of the second light-emitting control module 17 is electrically connected to the enable signal terminal Emit. The storage module 18 is electrically connected to the first power supply voltage terminal PVDD, and the second terminal of the storage module 18 is electrically connected to the first node N1.

[0046] Figure 3 This invention provides a timing diagram for a pixel driving circuit. For example, taking a sub-pixel where the first pixel driving circuit is located in row 2m-1 and the second pixel driving circuit is located in row 2m, and where the effective levels of the first scan signal s1 provided by the first scan signal terminal S1, the second scan signal s2 provided by the second scan signal terminal S2, the third scan signal s3 provided by the third scan signal terminal S3, the fourth scan signal s4 provided by the fourth scan signal terminal S4, and the enable signal emit provided by the enable signal terminal Emit are all low-level signals, in conjunction with reference to... Figure 2 and Figure 3 As shown, Figure 3 An exemplary timing diagram of the driving circuit for the first pixel located in the (2m-1)th row of sub-pixels is shown.

[0047] During the reset phase T1, the third scan signal s3 provided by the third scan signal terminal S3 is a low-level signal, which controls the first initialization module 14 to be turned on, so that the first reference signal provided by the first reference signal terminal Vref1 can reset the first node N1. At the same time, the fourth scan signal s4 provided by the fourth scan signal terminal S4 is a low-level signal, which controls the second initialization module 15 to be turned on, so that the second reference signal provided by the second reference signal terminal Vref2 can reset the first electrode of the light-emitting element 20.

[0048] During the data writing phase T2, the first scan signal s1 provided by the first scan signal terminal S1 is a low-level signal, controlling the threshold compensation module 11 to be turned on. Simultaneously, the second scan signal s2 provided by the second scan signal terminal S2 is a low-level signal, controlling the data line writing module 13 to be turned on. This allows the data signal Vdata provided by the data signal terminal Data to be written to the first node N1 through the turned-on driving module 12 and threshold compensation module 11, and stored in the storage module 18. When the second scan signal s2 provided by the second scan signal terminal S2 changes from a low-level signal to a high-level signal, the data writing module 13 is turned off. At this time, since the first scan signal s1 provided by the first scan signal terminal S1 remains a low-level signal, threshold compensation can continue to be performed on the driving module 12. The duration of the threshold compensation phase T20 for the driving module 12 of the first pixel driving circuit of the 2m-1 row sub-pixel is the time between the moment when the second scan signal s2 provided by the second scan signal terminal S2 changes from a high-level signal to a low-level signal and the moment when the first scan signal s1 provided by the first scan signal terminal S1 changes from a low-level signal to a high-level signal.

[0049] During the light-emitting stage T3, the first scan signal s1 provided by the first scan signal terminal S1, the second scan signal s2 provided by the second scan signal terminal S2, the third scan signal s3 provided by the third scan signal terminal S3, and the fourth scan signal s4 provided by the fourth scan signal terminal S4 are all kept at high level signals, while the enable signal emit provided by the enable signal terminal Emit is kept at low level signal, controlling the first light-emitting control module 16 and the second light-emitting control module 17 to be turned on, so that a current loop is formed between the first power supply voltage terminal PVDD and the second power supply voltage terminal PVEE. Under the action of the potential of the first power supply voltage terminal PVDD and the first node N1, a driving current is generated and provided to the light-emitting element 20, driving the light-emitting element 20 to emit light, thereby realizing the image display of the display panel 100.

[0050] It should be noted that the stage in which the second initialization module 15 resets the first electrode of the light-emitting element 20 can also be located in the data writing stage and the threshold compensation stage, or the reset stage, the data writing stage and the threshold compensation stage, which can be set according to the actual situation.

[0051] Optional, Figure 4 This is a driving timing diagram of a display panel provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 2 and Figure 4As shown, when the nth frame is displayed, the duration of the data writing phase and threshold compensation phase of the first pixel driving circuit is t1, and the duration of the data writing phase and threshold compensation phase of the second pixel driving circuit is t2; when the (n+1)th frame is displayed, the duration of the data writing phase and threshold compensation phase of the second pixel driving circuit is t1, and the duration of the data writing phase and threshold compensation phase of the first pixel driving circuit is t2.

[0052] For example, taking a sub-pixel where the first pixel driving circuit is located in the (2m-1)th row and the second pixel driving circuit is located in the 2mth row, and taking the first scan signal s1 provided by the first scan signal terminal S1 and the second scan signal s2 provided by the second scan signal terminal S2 as an example... Figure 4The driving timing of the first scan signal s1 provided by the first scan signal terminal S1 and the second scan signal s2 provided by the second scan signal terminal S2 in the pixel driving circuit 10 is shown only as an example. When the nth frame of the display screen is displayed, the threshold compensation module 11 of both the first pixel driving circuit and the second pixel driving circuit is controlled to be turned on by the first scan signal s1 provided by the first scan signal terminal S1. At this time, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit. That is, the moment when the second scan signal s2(2m-1) controlling the data writing module 13 of the first pixel driving circuit that controls the 2m-1 row of sub-pixels to switch from a low level signal to a high level signal is earlier than the moment when the second scan signal s2(2m) controlling the data writing module 13 of the second pixel driving circuit that controls the 2m row of sub-pixels to switch from a low level signal to a high level signal is earlier. This makes the duration of the data writing stage and the threshold compensation stage of the first pixel driving circuit t1 and the duration of the data writing stage and the threshold compensation stage of the second pixel driving circuit t2, so that t1 is greater than t2. When the display screen is displayed in the (n+1)th frame, the threshold compensation modules 11 of the first pixel driving circuit and the second pixel driving circuit are both controlled to be turned on by the first scanning signal s1 provided by the first scanning signal terminal S1. At this time, the data writing stage of the second pixel driving circuit is earlier than the data writing stage of the first pixel driving circuit. That is, the moment when the second scanning signal s2(2m) of the second pixel driving circuit that controls the data writing module 13 of the second pixel driving circuit that controls the 2m row sub-pixels changes from a low level signal to a high level signal is earlier than the moment when the second scanning signal s2(2m-1) of the first pixel driving circuit that controls the data writing module 13 of the 2m-1 row sub-pixels changes from a low level signal to a high level signal. This makes the duration of the data writing stage and the threshold compensation stage of the second pixel driving circuit t1, and the duration of the data writing stage and the threshold compensation stage of the first pixel driving circuit t2. Therefore, t1 is greater than t2. Thus, in two adjacent display frames, the total threshold compensation time of the first pixel driving circuit and the total threshold compensation time of the second pixel driving circuit are both t1+t2, thereby eliminating the difference in display brightness between the sub-pixel P corresponding to the first pixel driving circuit and the sub-pixel P corresponding to the second pixel driving circuit, and improving the display effect of the display panel 100.

[0053] Optionally, based on any of the above embodiments, the pixel driving circuit 10 includes a plurality of thin-film transistors, all of which are P-type or N-type thin-film transistors.

[0054] Specifically, when the thin-film transistor is a P-type thin-film transistor, the level signal controlling the thin-film transistor to turn on is a low-level signal, and the level signal controlling the thin-film transistor to turn off is a high-level signal. Conversely, when the thin-film transistor is an N-type thin-film transistor, the level signal controlling the thin-film transistor to turn on is a high-level signal, and the level signal controlling the thin-film transistor to turn off is a low-level signal.

[0055] For example, Figure 5 Another schematic diagram of a pixel driving circuit is provided for an embodiment of the present invention, such as... Figure 5 As shown, the pixel driving circuit 10 contains multiple thin-film transistors, all of which are P-type thin-film transistors. In another embodiment, Figure 6 A schematic diagram of another pixel driving circuit is provided for embodiments of the present invention, such as... Figure 6 As shown, the multiple thin-film transistors in the pixel driving circuit 10 are all N-type thin-film transistors. The specific operation of the pixel driving circuit can be found in the description above, and will not be repeated here.

[0056] In another alternative embodiment, Figure 7 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the driving module 12, the data writing module 13, the first light emission control module 16, the second light emission control module 17, and the second initialization module 15 all include P-type thin-film transistors, while the first initialization module 14 and the threshold compensation module 11 both include N-type thin-film transistors.

[0057] Understandably, due to the operating characteristics of transistors, even when the transistor is off, leakage current will occur when a potential difference exists between the first and second terminals. Since the voltage provided by the first reference signal terminal Vref1 received by the first terminal of the first initialization module 14 is low, when the potential of the first node N1 is higher than the voltage provided by the first reference signal terminal Vref1, a potential difference can easily occur across the first initialization module 14 even when it is off. Therefore, the first initialization module 14 can be configured to include an N-type thin-film transistor. Compared to a P-type thin-film transistor, the N-type thin-film transistor has a larger on / off ratio and lower off-state current, which can reduce the leakage current of the transistor and make the potential of the first node N1 more stable, thereby ensuring the stability of the light emission brightness of the light-emitting element 20. Similarly, since the voltage received at the second terminal of the driving module 12 is usually greater than the potential of the first node N1, even if the threshold compensation module 11 is disconnected, a potential difference may still occur across the threshold compensation module 11. Therefore, the threshold compensation module 11 can be configured to include an N-type thin-film transistor, which can also reduce transistor leakage current and make the potential of the first node N1 more stable, thereby ensuring the stability of the light-emitting element 20's brightness. Furthermore, since N-channel transistors have low power consumption, they also help reduce the power consumption of the display panel.

[0058] Continue to refer to Figure 5 , Figure 6 and Figure 7 The storage module 18 includes a capacitor.

[0059] Optional, continue to refer to Figure 2 , Figure 5 , Figure 6 and Figure 7 The first reference signal terminal Vref1 can be reused as the second reference signal terminal Vref2, and the second scan signal terminal S2 can be reused as the fourth scan signal terminal S4, so as to reduce the number of signal terminals, thereby reducing the number of signal lines transmitting the fourth scan signal and the number of signal lines transmitting the second reference signal, which is beneficial to the narrow bezel design of the display panel.

[0060] Optional, Figure 8 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, as shown below. Figure 8 As shown, the pixel driving circuit 10 also includes a bias adjustment module 19. The first end of the bias adjustment module 19 is electrically connected to the bias voltage terminal Vref3, the control terminal of the bias adjustment module 19 is electrically connected to the fifth scan signal terminal S5, and the second end of the bias adjustment module 19 is electrically connected to the first or second end of the driving module 12.

[0061] For example, Figure 8A schematic diagram of the structure showing the second terminal of the bias adjustment module 19 electrically connected to the first terminal of the drive module 12 is shown. The fifth scan signal provided by the fifth scan signal terminal S5 can control the bias adjustment module 19 to be turned on or off. When the bias adjustment module 19 is turned on, the bias voltage provided by the bias voltage terminal Vref3 can periodically reset the first terminal of the drive module 12, thereby improving the offset or hysteresis phenomenon of the transistor characteristics after long-term operation in the drive module.

[0062] In other embodiments, Figure 9 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, as shown below. Figure 9 As shown, Figure 9 A schematic diagram of the structure showing the electrical connection between the second terminal of the bias adjustment module 19 and the second terminal of the drive module 12 is shown. The fifth scan signal s5 provided by the fifth scan signal terminal S5 can control the bias adjustment module 19 to be turned on or off. When the bias adjustment module 19 is turned on, the bias voltage provided by the bias voltage terminal Vref3 can periodically reset the second terminal of the drive module 12, which can also improve the offset or hysteresis phenomenon of the transistor characteristics after long-term operation in the drive module.

[0063] In an alternative embodiment, Figure 10 This is a schematic diagram of another pixel driving circuit provided in an embodiment of the present invention, as shown below. Figure 10 As shown, the second end of the bias adjustment module 19 is electrically connected to the first end of the drive module 12, and the data writing module 13 is multiplexed as the bias adjustment module 19. In this way, the structure of the pixel drive circuit 10 can be simplified, the number of signal terminals can be reduced, the cost can be reduced, and the display panel can be made thinner and lighter with a narrow bezel design.

[0064] It should be noted that in any of the above embodiments, the bias adjustment module 19 may include a P-type thin film transistor or an N-type thin film transistor, which can be set according to the actual situation, and no specific limitation is made here.

[0065] Optional, Figure 11 This is a schematic diagram of another display panel structure provided in an embodiment of the present invention. Figure 12 This is a driving timing diagram for another display panel provided in an embodiment of the present invention, in conjunction with reference to [reference needed]. Figure 2 , Figure 11 and Figure 12As shown, the second scanning signal terminal S2 includes a first sub-scanning signal terminal S21 and a second sub-scanning signal terminal S22. The first sub-scanning signal terminal S21 is electrically connected to the control terminal of the data writing module 13 of the first pixel driving circuit, and the second sub-scanning signal terminal S22 is electrically connected to the control terminal of the data writing module 13 of the second pixel driving circuit. When the nth frame of the display screen is displayed, the control signals output by the first sub-scanning signal terminal S21 and the second sub-scanning signal terminal S22 sequentially control the first pixel driving circuit and the second pixel driving circuit to write the corresponding data signals. When the n+1th frame of the display screen is displayed, the control signals output by the second sub-scanning signal terminal S22 and the first sub-scanning signal terminal S21 sequentially control the second pixel driving circuit and the first pixel driving circuit to write the corresponding data signals.

[0066] Specifically, during the display of the nth frame, the control signal (i.e., the first scan signal s1) provided by the first sub-scan signal terminal S21 is sequentially shifted and provided to the data writing module 13 of the first pixel driving circuit to control the data writing module 13 to be turned on, so that the data signal terminal Data in the first pixel driving circuit receives the corresponding data signal and writes it to the first node N1, completing the writing of the corresponding data signal to the first pixel driving circuit. The control signal (i.e., the second scan signal s2) provided by the second sub-scan signal terminal S22 is sequentially shifted and provided to the data writing module 13 of the second pixel driving circuit to control the data writing module 13 to be turned on, so that the data signal terminal Data in the second pixel driving circuit receives the corresponding data signal and writes it to the first node N1, completing the writing of the corresponding data signal to the second pixel driving circuit.

[0067] Optional, continue to refer to Figure 11 and Figure 12As shown, the display panel 100 also includes a non-display area NA surrounding the display area AA. The non-display area NA includes multiple cascaded first shift registers 30 and second shift registers 40. The output terminal of the first shift register 30 is the first sub-scan signal terminal S21, and the output terminal of the second shift register 40 is the second sub-scan signal terminal S22. The input terminal of the first shift register 30 is electrically connected to the first clock signal terminal CLK1 and the second clock signal terminal CLK2, and the input terminal of the second shift register 40 is electrically connected to the third clock signal terminal CLK3 and the fourth clock signal terminal CLK4. When the nth frame of the display screen is displayed, the first clock signal terminal CLK1 and the second clock signal terminal CLK4 are connected to the first clock signal terminal CLK1 and the second clock signal terminal CLK2. The clock signals CLK2, CLK3, and CLK4 are provided sequentially to control the control signals output by the first shift register 30 and the second shift register 40 to write the corresponding data signals to the first pixel driving circuit and the second pixel driving circuit. When the display screen is displayed at frame n+1, the clock signals CLK2, CLK1, CLK4, and CLK3 are provided sequentially to control the control signals output by the second shift register 40 and the first shift register 30 to write the corresponding data signals to the second pixel driving circuit and the first pixel driving circuit.

[0068] The first shift register 30 and the second shift register 40 can be located at the same end of the display area AA, or at opposite ends of the display area AA; no specific limitation is made here. For example, Figure 11 The diagram shows that a first shift register 30 and a second shift register 40 are set at both ends of the display area AA. In this way, for the same row of sub-pixels P, they can be controlled by the shift registers on both sides at the same time, so as to avoid the difference in the control signals received by the sub-pixels due to loss during the control signal transmission process, which would affect the display effect.

[0069] Specifically, the signal input terminal of the first-stage first shift register 30 is electrically connected to the first start signal line STV1 that transmits the start pulse signal Stv. The signal input terminal from the second-stage first shift register 30 to the last-stage first shift register 30 is electrically connected to the signal output terminal (i.e., the first sub-scan signal terminal S21) of the first-stage first shift register 30 above it. This allows the start pulse signal Stv transmitted by the first start signal line STV1 to control the start and end times of the effective level (e.g., low level signal) of the first scan signal s21(1) output by the first-stage first shift register 30. In the second-stage first shift register 30, the first scan signal s21(1) output by the signal output terminal of the first-stage first shift register 30 controls the start and end times of the effective level of the first scan signal s21(2) output by it, and so on. Similarly, the signal input terminal of the first-stage second shift register 40 is electrically connected to the second start signal line STV2 that transmits the start pulse signal Stv. The signal input terminal from the second-stage second shift register 40 to the last-stage second shift register 40 is electrically connected to the signal output terminal (i.e., the second sub-scan signal terminal S22) of the previous-stage second shift register 40. This allows the start pulse signal Stv transmitted by the second start signal line STV2 to control the start and end times of the effective level (e.g., low-level signal) of the second scan signal s22(1) output by the first-stage second shift register 40. In the second-stage second shift register 40, the first scan signal s22(1) output by the signal output terminal of the first-stage second shift register 40 controls the start and end times of the effective level of the second scan signal s22(2) output by it, and so on.

[0070] Continue to refer to Figure 12When the nth frame is displayed, the first clock signal terminal CLK1, the second clock signal terminal CLK2, the third clock signal terminal CLK3, and the fourth clock signal terminal CLK4 provide clock signals in sequence. That is, the first clock signal Clk1 provided by the first clock signal terminal CLK1, the second clock signal Clk2 provided by the second clock signal terminal CLK2, the third clock signal Clk3 provided by the third clock signal terminal CLK3, and the fourth clock signal Clk4 provided by the fourth clock signal terminal CLK4 are shifted in sequence. This allows the control signal output by the first shift register 30 (i.e., the first scan signal s21) and the control signal output by the second shift register 40 (i.e., the second scan signal s22) to control the first pixel driving circuit and the second pixel driving circuit to write the corresponding data signals in sequence. When the screen is displayed in the (n+1)th frame, the second clock signal terminal CLK2, the first clock signal terminal CLK1, the fourth clock signal terminal CLK4, and the third clock signal terminal CLK3 provide clock signals in sequence. That is, the timing of the first clock signal Clk1 provided by the first clock signal terminal CLK1 and the second clock signal Clk2 provided by the second clock signal terminal CLK2 is swapped, and the timing of the third clock signal Clk3 provided by the third clock signal terminal CLK3 and the fourth clock signal Clk4 provided by the fourth clock signal terminal CLK4 is swapped. This causes the second clock signal Clk2 provided by the second clock signal terminal CLK2, the first clock signal Clk1 provided by the first clock signal terminal CLK1, the fourth clock signal Clk4 provided by the fourth clock signal terminal CLK4, and the third clock signal Clk3 provided by the third clock signal terminal CLK3 to shift in sequence. This allows the control signal output by the second shift register 40 (i.e., the second scan signal s22) and the control signal output by the first shift register 30 (i.e., the first scan signal s21) to control the second pixel driving circuit and the first pixel driving circuit to write the corresponding data signals in sequence. This ensures that when the nth frame is displayed, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit, and when the (n+1)th frame is displayed, the data writing stage of the second pixel driving circuit is earlier than the data writing stage of the first pixel driving circuit. This makes the total threshold compensation time of the first pixel driving circuit the same as that of the second pixel driving circuit, eliminating the difference in display brightness between the sub-pixels corresponding to the first pixel driving circuit and the sub-pixels corresponding to the second pixel driving circuit, and improving the display effect of the display panel.

[0071] It should be noted that when displaying the nth frame and the (n+1)th frame, for the same row of sub-pixels, the timing of the first or second scan signal controlling the writing of data to that row of sub-pixels changes. Therefore, the data signal to be written also needs to be adjusted accordingly to ensure the accuracy of the written data signal and avoid affecting the display effect of the display panel.

[0072] Based on the same inventive concept, embodiments of the present invention also provide a method for driving a display panel. Figure 13 This is a flowchart of a display panel driving method provided in an embodiment of the present invention, executed by a display panel provided in any of the above embodiments, such as... Figure 13 As shown, the driving method includes:

[0073] S101. When the nth frame is displayed, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit.

[0074] S102. When the screen is displayed in the (n+1)th frame, the data writing stage of the second pixel driving circuit is earlier than the data writing stage of the first pixel driving circuit.

[0075] Where n is an integer greater than or equal to 1.

[0076] Reference Figure 2 and Figure 13 In this embodiment, the pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit, located in sub-pixels of different rows. The control terminals of the threshold compensation modules of both the first and second pixel driving circuits are electrically connected to the same first scanning signal terminal, allowing the first scanning signal provided by the first scanning signal terminal to simultaneously control the on / off state of the threshold compensation modules in both the first and second pixel driving circuits. When the nth frame is displayed, the data writing phase of the first pixel driving circuit is earlier than the data writing phase of the second pixel driving circuit, resulting in a threshold compensation time greater than that of the second pixel driving circuit after writing the data signal. Similarly, when the (n+1)th frame is displayed, the data writing phase of the second pixel driving circuit is earlier than the data writing phase of the first pixel driving circuit, again resulting in a threshold compensation time greater than that of the first pixel driving circuit after writing the data signal, where n is an integer greater than or equal to 1. This ensures that the total threshold compensation time of the first pixel driving circuit and the total threshold compensation time of the second pixel driving circuit are the same in two adjacent display frames, thereby eliminating the difference in display brightness between the sub-pixels corresponding to the first pixel driving circuit and the sub-pixels corresponding to the second pixel driving circuit, and improving the display effect of the display panel.

[0077] Furthermore, embodiments of the present invention also provide a display device. Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 14As shown, the display device 200 includes a display panel 100 provided in any embodiment of the present invention. The display device 200 provided in the embodiments of the present invention can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, medical equipment, industrial control equipment, touch interactive terminal, etc. The embodiments of the present invention do not make any special limitations on these.

[0078] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, The display area includes a plurality of sub-pixels arranged in an array. Each sub-pixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit is used to drive the light-emitting element to emit light. The pixel driving circuit includes a threshold compensation module, and the control terminal of the threshold compensation module is electrically connected to the first scanning signal terminal. The pixel driving circuit includes a first pixel driving circuit and a second pixel driving circuit. The first pixel driving circuit and the second pixel driving circuit are located in the sub-pixels in different rows. The control terminals of the threshold compensation modules of the first pixel driving circuit and the second pixel driving circuit are electrically connected to the same first scanning signal terminal. When the nth frame is displayed, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit. When the screen is displayed in the (n+1)th frame, the data writing phase of the second pixel driving circuit is earlier than the data writing phase of the first pixel driving circuit. Where n is an integer greater than or equal to 1.

2. The display panel according to claim 1, characterized in that, The first pixel driving circuit and the second pixel driving circuit are located in the sub-pixels of two adjacent rows.

3. The display panel according to claim 2, characterized in that, The first pixel driving circuit is located in the sub-pixel of the 2m-1th row, and the second pixel driving circuit is located in the sub-pixel of the 2mth row, or the second pixel driving circuit is located in the sub-pixel of the 2m-1th row, and the first pixel driving circuit is located in the sub-pixel of the 2mth row, where m is an integer greater than or equal to 1.

4. The display panel according to claim 1, characterized in that, The pixel driving circuit also includes a driving module and a data writing module; The first end of the driving module is electrically connected to the first power supply voltage terminal, the second end of the driving module is electrically connected to the first electrode of the light-emitting element, the second electrode of the light-emitting element is electrically connected to the second power supply voltage terminal, and the control end of the driving module is electrically connected to the first node. The driving module is used to control the light-emitting element to emit light during the light-emitting stage. The first end of the data writing module is electrically connected to the data signal end, the second end of the data writing module is electrically connected to the first end of the driving module, and the control end of the data writing module is electrically connected to the second scan signal end. The data writing module is used to write data signals to the first node during the data writing stage. The first end of the threshold compensation module is electrically connected to the second end of the driving module, and the second end of the threshold compensation module is electrically connected to the first node. The threshold compensation module is used to perform threshold compensation on the driving module during the threshold compensation stage.

5. The display panel according to claim 4, characterized in that, When the nth frame is displayed, the duration of the data writing phase and threshold compensation phase of the first pixel driving circuit is t1, and the duration of the data writing phase and threshold compensation phase of the second pixel driving circuit is t2. When the image is displayed in the (n+1)th frame, the duration of the data writing phase and the threshold compensation phase of the second pixel driving circuit is t1, and the duration of the data writing phase and the threshold compensation phase of the first pixel driving circuit is t2.

6. The display panel according to claim 4, characterized in that, The second scanning signal terminal includes a first sub-scanning signal terminal and a second sub-scanning signal terminal. The first sub-scanning signal terminal is electrically connected to the control terminal of the data writing module of the first pixel driving circuit, and the second sub-scanning signal terminal is electrically connected to the control terminal of the data writing module of the second pixel driving circuit. When the nth frame is displayed, the control signals output by the first sub-scan signal terminal and the second sub-scan signal terminal sequentially control the first pixel driving circuit and the second pixel driving circuit to write the corresponding data signals. When the screen is displayed in the (n+1)th frame, the control signals output by the second sub-scan signal terminal and the first sub-scan signal terminal sequentially control the second pixel driving circuit and the first pixel driving circuit to write the corresponding data signals.

7. The display panel according to claim 6, characterized in that, It also includes a non-display area surrounding the display area, the non-display area including a plurality of cascaded first shift registers and second shift registers, the output of the first shift register being the first sub-scan signal terminal, and the output of the second shift register being the second sub-scan signal terminal; The input terminal of the first shift register is electrically connected to the first clock signal terminal and the second clock signal terminal, and the input terminal of the second shift register is electrically connected to the third clock signal terminal and the fourth clock signal terminal; When the nth frame is displayed, the first clock signal terminal, the second clock signal terminal, the third clock signal terminal and the fourth clock signal terminal provide clock signals in sequence, and control signals output by the first shift register and the second shift register control the first pixel driving circuit and the second pixel driving circuit to write corresponding data signals in sequence; When the screen is displayed in the (n+1)th frame, the second clock signal terminal, the first clock signal terminal, the fourth clock signal terminal and the third clock signal terminal provide clock signals in sequence, and the control signals output by the second shift register and the first shift register control the second pixel driving circuit and the first pixel driving circuit to write the corresponding data signals in sequence.

8. The display panel according to claim 4, characterized in that, The pixel driving circuit also includes: A first initialization module, wherein a first terminal of the first initialization module is electrically connected to a first reference signal terminal, a second terminal of the first initialization module is electrically connected to the first node, and a control terminal of the first initialization module is electrically connected to a third scan signal terminal; The second initialization module has a first terminal electrically connected to the second reference signal terminal, a second terminal electrically connected to the first electrode of the light-emitting element, and a control terminal electrically connected to the fourth scanning signal terminal. A first light-emitting control module, wherein a first terminal of the first light-emitting control module is electrically connected to the first power supply voltage terminal, a second terminal of the first light-emitting control module is electrically connected to the first terminal of the driving module, and a control terminal of the first light-emitting control module is electrically connected to an enable signal terminal. The second light-emitting control module has a first terminal electrically connected to the second terminal of the driving module, a second terminal electrically connected to the first electrode of the light-emitting element, and a control terminal electrically connected to the enable signal terminal. The storage module has a first end electrically connected to the first power supply voltage terminal and a second end electrically connected to the first node.

9. The display panel according to claim 8, characterized in that, The pixel driving circuit includes multiple thin-film transistors, all of which are either P-type or N-type thin-film transistors.

10. The display panel according to claim 8, characterized in that, The driving module, the data writing module, the first light emission control module, the second light emission control module, and the second initialization module all include P-type thin-film transistors, while the first initialization module and the threshold compensation module both include N-type thin-film transistors.

11. The display panel according to claim 8, characterized in that, The first reference signal terminal is multiplexed as the second reference signal terminal, and the second scan signal terminal is multiplexed as the fourth scan signal terminal.

12. The display panel according to claim 4, characterized in that, The pixel driving circuit further includes a bias adjustment module. The first end of the bias adjustment module is electrically connected to the bias voltage terminal, the control terminal of the bias adjustment module is electrically connected to the fifth scan signal terminal, and the second end of the bias adjustment module is electrically connected to the first or second end of the driving module.

13. The display panel according to claim 12, characterized in that, The second end of the bias adjustment module is electrically connected to the first end of the drive module, and the data writing module is multiplexed as the bias adjustment module.

14. A driving method for a display panel, characterized in that, Performed by the display panel according to any one of claims 1 to 13, the driving method includes: When the nth frame is displayed, the data writing stage of the first pixel driving circuit is earlier than the data writing stage of the second pixel driving circuit. When the screen is displayed in the (n+1)th frame, the data writing phase of the second pixel driving circuit is earlier than the data writing phase of the first pixel driving circuit. Where n is an integer greater than or equal to 1.

15. A display device, characterized in that, Includes the display panel described in any one of claims 1 to 13.

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