Etching Method for Sc-Containing Layer, Semiconductor Device, Manufacturing Method Thereof, and Process Equipment

Abstract

The present invention relates to the field of semiconductor technology, and in particular to an etching method for a Sc-containing layer, a semiconductor device, a manufacturing method thereof, and a process equipment. The etching method includes a main etching process step and an auxiliary etching process step that are executed cyclically. The main etching process step includes introducing a process gas into a process chamber and exciting to generate a plasma to etch the Sc-containing layer. The auxiliary etching process step includes at least one of a volatilization step and a cooling step. The manufacturing method includes the etching method. The semiconductor device forms a groove gate structure by applying the manufacturing method. The process equipment adopts the etching method or the manufacturing method. By using the etching method, the etching rate of the Sc-containing layer can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular, to an etching method for a Sc-containing layer, a semiconductor device, a manufacturing method thereof, and a process equipment. Background Art

[0002] Modern communication has entered the 5G era, and in the future development towards 6G, higher and higher requirements are put forward for the operating frequency of semiconductor devices. Among them, the operating frequency of semiconductor devices can be improved by increasing the mobility of carriers in the channel. Specifically, a high electron mobility semiconductor device based on a two-dimensional electron gas with high mobility can be selected. In this semiconductor device, the metal in the material of the two-dimensional electron gas system generally uses group IIIA elements (such as Al, Ga, In, etc.), or uses group IIIB metal elements (such as Sc, etc.) with a main valence state of +3.

[0003] The ionic radius of Sc is between Ga and In, and it has the ability to form a Sc-containing alloy with III-V compounds such as AlN and GaN well. The formed Sc-containing alloy has a high piezoelectric coefficient and spontaneous polarization rate. In the semiconductor device prepared with this Sc-containing alloy, the channel has a higher surface charge density and electron mobility. However, in the dry etching process of the Sc alloy, since the by-product ScCl3 generated has a significantly higher boiling point than other metal halides and is difficult to volatilize from the reaction system, the content of Sc affects the etching rate. The higher the content, the more difficult the dry etching is. And there is no effective rapid etching method for the Sc-containing alloy layer in the prior art, which limits the application and popularization of the Sc-containing alloy in semiconductor devices. Summary of the Invention

[0004] The purpose of the present invention is to provide an etching method for a Sc-containing layer, a semiconductor device, a manufacturing method thereof, and a process equipment to solve the technical problem of low etching rate when etching the Sc-containing alloy layer.

[0005] An embodiment of the present invention provides an etching method for a Sc-containing layer. The etching method includes a main etching process step and an auxiliary etching process step that are executed cyclically; wherein,

[0006] The main etching process step includes: introducing a process gas into the process chamber and exciting to generate plasma to etch the Sc-containing layer, and the process gas includes a chlorine-containing gas and an inert gas;

[0007] The auxiliary etching process step includes at least one of a volatilization step and a cooling step;

[0008] The volatilization step includes: reducing the lower electrode power to zero power or close to zero power, and reducing the process gas to zero flow rate or close to zero flow rate;

[0009] The cooling step includes: reducing the lower electrode power to zero power or close to zero power, reducing the chlorine-containing gas to zero flow rate or close to zero flow rate, and continuously introducing an inert gas.

[0010] Optionally, the main etching process step includes a first etching step and / or a second etching step. The process gases used in the first etching step and the second etching step are the same. The lower electrode power of the first etching step is greater than that of the second etching step.

[0011] Optionally, the ratio of the lower electrode power of the first etching step to that of the second etching step is (1.2 - 1.8):1;

[0012] and / or, the ratio of the process duration of the first etching step to that of the second etching step is 1:(4 - 6).

[0013] Optionally, the lower electrode power of the first etching step is 100W - 1000W; the lower electrode power of the second etching step is 100W - 1000W;

[0014] and / or, the process duration of the first etching step is 1.2s - 3s, and the process duration of the second etching step is 8s - 12s.

[0015] Optionally, in the main etching process step, the flow rate ratio of the chlorine-containing gas to the inert gas is (0.3 - 0.5):1;

[0016] and / or, in the main etching process step, the flow rate of the chlorine-containing gas is 20sccm - 200sccm, and the flow rate of the inert gas is 10sccm - 1000sccm.

[0017] Optionally, the chlorine-containing gas includes at least one of SiCl4, BCl3, and Cl2, and / or the inert gas includes Ar.

[0018] Optionally, the chlorine-containing gas includes BCl3 and Cl2, and the flow rate ratio of BCl3 to Cl2 is (0.9 - 1.1):1;

[0019] Or, the chlorine-containing gas includes SiCl4.

[0020] Optionally, the process duration of the volatilization step is 0.5s - 1.5s; and / or the process duration of the cooling step is 0.5s - 1.5s.

[0021] Compared with the prior art, the etching method for the Sc layer provided by the embodiment of the present invention has the following beneficial effects:

[0022] In an embodiment of the present invention, in the main etching process step, process gases such as chlorine-containing gas and inert gas are introduced into the process chamber and excited to generate plasma to effectively etch the Sc-containing layer; in the auxiliary etching process step, the power of the lower electrode is reduced to zero power or close to zero power. When the process gas is reduced to zero flow rate or close to zero flow rate, it is convenient for the etching by-products to volatilize quickly during evacuation. When the chlorine-containing gas is reduced to zero flow rate or close to zero flow rate and the inert gas continues to be introduced, it is not only convenient for at least part of the etching by-products to volatilize quickly during evacuation, but also can take away the heat of the Sc-containing layer to achieve etching uniformity; by repeatedly executing the main etching process step and the auxiliary etching process step in this way, the etching by-products generated in each cycle step can be volatilized in time, thereby reducing or even avoiding the influence on the etching depth and etching quality of the subsequent cycle steps, ensuring the etching depth and etching quality (such as etching uniformity) of each cycle step, and further improving the etching rate of the Sc-containing layer, that is, realizing the rapid etching of the Sc-containing layer.

[0023] An embodiment of the present invention further provides a manufacturing method of a semiconductor device, including the steps of:

[0024] Providing a substrate;

[0025] Forming a Sc-containing layer on the substrate;

[0026] Applying the above etching method to etch the Sc-containing layer to form a groove with a predetermined depth, where the predetermined depth is less than the thickness of the Sc-containing layer;

[0027] Forming a gate in the groove and forming source and drain electrodes on both sides of the groove.

[0028] Using the etching method of the Sc-containing layer provided by the embodiment of the present invention can produce the same beneficial effects as the above etching method, that is, improving the etching efficiency, which will not be elaborated here.

[0029] An embodiment of the present invention further provides a semiconductor process equipment, including a process chamber, an air inlet assembly, an upper electrode assembly, a lower electrode assembly and a controller. The controller includes at least one processor and at least one memory. A computer program is stored in the memory, and when the computer program is executed by the processor, the above etching method or the above manufacturing method is realized.

[0030] The process equipment provided by the embodiment of the present invention has the beneficial effects of the above etching method and manufacturing method, which will not be elaborated here.

[0031] An embodiment of the present invention further provides a semiconductor device, including:

[0032] A substrate;

[0033] A Sc-containing layer is provided on the substrate, and a groove is formed on a side of the Sc-containing layer away from the substrate, and a depth of the groove is less than a thickness of the Sc-containing layer;

[0034] A source electrode is provided on a first side of the groove;

[0035] A drain electrode is provided on a second side of the groove, the second side is opposite to the first side, and a distance between the source electrode and an edge of the first side of the groove is less than a distance between the drain electrode and an edge of the second side of the groove;

[0036] A gate electrode is provided in the groove, and a distance between the gate electrode and the source electrode is less than a distance between the gate electrode and the drain electrode.

[0037] Optionally, the Sc-containing layer includes Sc x Al 1-x N, where a value range of x is less than 43%; or,

[0038] A distance between a bottom of the groove and a side of the Sc-containing layer facing the substrate ranges from 1 nm to 100 nm; or,

[0039] A distance between the source electrode and an edge of the first side of the groove is from 0.1 μm to 0.5 μm; or,

[0040] A distance between the drain electrode and an edge of the second side of the groove is from 0.5 μm to 5 μm; or,

[0041] A length of the gate electrode is from 0.5 μm to 5 μm, and a width thereof is from 0.1 mm to 10 mm.

[0042] In the semiconductor device provided by an embodiment of the present invention, the Sc-containing layer is a barrier layer, and the formation of the groove can thin the barrier layer where the gate electrode is located. In this way, when a gate voltage is provided to the gate electrode for regulation, a potential well appears, thereby forming a two-dimensional electron gas, achieving a high electron mobility of the semiconductor device; when no gate voltage is applied, the potential well of the formed two-dimensional electron gas disappears, and the semiconductor device is in an off state, that is, the semiconductor device is a normally-off semiconductor device, realizing the safety control performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained according to the provided drawings without creative efforts.

[0044] Figure 1Schematic cross-sectional structure diagram of a semiconductor device with a Sc layer provided by an embodiment of the present invention;

[0045] Figures 2a - 2n Schematic process flow diagram of a manufacturing method of a Sc-containing semiconductor device provided by an embodiment of the present invention;

[0046] Figure 3a In an embodiment of the present invention, etching Sc x Al 1-x N result characterization diagram;

[0047] Figure 3b For Figure 3a In, partial enlarged schematic diagram at L;

[0048] Figures 3c - 3d For Figure 3a In, partial enlarged schematic diagram at R;

[0049] Figures 4a - 4d For Figure 3a In, partial enlarged schematic diagram at M, the difference lies in the etching thickness of Sc x Al 1-x N;

[0050] Figures 5a - 5d Etching Sc of Comparative Example 1 x Al 1-x N result characterization diagram;

[0051] Figures 6a - 6b Etching Sc of Comparative Example 1 x Al 1-x N by-product EDX characterization diagram;

[0052] Figure 7 Etching result statistical chart of Comparative Example 2;

[0053] Figures 8a - 8b Etching result characterization diagram of Comparative Example 3;

[0054] Figures 9a - 9d Etching result characterization diagram of Comparative Example 4;

[0055] Figure 10 Schematic structure diagram of semiconductor process equipment in an embodiment of the present invention;

[0056] Figures 11a - 11b For Figure 1 Energy level schematic diagram of the semiconductor device in;

[0057] Explanation of reference numerals:

[0058] 100 - epitaxial wafer; 110 - epitaxial layer; 120 - substrate; 130 - buffer layer;

[0059] 200 - Barrier layer; 210 - Source electrode; 220 - Gate electrode; 230 - Drain electrode; 240 - Groove;

[0060] 310 - First photoresist layer; 311 - First through - groove;

[0061] 320 - Second photoresist layer; 321 - Second through - groove; 322 - Third through - groove;

[0062] 330 - Third photoresist layer; 331 - Fourth through - groove;

[0063] 400 - Passivation layer;

[0064] 500 - Process chamber; 510 - Upper electrode assembly; 520 - Lower electrode assembly;

[0065] 511 - RF coil; 512 - Upper RF power supply; 513 - Upper matcher;

[0066] 521 - Wafer carrier device; 522 - Lower RF power supply; 523 - Lower matcher. Detailed implementation manners

[0067] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0068] Sc is a group IIIB metal element with a main valence state of +3. Its ionic radius is between Ga and In, and it has the ability to form alloys well with III - V compounds such as AlN and GaN, such as Sc x Al 1-x N, etc. The Sc - containing layer (Sc x Al 1- x N) has a relatively high piezoelectric coefficient and spontaneous polarization rate. The semiconductor devices prepared can make the channel have a higher surface charge density (for example, the mobility of the HEMT using Sc x Al 1-x N as the barrier layer is about 5 times that of Al x Ga 1-x N), thereby improving the mobility of the semiconductor device. In the related etching processes for dry etching of the Sc - containing layer, Sc reacts with Cl to form a by - product ScCl3. This by - product will adhere to the sidewalls of the etching holes and is not easily volatilized. Therefore, it affects the etching rate of the Sc - containing layer, and the etching angle of the Sc - containing layer cannot be consistent with the angle of the photoresist, affecting the etching uniformity and etching quality.

[0069] The embodiment of the present invention provides an etching method for a Sc-containing layer, a semiconductor device, a manufacturing method thereof, and a process equipment. During the etching process, the etching rate and the etching quality can be improved, and the angle of the Sc-containing layer can be made basically consistent with the angle of the photoresist. The present invention is further described in detail below through specific embodiments and in combination with the accompanying drawings.

[0070] Embodiment 1

[0071] The embodiment of the present invention provides an etching method for a Sc-containing layer, the etching method comprising a main etching process step and an auxiliary etching process step which are performed cyclically; wherein:

[0072] The main etching process step includes: introducing a process gas into the process chamber and exciting to generate plasma to etch the Sc-containing layer, wherein the process gas includes a chlorine-containing gas and an inert gas;

[0073] The auxiliary etching process step includes: at least one of a volatilization step and a cooling step;

[0074] The volatilization step includes: reducing the power of the lower electrode to zero power or close to zero power, reducing the process gas to zero flow or close to zero flow;

[0075] The cooling step includes: reducing the power of the lower electrode to zero power or close to zero power, reducing the chlorine-containing gas to zero flow or close to zero flow, and continuing to introduce inert gas.

[0076] In the embodiment of the present invention, in the main etching process step, process gases such as chlorine-containing gas and inert gas are introduced into the process chamber and excited to generate plasma, so as to etch the Sc-containing layer; in the auxiliary etching process step, the power of the lower electrode is reduced to zero power or close to zero power. When the process gas is reduced to zero flow or close to zero flow, it is convenient for the by-products generated by the etching process to volatilize quickly during vacuuming. When the chlorine-containing gas is reduced to zero flow or close to zero flow and the inert gas is continuously introduced, it is convenient not only for at least part of the by-products generated by the etching process to volatilize quickly during vacuuming, but also for the heat of the Sc-containing layer to be taken away, so as to ensure the uniformity of etching; in this way, the main etching process step and the auxiliary etching process step are cyclically executed, so as to volatilize the by-products generated in each cycle step in time, thereby reducing or even avoiding affecting the etching depth and etching quality of the subsequent cycle step, so as to ensure the etching depth and etching quality (such as etching uniformity) of each cycle step, and improve the etching rate and etching uniformity of the Sc-containing layer, that is, to achieve rapid etching of the Sc-containing layer.

[0077] In the embodiments of the present invention, the main etching process step includes at least one of a first etching step and a second etching step. Among them, the process gases used in the first etching step and the second etching step are the same, and the lower electrode power of the first etching step is greater than that of the second etching step. The lower electrode power of the first etching step is greater than that of the second etching step. With such a setting, some chemical bonds are broken during the process of the first etching step, which facilitates the subsequent etching in the second etching step and generates a large amount of heat, which is beneficial to the volatilization of by-products.

[0078] In the embodiments of the present invention, the power ratio of the lower electrodes of the first etching step and the second etching step can be selected as (1.2 - 1.8):1, preferably (1.3 - 1.7):1, more preferably (1.4 - 1.6):1, and even more preferably 1.5:1. With such a matching of the lower electrode power, the etching efficiency and quality in the corresponding etching process can be ensured, which is beneficial to the timely volatilization of by-products.

[0079] Specifically, in the embodiments of the present invention, the lower electrode power of the first etching step is 100W - 1000W, preferably 300W - 800W, more preferably 500W - 700W, and even more preferably 600W; the lower electrode power of the second etching step is 100W - 1000W, preferably 200W - 800W, more preferably 300W - 500W, and even more preferably 400W. With such a setting of the lower electrode power, the etching efficiency and quality in the corresponding etching process can be ensured, which is beneficial to the timely volatilization of by-products.

[0080] In the embodiments of the present invention, the process duration ratio of the first etching step to the second etching step is 1:(4 - 6), preferably 1:5. With such a matching of the process duration, the etching efficiency and quality in the corresponding etching process can be ensured.

[0081] Specifically, in the embodiments of the present invention, the process duration of the first etching step is 1.2s - 3s, preferably 1.5s - 2.5s, and even more preferably 2s; the process duration of the second etching step is 8s - 12s, preferably 9s - 11s, and even more preferably 10s. With such a setting of the process duration, the etching efficiency and quality in the corresponding etching process can be ensured.

[0082] In the embodiments of the present invention, in the main etching process step, the flow rate ratio of the chlorine-containing gas to the inert gas is (0.3 - 0.5):1, preferably (0.35 - 0.45):1, and even more preferably 0.4:1. With such a matching of the chlorine-containing gas and the inert gas, the etching efficiency and quality can be ensured in the corresponding etching process.

[0083] Specifically, in the main etching process step, the flow rate of the chlorine-containing gas is 20 sccm to 200 sccm, preferably 25 sccm to 150 sccm, more preferably 30 sccm to 100 sccm, still more preferably 35 sccm to 70 sccm, and even more preferably 40 sccm. The flow rate of the inert gas is 10 sccm to 1000 sccm, preferably 30 sccm to 800 sccm, more preferably 50 sccm to 500 sccm, still more preferably 80 sccm to 200 sccm, and even more preferably 100 sccm. By setting the gas flow rates of the chlorine-containing gas and the inert gas in this way, the etching efficiency and quality can be ensured during the corresponding etching process.

[0084] In the embodiment of the present invention, in the main etching process step, the chlorine-containing gas includes at least one of SiCl4, BCl3, and Cl2. For example, the chlorine-containing gas includes BCl3 and Cl2, and the flow rate ratio of BCl3 to Cl2 is (0.9 to 1.1):1, preferably (0.99 to 1.05):1, and more preferably 1:1; alternatively, the chlorine-containing gas includes SiCl4. Both BCl3 and SiCl4 can play an etching role and a sidewall protection role, while Cl2 only has a pure etching role. Therefore, when selecting a chlorine-containing gas with sidewall protection performance (such as BCl3 and SiCl4), the sidewalls can be protected during the etching process, thereby achieving anisotropic etching and ensuring the angle consistency between the Sc-containing layer and the photoresist during the etching process. Selecting Cl2 can increase the etching rate, ensure the etching rate, and reduce the deposition amount of sidewall deposits, facilitating the subsequent cleaning process and ensuring the etching angle consistency between the Sc-containing layer and the photoresist during the etching process. Therefore, when selecting the process gas, try to select a chlorine-containing gas with sidewall protection performance and Cl2 with a high etching rate to simultaneously ensure the etching efficiency and the angle consistency, and further ensure the etching uniformity and quality.

[0085] In the embodiment of the present invention, in the main etching process step, the inert gas includes Ar; selecting Ar as the inert gas can ensure the etching efficiency and quality during the corresponding etching process.

[0086] In the embodiment of the present invention, the process duration of the volatilization step is 0.5 s to 1.5 s, more preferably 0.8 s to 1.2 s, and even more preferably 1 s; by setting it in this way, the purpose of setting the process duration of the volatilization step to a shorter time (such as 1 s, 2 s, etc.) is to reduce the overall process duration without affecting the etching quality, thereby increasing the etching rate.

[0087] In the embodiments of the present invention, the process duration of the cooling step is 0.5 s to 1.5 s, more preferably 0.8 s to 1.2 s, and even more preferably 1 s. By setting it in this way, the purpose of setting the process duration of the cooling step to a relatively short time (for example, 1 s, 2 s, etc.) is to reduce the overall process duration and improve the etching rate without affecting the etching quality. However, the process duration cannot be too short, otherwise the effect of this step cannot be achieved. Although a longer process duration for the volatilization step and the cooling step has a better effect, it will affect the production capacity. In the examples of the present invention, the process durations of the volatilization step and the cooling step are set to 1 s.

[0088] In the volatilization step, the power of the lower electrode and all process gases can be turned off to facilitate the rapid volatilization of by-products under the action of vacuum pumping; or, the power of the lower electrode in the volatilization step can be set to a relatively small value, even adjusted to be close to zero, for example, 1 W, and the process gases in the volatilization step can be set to a relatively small value, even adjusted to be close to zero, for example, the gas flow rates of the chlorine-containing gas and Ar are both set to 1 sccm. By setting it in this way, on the one hand, the by-products can still be volatilized in time, and on the other hand, when quickly switching process steps, there is no need to turn on / off the radio frequency and no need to open / close the gas pipeline valves, thus avoiding the frequent on / off of the radio frequency and the frequent opening / closing of the gas pipeline valves.

[0089] In the cooling step, the power of the lower electrode and the chlorine-containing gas can be turned off, and a small flow rate of Ar can still be introduced to facilitate the timely cooling of the wafer to be etched and the timely volatilization of at least part of the by-products under the action of vacuum pumping; or, the power of the lower electrode in the cooling step can be set to a relatively small value, even adjusted to be close to zero, for example, 1 W, the chlorine-containing gas in the cooling step can be adjusted to be close to zero, for example, 1 sccm, and a small gas flow rate of Ar can continue to be introduced, for example, 10 sccm. By setting it in this way, on the one hand, the wafer to be etched can still be cooled in time and at least part of the by-products can be volatilized in time, and on the other hand, when quickly switching process steps, there is no need to turn on / off the radio frequency and no need to open / close the gas pipeline valves, thus avoiding the frequent on / off of the radio frequency and the frequent opening / closing of the gas pipeline valves.

[0090] In the embodiments of the present invention, a stabilization step and a glow discharge step can also be included before cycling the main etching process step and the auxiliary etching process step, and a desorption step can also be included after cycling the main etching process step and the auxiliary etching process step. Among them, the process parameters in each step are shown in the following specific examples.

[0091] In the embodiments of the present invention, the etching method mainly includes a main etching process step and an auxiliary etching process step. Among them, the main etching process step includes at least one of a first etching step and a second etching step, and the auxiliary etching process step includes at least one of a volatilization step and a cooling step. Hereinafter, taking the main etching process step including the first etching step and the second etching step, and the auxiliary etching process step including the volatilization step and the cooling step as an example, the present invention will be described in more detail as follows.

[0092] In a specific example of the present invention, the etching method specifically includes the following steps:

[0093] S1100, stabilization step;

[0094] During the process of the stabilization step, the chamber pressure is 1 mTorr to 30 mTorr, preferably 3 mTorr to 10 mTorr, and further preferably 5 mTorr; the upper electrode power is zero, the lower electrode power is zero, the argon (Ar) flow rate is 10 sccm to 1000 sccm, preferably 30 sccm to 800 sccm, further preferably 50 sccm to 500 sccm, further preferably 80 sccm to 200 sccm, and more preferably 100 sccm; the flow rate of the chlorine-containing gas is 20 sccm to 200 sccm, preferably 25 sccm to 150 sccm, further preferably 30 sccm to 100 sccm, still further preferably 35 sccm to 70 sccm, and more preferably 40 sccm; the process duration is 2 s to 8 s, preferably 4 s to 6 s, and further preferably 5 s.

[0095] S1200, glow starting step;

[0096] During the process of the starting step, the chamber pressure is 1 mTorr to 30 mTorr, preferably 3 mTorr to 10 mTorr, more preferably 5 mTorr; the power at the center of the upper electrode is 100 W to 1000 W, preferably 300 W to 800 W, further preferably 600 W; the power at the edge of the upper electrode is 500 W to 1500 W, preferably 700 W to 1300 W, further preferably 800 W to 1200 W, further preferably 900 W to 1000 W, more preferably 1000 W; the power of the lower electrode is zero, the flow rate of argon (Ar) is 10 sccm to 1000 sccm, preferably 30 sccm to 800 sccm, further preferably 50 sccm to 500 sccm, further preferably 80 sccm to 200 sccm, more preferably 100 sccm; the flow rate of the chlorine-containing gas is 20 sccm to 200 sccm, preferably 25 sccm to 150 sccm, further preferably 30 sccm to 100 sccm, still further preferably 35 sccm to 70 sccm, more preferably 40 sccm; the process duration is 2 s to 8 s, preferably 4 s to 6 s, further preferably 5 s.

[0097] S1310, the first etching step;

[0098] During the process of the first etching step, the power of the lower electrode is 100 W to 1000 W, further preferably 300 W to 800 W, further preferably 500 W to 700 W, more preferably 600 W. With such settings, the etching efficiency and quality can be ensured. Since the power of the lower electrode is relatively high, some chemical bonds can be broken during the process to facilitate subsequent etching, and a large amount of heat is generated, which is beneficial to the volatilization of by-products.

[0099] During the process of the first etching step, the flow rate of argon (Ar) is 10 sccm to 1000 sccm, preferably 30 sccm to 800 sccm, further preferably 50 sccm to 500 sccm, further preferably 80 sccm to 200 sccm, more preferably 100 sccm; the flow rate of the chlorine-containing gas is 20 sccm to 200 sccm, preferably 25 sccm to 150 sccm, further preferably 30 sccm to 100 sccm, still further preferably 35 sccm to 70 sccm, more preferably 40 sccm. By setting the flow rates of the chlorine-containing gas and the inert gas in this way, the etching efficiency and quality can be ensured.

[0100] During the process of the first etching step, the process duration is 1 s to 5 s, preferably 1.5 s to 3 s, further preferably 2 s. With such settings, the etching efficiency and quality can be ensured.

[0101] In addition, during the process of the first etching step, the chamber pressure is 1 mTorr to 30 mTorr, preferably 3 mTorr to 10 mTorr, and more preferably 5 mTorr; the center power of the upper electrode is 100 W to 1000 W, preferably 300 W to 800 W, and further preferably 600 W; the edge power of the upper electrode is 500 W to 3000 W, preferably 1000 W to 2000 W, and further preferably 1500 W.

[0102] S1320, the second etching step;

[0103] During the process of the second etching step, the power of the lower electrode is 100 W to 1000 W, preferably 200 W to 800 W, further preferably 300 W to 500 W, and more preferably 400 W; with such settings, the etching efficiency and quality can be ensured.

[0104] During the process of the second etching step, the flow rate of argon (Ar) is 10 sccm to 1000 sccm, preferably 30 sccm to 800 sccm, further preferably 50 sccm to 500 sccm, further preferably 80 sccm to 200 sccm, and more preferably 100 sccm; the flow rate of the chlorine-containing gas is 20 sccm to 200 sccm, preferably 25 sccm to 150 sccm, further preferably 30 sccm to 100 sccm, still further preferably 35 sccm to 70 sccm, and more preferably 40 sccm; by setting the flow rates of the chlorine-containing gas and the inert gas in this way, the etching efficiency and quality can be ensured.

[0105] During the process of the second etching step, the process duration is 5 s to 15 s, preferably 8 s to 12 s, and further preferably 10 s; with such settings, the etching efficiency and quality can be ensured.

[0106] In addition, during the process of the second etching step, the chamber pressure is 1 mTorr to 30 mTorr, preferably 5 mTorr; the center power of the upper electrode is 100 W to 1000 W, preferably 300 W to 800 W, and further preferably 600 W; the edge power of the upper electrode is 500 W to 3000 W, preferably 1000 W to 2000 W, and further preferably 1500 W.

[0107] S1330, the volatilization step;

[0108] During the process of the volatilization step, the power of the lower electrode is 0.5 W to 5 W, preferably 0.8 W to 2 W, and more preferably 1 W; the flow rate of argon (Ar) is 0.5 sccm to 5 sccm, preferably 0.8 sccm to 2 sccm, and more preferably 1 sccm; the flow rate of the chlorine-containing gas is 0.5 sccm to 5 sccm, preferably 0.8 sccm to 8 sccm, and more preferably 1 sccm. With such settings, on the one hand, the by-products can be volatilized in time, and on the other hand, when quickly switching process steps, it is not necessary to turn on / off the radio frequency, nor to open / close the gas pipeline valves, thus avoiding the frequent on / off of the radio frequency and the frequent opening / closing of the gas pipeline valves.

[0109] During the process of the volatilization step, the process duration is 0.5 s to 1.5 s, preferably 0.8 s to 1.2 s, and more preferably 1 s. With such settings, the overall process duration can be reduced without affecting the etching quality, thereby improving the etching rate.

[0110] In addition, during the process of the volatilization step, the chamber pressure is 1 mTorr to 30 mTorr, preferably 5 mTorr; the center power of the upper electrode is 100 W to 1000 W, preferably 300 W to 800 W, and more preferably 600 W; the edge power of the upper electrode is 500 W to 3000 W, preferably 1000 W to 2000 W, and more preferably 1500 W.

[0111] S1340, cooling step;

[0112] During the process of the cooling step, the power of the lower electrode is 0.5 W to 5 W, more preferably 0.8 W to 2 W, and more preferably 1 W; the flow rate of argon (Ar) is 1 sccm to 15 sccm, more preferably 8 sccm to 12 sccm, and more preferably 10 sccm; the flow rate of the chlorine-containing gas is 0.5 sccm to 5 sccm, more preferably 0.8 sccm to 8 sccm, and more preferably 1 sccm. On the one hand, the wafer to be etched can still be cooled in time, and at least part of the by-products can be volatilized in time. On the other hand, when quickly switching process steps, it is not necessary to turn on / off the radio frequency, nor to open / close the gas pipeline valves, thus avoiding the frequent on / off of the radio frequency and the frequent opening / closing of the gas pipeline valves.

[0113] During the process of the cooling step, the process duration is 0.5 s to 1.5 s, more preferably 0.8 s to 1.2 s, and even more preferably 1 s. With such settings, the overall process duration can be reduced without affecting the etching quality, thereby improving the etching rate.

[0114] In addition, during the process of the cooling step, the chamber pressure is 1 mTorr to 30 mTorr, preferably 3 mTorr to 10 mTorr, and more preferably 5 mTorr; the power at the center of the upper electrode is 100 W to 1000 W, preferably 300 W to 800 W, and more preferably 600 W; the power at the edge of the upper electrode is 500 W to 3000 W, preferably 1000 W to 2000 W, and more preferably 1500 W.

[0115] S1400, the desorption step;

[0116] During the process of the desorption step, the chamber pressure is 10 mTorr to 100 mTorr, preferably 30 mTorr to 70 mTorr, and more preferably 50 mTorr; the power at the center of the upper electrode is 100 W to 1000 W, preferably 300 W to 700 W, and more preferably 400 W to 600 W, and even more preferably 500 W; the power at the edge of the upper electrode is 100 W to 1000 W, preferably 300 W to 700 W, and more preferably 400 W to 600 W, and even more preferably 500 W; the power of the lower electrode is zero; the chlorine-containing gas includes chlorine gas, and the flow rate of chlorine gas is 10 sccm to 1000 sccm, preferably 20 sccm to 500 sccm, more preferably 50 sccm to 200 sccm, and even more preferably 100 sccm, and the flow rate of argon (Ar) is 10 sccm to 1000 sccm, preferably 50 sccm to 600 sccm, more preferably 100 sccm to 300 sccm, and even more preferably 200 sccm; the process duration is 2 s to 8 s, preferably 4 s to 6 s, and more preferably 5 s.

[0117] In the examples of the present invention, the chlorine-containing gas in the above-mentioned stabilization step, glow discharge step, first etching step, and second etching step includes BCl3 and Cl2. Among them, the flow rate of BCl3 is 10 sccm to 100 sccm, preferably 15 sccm to 50 sccm, and more preferably 20 sccm; the flow rate of Cl2 is 10 sccm to 100 sccm, preferably 15 sccm to 50 sccm, and more preferably 20 sccm. In addition, the chlorine-containing gas SiCl4 can be used to replace the above-mentioned chlorine-containing gases BCl3 and Cl2, and the flow rate of SiCl4 is 10 sccm to 100 sccm, preferably 15 sccm to 50 sccm, and more preferably 20 sccm.

[0118] In addition, in the examples of the present invention, the coolant temperature of the pedestal is -15°C to 60°C, preferably 0°C to 50°C, and more preferably 40°C.

[0119] To present the etching method in the above examples of the present invention more clearly and in detail, the process parameters in each process step are described in the following table. See Table 1 and Table 2 below for details.

[0120]

[0121] Table 1: Plasma Etching Process Recipe in the Examples of the Present Invention

[0122]

[0123] Table 2: Process Recipes for the Main Etching Process Step and the Auxiliary Etching Process Step in the Examples of the Present Invention. In the above-mentioned cyclic execution of the main etching process step and the auxiliary etching process step, at least one of the first etching step and the second etching step is selected, and at least one of the volatilization step and the cooling step is selected. For example, it can be the first etching step + cooling step in a cycle, the second etching step + cooling step in a cycle, the first etching step + volatilization step in a cycle, the second etching step + volatilization step in a cycle. It can also be selected to cycle the first etching step + volatilization step + cooling step, the second etching step + volatilization step + cooling step, the first etching step + the second etching step + cooling step, the first etching step + the second etching step + volatilization step. It can also select all of them, that is: cycle the first etching step + the second etching step + volatilization step + cooling step (in Table 2, the main etching process step includes the first etching step and the second etching step, and the auxiliary etching process step includes the volatilization step and the cooling step), and BCl3 and Cl2 can also use chlorine-containing gases such as SiCl4; among them, BCl3 and SiCl4 can not only play an etching role but also play a sidewall protection role, and Cl2 only has a pure etching role. Therefore, when selecting a chlorine-containing gas with sidewall protection performance (such as BCl3 and SiCl4), during the etching process, it can protect the sidewalls, thereby realizing anisotropic etching and ensuring the angle consistency between the Sc-containing layer and the photoresist during the etching process. Selecting Cl2 can accelerate the etching rate, ensure the etching rate, and reduce the deposition amount of sidewall deposits, facilitating the subsequent cleaning process and ensuring the etching angle consistency between the Sc-containing layer and the photoresist during the etching process; therefore, when selecting the process gas, try to select a chlorine-containing gas with sidewall protection performance and Cl2 with a high etching rate to simultaneously ensure the etching efficiency and the angle consistency, and further ensure the etching uniformity and the etching quality.

[0124] Specifically in the examples of the present invention, the lower electrode power of the first etching step should be significantly greater than that of the second etching step, while the lower electrode power in the volatilization step and the cooling step should be as low as possible. The gas flow rate (chlorine-containing gas and inert gas) in the volatilization step should be as small as possible, and the chlorine-containing gas flow rate in the cooling step should be as small as possible. A little inert gas flow rate should be appropriately reserved in the cooling step to better cool the wafer to be etched.

[0125] The purpose of setting the lower electrode power, chlorine-containing gas flow rate and Ar gas flow rate parameter values ​​of the volatilization step to 1 is to avoid frequent opening and closing of the radio frequency and frequent opening and closing of the valve of the gas pipeline when the volatilization step is quickly switched; the purpose of setting the lower electrode power and chlorine-containing gas flow rate parameter values ​​of the cooling step to 1 and the Ar gas flow rate parameter to 10 (that is, continuing to introduce a small amount of inert gas such as Ar) is to avoid frequent opening and closing of the radio frequency and frequent opening and closing of the valve of the gas pipeline when the cooling step is quickly switched, and to ensure the cooling effect of the wafer to be etched; the purpose of setting the process duration to a shorter time (for example, 1s, 2s, etc.) is to reduce the process time and increase the etching rate without affecting the etching quality, but the process duration cannot be too short, otherwise the effect of this step will not be achieved. Although longer process durations of the volatilization step and the cooling step will have better effects, they will affect production capacity. In the example of the present invention, the process durations of the volatilization step and the cooling step are set to 1s.

[0126] The power of the lower electrode in the first etching step is greater than that in the second etching step. Its function is to break some chemical bonds in the first etching process to facilitate subsequent etching and generate a large amount of heat, which is beneficial to the volatilization of by-products. In the volatilization step, the power of the lower electrode is turned off, all air intakes are turned off, and vacuum is drawn. Under the action of vacuum, the by-products are quickly volatilized (there is no other air intake, so only the by-products can be extracted). In the cooling step, the power of the lower electrode is turned off, most of the air intakes involved in the chemical reaction are turned off (Ar inert gas is retained), and vacuum is drawn to take away the heat generated on the wafer to ensure etching uniformity. In this process, some by-products will also be quickly volatilized.

[0127] It should be noted that, in this embodiment, the Sc-containing layer is Sc x Al 1-x Taking N material as an example, Sc is a metal element that can react with chlorine to generate ScCl3 with certain volatility but not very good volatility. The etching method provided in the embodiment of the present invention can volatilize the byproduct ScCl3 well during the etching process. Other materials containing Sc can also be etched using the method provided in the embodiment of the present invention. Figures 3a - 3b As shown in the result characterization diagram of etching the Sc-containing layer, it can be seen that by using the etching method provided by the embodiment of the present invention, there is no obvious by-product on the side wall, the etching process can be smoothly carried out in each cycle stage, and the angle (tilt) of the Sc-containing layer after etching is basically consistent with that of the photoresist, and the etching is relatively uniform, which not only ensures the etching rate, but also ensures the etching quality. Figures 3a - 3b The dimensions in the figure are only approximate values ​​for a specific example, and are only used to show the angle relationship between the etched Sc layer and the photoresist. For example, in the figure, the angles of the Sc layer and the photoresist are both about 65°. In fact, in addition to this angle, the angles of the two can reach 75° at the same time, that is, the dimensions in the figure do not have a limiting effect on the present invention.

[0128] Depend on Figures 3a - 3d It can be seen that Sc x Al 1-x The angle of the N barrier layer is consistent with that of the photoresist, indicating that the etching process is not affected by the sidewall deposition byproducts. Figures 3a - 3d It is only used to illustrate the etching results and is not a structural part of a real semiconductor device.

[0129] Using the IEP (Interferometry End Point) or LEP (Laser-Interferometry End Point) method to indicate the etching end point, Sc layers of different thicknesses can be obtained. x Al 1-x N barrier layer, such as Figures 4a - 4d As shown, the Sc that can be obtained by the etching method provided by the embodiment of the present invention is x Al 1-x The thickness of the N barrier layer can be about 100 nm ( Figure 4a 103nm), 50nm( Figure 4b 46.3nm), 30nm( Figure 4c 26.4nm), etc., among which, Figure 4d Medium x Al 1-x The thickness of the N barrier layer is about 10 nm, but it is not marked because it is too thin. Figures 4a - 4d It can be seen that the etching method provided in the embodiment of the present invention can etch a Sc-containing layer with a wide thickness range, and the etching thickness is easy to control, that is, not only can a thicker Sc-containing layer (such as 100nm Sc x Al 1-x N barrier layer), and can also etch a thinner Sc-containing layer (such as Sc below 10nm). x Al 1-x N barrier layer). By introducing a recessed gate structure into the manufacturing of a semiconductor device containing a Sc layer, a normally-off semiconductor device, such as a normally-off transistor containing a Sc layer, can be manufactured.

[0130] It should be noted that this characterization diagram is not part of a real semiconductor device, but is only used to schematically present the etching results, which can simulate Figures 2a - 2n (The manufacturing method of the semiconductor device containing the Sc layer will be described in detail in the second embodiment below) The processing effect diagram of the manufactured semiconductor device can be characterized by SEM without using TEM (Transmission Electron Microscope).

[0131] It should be noted that in the embodiments of the present invention, Figures 3a - 3d , Figures 4a - 4d are all electron microscope photos. In order to facilitate the presentation of contrast, during the experiment, Sc x Al 1-x N has a metal layer below it. The metal layer is relatively thin, within about 100 nm, and when etching the Sc x Al 1-x N layer, it will not be etched all the way to the metal layer. Therefore, this metal layer will not affect the etching result of the Sc x Al 1-x N layer. That is to say, whether there is a metal layer or GaN below the Sc x Al 1-x N layer, it will not affect the etching result. Therefore, when manufacturing a semiconductor device containing a Sc layer, a GaN layer can be provided below the Sc x Al 1-x N layer. In addition, Figures 4a - 4d The dimensions in [[ ]] are only approximate values of a specific example, and are only for presenting that Sc with different thicknesses can be etched x Al 1-x barrier layers, that is, the dimensions in the figure do not limit the present invention.

[0132] In addition, the first etching step in the embodiments of the present invention may include a bombardment step and / or an etching step, the second etching step may include a bombardment step and / or an etching step, and it may also be set that the first etching step is a bombardment step and the second etching step is an etching step. The present invention does not make any limitations in this regard.

[0133] The following is a further comparative description of the etching method of the embodiments of the present invention in combination with the following comparative examples.

[0134] Comparative Example 1

[0135] In this comparative example, for Sc x Al 1-x N, x = 20%, that is, the molar ratio of Sc content is 20%. Using the process formula in Table 3, Sc x Al 1-x N is etched, where the ESC temperature is 40 °C.

[0136]

[0137] Table 3: Plasma etching process formula of Comparative Example 1

[0138] In this comparative example, in the main etching step, the cyclic main etching process step and the auxiliary etching process step in the embodiments of the present invention are not adopted, and only the etching step is adopted. The process parameters are shown in Table 3. See Figures 5a - 5d, the SEM characterization results show that there are heavy by-products on the sidewalls in this comparative example, resulting in angle skew. Among them, the photoresist has an angle of about 75°, while the angle of Sc x Al 1-x N is only about 47°, and the inclination angles of the two are very different. It should be noted that Figures 5a - 5d is only used to illustrate the etching results and is not Figures 2a - 2n the semiconductor device shown. The sidewall by-products were characterized by Energy Dispersive X-Ray, and it was shown that it contained Sc, as Figures 6a - 6b shown, indicating that the by-products were caused by the low volatility of ScCl3, and the angles of the photoresist and Sc x Al 1-x N after etching were significantly inconsistent.

[0139] Comparative Example 2

[0140] In this comparative example, in the article titled A Novel Barrier Material for HighPower GaN-Based RF Transistors published by M.T. Hardy et al., Sc x Al 1-x N was etched using an upper electrode power of 200W and a lower electrode power of 30W - 70W. According to the result statistical chart as Figure 7 shown, it shows that its etching rate is low.

[0141] Comparative Example 3

[0142] In this comparative example, in the article titled FABRICATION AND CHARACTERISATIONOF SCALN-BASED PIEZOELECTRIC MEMS CANTILEVERS published by P.M. Mayrhofer et al., Sc x Al 1-x N was etched using an etching gas containing SiCl4, a chamber pressure of 15mTorr, an upper electrode power of 150W, and a lower electrode power of 225W. According to the etching result characterization diagram as Figures 8a - 8b shown, its etching rate is low, only 10nm / min.

[0143] Comparative Example 4

[0144] In this comparative example, in the article titled "High-fidelity patterning of AlN and ScAlN thin films with wet chemical etching" published by Konsta Airola et al., the etching morphology diagrams of Sc x Al 1-x N were obtained under different wet etching conditions. As shown in Figures 9a - 9d It can be seen from the figure that although the etching rate can reach more than 100 nm / min, when the size of the semiconductor device is small, it is difficult for the solution to enter the etching surface, and the acidic or alkaline solution used for etching will also affect other structures in the device.

[0145] From the comparative analysis of the above comparative example, it can be seen that the etching method of the Sc-containing layer provided in the embodiment of the present invention can achieve a high etching rate and etching uniformity due to the main etching process step and the auxiliary etching process step that are cyclically executed, thereby ensuring the etching efficiency and quality; and can achieve the angular consistency of the Sc-containing layer and the photoresist, can etch Sc-containing layers with different thicknesses, and can realize the thinning design of the Sc-containing layer, providing technical support for manufacturing normally-off semiconductor devices.

[0146] Embodiment 2

[0147] The embodiment of the present invention provides a manufacturing method of a semiconductor device, including the steps of:

[0148] S210, providing a substrate;

[0149] S220, forming a Sc-containing layer on the substrate; wherein, the Sc-containing layer can be used as a barrier layer, taking the Sc x Al 1-x N barrier layer as an example;

[0150] S230, using the etching method in Embodiment 1 above to etch the Sc-containing layer to form a groove with a predetermined depth, and the predetermined depth is less than the thickness of the Sc-containing layer;

[0151] S240, forming a gate in the groove, and forming a source electrode and a drain electrode on both sides of the groove.

[0152] Using the etching method of the Sc-containing layer provided in the embodiment of the present invention can produce the same beneficial effects as the above etching method, that is, improving the etching efficiency, which will not be elaborated here.

[0153] In the embodiment of the present invention, step S220 includes the following sub-steps:

[0154] S2202, obtaining a Sc precursor by electron beam evaporation;

[0155] S2204, obtain the Al precursor through a filamentous seepage chamber;

[0156] S2206, deposit and grow Sc x Al 1-x N barrier layer on the substrate by molecular beam epitaxy; wherein, among the process parameters of the molecular beam epitaxy method, the temperature is 500°C to 900°C, and the nitrogen flow rate is 0.1 sccm to 10 sccm.

[0157] In the embodiment of the present invention, step S210 includes the following sub-steps:

[0158] S2102, take a substrate that has been cleaned;

[0159] S2104, deposit a buffer layer on the substrate;

[0160] S2106, deposit an epitaxial layer on the buffer layer.

[0161] Among them, in step 2104, the buffer layer includes a first buffer layer and a second buffer layer, and includes the following sub-steps:

[0162] (1) Introduce trimethylaluminum and ammonia into the reaction chamber, and deposit a first buffer layer on the substrate; the thickness of the first buffer layer is 4 nm to 6 nm, preferably 5 nm, the temperature is 680°C to 720°C, preferably 700°C, and the deposition growth rate is 0.8 nm / min - 1.2 nm / min, preferably 1 nm / min;

[0163] (2) Continue to introduce trimethylaluminum and ammonia into the reaction chamber, and form a second buffer layer on the first buffer layer; the thickness of the second buffer layer is 4 nm to 96 nm, the temperature is 780°C to 820°C, preferably 800°C, and the deposition growth rate is 4.5 nm / min - 5.5 nm / min, preferably 5 nm / min.

[0164] Step 2106 includes the following steps: Introduce trimethylgallium and ammonia into the reaction chamber, and deposit an epitaxial layer on the second buffer layer; in this process step, the temperature is 1050°C to 1150°C, preferably 1100°C.

[0165] The above step S2102 includes the following sub-steps:

[0166] (1) Select a substrate, and the substrate is a sapphire substrate, a silicon carbide substrate or a silicon substrate;

[0167] (2) Select a cleaning solvent, and the cleaning solvent is a mixed solution of concentrated sulfuric acid with a concentration of 98% and hydrogen peroxide with a concentration of 30%, wherein the volume ratio of 98% concentrated sulfuric acid to 30% hydrogen peroxide is 6 / 4 to 8 / 2, preferably 7 / 3;

[0168] (3) Place the substrate in a cleaning solvent, heat it to a preset cleaning temperature, and heat for at least 30 minutes or until the bubbles disappear; wherein, the preset cleaning temperature is 105°C to 115°C, preferably 110°C;

[0169] (4) Take the substrate out of the cleaning solvent and clean it with ultrapure water.

[0170] In the embodiment of the present invention, the following sub-steps are included in step 230:

[0171] S2302, spin-coat a first photoresist on the barrier layer, and perform exposure, development, and fixing on the first photoresist to obtain a first mask plate with a first through groove, and the part of the barrier layer exposed by the first through groove is the position of the groove;

[0172] Among them, the thickness of the first photoresist is 0.5 μm to 10 μm, preferably 3 μm; the exposure duration is 3 s to 20 s, preferably 6 s; the development duration is 45 s to 120 s, preferably 75 s; the fixing duration is 60 s to 300 s, preferably 120 s;

[0173] S2304, etch the first mask plate and the barrier layer. Among them, etch the area opposite to the first through groove to form a groove;

[0174] This etching process step adopts the steps provided in the etching method of the first embodiment above, including: a stabilization step, a glow step, a main etching process step, an auxiliary etching process step, and a desorption step. Among them, the main etching process step and the auxiliary etching process step are cyclically executed. The main etching process step includes at least one of a first etching step and a second etching step. The auxiliary etching process step includes at least one of a volatilization step and a cooling step. The process steps and their process parameters are as described in the first embodiment above and will not be elaborated here;

[0175] S2306, remove the first photoresist and by-products. This step includes the following sub-steps:

[0176] (1) If the first photoresist still remains, soak and rinse the first photoresist with an organic liquid medicine until the first photoresist completely falls off;

[0177] (2) Remove the by-products of the first photoresist and the by-products generated by the etching process in step S2304.

[0178] In the embodiment of the present invention, step S240 includes the following sub-steps:

[0179] S2402, spin-coat a second photoresist on the barrier layer with a groove, and perform exposure, development, and fixing on the second photoresist to obtain a second mask plate with a second through groove and a third through groove. The part of the barrier layer exposed by the second through groove is the source position, and the part of the barrier layer exposed by the third through groove is the drain position;

[0180] Among them, the thickness of the second photoresist is 0.5 μm to 10 μm, more preferably 1 μm to 5 μm, and further preferably 3 μm; the width of the second through groove is 5 μm to 500 μm, more preferably 6 μm to 200 μm, further preferably 7 μm to 100 μm, more preferably 8 μm to 50 μm, and further preferably 10 μm; the width of the third through groove is 5 μm to 500 μm, more preferably 6 μm to 200 μm, further preferably 7 μm to 100 μm, more preferably 8 μm to 50 μm, and further preferably 10 μm; the exposure duration is 3 s to 20 s, more preferably 5 s to 10 s, and further preferably 6 s; the development duration is 45 s to 120 s, more preferably 60 s to 100 s, and further preferably 75 s; the fixing duration is 60 s to 300 s, more preferably 80 s to 200 s, and further preferably 120 s;

[0181] S2404, perform metal ion deposition on the source and drain positions of the second photoresist and the barrier layer to form the source and drain; or, thermally evaporate the source and drain on the barrier layer;

[0182] Among them, in the physical vapor deposition process, Ti ions and Al ions are sequentially deposited to obtain a Ti layer and an Al layer; the chamber pressure of the reaction chamber is 10 mTorr to 100 mTorr; the upper electrode power is 750 W to 3000 W, the lower electrode power is 5 W to 500 W, the process gas includes argon, and the argon flow rate is 50 sccm to 500 sccm; or, in the thermal evaporation process, the chamber pressure of the reaction chamber is 5×10 -5 Pa to 5×10 -4 Pa, preferably 1×10 -4 Pa, the current is 1 mA to 20 mA, preferably 5 mA.

[0183] S2406, remove the second photoresist and by-products. Among them, this step includes the following sub-steps:

[0184] (1) If the second photoresist still remains, soak and rinse the second photoresist with an organic solution until the second photoresist completely falls off;

[0185] (2) Remove the by-products of the second photoresist and the by-products generated by the deposition process in step S2404, or remove the by-products of the second photoresist and the by-products generated by the thermal evaporation process in step S2404;

[0186] S2408, spin coat a third photoresist on a barrier layer having a groove, a source electrode, and a drain electrode, and perform exposure, development, and fixing on the third photoresist to obtain a third mask plate having a fourth through groove. The portion of the barrier layer exposed by the fourth through groove is the gate position, and the gate position is located within the groove;

[0187] Among them, the thickness of the third photoresist is 0.5 μm to 10 μm, more preferably 1 μm to 5 μm, and even more preferably 3 μm; the exposure duration is 3 s to 20 s, more preferably 5 s to 10 s, and even more preferably 6 s; the development duration is 45 s to 120 s, more preferably 60 s to 100 s, and even more preferably 75 s; the fixing duration is 60 s to 300 s, more preferably 80 s to 200 s, and even more preferably 120 s;

[0188] S2410, deposit metal ions on the third photoresist and the gate position within the groove to form a gate; alternatively, this step is to thermally evaporate and deposit to form a gate at the gate position of the groove;

[0189] Among them, physical vapor deposition is used to sequentially deposit Ni ions and Au ions to obtain a Ni layer and an Au layer; the chamber pressure of the reaction chamber is 10 mTorr to 100 mTorr; the upper electrode power is 750 W to 3000 W, the lower electrode power is 5 W to 500 W, the process gas includes argon, and the argon flow rate is 50 sccm to 500 sccm; alternatively, during the thermal evaporation process, the chamber pressure of the reaction chamber is 5×10 -5 Pa to 5×10 -4 Pa, preferably 1×10 -4 Pa, the current is 1 to 20 mA, preferably 5 mA.

[0190] S2412, remove the third photoresist and by-products. Among them, this step includes the following sub-steps:

[0191] (1) If the third photoresist still remains, soak and rinse the second photoresist with an organic liquid medicine until the third photoresist completely falls off;

[0192] (2) Remove the by-products of the third photoresist and the by-products generated by the deposition process in step S2410; alternatively, remove the by-products of the third photoresist and the by-products generated by the thermal evaporation process in step S2410.

[0193] In the embodiments of the present invention, after step S240, the following steps are further included:

[0194] S250, deposit a passivation layer on the barrier layer having a source electrode, a gate electrode, a drain electrode, and a groove.

[0195] Specifically, in the deposition process of this step, a passivation layer is formed by plasma-enhanced chemical vapor deposition or high-density plasma chemical vapor deposition. Among them, the passivation layer includes a SiN layer and a SiO2 layer. The chamber pressure of the reaction chamber is 1 mTorr to 1000 mTorr. If high-density plasma chemical vapor deposition is used, the chamber pressure is preferably 5 mTorr. If plasma-enhanced chemical vapor deposition is used, the chamber pressure is preferably 500 mTorr. The power of the upper electrode is 500 W to 15000 W, preferably 5000 W. The power of the lower electrode is 0 to 15000 W, preferably 5000 W. The process gas includes SiH4 and O2. The flow rate of SiH4 is 10 sccm to 1000 sccm, preferably 50 sccm. The flow rate of O2 is 10 sccm to 1000 sccm, preferably 500 sccm. The coolant temperature of the pedestal is -15°C to 100°C, preferably 40°C.

[0196] In the embodiment of the present invention, after step S250, the following steps are further included:

[0197] S260, encapsulation and cutting to obtain a semiconductor device containing a Sc layer. For example, a transistor containing a Sc layer is obtained.

[0198] To further explain the manufacturing method of the semiconductor device provided by the embodiment of the present invention, a specific example is listed below, as described in detail below:

[0199] S301, cleaning the substrate to obtain a substrate meeting the cleanliness requirements. As Figure 2a shown, among them, the substrate can be selected from sapphire, silicon carbide, silicon, etc. Taking silicon as an example, the RCA standard cleaning method is adopted. Commercially available 98% concentrated sulfuric acid and commercially available 30% hydrogen peroxide are mixed at a volume ratio of 7:3. After putting the silicon wafer in, it is heated to 110°C until the bubbles disappear (at least thirty minutes or more), and then the silicon wafer is taken out and cleaned with ultrapure water.

[0200] S302, growing an AlN buffer layer by Metal-Organic Chemical Vapor Deposition (MOCVD). The thickness of the AlN buffer layer is 10 nm to 100 nm, preferably 40 nm. As Figure 2b shown, specifically, trimethylaluminum and ammonia are introduced into the reaction chamber, the temperature is raised to 700°C, and the growth rate is controlled at 1 nm / min to deposit a 5-nm-thick AlN nucleation layer on the substrate. Then, the introduction of trimethylaluminum and ammonia is continued, the temperature in the chamber is raised to 800°C, and the growth rate is increased to 5 nm / min to form an AlN buffer layer.

[0201] S303. Based on step S302, stop introducing trimethylaluminum, continue to introduce trimethylgallium and ammonia into the reaction chamber, heat up to 1100 °C, and continue to deposit the GaN epitaxial layer thereon, as Figure 2c shown. The thickness of the GaN epitaxial layer is 1 μm to 10 μm, preferably 3 μm;

[0202] S304. Use the molecular beam epitaxy (MBE) method to grow Sc x Al 1-x N to obtain the epitaxial layer 200, as Figure 2d shown, wherein the thickness of the epitaxial layer 200 is 0.01 μm to 1 μm, the temperature is 500 °C to 900 °C, the nitrogen flow rate is 0.1 sccm to 10 sccm, the Sc precursor can be obtained by electron beam evaporation, and the Al precursor can be obtained by a filament effusion cell;

[0203] S305. Spin-coat photoresist, as Figure 2e shown, to obtain the first photoresist layer 310, wherein the thickness of the first photoresist layer 310 is 0.5 μm to 10 μm, preferably 3 μm. Expose, develop. The mask is designed and processed in advance so that the distance from the groove part (calculated separately from both ends of the groove) to the source and drain is 0.3 μm and 1 μm respectively. The exposure duration is 3 s to 20 s, preferably 6 s, the development duration is 45 s to 120 s, preferably 75 s, and the fixing duration is 60 s to 300 s, preferably 120 s, to pattern the photoresist.

[0204] It should be noted that for a voltage-resistant device, the distance between the gate and the drain can affect the voltage that the device can withstand, while for a radio frequency device, the distance between the gate and the source can affect the current density, on-resistance, and peak transconductance of the device. Reducing the distance between the gate and the source can improve the above parameters. Therefore, the distance between the gate and the drain is set to be 1 to 5 times the distance between the gate and the source, that is, the ratio of the distance between the gate and the drain to the distance between the gate and the source is (1 - 5):1.

[0205] S306. Plasma etch Sc x Al 1-x N, as Figure 2fAs shown, a grooved gate is formed with a chamber pressure of 1 mTorr to 30 mTorr, preferably 5 mTorr, an upper electrode power of 500 W to 3000 W, a center power of the upper electrode preferably 600 W, and an edge power of the upper electrode preferably 1500 W; the lower electrode power in the main etching process step is 100 W to 1000 W, the lower electrode power in the first etching step is preferably 600 W, and the lower electrode power in the second etching step is preferably 400 W; the lower electrode power in the auxiliary etching process step is close to zero, preferably 1 W; the argon (Ar) flow rate in the main etching process step is 10 sccm to 1000 sccm, preferably 100 sccm, the BCl3 flow rate is 10 sccm to 100 sccm (other chlorine-containing gases such as SiCl4 can also be used), preferably 20 sccm, and the Cl2 flow rate is 10 sccm to 100 sccm (other chlorine-containing gases such as SiCl4 can also be used); the process gas flow rate in the auxiliary etching process step is close to zero, wherein the chlorine-containing gas and Ar flow rates in the volatilization step are both preferably 1 sccm, the chlorine-containing gas flow rate in the cooling step is preferably 1 sccm, and the Ar flow rate is preferably 10 sccm; the temperature of the base coolant is -15 °C to 60 °C, preferably 40 °C.

[0206] Specifically, the etching process steps adopt the steps provided in the etching method of the first embodiment above, including: a stabilization step, a glow discharge step, a main etching process step, an auxiliary etching process step, and a desorption step. Among them, the main etching process step and the auxiliary etching process step are executed cyclically. The main etching process step includes at least one of the first etching step and the second etching step, and the auxiliary etching process step includes at least one of the volatilization step and the cooling step. The process steps and their process parameters refer to the content described in the first embodiment above and will not be elaborated here.

[0207] S307, wet stripping, as Figure 2g shown, wherein an organic liquid medicine, such as acetone, etc., is used, and the time is not limited. Soak until most of the photoresist falls off the Sc layer surface, and then rinse with flowing organic liquid medicine until the photoresist completely falls off the Sc layer surface to remove the residue of the photoresist and the by-products of the etching process;

[0208] S308, spin-coating photoresist, as Figure 2h shown, to obtain the second photoresist layer 320. The thickness of the second photoresist layer 320 is 0.5 μm to 10 μm, preferably 3 μm. Expose, develop, and design and process the mask in advance, and make the electrode widths of the source and drain about 5 μm to 500 μm, preferably 10 μm. The exposure duration is 3 s to 20 s, preferably 6 s, the development duration is 45 s to 120 s, preferably 75 s, and the fixing duration is 60 s to 300 s, preferably 120 s to pattern the photoresist;

[0209] S309, fabricate the source and drain metals Ti / Al to form an ohmic contact with the conductive channel, as Figure 2i shown. Specifically, use the Physical Vapor Deposition (PVD) method. Among them, the thickness of Ti is 0.05μm - 0.2μm, preferably 0.1μm, and the thickness of Al is 0.1μm - 0.5μm, preferably 0.3μm. In terms of process conditions, the chamber pressure is 10mTorr - 100mTorr, the upper electrode power is 750W - 3000W, the lower electrode power is 5W - 500W, and the Ar flow rate is 50sccm - 500sccm; Optionally, this step can also be prepared by thermal evaporation. The chamber pressure is 5×10 -5 Pa - 5×10 -4 Pa, preferably 1×10 -4 Pa, the current is 1mA - 20mA, preferably 5mA;

[0210] S310, wet stripping, as Figure 2j shown. Specifically, this step is basically the same as step S07;

[0211] S311, spin-coat photoresist, as Figure 2k shown, to obtain the third photoresist 330, whose thickness is 0.5μm - 10μm, preferably 3μm. The exposure, development, and mask are designed and processed in advance, so that the distance between the gate metal and the drain metal of the device is about 1μm - 10μm, preferably 5μm, the distance between the gate metal and the source metal is about 0.5μm - 5μm, preferably 1μm, the gate length is about 0.5μm - 5μm, preferably 1μm, the gate width is about 0.1mm - 10mm, preferably 3mm, and the effective area of the semiconductor device is about (1 - 10)×10 -4 cm 2 (the area including the source and drain), the exposure duration is 3s - 20s, preferably 6s, the development duration is 45s - 120s, preferably 75s, and the fixing duration is 60s - 300s, preferably 120s, to pattern the photoresist;

[0212] S312, fabricate the gate metal Ni / Au, as Figure 2l shown. Specifically, the thickness of Ni is 1nm - 10nm, preferably 5nm, and the thickness of Au is 10nm - 100nm, preferably 50nm. It can be realized by PVD or thermal evaporation, similar to step S309;

[0213] S313, wet stripping, as Figure 2m shown. This step is basically the same as step S307;

[0214] In S314, a passivation layer is deposited on the surface of a semiconductor device by plasma enhanced chemical vapor deposition (PECVD) or high density plasma chemical vapor deposition (HDPCVD) to protect the semiconductor device, such as Figure 2n shown. Specifically, taking SiN with a thickness of 300 nm plus SiO2 with a thickness of 600 nm as an example, the process parameters of this step are that the chamber pressure is 1 mTorr to 1000 mTorr, preferably 5 mTorr when using HDPCVD, and preferably 500 mTorr when using PECVD; the upper electrode power is 500 W to 15000 W, preferably 5000 W; the lower electrode power is 0 to 15000 W, preferably 5000 W; the flow rate of SiH4 is 10 sccm to 1000 sccm, preferably 50 sccm; the flow rate of O2 is 10 sccm to 1000 sccm, preferably 500 sccm; and the temperature of the base coolant is -15 °C to 100 °C, preferably 40 °C;

[0215] S315. Encapsulation and cutting.

[0216] An embodiment of the present invention also provides a semiconductor device, which includes: a substrate, a Sc-containing layer, a source electrode, a drain electrode, and a gate electrode; wherein, the Sc-containing layer is disposed on the substrate, a groove is formed on a side of the Sc-containing layer away from the substrate, and the depth of the groove is less than the thickness of the Sc-containing layer; the source electrode is disposed on a first side of the groove; the drain electrode is disposed on a second side of the groove, the second side is opposite to the first side, and the distance between the source electrode and the edge of the first side of the groove is less than the distance between the drain electrode and the edge of the second side of the groove; the gate electrode is disposed in the groove, and the distance between the gate electrode and the source electrode is less than the distance between the gate electrode and the drain electrode. In this embodiment, the groove can be formed, for example, by using the etching method of the Sc-containing layer described above.

[0217] This semiconductor device has a Sc-containing layer, and the Sc-containing layer is a barrier layer. By applying the above etching method to etch the Sc-containing layer to form a groove with a predetermined depth, the formation of the groove and the gate electrode in the groove form a groove-gate structure. Compared with the related art, this groove-gate structure can thin the barrier layer where the gate electrode is located. Thus, when a gate voltage is provided to the gate electrode for regulation, a potential well appears, thereby forming a two-dimensional electron gas, achieving a high electron mobility of the semiconductor device; when no gate voltage is applied, the potential well of the formed two-dimensional electron gas disappears, and the semiconductor device is in an off state, that is, this semiconductor device is a normally-off semiconductor device, realizing the safety control performance of the semiconductor device.

[0218] In an embodiment of the present invention, the Sc-containing layer includes Scx Al 1-x N, where the value range of x is less than 43%, preferably 20% - 40%, more preferably 22% - 38%, still more preferably 25% - 35%, still more preferably 28% - 32%, and most preferably 30%; the distance between the bottom of the groove and the side of the Sc-containing layer facing the substrate is 1 nm - 100 nm, preferably 2 nm - 20 nm, more preferably 3 nm - 10 nm, and most preferably 5 nm; the distance between the source electrode and the edge of the first side of the groove is 0.1 μm - 0.5 μm; the distance between the drain electrode and the edge of the second side of the groove is 0.5 μm - 5 μm; the length of the gate electrode is 0.5 μm - 5 μm, more preferably 0.6 μm - 2 μm, and still more preferably 1 μm, and the width is 0.1 mm - 10 mm, more preferably 1 mm - 5 mm, and still more preferably 3 mm.

[0219] Taking the fabrication of a transistor with a Sc-containing layer as an example, as Figure 1 shown, the transistor includes a substrate 120, a Sc-containing layer (i.e., a barrier layer 200), a source electrode 210, a drain electrode 230, and a gate electrode 220; wherein, the Sc-containing layer is disposed above the substrate 120; a groove 240 is formed on the side of the Sc-containing layer away from the substrate, and the depth of the groove 240 is less than the thickness of the Sc-containing layer; the source electrode 210 is disposed on the first side of the groove 240; the drain electrode 230 is disposed on the second side of the groove 240, the second side is opposite to the first side, and the distance between the source electrode 210 and the edge of the first side of the groove 240 is less than the distance between the drain electrode 230 and the edge of the second side of the groove 240; the gate electrode 220 is disposed in the groove 240, and the distance between the gate electrode 220 and the source electrode 210 is less than the distance between the gate electrode 220 and the drain electrode 230.

[0220] Specifically, in this embodiment, there is also a buffer layer 130 and an epitaxial layer 110 between the substrate 120 and the Sc-containing layer. Among them, the epitaxial layer 110, the buffer layer 130, and the substrate 12 are sequentially disposed from top to bottom to form an epitaxial wafer 100. Please continue to refer to Figure 1 ; a barrier layer 200 is deposited on the epitaxial layer 110 of the epitaxial wafer 100. The barrier layer 200 has a source electrode 210, a gate electrode 220, a drain electrode 230, and a groove 240 arranged at intervals. The opening of the groove 240 faces away from the epitaxial layer 110, and the bottom of the groove 240 does not reach the epitaxial layer 110, that is, the depth of the groove 240 is less than the thickness of the barrier layer 200, and the gate electrode 220 is located in the groove 240; the barrier layer 200 is a Sc-containing layer. In this embodiment, the barrier layer 200 still takes the Sc x Al 1-x N barrier layer as an example.

[0221] The distance h between the bottom of the groove 240 and the side of the Sc-containing layer facing the substrate is 1 nm to 100 nm, preferably 2 nm to 20 nm, more preferably 3 nm to 10 nm, and even more preferably 5 nm; the groove 240 has a first edge (i.e., the edge on the first side) and a second edge (i.e., the edge on the second side) that are oppositely arranged, wherein the first edge is located between the gate 220 and the source 210, and the second edge is located between the gate 220 and the drain 230; the distance M from the first edge to the source 210 is 0.1 μm to 0.5 μm, and the distance N from the second edge to the drain 230 is 0.5 μm to 5 μm; the length G of the gate 220 is 0.5 μm to 5 μm, more preferably 0.6 μm to 2 μm, and even more preferably 1 μm; the width of the gate 220 is 0.1 mm to 10 mm, more preferably 1 mm to 5 mm, and even more preferably 3 mm. With such a setting, as Figure 11a shown, when a gate voltage is provided to the gate for regulation, a potential well appears, thereby forming a two-dimensional electron gas, achieving a high electron mobility of the semiconductor device; as Figure 11b shown, when no gate voltage is applied, the potential well of the formed two-dimensional electron gas disappears, and the semiconductor device is in an off state, that is, the semiconductor device is a normally-off semiconductor device, achieving the safety control performance of the semiconductor device.

[0222] The thickness H of the barrier layer 200 is 0.01 μm to 1 μm, preferably 0.01 μm to 0.5 μm, more preferably 0.01 μm to 0.1 μm, more preferably 0.01 μm to 0.05 μm, and even more preferably 0.03 μm. The epitaxial layer 110 takes the GaN epitaxial layer as an example, and its thickness is 1 μm to 10 μm, preferably 2 μm to 5 μm, and more preferably 3 μm.

[0223] The length Y of the source 210 is 5 μm to 500 μm, more preferably 6 μm to 100 μm, more preferably 7 μm to 50 μm, and even more preferably 10 μm. The source 210 includes a Ti layer and an Al layer, and the Ti layer is located between the barrier layer 200 and the Al layer; the thickness of the Ti layer is 0.05 μm to 0.2 μm, preferably 0.1 μm; the thickness of the Al layer is 0.1 μm to 0.5 μm, preferably 0.3 μm.

[0224] The length D of the drain 230 is 5 μm to 500 μm, more preferably 6 μm to 100 μm, more preferably 7 μm to 50 μm, and even more preferably 10 μm. The drain 230 and the source 210 can have the same size. Specifically, the drain 230 includes a Ti layer and an Al layer, and the Ti layer is located between the barrier layer 200 and the Al layer; the thickness of the Ti layer is 0.05 μm to 0.2 μm, preferably 0.1 μm; the thickness of the Al layer is 0.1 μm to 0.5 μm, preferably 0.3 μm.

[0225] The gate 220 includes a Ni layer and an Au layer. The Ni layer is located between the barrier layer 200 and the Au layer. The thickness of the Ni layer is 1 nm to 10 nm, preferably 5 nm; the thickness of the Au layer is 10 nm to 100 nm, preferably 50 nm.

[0226] The distance y between the gate 220 and the source 210 is 0.5 μm to 5 μm, preferably 1 μm; the distance d between the gate 220 and the drain 230 is 1 μm to 10 μm, preferably 5 μm; the distance d between the gate 220 and the drain 230 is set as the first distance, and the distance y between the gate 220 and the source 210 is the second distance, and the ratio d / y of the first distance to the second distance is 1 to 5.

[0227] The distance m between the first edge of the groove 240 and the gate 220 is 0.1 μm to 1 μm, further preferably 0.2 μm to 5 μm, further preferably 0.3 μm; the distance n between the second edge of the groove 240 and the gate 220 is 0.3 μm to 5 μm, further preferably 0.5 μm to 3 μm, further preferably 1 μm.

[0228] In the embodiment of the present invention, the buffer layer 130 is an AlN buffer layer, and the thickness of the buffer layer 130 is 10 nm to 100 nm, further preferably 20 nm to 60 nm, further preferably 40 nm.

[0229] The Sc layer-containing semiconductor provided by the embodiment of the present invention, such as a transistor, can achieve both high electron mobility and normally-off type.

[0230] Embodiment III

[0231] The embodiment of the present invention provides a process equipment, actually a semiconductor process equipment, such as Figure 10 As shown, the semiconductor process equipment includes a process chamber 500, a gas inlet assembly (not shown in the figure), an upper electrode assembly 510, a lower electrode assembly 520, and a controller (not shown in the figure). The controller includes at least one processor and at least one memory. A computer program is stored in the memory, and when the computer program is executed by the processor, the etching method and manufacturing method of any one of the above embodiments are realized.

[0232] Exemplarily, the controller can be a host computer or a slave computer. Among them, the controller can control the opening of the valve of the gas inlet assembly to introduce the corresponding process gas into the interior of the process chamber 500; the controller can also control the opening degree of the valve of the gas inlet assembly to control the flow rate of the process gas. The controller can also control the evacuation of the interior of the process chamber 500 by controlling the evacuation assembly to control the pressure inside the process chamber 500 and discharge reaction by-products, etc.

[0233] The upper electrode assembly 510 includes a radio frequency coil 511, an upper radio frequency power supply 512, and an upper matcher 513. The controller is further configured to control the upper radio frequency power supply 512 to supply upper electrode power to the radio frequency coil 511 through the upper matcher 513, so that the radio frequency coil 511 excites process gas inside the process chamber 500 to generate plasma.

[0234] The lower electrode assembly 520 includes a wafer carrier device 521, a lower radio frequency power supply 522, and a lower matcher 523. The controller is further configured to control the lower radio frequency power supply 522 to supply lower electrode power to the lower electrode of the wafer carrier device 523 through the lower matcher 523, so that the lower electrode of the wafer carrier device 523 provides a radio frequency bias voltage to adsorb plasma above an object to be etched (not shown in the figure) and bombard the object to be etched.

[0235] The semiconductor process equipment according to an embodiment of the present invention may be an inductively coupled plasma (ICP) etching equipment or a capacitively coupled plasma (CCP) etching equipment. The embodiment of the present invention does not limit the type of the semiconductor process equipment.

[0236] The process equipment provided by the embodiment of the present invention has the beneficial effects of the above etching method and manufacturing method, which will not be elaborated here.

[0237] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by terms such as "upper", "lower", "front", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0238] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the term "installation" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meaning of the above terms in the present invention can be understood according to specific situations.

[0239] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An etching method with a Sc layer, characterized in that, The etching method includes a main etching process step and an auxiliary etching process step that are executed cyclically; wherein, The main etching process step includes: introducing a process gas into the process chamber and exciting to generate plasma, and etching the Sc-containing layer, and the process gas includes a chlorine-containing gas and an inert gas; The auxiliary etching process step includes at least one of a volatilization step and a cooling step; The volatilization step includes: reducing the lower electrode power to zero power or close to zero power, and reducing the process gas to zero flow rate or close to zero flow rate; The cooling step includes: reducing the lower electrode power to zero power or close to zero power, reducing the chlorine-containing gas to zero flow rate or close to zero flow rate, and continuing to introduce the inert gas.

2. The etching method according to claim 1, characterized in that, The main etching process step includes a first etching step and / or a second etching step. The process gases used in the first etching step and the second etching step are the same, and the lower electrode power of the first etching step is greater than the lower electrode power of the second etching step.

3. The etching method according to claim 2, wherein The ratio of the lower electrode power of the first etching step to the second etching step is (1.2 - 1.8):1; and / or, the ratio of the process duration of the first etching step to the second etching step is 1:(4 - 6).

4. The etching method according to claim 3, characterized in that, The lower electrode power of the first etching step is 100W - 1000W; the lower electrode power of the second etching step is 100W - 1000W; and / or, the process duration of the first etching step is 1.2s - 3s, and the process duration of the second etching step is 8s - 12s.

5. The etching method according to any one of claims 1-4, characterized in that, In the main etching process step, the flow rate ratio of the chlorine-containing gas to the inert gas is (0.3 - 0.5):1; and / or, in the main etching process step, the flow rate of the chlorine-containing gas is 20sccm - 200sccm, and the flow rate of the inert gas is 10sccm - 1000sccm.

6. The etching method according to claim 5, characterized in that The chlorine-containing gas includes at least one of SiCl4, BCl3, and Cl2, and / or the inert gas includes Ar.

7. The etching method according to claim 6, characterized in that, The chlorine-containing gas includes BCl3 and Cl2, and the flow rate ratio of BCl3 to Cl2 is (0.9 - 1.1):1; Alternatively, the chlorine-containing gas includes SiCl4.

8. The etching method according to any one of claims 1-4, characterized in that, The process duration of the volatilization step is 0.5 - 1.5s; and / or, the process duration of the cooling step is 0.5 - 1.5s.

9. A manufacturing method of a semiconductor device, characterized in that, Including the steps: Providing a substrate; Forming a Sc-containing layer on the substrate; Applying the etching method according to any one of claims 1 - 8 to etch the Sc-containing layer to form a groove with a predetermined depth, and the predetermined depth is less than the thickness of the Sc-containing layer; Forming a gate in the groove, and forming a source electrode and a drain electrode on both sides of the groove.

10. A semiconductor process equipment, comprising a process chamber, an intake assembly, an upper electrode assembly, a lower electrode assembly and a controller, characterized in that, The controller includes at least one processor and at least one memory. A computer program is stored in the memory, and when the computer program is executed by the processor, it implements the etching method according to any one of claims 1 - 8, or implements the manufacturing method according to claim 9.

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