Method, apparatus, storage medium, and program product for light source mask optimization

Abstract

The application provides a method, device, storage medium and program product for light source mask optimization, applied to the field of semiconductors. The method comprises the following steps: acquiring a test pattern and a test light source; when it is detected that the photoetching imaging quality under the combination of the test light source and the test pattern meets the corresponding photoetching process condition, acquiring an auxiliary pattern placement rule; obtaining a to-be-optimized pattern according to the auxiliary pattern placement rule and the test pattern; taking the to-be-optimized pattern as the input of first optimization, performing first optimization on the to-be-optimized pattern, and obtaining a first pattern. The auxiliary pattern is placed into the test pattern in advance according to the auxiliary pattern placement rule to obtain the to-be-optimized pattern, and subsequent optimization is directly performed on the to-be-optimized pattern, so that the related operation of generating the auxiliary pattern is reduced, the calculation amount is reduced, the calculation time is reduced, and the efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to methods, apparatus, storage media, and program products for optimizing light source masks. Background Technology

[0002] In the semiconductor field, photolithography is a crucial process in integrated circuit manufacturing. Specifically, it involves transferring a mask pattern from a photomask onto the object to be processed using exposure. As integrated circuits evolve and semiconductor devices shrink in size, the demand for enhanced photolithographic resolution and process windows (PWs) is growing stronger.

[0003] In existing technologies, the source mask optimization (SMO) method is used to increase the lithography process window, enhance optical performance, and meet manufacturing requirements. However, the source mask optimization method often requires multiple iterative calculations, resulting in a large computational load and consuming a significant amount of computation time. Summary of the Invention

[0004] In view of this, it is necessary to provide methods, devices, storage media and program products for light source mask optimization. By placing the auxiliary graphic on the test graphic in advance according to the auxiliary graphic placement rules, the graphic to be optimized can be obtained. Subsequently, the optimization can be performed directly on the graphic to be optimized, reducing the operation related to generating auxiliary graphics, thereby reducing the amount of calculation, reducing the calculation time and improving efficiency.

[0005] In a first aspect, embodiments of this application provide a method for optimizing a light source mask. The method includes acquiring a test pattern and a test light source; when it is detected that the photolithography imaging quality under the combination of the test light source and the test pattern meets the corresponding photolithography process conditions, acquiring auxiliary pattern placement rules; obtaining a pattern to be optimized based on the auxiliary pattern placement rules and the test pattern; and using the pattern to be optimized as input for a first optimization, performing a first optimization on the pattern to be optimized to obtain a first pattern.

[0006] In this embodiment, when the lithography imaging quality meets the corresponding lithography process conditions, auxiliary pattern placement rules are obtained. During the next optimization, qualified auxiliary patterns (such as sub-resolution auxiliary patterns) are pre-placed into the test patterns participating in the first optimization (light source mask optimization or mask optimization) according to these rules, allowing direct execution of subsequent optimization processes for the light source and mask. This eliminates operations related to obtaining auxiliary patterns, such as obtaining the position of the sub-resolution auxiliary pattern through continuous mask pixelation calculations during light source mask optimization and optimizing free-form sub-resolution auxiliary patterns, thereby improving the iteration efficiency of light source mask optimization. This method, based on rapidly iterating to obtain mask optimization results that meet mass production requirements, allows for faster acquisition of qualified sub-resolution auxiliary pattern placement rules from the mask optimization results, providing a rule-based basis for inserting sub-resolution auxiliary patterns for optical proximity effects. This method achieves faster light source mask optimization iteration efficiency and accelerates the confirmation of optimal optical system settings at the overall engineering level.

[0007] In some embodiments, using the graphic to be optimized as input for the first optimization and performing a first optimization on the graphic to be optimized to obtain a first graphic includes: using the graphic to be optimized as input for the first optimization; and correcting the target graphic in the graphic to be optimized according to a penalty function to obtain the first graphic.

[0008] In some embodiments, when it is detected that the lithographic imaging quality under the combination of the test light source and the test pattern meets the corresponding lithographic process conditions, obtaining the auxiliary pattern placement rules includes: performing light source mask optimization on the test light source and the test pattern to obtain an optimized first light source and an optimized first mask pattern; performing a first simulation evaluation on the first light source and the first mask pattern to obtain a first lithographic imaging quality; when it is detected that the first lithographic imaging quality meets the first lithographic process conditions, performing mask optimization on the first light source and the test pattern to obtain a corresponding optimized second mask pattern; performing a second simulation evaluation on the first light source and the second mask pattern to obtain a second lithographic imaging quality; when it is detected that the second lithographic imaging quality meets the second lithographic process conditions, obtaining the auxiliary pattern placement rules to obtain the first optimized input based on the auxiliary pattern placement rules.

[0009] In some embodiments, using the graphic to be optimized as input to the first optimization and performing a first optimization on the graphic to be optimized to obtain a first graphic includes: using the graphic to be optimized and a first light source as input to the first optimization; performing a first optimization based on a penalty function, the first light source, and a target graphic in the graphic to be optimized to obtain a first graphic.

[0010] In some embodiments, obtaining the graphic to be optimized based on the auxiliary graphic placement rules and the test graphic includes: adding auxiliary graphics to the test graphic according to the auxiliary graphic placement rules to obtain the graphic to be optimized.

[0011] In some embodiments, adding auxiliary graphics to a test graphic according to auxiliary graphic placement rules to obtain a graphic to be optimized includes: obtaining a selected graphic; wherein the selected graphic is a graphic in the test graphic that restricts the process window; and adding auxiliary graphics to the selected graphic according to auxiliary graphic placement rules to obtain a graphic to be optimized.

[0012] In some embodiments, the placement rules for auxiliary graphics include: the size of the auxiliary graphics, the distance between the auxiliary graphics and the target graphics, and the distance between the auxiliary graphics.

[0013] Secondly, embodiments of this application provide an electronic device, which includes at least one processor and a memory, wherein...

[0014] The memory is used to store instructions, and the processor is used to execute the instructions to implement any of the methods mentioned above.

[0015] Thirdly, embodiments of this application provide a computer-readable storage medium storing a program that causes an electronic device to perform any of the methods described above.

[0016] Fourthly, embodiments of this application provide a computer program product including computer-readable instructions that, when executed by one or more processors, implement the method described above.

[0017] Understandably, the electronic device provided in the second aspect, the computer-readable storage medium provided in the third aspect, and the computer program product provided in the fourth aspect correspond to the methods provided in the first or second aspect. Therefore, the beneficial effects or various implementation methods that they can achieve can be referred to above, and will not be repeated here. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of an electronic device structure provided in an embodiment of this application.

[0019] Figure 2A This is a schematic diagram of a light source optimization process provided in an embodiment of this application.

[0020] Figure 2B This is a schematic diagram of a light source mask optimization process provided in an embodiment of this application.

[0021] Figure 3 This is a flowchart illustrating a light source mask optimization method provided in an embodiment of this application.

[0022] Figure 4 This is a schematic diagram illustrating the optimization process based on a penalty function, as provided in an embodiment of this application.

[0023] Figure 5This is a flowchart illustrating a method for optimizing a light source mask, provided as an embodiment of this application.

[0024] Figure 6 This is a flowchart illustrating another method for optimizing a light source mask provided in an embodiment of this application.

[0025] Figures 7A to 7F This is a schematic diagram of a process for optimizing a light source mask, provided as an embodiment of this application.

[0026] Figure 8 This is a schematic diagram of a pre-set sub-resolution auxiliary graphic provided in an embodiment of this application.

[0027] Figure 9 This is a schematic diagram illustrating the addition of sub-resolution auxiliary graphics as provided in an embodiment of this application.

[0028] Figure 10 A schematic diagram of comparative experimental results provided for embodiments of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0030] In this application, the terms "optimize," "extract," "adjust," "generate," "determine," "calculate," etc., are used to describe the operation of the disclosed methods, apparatus, or systems. These terms are highly abstract concepts of actual, executable operations, such as those performed by one or more electronic devices (e.g., computers) connected to or disconnected from a network, and having user interfaces and data communication interfaces or network interfaces for receiving user / designer input and / or commands to exchange data with semiconductor process equipment or semiconductor testing equipment. The actual operations corresponding to these terms may vary depending on the specific implementation and are readily identifiable by those skilled in the art.

[0031] Some or all of the techniques / operations / steps disclosed in the embodiments of this application can be executed, wholly or partially, by software, which includes electronically executable instructions stored on an electronically readable medium. For example, such software may include suitable electronic design automation (EDA) software tools. This software can be executed on one or more electronic devices or electronic device systems. For clarity, the embodiments of this application describe only certain aspects of the software-based implementation. Other details known to those skilled in the art are omitted. For example, it should be understood that the techniques of the embodiments of this application are not limited to any particular electronic device language, electronic device program, or electronic device. For example, the techniques of the embodiments of this application can be implemented using any commercially available electronic device that executes a program written in any commercially available language or other suitable language. Any method of the embodiments of this application can be performed alternatively (partially or completely) in hardware (e.g., processors, transient and non-transitory memory devices, and various circuits).

[0032] Due to the complexity of some electronic design automation processes and the large size of many circuits, various electronic design automation tools are configured to operate on computing systems capable of executing multiple processing threads or multiple processors simultaneously. Electronic device networks consist of components and operations with a host or master electronic device and one or more remote or service electronic devices.

[0033] It should be noted that any data (e.g., mask patterns, parameters, or control data) generated by any method disclosed in the embodiments of this application can be stored in electronically readable (transient or non-transient) storage media, such as volatile memory components (e.g., Dynamic Random-access Memory (DRAM) or Static Random Access Memory (SRAM)), or non-volatile memory components (e.g., hard disks). This data can be created, updated, or stored using local electronic devices or via a network (e.g., via server electronic devices), and can be exchanged between electronic devices, semiconductor process equipment, and semiconductor testing equipment.

[0034] In some embodiments, the mask is a patterned substrate used to pattern photoresist coated on a semiconductor wafer during a photolithography process. Although only one mask is described in some embodiments, those skilled in the art will understand that the design principles according to embodiments of this application can be used to fabricate various semiconductor layers to form an integrated circuit.

[0035] In some embodiments, the mask pattern or electron beam pattern is an electronic file or data type that can be read by a semiconductor processing machine or semiconductor testing machine to allow the machine to obtain information contained in the electronic file or data. This information includes, but is not limited to, multiple locations in the mask to be manufactured and the characteristics of these locations (i.e., based on this electronic file or data type, whether a portion of the photoresist layer should be retained or removed after exposure using the manufactured mask, followed by a development process).

[0036] In some embodiments, semiconductor manufacturing equipment may include a lithography machine and an electron beam writer (e-beam). In some embodiments, semiconductor testing equipment includes a scanning electron microscope. Semiconductor manufacturing or testing equipment is, but is not limited to, tools such as motors, optical components (e.g., light sources or lenses), image acquisition devices, and electronic devices. The electronic devices in this application embodiment include a processor, a user interface, transient and / or non-transitory electronically readable media, and software, programs, or instructions stored in the non-transitory electronically readable media. When the software, program, or instructions are executed, the processor of the electronic device generates commands to control the operation of the hardware or software modules of the semiconductor manufacturing or testing equipment.

[0037] Please see Figure 1 , Figure 1 This is a schematic diagram of an electronic device structure provided in an embodiment of this application.

[0038] like Figure 1 As shown, the electronic device 100 includes a central processing unit 101, which can perform various appropriate actions and processes according to computer program instructions stored in a first memory 102 or loaded from a storage unit 108 into a second memory 103. The first memory 102 may be, for example, a read-only memory (ROM), and the second memory 103 may be, for example, a random access memory (RAM). The first memory 102 and the second memory 103 can also store various programs and data required for the operation of the electronic device 100. The central processing unit 101, the first memory 102, and the second memory 103 are interconnected via a bus 104. An input / output (I / O) interface 105 is also connected to the bus 104.

[0039] Multiple components in electronic device 100 are connected to I / O interface 105, including: input unit 106, such as keyboard, mouse, etc.; output unit 107, such as various types of displays, speakers, etc.; storage unit 108, such as disk, optical disk, etc.; and communication unit 109, such as network card, modem, wireless transceiver, etc. Communication unit 109 allows electronic device 100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0040] Central processing unit 101 executes the various methods and processes described above, such as Figure 3 , Figure 5 , Figure 6 The method is illustrated. For example, in some embodiments, Figure 3 , Figure 5 , Figure 6 The method shown can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as storage unit 108. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 100 via first memory 102 and / or communication unit 109. When the computer program is loaded into second memory 103 and executed by central processing unit 101, the above-described method can be performed. Figure 3 , Figure 5 , Figure 6 One or more steps of the method shown. Alternatively, in other embodiments, the central processing unit 101 may be configured to perform [the following steps] by any other suitable means (e.g., by means of firmware). Figure 3 , Figure 5 , Figure 6 The method shown.

[0041] As we understand it, photolithography is a key technology in integrated circuit manufacturing, responsible for transferring mask patterns onto silicon wafers. A layout typically contains both densely distributed patterns (such as 1:1 equally spaced lines) and sparse patterns (independent lines). The design of logic devices, in particular, offers greater flexibility. Both theoretical and experimental results clearly demonstrate that the photolithography process window (PW) for densely distributed patterns differs from that for sparse patterns. Conditions suitable for dense pattern exposure are not suitable for sparse pattern exposure. The process window refers to the range of exposure dose and defocus that ensures the mask pattern can be correctly replicated onto the silicon wafer. It contains three aspects of information: imaging accuracy, exposure, and depth of focus. The process window reflects the sensitivity of linewidth to exposure energy and focus; lower sensitivity is better, and a larger window indicates a more stable process. The process window can be used to evaluate the optimization effect of light source mask optimization (also known as light source mask co-optimization). If the same mask contains both dense and sparse patterns, there is a risk that the photolithography process window may not meet the requirements. The lithography process window for dense lines (L / S = 1:1) is larger than that for independent lines, while the lithography process window for semi-sparse lines (L / S ~ 1:3) is even smaller than that for independent lines. Under off-axis illumination conditions, this relationship between the process window and pattern density is more pronounced.

[0042] Adding auxiliary patterns to the design can solve the technical challenge of excessively small process windows for non-dense periodic patterns. Auxiliary patterns are very small patterns placed around sparse patterns, making the sparse patterns appear as dense patterns from an optical perspective. During exposure, they only scatter light and do not form patterns on the photoresist. Auxiliary patterns are also called sub-resolution assisted features (SRAF) or scattering bars (SB). Auxiliary patterns cannot be too small; excessively small auxiliary patterns will increase the difficulty of mask fabrication.

[0043] With the further development of computing technology, sub-resolution auxiliary graphics can also be inserted entirely through model calculations, a method known as model-based SRAF (SRAF). Model-based SRAF is used in the photolithography of logic devices. In the current research and evaluation of photolithography processes and materials, computer simulation algorithms are used to insert sub-resolution auxiliary graphics, thereby improving the photolithography process window. Inserting sub-resolution auxiliary graphics into the physical design layout using computer models has become a crucial step in bringing photolithography to mass production. The image log slope of the target graphic (main graphic) is calculated based on the size and insertion position of the sub-resolution auxiliary graphic. Then, iterative parameter adjustments are performed until the maximum contrast is achieved. Finally, under software calculation, the auxiliary lines are placed at a certain distance from the target graphic and adjusted to an appropriate size to maximize the image log slope of the target graphic.

[0044] In the development of photolithography processes, source mask optimization is a crucial step in determining source conditions based on photolithography capabilities and physical layout design rules. This process also requires inserting suitable sub-resolution auxiliary patterns in terms of size and position. Source mask optimization is a complex and computationally intensive algorithm that selects a few critical patterns (e.g., an upper limit of 30) to represent the entire layout design according to certain rules. The fewer critical process window patterns involved, the shorter the optimization iteration time. These critical patterns are optimized using source masks to obtain source conditions that allow the entire layout to have a qualified common window. In this process, the continuous transmission mask (CTM) is a grayscale image calculated after modeling the electric field transmission on the mask plane. The core (seed) of the sub-resolution auxiliary patterns is extracted from the optimized CTM, i.e., the auxiliary pattern seed is extracted, and the placement of the sub-resolution auxiliary patterns is guided by the auxiliary pattern seed.

[0045] Source optimization (SO) is the process of finding the best matching light source given a mask pattern, i.e., a fixed target pattern. This process involves only one variable: the light source. Please refer to [link / reference]. Figure 2A During the light source optimization process, constraints are added to an unconstrained free light source 21 to obtain a free light source 22 or a parameterized light source 23.

[0046] Mask optimization (MO), also known as optical proximity correction (OPC), is a process that, under a given light source, finds a way to make the lithographic profile after exposure match the target pattern by moving segments of the line edges of the mask pattern. This process uses only one variable: the mask.

[0047] Light source mask optimization, also known as joint optimization of the light source and mask, involves both the light source and mask patterns acting as variables, working together to find the optimal matching solution through iterations of a penalty function. This joint optimization aims to reduce overall edge placement errors. In this process, sub-resolution auxiliary patterns are inserted into the mask pattern. These auxiliary patterns are small patterns placed around the sparse pattern, making the sparse pattern appear as a dense pattern from an optical perspective. They only modulate the light and do not form an image on the photoresist. For example... Figure 2B As shown, continuous transmission mask calculation is performed on the mask image to be optimized, resulting in a continuous transmission mask grayscale image 24. The initial position and shape of the sub-resolution auxiliary image are extracted from the continuous transmission mask grayscale image 24. Further optimization with added constraints yields a polygonal mask image 25. Further optimization of the polygonal mask image 25 results in the optimized mask image 26.

[0048] This application uses flowcharts to illustrate the operations performed by an electronic device according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously, as needed. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0049] Please see Figure 3 , Figure 3 This is a flowchart illustrating a light source mask optimization method provided in an embodiment of this application. This light source mask optimization method can be executed by the aforementioned computer.

[0050] Step S31: The computer acquires the optimization parameters, which include the test light source and the test pattern.

[0051] The test light source is the light source to be optimized. The test pattern is the mask pattern to be optimized, and the test pattern can be a test pattern defined according to the design rules.

[0052] In some embodiments, the optimization parameters may also include specific conditions for lithography required for optimizing the light source mask, such as the lithography machine model and related hardware parameters, the numerical aperture size and polarization direction of the light source, the structure of the photoresist film layer, the actual chip pattern, and the pattern used to calibrate the exposure agent. This application does not specifically limit these.

[0053] Step S32: The computer performs continuous transmission mask calculation based on the test light source and test pattern to obtain a grayscale and tone image of the continuous transmission mask and a preliminarily optimized light source.

[0054] In this embodiment, the computer performs continuous transmission mask calculation based on the test light source and the test pattern. This involves dividing the light source into pixelated grid points and converting the binary test pattern into a continuous transmission mask grayscale image. The test light source containing the pixelated grid points is applied to the continuous transmission mask grayscale image to obtain the light intensity distribution on the wafer surface, i.e., the preliminarily optimized light source. During this process, the test pattern is not in binary 0 or 1 form (0 represents opacity, 1 represents transparency), but rather exhibits a continuous phase change. In this form, both the test light source and the test pattern can be optimized with maximum degrees of freedom to obtain a better matching result between the light source pattern and the mask pattern. Computer-based continuous transmission mask calculation is a mature existing technology and will not be elaborated further here.

[0055] In this embodiment, each pixel in the continuously transmitted mask grayscale image is assigned a value between 0 and 1 (e.g., 0.1, 0.2, 0.3, etc.) instead of a binary value of 0 or 1. In other embodiments, the continuously transmitted mask grayscale image may be a pixelated grayscale image, wherein each pixel has multiple values ​​(e.g., the values ​​are in the range [-255, 255], the normalized values ​​are in the range [0, 1] or [-1, 1] or other suitable ranges).

[0056] Step S33: The computer extracts auxiliary graphic seeds based on the continuously transmitted mask grayscale tones image.

[0057] In this embodiment, the computer extracts auxiliary graphic seeds, or sub-resolution auxiliary graphic seeds (ASRF seeds), from the target graphic in the continuously transmitted mask grayscale tones image. Extracting auxiliary graphic seeds is a well-established existing technology and will not be elaborated upon here.

[0058] Step S34: The computer obtains a free-form auxiliary graphic based on the auxiliary graphic seed.

[0059] In this embodiment, the computer obtains a free-form auxiliary graphic based on the auxiliary graphic seed, that is, a free-form sub-resolution auxiliary graphic. The free-form auxiliary graphic includes multiple sub-resolution auxiliary graphics, which can be added to the test graphic. The computer obtaining a free-form auxiliary graphic based on the auxiliary graphic seed is a well-established existing technology and will not be elaborated further here.

[0060] Step S35: The computer obtains the mask pattern to be optimized based on the free-form auxiliary graphics and the test graphics.

[0061] In this embodiment, the computer adds sub-resolution auxiliary graphics to the test graphic based on free-form auxiliary graphics to obtain the mask graphic to be optimized. Adding auxiliary graphics to the test graphic is a well-established existing technology and will not be described in detail here.

[0062] Step S36: The computer optimizes the mask pattern to be optimized, the light source to be preliminarily optimized, and the penalty function to obtain the optimized first light source pattern and the optimized first mask pattern.

[0063] In this embodiment, the computer uses a penalty function to jointly (cooperatively) optimize the initially optimized light source and the mask pattern to be optimized. This optimizes the shape of the initially optimized light source, the light intensity of each pixel on the initially optimized light source, and corrects the target pattern and auxiliary patterns in the mask pattern to be optimized, thereby obtaining the optimized first light source pattern and the optimized first mask pattern. The light source pattern refers to the light source itself, which includes the illumination intensity at various locations of the light source, reflecting the intensity distribution of the light source.

[0064] Specifically, the computer needs to select and insert sub-resolution auxiliary graphics positions based on the auxiliary graphic seed to obtain free-form auxiliary graphics. This results in a sub-resolution auxiliary graphic with continuous phase changes, formed by continuously transmitting the mask's grayscale and tonal images. After completing these steps, the computer fits the continuously changing test graphic and the free-form auxiliary graphic onto a bounded geometric shape according to predefined design rules, and performs corresponding graphic cleanup to remove small fragments generated during the fitting process. After the initial optimization of the light source, mask, and SRAF, the grid points of the initially optimized light source and test graphic are gradually refined in subsequent optimization processes. The free-form light source is then fitted to a hardware-implementable form to obtain the optimized first light source graphic. Typically, the number of grid points in the free-form light source is 201×201 or 251×251, and the fitted light source forms are mainly of three types: light sources from the DOE library, parameterized DOE light sources, and free-form light sources. Light sources from the DOE library use existing light source forms, suitable for lithography of non-critical layers, without increasing hardware implementation costs. Parametric DOE lights are extensions of the DOE library, allowing some geometric parameters of the DOE light source to be changed to achieve better resolution. Freeform lights use a pixelated light source format, offering a high degree of freedom and enabling optimization of the resolution of specific graphics.

[0065] In this embodiment, since the test light source is obliquely incident on the mask pattern, the actual pattern on the wafer will be offset. Therefore, it is necessary to set the mask pattern to defocus to correct the offset. The mask defocus amount is set as the parameter to be optimized, and the photoresist image under different mask defocus amounts is calculated. The edge placement error (EPE) between the simulated photolithographic profile and the actual target pattern is used as the penalty function, which is as follows:

[0066] CF=∑ pw ∑ x (pw,x)||EPE|| p

[0067] Where CF is the cost function; pw represents different exposure conditions (exposure dose and defocus); x is each imaging evaluation point or control point; w represents the weight; EPF uses the norm of P, and P can be an even number. The larger the value of P, the stronger the optimization capability for EPE, and thus the greater the possible reduction of the overall EPE value.

[0068] In this embodiment, a free-form sub-resolution auxiliary pattern is added to the test image to obtain the mask pattern to be optimized. Each evaluation point in the test light source and the mask pattern to be optimized is jointly optimized to minimize the penalty function, thereby minimizing the edge placement error. Different exposure conditions are defined manually based on the approximate fluctuation range of the actual process; generally, focus fluctuation is ±40nm, dose fluctuation is ±5%, and mask manufacturing error fluctuation is ±0.5nm. x represents each evaluation point / control point, which can be manually defined and generally corresponds to the point measured during final verification on the wafer.

[0069] The following section details the optimization process based on the penalty function. Please refer to the attached document. Figure 4 The test light source 41 is a ring light source. The intensity distribution of the test light source 41 is as follows: Figure 4 As shown in the figure. The horizontal axis is the x-axis (x position) and the vertical axis is the y-axis (y position). Different gray values ​​represent different light intensities. As can be seen from the figure, the range of light intensity is [0-1]. Black represents light intensity of 0, which is the darkest, and white represents light intensity of 1, which is the brightest.

[0070] During the light source mask optimization process, the computer starts with an unrestricted light source (test light source 41) and moves it along the edge of the test image. The test light source 41 illuminates the test image to obtain various imaging evaluation points 43 (such as...). Figure 4 The algorithm calculates the edge placement error (EPE) between the simulated lithographic profile 42 and the imaging evaluation point 43 (using a rectangular bounding box). It also introduces exposure energy (dose), focus, and mask error, and calculates the edge deviation between the lithographic profile and the target pattern caused by these perturbations based on a penalty function (also called an evaluation function).

[0071] Light source mask optimization is achieved based on an edge deviation penalty function. This penalty function incorporates all imaging evaluation points on the pattern under different process conditions, and performs a weighted average of the edge position errors under different process conditions and imaging evaluation points. Through continuous correction of the light source and mask patterns, an optimal illumination condition is found that minimizes the penalty function. The exposure energy and focus at position 44 are optimal.

[0072] In some embodiments, for the graphic structure that restricts the process window, which is usually a region with potential defects, the necessary optimization simulation conditions for the global graphic structure can be adjusted first, such as adjusting parameters like exposure process conditions, light source type, and polarization state. Then, the process window matrix in the optimization parameters can be adjusted separately for this part of the graphic. For example, if the depth of focus is insufficient, the defocus amount can be appropriately increased; if the exposure latitude is insufficient, the exposure dose fluctuation can be fine-tuned; if the mask error enhancement factor is too large, the adjustment graphic bias can be appropriately increased.

[0073] In some embodiments, the light source mask optimization method further includes: a computer performing a first simulation evaluation on the first light source pattern and the first mask pattern to obtain a first lithographic imaging quality, and performing corresponding operations based on the first lithographic imaging quality and the first lithographic process conditions.

[0074] In this embodiment, the computer uses EDA tools to perform light source mask optimization simulation on the free-form auxiliary pattern, the test pattern, and the initially optimized light source. In this optimization simulation, process parameters for evaluating the lithography performance of the test pattern participating in the optimization can be obtained, i.e., lithography imaging quality. Evaluation indicators for lithography imaging quality include process window, image log slope (ILS), normalized image log slope (NILS), mask error enhancement factor (MEEF), depth of focus (DOF), exposure energy tolerance, critical dimensions, and process variation band (PVband), etc.

[0075] Among these, depth of focus characterizes the relationship between the imaging quality of the exposure system and the position on the wafer surface. Within the focusing range, the exposure imaging quality can be guaranteed. A larger depth of focus indicates higher process stability. Exposure energy tolerance, typically set at 5% in the process, is used to evaluate the depth of focus and other results under this condition. The mask error enhancement factor is defined as the slope of the change in photoresist linewidth on the wafer with the change in pattern linewidth on the mask; a smaller mask error enhancement factor value indicates a more stable process. A smaller critical dimension increment indicates higher process precision. A smaller process variation band (PV band) value indicates a more stable process and smaller pattern exposure error.

[0076] In this embodiment, after performing light source mask optimization simulation, the simulation results are output. The process inspection requirement is determined to be ±10% of the pattern width with a feature size tolerance, and the depth of focus at 5% exposure latitude is used as the evaluation index for lithographic imaging quality. The results of the light source mask optimization are analyzed. If the depth of focus does not meet the requirement (greater than or equal to 80 nanometers in this embodiment), the first lithographic imaging quality does not meet the first lithographic process conditions. The computer then re-executes steps S21 to S25, meaning it needs to re-acquire the test pattern or test light source and then repeat the light source mask optimization process. If the depth of focus is greater than or equal to 80 nanometers, the first lithographic imaging quality meets the first lithographic process conditions. If, under the condition that the first lithographic imaging quality meets the first lithographic process conditions, it is necessary to further increase the process window and iterate the light source mask optimization, the computer also needs to re-execute steps S21 to S25.

[0077] In implementing the embodiments of this application, the inventors discovered that the light source mask optimization method requires multiple iterations. Each iteration involves recalculating the continuous transmission mask, regenerating the continuous transmission mask grayscale image, re-obtaining auxiliary graphic seeds based on the continuous transmission mask grayscale image, re-filling the auxiliary graphic seeds into a free-form sub-resolution auxiliary graphic, and re-correcting the free-form sub-resolution auxiliary graphic according to mask rule check (MRC). Therefore, the light source mask optimization method is computationally intensive, consumes a significant amount of computation time, and has low optimization efficiency. In existing technologies, reducing computational load involves selecting suitable test graphics for optimization, thereby reducing the input for light source mask optimization. However, the number of selected test graphics still requires a huge amount of computation for light source mask optimization. The inventors also found that the multiple continuous transmission mask calculations during the light source mask optimization process are the main reason affecting the iteration speed.

[0078] In view of this, embodiments of this application provide a method for optimizing light source masks. This method involves obtaining qualified auxiliary graphic placement rules and pre-adding (placing) qualified auxiliary graphics into the graphics (such as test graphics or selected graphics) participating in light source mask optimization according to these rules, thus obtaining the graphic to be optimized. Subsequently, light source mask optimization is directly performed on this graphic without the need for operations related to generating auxiliary graphics. These operations include, but are not limited to, the following: performing continuous transmission mask calculations during light source mask optimization; generating continuous transmission mask grayscale tones; obtaining auxiliary graphic seeds based on the continuous transmission mask grayscale tones; filling the auxiliary graphic seeds into free-form sub-resolution auxiliary graphics; and checking and correcting the free-form sub-resolution auxiliary graphics according to mask rules. This significantly reduces computational load and time, thereby improving the iteration efficiency of light source mask optimization.

[0079] Please see Figure 5 , Figure 5 This is a flowchart illustrating a method for optimizing a light source mask, provided as an embodiment of this application. The method can be executed by the aforementioned computer.

[0080] Step S51: Obtain the test pattern and test light source.

[0081] Integrated circuit products are manufactured by an integrated circuit manufacturing system. An integrated circuit manufacturing system may include several entities, such as a design house, a mask house, and an integrated circuit manufacturer (i.e., a wafer fab). The design house generates an integrated circuit design layout (also known as an IC design pattern). The integrated circuit design layout contains various circuit patterns designed for the integrated circuit product according to the specifications of the integrated circuit product being manufactured. The mask house uses the integrated circuit design layout to manufacture one or more masks, which are used to manufacture the various layers of the integrated circuit product according to the integrated circuit design layout. A photomask (or reticle) is a patterned substrate used in the photolithography process to pattern a wafer (e.g., a semiconductor wafer). The mask house performs mask data preparation, and the integrated circuit design layout is compiled into a form that can be written to a mask writer to produce a mask. That is, the integrated circuit design layout is compiled into machine-readable instructions for a mask writer, such as an electron beam writer. The mask company executes mask data to generate a mask pattern (mask layout or mask pattern) corresponding to the target pattern defined by the integrated circuit design layout. The mask company's computer includes various programs for optimizing the mask pattern. For example, by executing the light source mask optimization method provided in this application embodiment, the mask company's computer enables a final pattern to be formed on a wafer using a photolithography process employing the mask. This final pattern is manufactured from a mask pattern with enhanced resolution and accuracy; that is, the final pattern is an optimized mask pattern with enhanced resolution and accuracy.

[0082] In this embodiment, the test pattern refers to a pattern on the mask used for optimization, i.e., the mask pattern to be optimized. The test pattern is typically a pattern within the design layout; in specific implementations, it can be a representative pattern within the design layout or a pattern that presents significant challenges for photolithography. In this embodiment, there can be one or multiple test patterns, which can be selected or designed by the photolithography engineer.

[0083] The test graphics may include unit graphics, which can be independent line graphics, independent square graphics, independent rectangle graphics, L-shaped graphics, U-shaped graphics, T-shaped graphics, and H-shaped graphics, etc. Test graphics may also include composite graphics formed by combinations of unit graphics, where composite graphics may include: periodic line graphics, periodic array graphics of squares, staggered square graphics, periodic array graphics of rectangles, staggered rectangular graphics, end-to-end periodic graphics, end-to-line periodic graphics, etc. This application does not specifically limit these aspects.

[0084] In this embodiment, the test light source can be selected from a light source library as the optimized base light source. For example, the test light source can be an annular light source, which refers to a light source where energy is concentrated in a ring shape. The test light source includes the illumination intensity at various locations, reflecting the intensity distribution of the test light source, which can be referenced... Figure 4 Schematic diagram of the intensity distribution of the ring light source.

[0085] Step S52: When the photolithography imaging quality under the combination of test light source and test pattern is detected to meet the corresponding photolithography process conditions, obtain the auxiliary pattern placement rules.

[0086] The evaluation metrics for lithography imaging quality include, but are not limited to: process window, image logarithmic slope, normalized image logarithmic slope, mask error enhancement factor (MEEF), depth of focus, critical dimension (CD), exposure latitude (EL), and MEEF. Users can select the appropriate metrics to evaluate lithography imaging quality based on their specific circumstances; this application does not impose any specific limitations on this selection.

[0087] The lithography process conditions are used to determine whether the detection indicators used to evaluate the lithography imaging quality meet the preset indicators. For example, the lithography process conditions use the feature size tolerance at a preset measurement position as the measurement standard to determine whether the depth of focus, exposure latitude, mask error enhancement factor, etc., meet the preset indicators. For instance, the process detection requirement is set as ±10% of the pattern width (feature size tolerance), and the depth of focus at 5% exposure latitude is used as the detection indicator to evaluate the lithography imaging quality. The results of the co-optimization of the light source and mask are analyzed. If the depth of focus meets the preset indicator (e.g., depth of focus greater than or equal to 80 nanometers), the lithography imaging quality under the test light source and test pattern combination meets the corresponding lithography process conditions. If the depth of focus does not meet the preset indicator (e.g., depth of focus less than 80 nanometers), the lithography imaging quality under the test light source and test pattern combination does not meet the corresponding lithography process conditions.

[0088] The rules for placing auxiliary graphics include, but are not limited to: the size (length, width) of the auxiliary graphics, the distance between auxiliary graphics, and the distance between the auxiliary graphics and the target graphic.

[0089] In some embodiments, the computer performs light source mask optimization on the test light source and test pattern to obtain an optimized first light source and an optimized first mask pattern. A first simulation evaluation is performed on the first light source and the first mask pattern to obtain a first lithographic imaging quality. When the first lithographic imaging quality is detected to meet the first lithographic process conditions, mask optimization is performed on the first light source and test pattern to obtain a corresponding optimized second mask pattern. A second simulation evaluation is performed on the first light source and the second mask pattern to obtain a second lithographic imaging quality. When the second lithographic imaging quality is detected to meet the second lithographic process conditions, auxiliary pattern placement rules are obtained. That is, when the lithographic imaging quality corresponding to the light source mask optimization of the test light source and test pattern meets the corresponding lithographic process conditions, and the lithographic imaging quality corresponding to the mask optimization of the first light source and test pattern also meets the corresponding lithographic process conditions, it is considered that the lithographic imaging quality under the combination of the test light source and test pattern meets the corresponding lithographic process conditions. When the lithographic imaging quality corresponding to the mask optimization also meets the corresponding lithographic process conditions, corresponding auxiliary pattern placement rules are obtained. Each test pattern has its corresponding auxiliary pattern placement rules. The first lithography process conditions and the second lithography process conditions can be the same or different.

[0090] In this embodiment, during the optimization of the test light source and test pattern (e.g., mask optimization), the computer calculates the imaging contrast of the target pattern on the test pattern based on the size and insertion position of the auxiliary pattern. These parameters are then continuously adjusted until the maximum contrast is achieved. At this point, the size and insertion position of the corresponding auxiliary pattern constitute the auxiliary pattern placement rule. The accuracy of the obtained auxiliary pattern is very high; therefore, the test pattern including this auxiliary pattern is also very accurate. Consequently, the auxiliary pattern placement rules extracted from this test pattern are more accurate, making subsequent additions of auxiliary patterns to the test pattern using these placement rules more accurate. Furthermore, this method obtains auxiliary pattern placement rules, which can be used to add auxiliary patterns to the test pattern. This method is fast, convenient, and simple to apply, meeting the dual requirements of speed and accuracy for mass production.

[0091] The inventors discovered that after several iterations of light source mask optimization and mask optimization, the lithographic imaging quality corresponding to both optimizations meets the corresponding lithographic process conditions, thus stabilizing the pattern limiting the process window. The auxiliary pattern placement rules obtained after mask optimization can be used for further optimization. That is, when the first lithographic imaging quality corresponding to light source mask optimization using the test pattern meets the first lithographic process conditions, and the second lithographic imaging quality corresponding to mask optimization based on the optimized first light source and all test patterns also meets the second lithographic process conditions, the auxiliary pattern placement rules corresponding to mask optimization can be obtained, and the input for the first optimization can be generated based on these rules.

[0092] Step S53: Obtain the graphic to be optimized based on the placement rules of the auxiliary graphic and the test graphic.

[0093] In this embodiment, each test graphic has its corresponding auxiliary graphic placement rule, that is, each test graphic has its corresponding auxiliary graphic and the position of each auxiliary graphic. The computer adds the corresponding auxiliary graphic to the vicinity of the target graphic of the test graphic according to the auxiliary graphic placement rule to obtain the graphic to be optimized, which includes the auxiliary graphic and the target graphic.

[0094] Step S54: Use the graphic to be optimized as the input for the first optimization, perform the first optimization on the graphic to be optimized, and obtain the first graphic.

[0095] In this embodiment, the first optimization can be either mask optimization or light source mask optimization. When the first optimization is mask optimization, it is necessary to ensure that the light source in the mask optimization is the same light source used to obtain the auxiliary graphic placement rules.

[0096] In the embodiments of this application, the inventors found that when the photolithography imaging quality under the combination of the test light source and the test pattern meets the corresponding photolithography process conditions, the effect of increasing the process window by updating the auxiliary pattern placement rules is not significant. The pattern limiting the process window is basically stable. Increasing the process window can be achieved by adjusting the optical parameters (such as the parameters in the penalty function).

[0097] In this embodiment, the computer pre-adds (places) the corresponding qualified auxiliary graphics to the corresponding test graphics participating in the subsequent first optimization (light source mask joint optimization or mask optimization) based on the auxiliary graphics placement rules, thus obtaining the graphics to be optimized. Subsequently, light source mask optimization or mask optimization is directly performed on the graphics to be optimized without the need for operations related to generating auxiliary graphics. Operations related to generating auxiliary graphics include, but are not limited to, the following: operations such as performing continuous transmission mask calculations during light source mask optimization, generating continuous transmission mask grayscale tones images, obtaining auxiliary graphics seeds based on the continuous transmission mask grayscale tones images, filling the auxiliary graphics seeds into free-form sub-resolution auxiliary graphics, and checking and correcting free-form sub-resolution auxiliary graphics according to mask rules. This greatly reduces the computational load and time, thereby improving the iteration efficiency of light source mask optimization. This embodiment provides a sub-resolution auxiliary graphics insertion rule basis for optical proximity effects, that is, when the light source mask has been optimized and the corresponding lithographic imaging quality after mask optimization meets the corresponding lithographic process conditions, the corresponding auxiliary graphics placement rules can be obtained. This approach, which relies on rapid iteration to generate optimization results that meet mass production requirements, allows for the faster acquisition of qualified placement rules for auxiliary graphics (such as sub-resolution auxiliary graphics) from the optimization results.

[0098] Please see Figure 6 , Figure 6 This is a flowchart illustrating another method for optimizing a light source mask, provided as an embodiment of this application. This method can be executed by the aforementioned electronic device.

[0099] Step S601: The computer acquires the test light source and key graphics.

[0100] In this embodiment, the computer selects key graphics from the test graphics or directly obtains key graphics input by the user. The key graphics are those selected from the test graphics for subsequent optimization. Key graphics can be representative of the mask pattern or graphics that are difficult to handle for photolithography. For details on how the computer obtains the test light source, test graphics, and key graphics, please refer to [reference needed]. Figure 3 or Figure 5 This will not be elaborated upon here.

[0101] In some embodiments, the computer may refer to Figure 3 or Figure 5 A test pattern is obtained, and then N key patterns are selected from the test pattern according to the diffraction order. The counting unit of N is ten, and the value of N does not exceed 30, and is generally between 10 and 20. This application does not specifically limit this.

[0102] In this embodiment, the light source mask optimization method has very high computational requirements, making it impossible to perform global optimization on all layouts (mask patterns) of the entire integrated circuit product or chip. Therefore, it is necessary to generate light sources using a small number of typical mask patterns to ensure that the computation speed is within an acceptable range. Thus, determining the test pattern is particularly important in the entire light source mask optimization process; it is necessary to select a test pattern that covers as many possible pattern structures as possible while satisfying design rules.

[0103] In some embodiments, the inputs for optimizing the light source mask also include repeating cells of static random access memory (SRAM) and some known weak points, which may be obtained empirically or during the design rule formulation process.

[0104] The number of selected test patterns plus actual weakness patterns can reach hundreds. Such a large number of patterns still requires a huge computational load for light source mask optimization. Therefore, further screening of the selected test patterns plus weakness patterns is necessary. The computer selects patterns based on their diffraction order. For patterns with periods that are integer multiples of each other, their diffraction spectra will overlap. In this case, patterns with smaller periods are preferred as key patterns. Patterns with larger periods can achieve optical performance similar to those with smaller periods by inserting sub-resolution auxiliary patterns. Pattern selection can significantly reduce the number of patterns involved in the calculation.

[0105] It is understood that computers can also select key graphics using other methods, and this application does not specifically limit this.

[0106] In this embodiment, the method for optimizing light source masks provided in this application offers a manual selection function. Users can adjust the number and weights of computational graphics based on existing weaknesses and experience to select key graphics. The computer acquires the key graphics selected by the user and uses them as input to the method for optimizing light source masks provided in this application. After graphics selection, the total number of input graphics can generally be reduced to a dozen or so.

[0107] Please refer to the following: Figure 7A The computer acquires the test light source 71 and key graphics 72. The test light source 71 is a ring light source.

[0108] Step S602: The computer optimizes the light source and key graphics using a light source mask to obtain the optimized first light source and the optimized first mask graphic.

[0109] Please refer to the embodiments in this application as well. Figure 7BThe computer performs continuous transmission mask calculations on the test light source 71 and key graphic 72, obtaining a continuous transmission mask grayscale image 73 and an optimized free-form light source 74. Please refer to the following: Figure 7C The computer extracts auxiliary graphic seeds 76 based on the pixels in the continuously transmitted grayscale image 73 and the target graphic 75. The computer then adds the sub-resolution auxiliary graphics to the key graphic 72 based on the auxiliary graphic seeds 76 to obtain the mask graphic to be optimized. Please refer to [link / reference needed]. Figure 7D and Figure 7E The computer uses a free-form light source 74 to perform co-optimization with the mask pattern to be optimized, obtaining a first mask pattern 77 and an unblurred free-form light source 78. The computer then rectangularizes the auxiliary patterns in the first mask pattern 77, obtaining a second mask pattern 79. The auxiliary patterns in the second mask pattern 79 are all rectangularized compared to those in the first mask pattern 77. The computer then uses a blurred free-form light source 80 and the second mask pattern 79 for co-optimization; please refer to the documentation for further details. Figure 7F The computer outputs an optimized first light source 81 and an optimized first mask pattern 82. The optimized first mask pattern 82 includes a corrected target pattern 83 and a sub-resolution auxiliary pattern 84.

[0110] The specific details of the computer's optimization of the light source mask for the test light source and key graphics can be found in Figure 2. This is an existing mature technology and will not be elaborated here.

[0111] Step S603: The computer performs a first simulation evaluation on the first light source and the first mask pattern to obtain the first lithography imaging quality and determine whether the first lithography imaging quality meets the first lithography process conditions.

[0112] In this embodiment of the application, a computer can use EDA tools to perform source mask optimization simulation. In this optimization simulation, detection indicators for evaluating the lithography imaging quality of each pattern involved in the optimization can be obtained, such as process window, mask error enhancement factor, normalized image log slope (NILS), and other process parameters that measure lithography performance.

[0113] For example, the computer determines that the feature size tolerance is ±10% of the pattern width as the process inspection requirement, and uses the depth of focus at 5% exposure latitude as the inspection index for evaluating the lithography imaging quality, and analyzes the results of the co-optimization of the light source and mask. If the depth of focus meets the preset index (e.g., depth of focus greater than or equal to 80 nanometers), the first lithography imaging quality meets the first lithography process conditions, and the computer executes step S604. If the depth of focus does not meet the preset index (e.g., depth of focus less than 80 nanometers), the first lithography imaging quality does not meet the first lithography process conditions, and the computer re-executes steps S601 to S603, that is, the computer re-acquires the test pattern and re-optimizes the light source and mask for the test light source and the test pattern.

[0114] Step S604: The computer performs mask optimization on the first light source and the test pattern to obtain the corresponding optimized second mask pattern.

[0115] In this embodiment, the computer performs mask optimization on the first light source and all test patterns in the test pattern library to obtain the corresponding optimized second mask pattern. For each test pattern, the computer moves segments of the line edges of the test pattern to find a scheme that makes the lithographic contour after exposure match the target pattern, thus obtaining the optimized second mask pattern corresponding to that test pattern.

[0116] In this embodiment, if the result of the above-mentioned light source mask optimization meets the requirements (i.e., the first lithography imaging quality meets the first lithography process conditions), then a further mask optimization verification is required. During mask optimization verification, the first light source obtained from the previous step of light source mask optimization is used to perform mask optimization verification on more test patterns and actual patterns. Generally, this involves performing mask optimization verification on the portion of patterns that were filtered out during the pattern selection process, or it can involve performing mask optimization verification on all test patterns in the test pattern library. The mask optimization verification process is the process of simulating optical proximity effect correction to modify the test pattern. During this process, the light source remains fixed. After the above process is completed, step S605 is executed to compare the simulation results of mask optimization with the actual wafer exposure data. If the evaluation is successful, the next step of optical proximity effect correction modeling and correction can be performed. Mask optimization is a mature existing technology and will not be elaborated further here.

[0117] In this embodiment of the application, when the computer performs mask optimization on the first light source and the test pattern, the corresponding optimized second mask pattern obtained includes auxiliary patterns. That is, when performing mask optimization, the placement rules of the auxiliary patterns corresponding to each test pattern can be obtained.

[0118] Step S605: The computer performs a second simulation evaluation on the first light source and the second mask pattern to obtain the second lithography imaging quality and determine whether the second lithography imaging quality meets the second lithography process conditions.

[0119] In this embodiment of the application, the computer can use EDA tools to perform mask optimization simulation. In this optimization simulation, detection indicators for evaluating the lithographic imaging quality of each pattern involved in the optimization can be obtained, such as process window, mask error enhancement factor, normalized image log slope (NILS), and other process parameters that measure lithographic performance.

[0120] For example, the computer determines that the feature size tolerance is ±10% of the pattern width as the process inspection requirement, and uses the depth of focus at 5% exposure latitude as the inspection index for evaluating the lithography imaging quality, and analyzes the results of the co-optimization of the light source and mask. If the depth of focus meets the preset index (e.g., depth of focus greater than or equal to 80 nanometers), the second lithography imaging quality meets the second lithography process conditions. If further optimization is needed, such as increasing the process window, the computer executes step S606. If the depth of focus does not meet the preset index (e.g., depth of focus less than 80 nanometers), the second lithography imaging quality does not meet the second lithography process conditions, the computer acquires the pattern that limits the process window, that is, the user selects the test pattern that limits the current process window, and uses the test pattern for step S602, that is, the computer re-optimizes the light source mask for the test light source and the test pattern that limits the process window.

[0121] The first photolithography process conditions and the second photolithography process conditions can be the same or different.

[0122] Step S606: The computer acquires the selected graphic.

[0123] In this embodiment, the computer acquires a selected graphic, which is a graphic selected by the user for further optimization. This selected graphic can be a graphic representing the limited process window determined by the user after analyzing the common process window corresponding to step S602 (light source mask optimization) and step S604 (mask optimization), as well as the image logarithmic slope / normalized image logarithmic slope / mask error enhancement factor / focus depth of each test graphic.

[0124] In some embodiments, the selected graphic can be a relatively stable graphic of the restricted process window. The user can record the graphic of the restricted process window after each optimization (light source mask optimization or mask optimization), and the graphic of the restricted process window that has been recorded a preset threshold number of times is used as the selected graphic. For example, if the computer executes steps S601 to S606, and the user records graphic A of the restricted process window after each optimization, then graphic A of the restricted process window is the selected graphic.

[0125] In some embodiments, if the first lithographic imaging quality meets the first lithographic process conditions and the second lithographic imaging quality meets the second lithographic process conditions, and if the process window needs to be further improved, the computer can obtain the corresponding third lithographic process conditions (such as a focal depth greater than or equal to 85 nanometers). The third lithographic process conditions are used to determine the first optimized lithographic imaging quality.

[0126] In this embodiment, by selecting specific graphics to further optimize the input of the first optimization, the input of the first optimization can be reduced, thus improving efficiency. Since the selected graphics are those that previously limited the process window during the optimization process, optimizing these selected graphics by the computer can more efficiently improve the process window.

[0127] Step S607: The computer acquires the placement rules for the auxiliary graphics.

[0128] In this embodiment of the application, if the second lithography imaging quality in step S605 meets the second lithography process conditions, it means that the auxiliary patterns inserted in each second mask pattern in step S604 are qualified, and the placement rules of the auxiliary patterns corresponding to each test pattern can be obtained.

[0129] When the lithography imaging quality corresponding to both the light source mask optimization in step S602 and the mask optimization in step S604 meets the corresponding lithography process conditions, the computer acquires the auxiliary pattern placement rules corresponding to the mask optimization in step S604, that is, acquires the auxiliary pattern placement rules corresponding to the second mask pattern, including the auxiliary pattern scale and the auxiliary pattern position. After the light source mask optimization and mask optimization have undergone iterations, the pattern restricting the process window has stabilized. At this point, acquiring the auxiliary pattern placement rules has little effect on increasing the process window. To increase the process window, it is better to adjust some optical parameters.

[0130] The order of steps S606 and S607 is not specifically limited. Step S607 can be executed first, followed by step S606. This embodiment of the application does not impose a specific limitation on this.

[0131] Step S608: The computer obtains the graphic to be optimized based on the auxiliary graphic placement rules and the selected graphic.

[0132] In this embodiment of the application, when the computer executes step S607, when initially inputting the test graphics from the test graphics library into the computer, it directly draws the sub-resolution auxiliary graphics into the corresponding position of the selected graphics according to the auxiliary graphics placement rules, and stores it as a special layer. This layer can exist in the computer's script, and its storage name can be consistent with the name of the sub-resolution auxiliary graphics in the software script. Then, the layer number of the sub-resolution auxiliary graphics is filled in the software script to inform the computer that this layer is a sub-resolution auxiliary graphics. In this way, the corresponding sub-resolution auxiliary graphics are added to the corresponding selected graphics according to the auxiliary graphics placement rules to obtain the graphics to be optimized.

[0133] In some embodiments, after the light source mask optimization in step S602 is iterated, if the lithography imaging quality in step S605 does not meet the lithography process conditions, the user selects about ten patterns that restrict the process window, performs light source mask optimization on these patterns, and obtains a first light source. If the result of the light source mask optimization can obtain a qualified process window, hundreds / thousands of test patterns (such as all test patterns in the test library) and the first light source obtained after light source mask optimization are used to perform mask optimization and process window checks. When the process window is found to meet the second lithography process conditions, that is, the lithography imaging quality of the mask optimization meets the corresponding lithography process conditions, auxiliary pattern placement rules are extracted using this as a node. The mask correction result and auxiliary pattern insertion result that can make the process window meet the standards can be determined. The light source mask optimization and the improved mask optimization process window are then further iterated. After mask optimization of all test patterns, satisfactory mask optimization results were obtained. However, patterns that restrict the process window were still identified. Analysis of the lithography process window confirmed that the most critical patterns limiting the process window were selected as the basis for subsequent iterations. Auxiliary patterns were pre-placed within these selected patterns to obtain the pattern to be optimized. This pattern was then fed back into the SMO for joint optimization of the light source and mask, aiming to obtain a larger process window (during this process, the auxiliary patterns are only pre-set once and are not regenerated during iterations).

[0134] After executing step S607, but before performing the first optimization (light source mask optimization or mask optimization), according to the auxiliary graphic placement rules corresponding to each test graphic, qualified sub-resolution auxiliary graphics are pre-placed in the selected graphics to obtain the graphic to be optimized. Please refer to [link / reference]. Figure 8 , Figure 8 This is a schematic diagram of a pre-set sub-resolution auxiliary graphic provided in an embodiment of this application. A sub-resolution auxiliary graphic 91 is pre-placed in the selected graphic 90, and the sub-resolution auxiliary graphic 91 (dashed box in the figure) is placed near the corresponding target graphic 92 (solid box in the figure).

[0135] Please refer to the following: Figure 9 Taking a selected graphic including target graphic 10 and target graphic 11, and inserting a resolution auxiliary graphic 12 into target graphic 10 and target graphic 11 as an example, when drawing the sub-resolution auxiliary graphic 12 into the selected graphic according to the auxiliary graphic placement rules, the approximate position of the sub-resolution auxiliary graphic 12 is determined based on the distance D1 between two adjacent target graphics (target graphic 10 and target graphic 11), and then the specific position of the sub-resolution auxiliary graphic 12 is determined based on the distance D2 between the sub-resolution auxiliary graphic 12 and target graphic 10. The scale of the sub-resolution auxiliary graphic 12 is determined based on its horizontal dimension (i.e., width) W1 and its vertical dimension (i.e., length) L1.

[0136] In some embodiments, step S606 can be replaced by obtaining a key graphic or a test graphic, then step S608 is to obtain the graphic to be optimized according to the auxiliary graphic placement rules and the key graphic, or to obtain the graphic to be optimized according to the auxiliary graphic placement rules and the test graphic.

[0137] Step S609: The computer takes the graphic to be optimized as the input for the first optimization, performs the first optimization on the graphic to be optimized, and obtains the first graphic.

[0138] In this embodiment, the graphic to be optimized is used as the input for the first optimization. The target graphic in the graphic to be optimized is then optimized according to a penalty function to obtain the first graphic. That is, during the first optimization process, only the target graphic in the graphic to be optimized is corrected, without needing to regenerate the auxiliary graphic. The operations for generating the auxiliary graphic include, but are not limited to, the following: performing continuous transmission mask calculation to generate a continuous transmission mask grayscale image; obtaining auxiliary graphic seeds based on the continuous transmission mask grayscale image; filling the auxiliary graphic seeds to form a free-form sub-resolution auxiliary graphic; and checking and correcting the free-form sub-resolution auxiliary graphic according to mask rules.

[0139] In the optimization process following step S605, the sub-resolution auxiliary graphics are only pre-set once. In subsequent iterative optimization processes, there is no need to regenerate the continuously transmitted mask grayscale image, nor is it necessary to pre-set the sub-resolution auxiliary graphics again. The computer can pre-place the qualified auxiliary graphics according to the auxiliary graphics placement rules obtained in step S607, thus obtaining the graphic to be optimized. The computer then directly acquires this graphic to be optimized and optimizes it, such as optimizing only the target graphics within the graphic to be optimized. In other embodiments, after the computer directly acquires the graphic to be optimized, the position and size of the auxiliary graphics within it can be optimized and adjusted, which also reduces the steps of generating auxiliary graphics and reduces the computational load.

[0140] In some embodiments, if the lithographic imaging quality corresponding to the first optimization meets the corresponding lithographic process conditions, a better process window line can be mass-produced through mask optimization, and an optimized and qualified light source and mask scheme can be output.

[0141] The following is a comparative experiment showing the use of existing light source mask optimization methods (without pre-set auxiliary patterns) and the method for light source mask optimization provided in the embodiments of this application (with pre-set auxiliary patterns). Please refer to [link / reference]. Figure 10 .

[0142] Experiment 1 was a baseline light source mask optimization experiment (without pre-set auxiliary graphics). The key graphics were selected by using diffraction order analysis to test the graphics. Twelve key graphics were selected to participate in the light source mask optimization calculation. The total running time was 1 hour and 38 minutes.

[0143] Experiment 2, based on the optimization results of Experiment 1, eliminated graphics that did not affect the process window, reducing the 12 key graphics in Experiment 1 to 7, leaving 7 graphics that truly constrained the process window as input for light source mask optimization. Building upon Experiment 1, light source mask optimization was again calculated and optimized for these 7 graphics that truly constrained the process window to find better light sources. The total runtime for the 7 key graphics was 58 minutes. Comparing Experiment 1 and Experiment 2, it was found that not only was the runtime reduced, but more specifically, after optimizing the light source mask for the graphics that truly constrained the process window, both the optimized light source mask and the optimized process window were larger than in Experiment 1. This demonstrates that the specially selected graphics in step S606 can improve efficiency and the process window size during optimization.

[0144] Experiment 3 is a new comparative experiment using the light source mask optimization method provided in the embodiments of this application, which pre-sets sub-resolution auxiliary graphics according to the placement rules of auxiliary graphics. Four of the seven graphics in Experiment 2 require the addition of sub-resolution auxiliary graphics. Based on the optimization results of Experiment 2, when the optimized lithography imaging quality meets the corresponding lithography process conditions, the size and placement position of the sub-resolution auxiliary graphics for these four graphics are extracted, yielding the placement rules for the auxiliary graphics corresponding to these four graphics. In Experiment 3, based on the placement rules for the auxiliary graphics corresponding to these four graphics, the corresponding sub-resolution auxiliary graphics are directly pre-set in these four graphics, resulting in four graphics to be optimized. This allows these four graphics to skip the steps related to generating auxiliary graphics, including continuous transmission mask calculation, during the light source mask optimization iteration, and directly enter the subsequent optimization iteration. Using this method, the running time of Experiment 3 is reduced from 58 minutes to 27 minutes compared to Experiment 2. In Experiment 3, the process window of the optimized light source mask and the optimized mask only decreased slightly compared to Experiment 2. The reason for the decrease is that the process window metric was not optimized. This process window metric can be understood as the parameter in the penalty function.

[0145] Experiment 4 serves as the control group for Experiment 3. Based on the optimization results of Experiment 2, Experiment 4 extracts the size and placement of sub-resolution auxiliary graphics for the four measured patterns when the optimized lithography imaging quality meets the corresponding lithography process conditions. This yields the placement rules for the auxiliary graphics corresponding to these four patterns. In Experiment 3, based on the placement rules for the auxiliary graphics corresponding to these four patterns, corresponding sub-resolution auxiliary graphics are directly pre-set in each of the four patterns, resulting in four patterns to be optimized. This allows these four patterns to skip the steps related to generating auxiliary graphics, including continuous transmission mask calculations, during the source mask optimization iteration, and directly proceed to subsequent optimization iterations. The difference between Experiment 4 and Experiment 3 lies in the modifications made to the parameters of source mask optimization (such as the parameters in the penalty function). Specifically, Experiment 4 optimizes the parameters limiting the process window (i.e., the parameters in the penalty function) to reduce the speed of source mask optimization while obtaining a larger process window after using pre-set sub-resolution auxiliary graphics. The results of Experiment 4 show that the runtime of Experiment 4 is slightly longer than that of Experiment 3, but still much shorter than that of Experiment 2, which did not use preset sub-resolution auxiliary graphics, and the process window can also be increased year by year.

[0146] Key parameters for optimizing the light source mask, such as those limiting the process window, can be improved by combining them with preset sub-resolution auxiliary graphics. This approach increases computation time slightly but further enhances the process window's performance. However, using preset sub-resolution auxiliary graphics significantly reduces runtime regardless of whether the parameters limiting the process window are optimized simultaneously.

[0147] This application provides a computer-readable storage medium containing computer-executable instructions for performing any of the methods described above.

[0148] While some exemplary embodiments of the inventive concept have been shown and described, one skilled in the art will understand that various modifications in form and detail may be made therein without departing from the spirit and scope defined by the appended claims. Therefore, the subject matter disclosed above should be understood as illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, alterations, and other embodiments falling within the essential spirit and scope of the inventive concept. Thus, the scope of the inventive concept is determined to the widest permissible interpretation of the appended claims and their equivalents to the fullest extent permitted by law, and such scope should not be limited or restricted by the above detailed description.

[0149] The descriptions of the processes corresponding to the above-mentioned figures each have their own emphasis. For parts of a process that are not described in detail, please refer to the relevant descriptions of other processes.

[0150] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. A computer program product for implementing license plate number recognition includes one or more computer instructions for performing license plate number recognition. When these computer program instructions are loaded and executed on a computer, all or part of the implementation according to the embodiments of this application is generated. Figure 3 , Figure 5 , Figure 6 The process or function.

[0151] The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another via wired (e.g., coaxial cable, fiber optic cable, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can access, or a data storage device such as a server or data center that integrates one or more available media. The available medium may be magnetic media (e.g., floppy disk, hard disk, magnetic tape), optical media (e.g., digital versatile disc (DVD)), or semiconductor media (e.g., solid-state disk (SSD)).

[0152] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0153] The above descriptions are embodiments provided in this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for light source mask optimization, characterized in that, The method comprises: acquiring a test pattern and a test light source; when detecting that the lithography imaging quality under the combination of the test light source and the test pattern meets the corresponding lithography process condition, acquiring an auxiliary pattern placement rule; obtaining a to-be-optimized pattern according to the auxiliary pattern placement rule and the test pattern; taking the to-be-optimized pattern as the input of a first optimization, and performing the first optimization on the to-be-optimized pattern to obtain a first pattern.

2. The method of claim 1, wherein, The taking the to-be-optimized pattern as the input of a first optimization, and performing the first optimization on the to-be-optimized pattern to obtain a first pattern comprises: taking the to-be-optimized pattern as the input of the first optimization; correcting a target pattern in the to-be-optimized pattern according to a penalty function to obtain the first pattern.

3. The method according to claim 1 or 2, characterized in that, The when detecting that the lithography imaging quality under the combination of the test light source and the test pattern meets the corresponding lithography process condition, acquiring an auxiliary pattern placement rule comprises: performing light source mask optimization on the test light source and the test pattern to obtain an optimized first light source and an optimized first mask pattern; performing first simulation evaluation on the first light source and the first mask pattern to obtain a first lithography imaging quality; when detecting that the first lithography imaging quality meets a first lithography process condition, performing mask optimization on the first light source and the test pattern to obtain a corresponding optimized second mask pattern; performing second simulation evaluation on the first light source and the second mask pattern to obtain a second lithography imaging quality; when detecting that the second lithography imaging quality meets a second lithography process condition, acquiring an auxiliary pattern placement rule to obtain the input of the first optimization based on the auxiliary pattern placement rule.

4. The method of claim 3, wherein, The taking the to-be-optimized pattern as the input of a first optimization, and performing the first optimization on the to-be-optimized pattern to obtain a first pattern comprises: taking the to-be-optimized pattern and the first light source as the input of the first optimization; performing the first optimization according to a penalty function, the first light source and a target pattern in the to-be-optimized pattern to obtain a first pattern.

5. The method according to any one of claims 1 to 4, characterized in that, The obtaining a to-be-optimized pattern according to the auxiliary pattern placement rule and the test pattern comprises: adding an auxiliary pattern in the test pattern according to the auxiliary pattern placement rule to obtain a to-be-optimized pattern.

6. The method according to any one of claims 1 to 4, characterized in that, The adding an auxiliary pattern in the test pattern according to the auxiliary pattern placement rule to obtain a to-be-optimized pattern comprises: acquiring a special selected pattern; wherein the special selected pattern is a pattern limiting the process window in the test pattern; adding an auxiliary pattern in the special selected pattern according to the auxiliary pattern placement rule to obtain a to-be-optimized pattern.

7. The method according to any one of claims 1 to 6, characterized in that, The auxiliary pattern placement rule comprises: the size of the auxiliary pattern, the distance between the auxiliary pattern and a target pattern, and the distance between the auxiliary patterns.

8. An electronic device, comprising: The electronic device comprises at least one processor, a memory, wherein The memory is configured to store instructions, and the processor is configured to execute the instructions to implement the method in any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a program, and the program causes the electronic device to execute the method in any one of claims 1 to 7.

10. A computer program product, characterised in that, The computer program product comprises computer readable instructions which, when executed by one or more processors, implement the method of any one of claims 1 to 7.

Images