Photodiode and method of manufacturing the same

Abstract

The embodiment of the present application provides a photodiode and a manufacturing method thereof, the photodiode comprising: a substrate; an N-type electrode contact layer on a first surface of the substrate; an absorption layer, a cap layer sequentially stacked on a second surface of the substrate; the first surface and the second surface being opposite surfaces; a first diffusion region and a second diffusion region both in the cap layer; a first semiconductor contact layer and a first P-type electrode contact layer both partially covering a surface of the first diffusion region; the first P-type electrode contact layer covering the first semiconductor contact layer; a second semiconductor contact layer and a second P-type electrode contact layer both partially covering a surface of the second diffusion region; the second P-type electrode contact layer covering the second semiconductor contact layer; and a diffusion barrier layer on the cap layer, together with the first P-type electrode contact layer, not completely covering the surface of the first diffusion region, and together with the second P-type electrode contact layer, completely covering the surface of the second diffusion region.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a photodiode and a manufacturing method thereof. BACKGROUND

[0002] Photodiodes can be classified into PN junction photodiodes, PIN (P type Intrinsic type N type Diodes) photodiodes, avalanche photodiodes (APD) and metal-semiconductor-metal (MSM) photodiodes. PIN photodiodes have been rapidly developed since the 1960s, and have the advantages of high energy resolution, short pulse rise time, high detection efficiency and stable performance when working at room temperature, and thus play an irreplaceable role in the fields of medical computed tomography (CT), luggage security inspection, container inspection, non-destructive testing of large industrial equipment, oil well logging, radioactive detection, environmental monitoring and the like. With the development of communication technology, PIN photodiodes are increasingly widely used in wavelength division multiplexing (WDM) channel monitoring, optical communication network monitoring, optical path protection monitoring, instrument and equipment optical path detection applications, which puts forward higher requirements on the response time of photodiodes to enable normal operation in high-speed data transmission systems.

[0003] However, photodiodes with fast response time used in such high-speed signal transmission are particularly susceptible to damage from electron static discharge (ESD) and dark current. SUMMARY

[0004] Therefore, an embodiment of the present application aims to provide a photodiode and a manufacturing method.

[0005] According to an aspect of the present application, a photodiode comprises:

[0006] a substrate;

[0007] an N-type electrode contact layer on a first surface of the substrate;

[0008] an absorption layer and a cap layer stacked in sequence on a second surface of the substrate; the first surface and the second surface are opposite surfaces;

[0009] a first diffusion region and a second diffusion region, both in the cap layer, the second diffusion region being used for charge discharge;

[0010] The first semiconductor contact layer and the first P-type electrode contact layer both partially cover the surface of the first diffusion region; the first P-type electrode contact layer covers the first semiconductor contact layer;

[0011] The second semiconductor contact layer and the second P-type electrode contact layer both partially cover the surface of the second diffusion region; the second P-type electrode contact layer covers the second semiconductor contact layer;

[0012] The diffusion barrier layer is located on the cap layer, and together with the first P-type electrode contact layer, does not completely cover the surface of the first diffusion region, and together with the second P-type electrode contact layer, completely covers the surface of the second diffusion region.

[0013] In the above scheme, the doping concentration of the second diffusion region is greater than or equal to the doping concentration of the first diffusion region.

[0014] In the above scheme, the second diffusion region is arranged around the first diffusion region.

[0015] In the above scheme, the photodiode further comprises: a transmittance enhancement layer located on the first diffusion region; the first semiconductor contact layer surrounds the transmittance enhancement layer; and the first P-type electrode contact layer partially covers the transmittance enhancement layer.

[0016] The distance between the edge of the transmittance enhancement layer and the edge of the first diffusion region is greater than a first preset value; the first preset value is 10 μm.

[0017] In the above scheme, the doping concentration of the absorption layer is less than a second preset value; the second preset value is 1e13 cm -3 .

[0018] In the above scheme, the photodiode further comprises a band gap layer,

[0019] The band gap layer is located between the absorption layer and the cap layer; the band gap layer has a band gap width greater than the band gap widths of the absorption layer and the cap layer.

[0020] In the above scheme, the material of the band gap layer comprises arsenic aluminum indium, the material of the absorption layer comprises arsenic gallium indium, and the material of the cap layer comprises indium phosphide.

[0021] In the above scheme, the photodiode further comprises a buffer layer, and the buffer layer is located between the substrate and the absorption layer.

[0022] According to another aspect of the present application, a method for manufacturing a photodiode comprises:

[0023] providing a substrate;

[0024] forming, on the second surface of the substrate, an absorption layer and a cap layer in sequence.

[0025] forming a first semiconductor contact layer and a second semiconductor contact layer on the cap layer; forming a diffusion barrier layer on the cap layer at a position between the first semiconductor contact layer and the second semiconductor contact layer;

[0026] forming a first diffusion region in the cap layer corresponding to the first semiconductor contact layer;

[0027] forming a second diffusion region in the cap layer corresponding to the second semiconductor contact layer; the second diffusion region is used for charge discharge;

[0028] forming a first P-type electrode contact layer partially covering a surface of the first diffusion region and covering the first semiconductor contact layer, and a second P-type electrode contact layer partially covering a surface of the second diffusion region and covering the second semiconductor contact layer;

[0029] forming an N-type electrode contact layer on a first surface of the substrate; the first surface and the second surface are opposite surfaces.

[0030] The method further includes:

[0031] forming a transparent material layer before forming the second diffusion region; the transparent material layer covers the diffusion barrier layer, the first semiconductor contact layer and part of the first diffusion region;

[0032] removing the transparent material layer on the first semiconductor contact layer after forming the second diffusion region, forming a transparent layer on the first diffusion region and forming an additional barrier layer on the diffusion barrier layer.

[0033] The photodiode provided by the embodiment of the present application includes: a substrate; an N-type electrode contact layer on a first surface of the substrate; an absorption layer, a cap layer and a second surface of the substrate are sequentially stacked; the first surface and the second surface are opposite surfaces; a first diffusion region and a second diffusion region are both in the cap layer, and the second diffusion region is used for charge discharge; a first semiconductor contact layer and a first P-type electrode contact layer both partially cover a surface of the first diffusion region; the first P-type electrode contact layer covers the first semiconductor contact layer; a second semiconductor contact layer and a second P-type electrode contact layer both partially cover a surface of the second diffusion region; the second P-type electrode contact layer covers the second semiconductor contact layer; and a diffusion barrier layer is on the cap layer, and together with the first P-type electrode contact layer, does not completely cover the surface of the first diffusion region, and together with the second P-type electrode contact layer, completely covers the surface of the second diffusion region. The photodiode provided by the embodiment of the present application effectively increases the area through which static electricity flows when static electricity is released, so that static electricity can be quickly released through the second diffusion region. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A schematic diagram of the implementation steps of a manufacturing method of a photodiode provided by an embodiment of the present application;

[0035] Figures 2a-2h A schematic diagram of the implementation steps of a manufacturing method of a photodiode provided by an embodiment of the present application;

[0036] Figures 3a-3c A top view of a photodiode provided by an embodiment of the present application. DETAILED DESCRIPTION

[0037] In order to make the technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be further described in detail below with reference to the drawings and embodiments. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation described herein. On the contrary, these implementations are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0038] The present application will be described in more detail by referring to the following paragraphs and the accompanying drawings. The advantages and features of the present application will be more apparent from the following description and claims. It should be noted that the drawings are very simplified and use non-precise proportions, only to facilitate, clearly assist the purpose of describing the embodiments of the present application.

[0039] It can be understood that the meanings of "on", "above" and "over" in the present application should be interpreted in the broadest way, so that "on" not only means the meaning of "on" with no intervening characteristics or layers between them (i.e. directly on something), but also includes the meaning of "on" with intervening characteristics or layers between them.

[0040] In addition, in order to facilitate the description, spatial relative terms such as "on", "above", "over", "upper", "top" and the like can be used herein to describe the relationship between one element or feature and another element or feature as shown in the drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptions used herein can also be interpreted accordingly.

[0041] In embodiments of the application, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can comprise a variety of semiconductor materials, such as silicon, germanium, arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as a glass, plastic, or sapphire substrate.

[0042] In embodiments of the application, the term "layer" refers to a portion of material that comprises a region having a thickness. A layer can extend over the entirety of an underlying or overlying structure, or can have an extent less than the underlying or overlying structure. Furthermore, a layer can be a region of a continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between a top surface and a bottom surface of a continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. A layer can extend horizontally, vertically, and / or along an inclined surface. A layer can comprise multiple sub-layers. For example, an interconnect layer can comprise one or more conductor and contact sub-layers (in which interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0043] In embodiments of the application, the terms "first", "second", and the like, do not necessarily have an ordinal or chronological significance.

[0044] It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0045] In the related art, the application of photodiodes including PIN photodiodes, avalanche diodes, etc. is to convert light into current signals, which requires fast response time to be able to operate in a high-speed data transmission system. The photodiodes with fast response time used in such high-speed signal transmission are particularly susceptible to damage from electrostatic discharge. Generally, the photodiode can be designed by adding capacitance and inductance in the package to increase the voltage and current threshold of electrostatic discharge. However, the photodiode in the optical splitter detector cannot be designed by adding capacitance and inductance to increase the voltage and current threshold of electrostatic discharge, and in application, the photodiode is required to have high voltage and current threshold of electrostatic discharge and low dark current performance, so it is necessary to improve the photodiode structure and preparation process.

[0046] Based on this, the photodiode provided by the embodiments of the present application effectively increases the area flowing through when the static charge is released, so that the static charge can be quickly released through the second diffusion region.

[0047] The embodiments of the present application provide a manufacturing method of a photodiode. Figure 1An implementation flowchart of a method for manufacturing a photodiode is provided for an embodiment of the present application. As shown in Figure 1 the method comprises the following steps:

[0048] Step 101, providing a substrate;

[0049] Step 102, sequentially forming a stacked absorption layer and a cap layer on a second surface of the substrate;

[0050] Step 103, forming a first semiconductor contact layer and a second semiconductor contact layer on the cap layer;

[0051] Step 104, forming a diffusion barrier layer on the cap layer at a position between the first semiconductor contact layer and the second semiconductor contact layer;

[0052] Step 105, forming a first diffusion region in the cap layer below the first semiconductor contact layer;

[0053] Step 106, forming a second diffusion region in the cap layer below the second semiconductor contact layer; the second diffusion region is used for charge discharge;

[0054] Step 107, forming a first P-type electrode contact layer partially covering a surface of the first diffusion region and covering the first semiconductor contact layer, and a second P-type electrode contact layer partially covering a surface of the second diffusion region and covering the second semiconductor contact layer;

[0055] Step 108, forming an N-type electrode contact layer on a first surface of the substrate; the first surface and the second surface are opposite surfaces.

[0056] Figures 2a-2h An implementation step cross-sectional view of a method for manufacturing a photodiode is provided for an embodiment of the present application. It should be understood that Figure 1 the operations shown in the figure are not exclusive, and other operations can be performed before, after or between any of the operations shown. The method for manufacturing a photodiode of the present embodiment will be described below in conjunction with Figure 1 , Figures 2a-2h .

[0057] It should be noted that the photodiode described in the embodiments of the present application includes but is not limited to a PIN photodiode.

[0058] Step 101 is performed to provide a substrate 1, which can include indium phosphorus (InP). The substrate 1 has a thickness greater than 150 μm.

[0059] In some embodiments, a buffer layer 2 is formed on the substrate 1 before step 102 is performed.

[0060] Here, the buffer layer 2 is used to solve the problems of lattice mismatch, hetero diffusion and polarity when growing a semiconductor on a hetero substrate, and also facilitates the transport of carriers.

[0061] In some embodiments, the material of the buffer layer 2 can include InP, the doping concentration of the buffer layer 2 can range from 1e17cm -3 -1.5e17cm -3 , and the thickness of the buffer layer 2 can range from 1.0 μm to 2.0 μm.

[0062] In some embodiments, the buffer layer 2 can be formed by a deposition process. The deposition process includes, but is not limited to, chemical vapor deposition.

[0063] Step 102 is performed to sequentially form a stacked absorption layer 3 and a cap layer 5 on the second surface of the substrate 1, obtaining an epitaxial wafer 100, as shown in Figure 2a It can be understood that when the buffer layer 2 is formed on the substrate 1, the absorption layer 3 and the cap layer 5 are formed on the buffer layer 2.

[0064] Here, the cap layer 5 is used to receive incident light and transmit the incident light to the absorption layer 3, where the incident light is converted into electrons.

[0065] Research shows that the dark current includes diffusion current and recombination current, and the size of the diffusion current and the recombination current is proportional to the intrinsic carrier concentration. The higher the carrier concentration, the greater the dark current. Experimental data show that when the intrinsic semiconductor has a doping concentration of 1e15cm -3 , 1e14cm -3 , and 1e13cm -3 , respectively, the dark current is 0.1 nA, 0.01 nA, and less than 0.01 nA, respectively, under a reverse voltage of 5 V. That is, the dark current can be reduced by reducing the doping concentration of the intrinsic semiconductor.

[0066] Based on this, in some embodiments, the method further includes that the doping concentration of the absorption layer 3 is less than a second preset value; and the second preset value is 1e13cm -3 .

[0067] In some embodiments, the material of the absorption layer 3 can include indium gallium arsenide (InGaAs), and the thickness of the absorption layer 3 can range from 1.0 μm to 3.5 μm.

[0068] In some embodiments, the material of the cap layer 5 can include InP, the doping concentration of the cap layer 5 is less than 5e15cm -3 , and the thickness of the cap layer 5 can range from 0.5 μm to 1.5 μm.

[0069] In some embodiments, the absorbing layer 3 and the cap layer 5 can be formed by a deposition process. The deposition process includes, but is not limited to, chemical vapor deposition.

[0070] It has been found that the diffusion current and the recombination current are related to the band gap of the material in the photodiode. The wider the band gap of the material, the more energy required for the electron to jump from the valence band to the conduction band, and the smaller the dark current. That is, the dark current can be reduced by setting a band gap layer with a material having a larger band gap value.

[0071] Based on this, in some embodiments, the method further comprises: forming a band gap layer 4 between the absorbing layer 3 and the cap layer 5; the band gap layer 4 has a band gap larger than that of the absorbing layer 3 and the cap layer 5.

[0072] In some embodiments, the material of the band gap layer 4 can include indium aluminum arsenide (InAlAs), the material of the absorbing layer can include InGaAs, and the material of the cap layer 5 can include indium phosphide.

[0073] Here, the band gap of the material of the band gap layer 4 is as wide as possible, and its lattice constant is as matched as possible to the contacting material to reduce the stress between different materials.

[0074] In some embodiments, the doping concentration of the band gap layer 4 can be less than or equal to 5e15cm -3 The thickness of the band gap layer 4 can range from 0.5μm to 1.0μm.

[0075] In some embodiments, the band gap layer 4 can be formed by a deposition process. The deposition process includes, but is not limited to, chemical vapor deposition.

[0076] In some embodiments, a contact layer 6 is formed on the cap layer 5 before step 103 is performed.

[0077] Here, the contact layer 6 can form a better ohmic contact with the metal.

[0078] In some embodiments, the material of the contact layer 6 can include InGaAs, the doping concentration of the contact layer 6 can be greater than or equal to 1e19cm -3 The thickness of the contact layer 6 can range from 0.05μm to 0.2μm.

[0079] In some embodiments, the contact layer 6 can be formed by a deposition process. The deposition process includes, but is not limited to, chemical vapor deposition. Step 103 is performed to form the first semiconductor contact layer 7 and the second semiconductor contact layer 8 on the cap layer 5, as shown in FIG. 1C. Figure 2b The contact layer 6 is formed with trenches to divide the contact layer 6 into the first semiconductor contact layer 7 and the second semiconductor contact layer 8.

[0080] In some embodiments, the first semiconductor contact layer 7 and the second semiconductor contact layer 8 can be formed by photolithography and chemical etching. The contact layer 6 is subjected to photolithography and chemical etching to form the first semiconductor contact layer 7 and the second semiconductor contact layer 8.

[0081] In some embodiments, the first semiconductor contact layer 7 is annular, and the second semiconductor contact layer 8 is located on both sides of the first semiconductor contact layer 7, as shown in FIG. 1D. Figure 3a

[0082] In some embodiments, the first semiconductor contact layer 7 is annular, and the second semiconductor contact layer 8 is separately surrounded around the first semiconductor contact layer 7, as shown in FIG. 1E. Figure 3b

[0083] In some embodiments, the first semiconductor contact layer 7 is annular, and the second semiconductor contact layer 8 is annular and surrounds the first semiconductor contact layer 7, as shown in FIG. 1F. Figure 3c

[0084] Here, the annular first semiconductor contact layer 7 formed in the middle position serves as an incident window for optical signals. The first semiconductor contact layer 7 and the second semiconductor contact layer 8 can form a good ohmic contact with the metal electrode layer.

[0085] It can be understood that the annular second semiconductor contact layer 8 surrounding the first semiconductor contact layer 7 is advantageous to provide a larger ohmic contact area.

[0086] Step 104 is performed to form a diffusion barrier layer 9 on the cap layer 5 at a position between the first semiconductor contact layer 7 and the second semiconductor contact layer 8, as shown in FIG. 1G. Figure 2c

[0087] Here, the diffusion barrier layer 9 can provide a barrier for ion implantation and other processes.

[0088] In some embodiments, the diffusion barrier layer 9 can be deposited by plasma enhanced chemical vapor deposition (PECVD).​​​​

[0089] In some embodiments, the diffusion barrier layer 9 can be silicon nitride (SiNx), and the thickness of the diffusion barrier layer 9 can range from 1000A to 2000A.

[0090] In step 105, a first diffusion region 10 is formed in the cap layer 5 below the first semiconductor contact layer 7, as shown in FIG. 1C. Figure 2c The projection of the first semiconductor contact layer 7 is within the projection of the first diffusion region 10, and the projected area of the first diffusion region 10 is larger than the projected area of the first semiconductor contact layer 7, as shown in FIG. 1C. Figure 3a

[0091] Here, the incident light enters the absorption layer from the surface of the first diffusion region that is not covered by the first P-type electrode contact layer, and is converted into electrons in the absorption layer.

[0092] In some embodiments, the doping concentration of the first diffusion region can range from 1e17cm -3 to 1e18cm -3 , and the thickness of the first diffusion region can be the same as the thickness of the cap layer.

[0093] In some embodiments, the first diffusion region can be formed by an open tube zinc (Zn) diffusion process. Specifically, after the diffusion barrier layer 9 covers the first semiconductor contact layer 7 and the second semiconductor contact layer 8, the diffusion barrier layer 9 can be processed by a photolithography and etching process to expose the first semiconductor contact layer 7, and then an open tube zinc (Zn) diffusion process can be used to dope the cap layer 5 at the middle position of the first semiconductor contact layer 7 to form a P-type first diffusion region 10.

[0094] In some embodiments, before step 105 is performed, a layer of antireflection material 11 is formed, as shown in FIG. 1D. Figure 2d The antireflection material 11 covers the surfaces of the diffusion barrier layer 9, the first semiconductor contact layer 7, and the first diffusion region 10.

[0095] Here, the antireflection material layer 11 also has the functions of diffusion barrier and passivation, and the antireflection material layer 11 has an antireflection function. In some embodiments, the antireflection material layer 11 can be antireflection for light with a wavelength of 1.55μm or 1.31μm.

[0096] In some embodiments, the antireflection material layer 11 can be a single layer of silicon nitride film or silicon oxide film, and the thickness of the antireflection material layer 11 can range from 1000A to 2000A.

[0097] ​In some embodiments, the antireflection material layer 11 can be formed by a deposition process. The deposition process includes, but is not limited to, chemical vapor deposition.

[0098] It can be understood that the photodiode herein receives the light signal through the first diffusion region 10 under the first semiconductor contact layer 7, and transmits the light signal to the absorption layer 3 to generate a photo current. The antireflection layer 13 formed by the subsequent processing of the antireflection material layer 11 by photolithography and etching reduces the reflection of the incident light, effectively reducing the energy loss.

[0099] In some embodiments, the photodiode further comprises: an antireflection layer on the first diffusion region; the first semiconductor contact layer surrounds the antireflection layer; and the first P-type electrode contact layer partially covers the antireflection layer.

[0100] The distance between the edge of the first semiconductor contact layer away from the edge of the antireflection layer and the edge of the first diffusion region is greater than a first preset value; and the first preset value is 10 μm.

[0101] In some embodiments, the antireflection layer 13 can be formed by photolithography and etching on the antireflection material layer 11.

[0102] In some embodiments, the distance between the edge of the antireflection layer 13 and the edge of the first diffusion region can range from 10 μm to 15 μm.

[0103] It can be understood that, in general, the distance between the edge of the antireflection layer 13 and the edge of the first diffusion region 8 ranges from 2 μm to 3 μm, and a larger distance range is more conducive to the lateral expansion of the current, avoiding the excessive concentration of the current at a certain point of the first diffusion region, resulting in excessive current and thus damaging the first diffusion region, and reducing the influence of electrostatic discharge on the photodiode.

[0104] Step 106 is performed, as shown in FIG. 6, a second diffusion region 12 is formed in the cap layer corresponding to the second semiconductor contact layer 8. Figure 2e

[0105] Here, the second diffusion region 12 is used for charge discharge. It can be understood that the second contact layer 8 partially covers the second diffusion region 12, and the part of the second diffusion region 12 not covered by the second contact layer 8 is covered by the blocking layer 9, so that light can only enter the absorption layer 3 through the part of the first diffusion region 10 not covered by the first contact layer 7, and cannot enter the absorption layer 3 through the second diffusion region 12.

[0106] In some embodiments, the doping concentration of the second diffusion region 12 can be greater than or equal to 3e18cm-3.​-3 The second diffusion region 12 can have the same thickness as the cap layer 5.

[0107] In some embodiments, the second diffusion region 12 can be formed by a molybdenum-zinc (MO-Zn) diffusion process. Specifically, the second semiconductor contact layer 8 is exposed by performing a photoetching and etching process on the antireflection material layer 11, and a window is formed in the barrier diffusion layer 9 and the antireflection material layer 11. The cap layer under the window in the antireflection material layer 11 can be doped to form a P-type second diffusion region 12 by a molybdenum-zinc (MO-Zn) diffusion process.

[0108] In some embodiments, the second diffusion region 12 is located on both sides of the first diffusion region 10, the projection area of the second semiconductor contact layer 8 is within the projection area of the second diffusion region 12, and the projection area of the second semiconductor contact layer 8 is smaller than the projection area of the second diffusion region 12, as shown in FIG. 2B. Figure 3a

[0109] In some embodiments, the second diffusion region 12 is located on both sides of the first diffusion region 10, the projection area of the second semiconductor contact layer 8 is within the projection area of the second diffusion region 12, and the projection area of the second semiconductor contact layer 8 is smaller than the projection area of the second diffusion region 12, as shown in FIG. 2B. Figure 3b

[0110] In some embodiments, the second diffusion region 12 is located on both sides of the first diffusion region 10, the projection area of the second semiconductor contact layer 8 is within the projection area of the second diffusion region 12, and the projection area of the second semiconductor contact layer 8 is smaller than the projection area of the second diffusion region 12, as shown in FIG. 2B. Figure 3c

[0111] In some embodiments, the doping concentration of the second diffusion region 12 is greater than or equal to the doping concentration of the first diffusion region 10.

[0112] Here, the second diffusion region 12 has a high doping concentration, and the static electricity accumulated on the surface of the photodiode is discharged through the second diffusion region 12.

[0113] ​​​It can be understood that when the doping concentration of the second diffusion region 12 is higher than that of the first diffusion region 10, the resistivity of the second diffusion region 12 is smaller than that of the first diffusion region 10. Since the second diffusion region 12 and the first diffusion region 10 are arranged in parallel, the voltage across the second diffusion region 12 is equal to the voltage across the first diffusion region 10, that is, the second diffusion region effectively clamps the voltage across the first diffusion region, and at the same time, the resistance of the second diffusion region is smaller than that of the first diffusion region, so most of the static electricity charges pass through the second diffusion region 12 and then enter the band gap layer 4, the absorption layer 3, the buffer layer 2 and the substrate 1, and the electrode on the substrate is grounded, thereby releasing the static electricity charges through this path. As can be seen, the second diffusion region provides a discharge path for the static electricity charges on the surface of the photodiode, thereby avoiding damage to the photodiode due to electrostatic discharge.

[0114] In some embodiments, before step 106 is performed, a ring-shaped contact via is formed on the first contact layer 7. In some specific embodiments, the antireflection layer 13 can be formed by removing the antireflection material layer 11 on the first semiconductor contact layer 7 through a photolithography and etching process, as shown in Figure 2f .

[0115] Here, the antireflection layer 13 reduces the energy loss of incident light and improves the performance of the photodiode.

[0116] Step 107 is performed to form a first P-type electrode contact layer 14 partially covering the surface of the first diffusion region and covering the first semiconductor contact layer 7, and a second P-type electrode contact layer 15 partially covering the surface of the second diffusion region 12 and covering the second semiconductor contact layer 8. As shown in Figure 2g .

[0117] Here, the first P-type electrode contact layer 14 partially covers the surface of the first diffusion region 10 and covers the first semiconductor contact layer 7, and the first diffusion region 10 has the antireflection layer 13, which provides an entrance for incident light to enter from the antireflection layer 13, and through the entrance, light energy is transmitted into the absorption layer 3 to complete photoelectric conversion. The second P-type electrode contact layer 15 partially covers the surface of the second diffusion region 12 and covers the second semiconductor contact layer 8, and light cannot enter the absorption layer 3 through the second diffusion region 12.

[0118] In some specific embodiments, the material of the first P-type electrode contact layer 14 can be titanium (Ti), platinum (Pt) or gold (Au), and in practical applications, the thickness of the first P-type electrode contact layer 14 can be in the range of about for Ti, about Au is about 1000 A

[0119] In some embodiments, a second P-type electrode contact layer 15 is formed in the annular via on the second semiconductor contact layer 8. The material of the second P-type electrode contact layer 15 can be Ti, Pt or Au. In practical applications, the thickness of the second P-type electrode contact layer 15 can range from about 100 A to about 1000 A. The thickness of Pt is about 1000 A The thickness of Au is about 1000 A

[0120] In some embodiments, an electrode 17 is formed on the first P-type electrode contact layer 14 and the second P-type electrode contact layer 15. The material of the electrode 17 can be Ti, Pt or Au. The thickness of the electrode 17 can range from about 100 A to about 1000 A. The thickness of Pt is about 1000 A The thickness of Au is about 1000 A

[0121] Here, the electrode 17 connects the photodiode to the outside.

[0122] In some embodiments, the epitaxial wafer 100 is polished before step 108 is performed.

[0123] In some embodiments, the epitaxial wafer 100 is polished by chemical mechanical polishing (CMP). The thickness of the epitaxial wafer 100 after polishing can range from about 130 μm to about 170 μm.

[0124] In step 108, an N-type electrode contact layer is formed on the first surface of the substrate. The first surface and the second surface are opposite to each other. As shown in Figure 2h .

[0125] In some embodiments, the N-type electrode contact layer is formed by a sputtering process. The sputtering process includes but is not limited to magnetron sputtering.

[0126] In some embodiments, the material of the N-type electrode contact layer 16 can be Ti, Pt or Au. The thickness of the N-type electrode contact layer 16 can range from about 100 A to about 1000 A. The thickness of Pt is about 1000 A The thickness of Au is about 1000 A

[0127] In some embodiments, the method further comprises cleaving the epitaxial wafer 100 along a crystal direction to obtain a single photodiode die.

[0128] The embodiment of the present application provides a photodiode and a manufacturing method thereof, the photodiode comprises: a substrate; an N-type electrode contact layer located on a first surface of the substrate; an absorption layer, a cap layer sequentially stacked on a second surface of the substrate; the first surface and the second surface are opposite surfaces; a first diffusion region and a second diffusion region are both located in the cap layer, and the second diffusion region is used for charge discharge; a first semiconductor contact layer and a first P-type electrode contact layer both partially cover a surface of the first diffusion region; the first P-type electrode contact layer covers the first semiconductor contact layer; a second semiconductor contact layer and a second P-type electrode contact layer both partially cover a surface of the second diffusion region; the second P-type electrode contact layer covers the second semiconductor contact layer; and a diffusion barrier layer is located on the cap layer, and together with the first P-type electrode contact layer, does not completely cover the surface of the first diffusion region, and together with the second P-type electrode contact layer, completely covers the surface of the second diffusion region. The photodiode provided by the embodiment of the present application firstly increases the area through which static electricity flows by arranging the second diffusion region, so that the static electricity can be quickly discharged through the second diffusion region; at the same time, the first diffusion region and the second diffusion region are arranged in parallel during static electricity discharge, so that the voltage at both ends of the second diffusion region is equal to the voltage at both ends of the first diffusion region, the second diffusion region effectively clamps the voltage at both ends of the first diffusion region, and the voltage at both ends of the first diffusion region is not too large to cause breakdown. Furthermore, the distance between the projection of the first semiconductor contact layer in the first P-type contact layer on the first diffusion region away from the edge of the antireflection layer and the edge of the first diffusion region is increased, the distance between the electrode and the edge of the diffusion region is larger, which is more conducive to the lateral expansion of the current, the current expands laterally, avoids the excessive concentration of the current at a certain point of the first diffusion region, and reduces the damage to the first diffusion region, thereby reducing the influence of electrostatic discharge on the photodiode. Finally, on one hand, the dark current is reduced by reducing the doping concentration of the absorption layer, and the smaller the doping concentration is, the smaller the dark current is; on the other hand, the dark current is reduced by arranging a band gap layer between the absorption layer and the cap layer, and the larger the band gap width value of the band gap layer is, the smaller the dark current is.

[0129] According to another aspect of the present disclosure, the embodiment of the present disclosure further provides a photodiode, comprising:

[0130] a substrate;

[0131] an N-type electrode contact layer located on a first surface of the substrate;

[0132] an absorption layer, a cap layer sequentially stacked on a second surface of the substrate; the first surface and the second surface are opposite surfaces;

[0133] a first diffusion region and a second diffusion region are both located in the cap layer, and the second diffusion region is used for charge discharge;

[0134] a first semiconductor contact layer and a first P-type electrode contact layer, both partially covering a surface of the first diffusion region; the first P-type electrode contact layer covering the first semiconductor contact layer;

[0135] a second semiconductor contact layer and a second P-type electrode contact layer, both partially covering a surface of the second diffusion region; the second P-type electrode contact layer covering the second semiconductor contact layer;

[0136] a diffusion barrier layer on the cap layer, together with the first P-type electrode contact layer, partially covering the surface of the first diffusion region, and together with the second P-type electrode contact layer, completely covering the surface of the second diffusion region.

[0137] In some embodiments, the second diffusion region has a doping concentration greater than or equal to that of the first diffusion region.

[0138] In some embodiments, the second diffusion region surrounds the first diffusion region.

[0139] In some embodiments, the photodiode further comprises: a transmittance enhancement layer on the first diffusion region; the first semiconductor contact layer surrounds the transmittance enhancement layer; and the first P-type electrode contact layer partially covers the transmittance enhancement layer.

[0140] The first semiconductor contact layer is away from the edge of the transmittance enhancement layer by a distance greater than a first preset value; the first preset value is 10 μm.

[0141] In some embodiments, the absorption layer has a doping concentration less than a second preset value; the second preset value is 1e13 cm -3 .

[0142] In some embodiments, the photodiode further comprises a bandgap layer,

[0143] The bandgap layer is between the absorption layer and the cap layer; the bandgap layer has a bandgap width greater than that of the absorption layer and the cap layer.

[0144] In some embodiments, the bandgap layer comprises arsenic-aluminum-indium, the absorption layer comprises arsenic-gallium-indium, and the cap layer comprises indium phosphide.

[0145] In some embodiments, the photodiode further comprises a buffer layer between the substrate and the absorption layer.

[0146] Here, the photodiode is formed by the method for forming a photodiode according to any one of the above embodiments. The layers included in the photodiode are described in detail in the above embodiments, and thus a detailed description thereof will not be repeated here.

[0147] In several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-targeted manner. The device embodiments described above are merely illustrative, for example, the division of the units is merely a logical functional division, and actual implementation can have another division manner, for example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling between the components shown or discussed.

[0148] The disclosed features in several method or device embodiments provided in the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments or device embodiments.

[0149] The specific embodiments of the present disclosure are described above, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A photodiode, characterized by, The photodiode comprises: a substrate; an N-type electrode contact layer on a first surface of the substrate; an absorbing layer and a cap layer sequentially stacked on a second surface of the substrate; the first surface and the second surface are opposite to each other; a first diffusion region and a second diffusion region, both in the cap layer, the second diffusion region is used for charge discharge; a first semiconductor contact layer and a first P-type electrode contact layer, both partially covering a surface of the first diffusion region; the first P-type electrode contact layer covers the first semiconductor contact layer; a second semiconductor contact layer and a second P-type electrode contact layer, both partially covering a surface of the second diffusion region; the second P-type electrode contact layer covers the second semiconductor contact layer; a diffusion barrier layer on the cap layer, together with the first P-type electrode contact layer, not completely covering the surface of the first diffusion region, and together with the second P-type electrode contact layer, completely covering the surface of the second diffusion region.

2. The photodiode of claim 1, wherein, The doping concentration of the second diffusion region is greater than or equal to the doping concentration of the first diffusion region.

3. The photodiode of claim 1, wherein, The second diffusion region surrounds the first diffusion region.

4. The photodiode of claim 1, wherein, The photodiode further comprises: an anti-reflection layer on the first diffusion region; the first semiconductor contact layer surrounds the anti-reflection layer; and the first P-type electrode contact layer partially covers the anti-reflection layer. The distance between the edge of the anti-reflection layer away from the first semiconductor contact layer and the edge of the first diffusion region is greater than a first preset value; the first preset value is 10 μm.

5. The photodiode of claim 1, wherein: The doping concentration of the absorption layer is less than a second preset value; the second preset value is 1e13 cm -3 .

6. The photodiode of claim 1, wherein, the photodiode further comprises a bandgap layer, the bandgap layer is between the absorbing layer and the cap layer; the bandgap layer has a bandgap width greater than the bandgap width of the absorbing layer and the cap layer.

7. The photodiode of claim 6, wherein, The material of the bandgap layer comprises arsenic aluminum indium, the material of the absorbing layer comprises arsenic gallium indium, and the material of the cap layer comprises indium phosphide.

8. The photodiode of claim 1, wherein, The photodiode further comprises a buffer layer between the substrate and the absorbing layer.

9. A method of manufacturing a photodiode, characterized by, The method comprises: providing a substrate; sequentially forming an absorbing layer and a cap layer on a second surface of the substrate; forming a first semiconductor contact layer and a second semiconductor contact layer on the cap layer; forming a diffusion barrier layer on the cap layer at a position between the first semiconductor contact layer and the second semiconductor contact layer; forming a first diffusion region below the first semiconductor contact layer in the cap layer; forming a second diffusion region below the second semiconductor contact layer in the cap layer; the second diffusion region is used for charge discharge; forming a first P-type electrode contact layer partially covering a surface of the first diffusion region and covering the first semiconductor contact layer, and a second P-type electrode contact layer partially covering a surface of the second diffusion region and covering the second semiconductor contact layer; forming an N-type electrode contact layer on a first surface of the substrate; the first surface and the second surface are opposite to each other.

10. The method of fabricating a photodiode according to claim 9, wherein The method further comprises: before forming the second diffusion region, forming an anti-reflection material layer; the anti-reflection material layer covers the diffusion barrier layer, the first semiconductor contact layer, and part of the first diffusion region; After forming the second diffusion region, the antireflective material layer on the first semiconductor contact layer is removed, an antireflective layer is formed on the first diffusion region and an additional barrier layer is formed on the diffusion barrier layer.

Images