High dynamic range cmos image sensor pixel and imaging system

Abstract

The present disclosure relates to high dynamic range CMOS image sensor pixels with reduced metal-insulator-metal lateral overflow integrated capacitor latency. A pixel circuit includes a photodiode configured to photo generate image charge in response to incident light. A transfer transistor is configured to transfer the image charge from the photodiode to a floating diffusion region. A reset transistor is coupled between a reset voltage source and the floating diffusion region. A lateral overflow integrated capacitor (LOFIC) includes an insulating region disposed between a first metal electrode and a second metal electrode. The first metal electrode is coupled to a bias voltage source, the second metal electrode is selectively coupled to the floating diffusion region, and excess image charge photo generated by the photodiode during an idle period is configured to overflow from the photodiode into the floating diffusion region through the transfer transistor.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to image sensors, and in particular, but not exclusively, to high dynamic range (HDR) complementary metal-oxide-semiconductor (CMOS) image sensors. BACKGROUND

[0002] Image sensors have become ubiquitous and are now widely used in digital cameras, cell phones, surveillance cameras, and in medical, automotive, and other applications. As image sensors are integrated into a wider range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many aspects as possible (e.g., resolution, power consumption, dynamic range, etc.) through device architecture design and image acquisition processing. The technology for manufacturing image sensors continues to rapidly evolve. For example, the demand for higher resolution and lower power consumption encourages further miniaturization and integration of these devices.

[0003] A typical complementary metal-oxide-semiconductor (CMOS) image sensor operates in response to image light from an external scene incident on the image sensor. The image sensor includes an array of pixels having a light-sensitive element (e.g., a photodiode) that absorbs a portion of the incident image light and photo-generates image charge after absorbing the image light. The image charge photo-generated by the pixel is measurable as an analog output image signal on a column bit line, which varies with the incident image light. In other words, the amount of photo-generated image charge is proportional to the intensity of the image light, which is read out from the column bit line as an analog signal and converted to a digital value to produce a digital image (i.e., image data) representing the external scene.

[0004] Standard image sensors have a limited dynamic range of about 60 to 70 dB. However, the luminance dynamic range of real-world scenes is much greater. For example, natural scenes often span a range of 90 dB or more. To capture details in both bright highlights and dim shadows simultaneously, high dynamic range (HDR) techniques have been used in image sensors to increase the captured dynamic range. One common technique to increase the dynamic range is to merge multiple exposures captured with a standard (low dynamic range) image sensor at different exposure settings into a single linear HDR image, which results in a much greater dynamic range image than a single exposure image. SUMMARY

[0005] Embodiments of the present disclosure provide a pixel circuit comprising: a photodiode configured to photo generate image charges during a response to incident light; a floating diffusion region coupled to receive the image charges; a transfer transistor coupled between the photodiode and the floating diffusion region, wherein the transfer transistor is configured to transfer the image charges from the photodiode to the floating diffusion region; a reset transistor coupled between a reset voltage source and the floating diffusion region, wherein the reset transistor is configured to switch in response to a reset control signal; and a lateral overflow integrated capacitor (LOFIC) comprising an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to a bias voltage source, wherein the second metal electrode is selectively coupled to the floating diffusion region, wherein excess image charges photo generated by the photodiode during an idle period are configured to overflow from the photodiode into the floating diffusion region through the transfer transistor.

[0006] Another embodiment of the present disclosure provides an imaging system comprising: a pixel array comprising a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits comprises: a photodiode configured to photo generate image charges in response to incident light; a floating diffusion region coupled to receive the image charges; a transfer transistor coupled between the photodiode and the floating diffusion region, wherein the transfer transistor is configured to transfer the image charges from the photodiode to the floating diffusion region; a reset transistor coupled between a reset voltage source and the floating diffusion region, wherein the reset transistor is configured to switch in response to a reset control signal; and a lateral overflow integrated capacitor (LOFIC) comprising an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to a bias voltage source, wherein the second metal electrode is selectively coupled to the floating diffusion region, wherein excess image charges photo generated by the photodiode during an idle period are configured to overflow from the photodiode into the floating diffusion region through the transfer transistor, wherein the idle period occurs before a pre-charge period, the pre-charge period occurs before an integration period, the integration period occurs before a readout period; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to read out image data from the plurality of pixel circuits. BRIEF DESCRIPTION OF DRAWINGS

[0007] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views.

[0008] Figure 1An example of an imaging system including a pixel array is illustrated in accordance with the teachings of this disclosure.

[0009] Figure 2A A schematic diagram of an example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during an integration period in accordance with the teachings of this disclosure is illustrated.

[0010] Figure 2B A diagram representing a cross-section of an example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during an integration period in accordance with the teachings of this disclosure is illustrated.

[0011] Figure 2C A schematic diagram of an example of a pixel circuit including a LOFIC during a pre-charge period in accordance with the teachings of this disclosure is illustrated.

[0012] Figure 2D A schematic diagram of an example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during an integration period in accordance with the teachings of this disclosure is illustrated.

[0013] Figure 2E A diagram representing a cross-section of an example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during an integration period in accordance with the teachings of this disclosure is illustrated.

[0014] Figure 3 An example of a timing diagram of example signal values in an example pixel circuit including a LOFIC during idle, pre-charge, integration, and readout periods in accordance with the teachings of this disclosure is illustrated.

[0015] Figure 4A A schematic diagram of another example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during an idle period in accordance with the teachings of this disclosure is illustrated.

[0016] Figure 4B A schematic diagram of another example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during an integration period in accordance with the teachings of this disclosure is illustrated.

[0017] Figure 5A A schematic diagram of yet another example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during an idle period in accordance with the teachings of this disclosure is illustrated.

[0018] Figure 5B A schematic diagram of yet another example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during a pre-charge period in accordance with the teachings of this disclosure is illustrated.

[0019] Figure 5CA timing diagram illustrating example signal values in another example pixel circuit including a lateral overflow integrated capacitor (LOFIC) during an integration period in accordance with the teachings of this disclosure.

[0020] Figure 6 A timing diagram illustrating one example of example signal values in another example pixel circuit including a LOFIC during idle, pre-charge, integration, and readout periods in accordance with the teachings of this disclosure.

[0021] Corresponding reference characters indicate corresponding components throughout the drawings. Skilled artisans will appreciate that the elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures can be exaggerated relative to other elements to help to improve understanding of various embodiments of the present application. Also, common but well-understood elements that are useful in a commercially feasible embodiment often are not depicted in order to facilitate a less obstructed view of these various embodiments of the present application. DETAILED DESCRIPTION

[0022] Described herein relate to examples of imaging systems having a pixel array including pixel circuits having LOFICs that provide reduced image lag. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the technology described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring certain aspects.

[0023] Reference throughout this specification to "one example" or "an example" means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present application. Thus, the appearances of the phrases "in one example" or "in one embodiment" in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more examples.

[0024] For ease of description, spatially relative terms, such as "below", "beneath", "above", "on", "upon", "top", "bottom", "left", "right", "center", "intermediate", and the like, can be used herein for describing an element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over or rotated, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Additionally, it will be understood that, when a element is referred to as being "between" two other elements, it can be the only element between the two other elements or one or more other elements can also be present between the two other elements.

[0025] In this specification, several technical terms are used. Such terms are to take their ordinary meaning in the field of the specification unless specifically redefined herein or the context of their use clearly dictates otherwise. It is noted that element names and symbols can be used interchangeably in this document (e.g., Si and silicon); however, both have the same meaning.

[0026] As will be discussed, various examples of imaging systems include pixel arrays having pixel circuits that include lateral overflow integrated capacitors (LOFICs) configured to provide reduced image lag. It will be appreciated that LOFICs can be included in pixel circuits to increase the full well capacity of the pixel circuits and thereby increase the high dynamic range capability of the corresponding image sensor. LOFIC capacitance is directly related to full well capacity. Thus, as the capacitance of a LOFIC employed in a pixel circuit increases, the full well capacity of the pixel circuit also increases. For this reason, higher LOFIC capacitance is generally desirable. However, due to the large RC load as the capacitance of the LOFIC increases, the time required for a row driver of the imaging system to charge and / or reset the LOFIC also increases. Thus, as the capacitance of a LOFIC in a pixel circuit increases, image lag increases, which results in slower frame rates.

[0027] It will be appreciated that image lag resulting from LOFICs can be associated with high dielectric constant or high-k materials included in the insulating material of a metal-insulator-metal (MIM) LOFIC due to the hysteresis characteristics and slow relaxation behavior of high-k materials requiring long discharge times (e.g., hundreds of milliseconds). The high-k material relaxation behavior can result in degraded image quality, such as image lag, due to a number of mechanisms including trap-to-trap tunneling, structural relaxation, coupling with phonon energy, etc.

[0028] In accordance with the teachings of this disclosure, when the readout speed of the image sensor and the frame readout speed are fixed, it is appreciated that the pixel circuit including the LOFIC can be configured such that during the idle period, any photo-generated charge does not overflow and is stored in the LOFIC and is reset during the pre-charge period to reduce image lag. Thus, as will be shown in various examples below, an example pixel circuit includes a photodiode configured to photo- generate image charge in response to incident light. A floating diffusion region is coupled to receive the image charge from the photodiode. In one example, a reset transistor is coupled between a bias voltage source and the floating diffusion region. In another example, a reset transistor is coupled between a reset voltage source and the floating diffusion region. The reset transistor is configured to switch in response to a reset control signal. The pixel circuit also includes a LOFIC that provides additional storage capacity, which is configured to store image charge for high dynamic range (HDR) image acquisition.

[0029] In various examples, the LOFIC is a metal-insulator-metal (MIM) storage capacitor including a high-k insulating region disposed between a first metal electrode and a second metal electrode. In various examples, the first metal electrode is coupled to a bias voltage source and the second metal electrode is locally coupled to the reset transistor through one or more circuit elements of the pixel circuit including the floating diffusion region of the pixel circuit. In various examples, the reset transistor is turned on to locally couple both the first metal electrode and the second metal electrode of the LOFIC to the same bias voltage from the bias voltage source through the pixel circuit to reset or auto-zero the LOFIC. In various examples, the LOFIC can be reset or auto-zeroed during the idle period, as well as during the pre-charge period and during LOFIC reset during the readout period of the pixel circuit.

[0030] In various examples, the LOFIC can be disposed in a location separate from the anti-overflow path from the photodiode of the pixel circuit, such that there is no charge stress across the LOFIC during the idle period. Thus, the active row of the LOFIC with stored charge has sufficient idle period to fully discharge before the integration period of the next frame. In various examples, the idle row has no charge across the LOFIC during the idle period because the excess charge is configured to overflow into one or more floating diffusion regions, the charge then being drained through the reset transistor during the idle period. As such, excess image charge photo-generated by the photodiode during the idle period is configured to overflow from the photodiode through the transfer transistor into the floating diffusion region and not the LOFIC. In various examples, excess image charge photo-generated by the photodiode during the integration period is configured to overflow from the photodiode into the LOFIC and not the floating diffusion region.

[0031] To illustrate, Figure 1To illustrate one example of an imaging system 100 having a pixel array with pixel circuits that provide LOFICs that reduce image lag in accordance with the teachings of this disclosure, particularity, Figure 1 The example depicted illustrates an imaging system 100 that includes a pixel array 102, bit lines 112, control circuitry 110, readout circuitry 106, and functional logic 108. In one example, the pixel array 102 is a two-dimensional (2D) array that includes a plurality of pixel circuits 104 (e.g., PI, P2,..., Pn) arranged in rows (e.g., Rl to Ry) and columns (e.g., CI to Cx) to acquire image data of a person, place, object, etc. that can then be used to render an image of the person, place, object, etc.

[0032] In various examples, each pixel circuit 104 can include one or more photodiodes configured to photo generate image charges in response to incident light. Image charges generated in the one or more photodiodes are transferred to a floating diffusion region included in each pixel circuit 104, which can be converted into an image signal that is then read out from each pixel circuit 104 by the readout circuitry 106 over the column bit lines 112. As will be discussed, in various examples, the pixel circuits 104 are also configured to provide HDR image signals, in which case image charges generated by the one or more photodiodes under bright illumination conditions can also be transferred to a LOFIC and / or additional floating diffusion region in each pixel circuit 104 to store image charges. For example, each pixel circuit 104 can include a LOFIC configured to store one or more excess image charges that overflow from the coupled one or more photodiodes during an integration period. In various examples, the readout circuitry 106 can be configured to read out the image signals over the column bit lines 112. In various examples, the readout circuitry 106 can include current sources, routing circuitry, and comparators, which can be included in an analog-to-digital converter or other.

[0033] In examples, digital image data values generated by the analog-to-digital converter in the readout circuitry 106 can then be received by the functional logic 108. The functional logic 108 can simply store the digital image data or even manipulate the digital image data by applying post image effects such as cropping, rotating, removing red eye, adjusting brightness, adjusting contrast, or others.

[0034] In one example, the control circuitry 110 is coupled to the pixel array 102 to control operation of the plurality of photodiodes in the pixel array 102. For example, the control circuitry 110 can generate a rolling shutter or shutter signal for controlling image acquisition. In other examples, image acquisition is synchronized with illumination effects such as a flash.

[0035] In one example, imaging system 100 is implemented on a single semiconductor wafer. In another example, imaging system 100 is on stacked semiconductor wafers. For example, pixel array 102 is implemented on a pixel wafer, and readout circuitry 106, control circuitry 110, and functional logic 108 are implemented on an application specific integrated circuit (ASIC) wafer, where the pixel wafer and ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) or one or more through-substrate vias (TSVs). For another example, pixel array 102 and control circuitry 110 are implemented on a pixel wafer, and readout circuitry 106 and functional logic 108 are implemented on an ASIC wafer, where the pixel wafer and ASIC wafer are stacked and interconnected by bonding (hybrid bonding, oxide bonding, or the like) and / or one or more through-substrate vias (TSVs).

[0036] In one example, imaging system 100 can be included in a digital camera, a cell phone, a laptop, an endoscope, a surveillance camera, or a car imaging device, or the like. Additionally, imaging system 100 can be coupled to other hardware, such as a processor (general purpose or otherwise), a memory element, an output (USB port, wireless transmitter, HDMI port, etc.), an illumination / flash, an electrical input (keyboard, touch display, touchpad, mouse, microphone, etc.), and / or a display. The other hardware can transmit instructions to imaging system 100, extract image data from imaging system 100, or manipulate image data supplied by imaging system 100.

[0037] Figure 2A A diagram illustrating one example of pixel circuit 204 including LOFIC during an idle period in accordance with the teachings of this disclosure is described. It is to be appreciated that Figure 2A Pixel circuit 204 can be an example of one of pixel circuits 104 included in pixel array 102 shown in Figure 1 The above similarly named and numbered elements are similarly coupled and function below.

[0038] As shown in the depicted example, pixel circuit 204 includes photodiode 214 configured to photo generate image charge in response to incident light. In the depicted example, pixel circuit 204 also includes first floating diffusion region FD1 218 coupled to receive image charge from photodiode 214 by transfer transistor 216. In an example, transfer transistor 216 is coupled to be controlled to transfer image charge from photodiode 214 to first floating diffusion region FD1 218, for example, during a readout period associated with pixel circuit 204, in response to a transfer control signal TX 236. In an example, pixel circuit 204 further includes second floating diffusion region FD2 220 coupled to receive image charge from first floating diffusion region FD1 218 by reset transistor 222. In an example, reset transistor 222 is coupled to be controlled to transfer image charge from first floating diffusion region FD1 218 to second floating diffusion region FD2 220, for example, during a reset period associated with pixel circuit 204, in response to a reset control signal RST 238. Figure 2AIn the depicted example, it is noted that during the idle period, excess image charge photo-generated in response to bright illumination conditions is also configured to overflow from photodiode 214 to first floating diffusion region FD1 218 through transfer transistor 216, which as will be discussed, is then drained through reset transistor 234 during the idle period. Source follower transistor 220 has a gate coupled to first floating diffusion region FD1 218, and row select transistor 222 is coupled to source follower transistor SF 220, such that source follower transistor 220 and row select transistor 222 are coupled between a power supply line and bit line 212 to output an image signal from pixel circuit 204 in response to a row select control signal RS 246 and the amount of charge at the gate of source follower transistor 220.

[0039] In Figure 2A In the depicted example, dual floating diffusion DFD transistor 224 is coupled between first floating diffusion region FD1 218 and second capacitor 228. Second capacitor 228 is further coupled to the source of reset transistor 234 and also coupled to receive a floating diffusion capacitor signal FDC 240 for charge readout operations. Second capacitor 228 can be a junction capacitor in combination with a metal capacitor or a metal-oxide-semiconductor capacitor (MOSCAP) for additional charge storage. The drain of dual floating diffusion DFD transistor 224 coupled to second capacitor 228 can also be referred to as second floating diffusion region FD2 226. Second capacitor 228 is coupled to receive excess image charge overflowing from photodiode 214 through transfer transistor 216 and dual floating diffusion DFD transistor 224. Reset transistor 234 is coupled between a bias voltage source 248 and dual floating diffusion transistor 224. The drain of reset transistor 234 is coupled to bias voltage source 248, and the source of reset transistor 234 is coupled to second capacitor 228 and the drain of dual floating diffusion transistor 224. Dual floating diffusion transistor 224 is coupled to be controlled in response to a dual floating diffusion control signal DFD 238 and reset transistor 234 is coupled to be controlled in response to a reset control signal RSTG 244.

[0040] As Figure 2AAs shown in the depicted example, overflow transistor 254 is coupled to photodiode 214, and a lateral overflow integrated capacitor (LOFIC) 232 is coupled between a bias voltage source 248 and overflow transistor 254. In various examples, it should be appreciated that transfer transistor 216 and overflow transistor 254 can be combined and formed or included in a bypass transistor having a dual gate structure to minimize unit pixel area. In an example, the dual gate structure included in the bypass transistor includes an overflow gate (e.g., overflow transistor 254) coupled between LOFIC 232 and photodiode 214 and a transfer gate (e.g., transfer transistor 216) coupled between photodiode 214 and first floating diffusion region FD1 218. In an example, overflow transistor 254 is controlled in response to an overflow control signal OFG 256. In an example, a low conversion gain transistor 230 is coupled between LOFIC 232 and first floating diffusion region FD1 218. In an example, low conversion gain transistor 230 is controlled in response to a low conversion gain control signal LFG 242. As such, LOFIC 232 is coupled between bias voltage source 248 and low conversion gain transistor 230 and between bias voltage source 248 and overflow transistor 254. Accordingly, it should be appreciated that LOFIC 232 is selectively coupled to first floating diffusion region FD1 218 through low conversion gain transistor 230, which is selectively coupled to reset transistor 234 through dual floating diffusion transistor 224. LOFIC 232 is coupled to receive excess image charge overflow from photodiode 214 through overflow transistor 254 during an integration period (e.g., under bright light conditions such as IR or LED light).

[0041] In an example, LOFIC 232 is implemented with a metal-insulator-metal capacitor including a high dielectric or high-k insulating material disposed between a first metal electrode and a second metal electrode. In various examples, the insulating material disposed between the first metal electrode and the second metal electrode of LOFIC 232 can be formed from a single layer of high-k material or a stack of multiple layers of high-k material. The exact composition and total thickness of the high-k material can depend on the desired LOFIC capacitance. In various examples, the high-k material can include one of aluminum oxide (AI2O3), zirconium dioxide (ZrO2), hafnium oxide (HfO), or combinations thereof.

[0042] In one example, it should be appreciated that the first metal electrode of LOFIC 232 can be referred to as a capacitor top metal (CTM) and the second metal electrode of LOFIC 232 can be referred to as a capacitor bottom metal (CBM).

[0043] In operation, the bias voltage source 248 is configured to provide a bias voltage VCAP to the drain of the reset transistor RST 234 and to the first metal electrode CTM of the LOFIC 232. Further, in the example depicted in FIG. 2, the bias voltage source 248 is also configured to provide a bias voltage VCAP to the second metal electrode CBM of the LOFIC 232. In other words, the bias voltage source 248 is configured to provide a bias voltage VCAP to both the first and second metal electrodes CTM and CBM of the LOFIC 232. Figure 2A During the idle period shown in the example depicted in FIG. 2, the reset transistor RST 234 is configured to turn on in response to the reset control signal RSTG 244, the double floating diffusion transistor 224 is configured to turn on in response to the double floating diffusion control signal 238, and the low transfer gain transistor 230 is configured to turn on in response to the low transfer gain control signal LFG 242. Thus, in accordance with the teachings of the present disclosure, the second metal electrode CBM of the LOFIC 232 is also coupled to the bias voltage source 248 through the first floating diffusion region FD1 218, through the low transfer gain transistor 230, and through the double floating diffusion transistor 224, which results in a special forced bias or auto-zero across the LOFIC 232 during the idle period and thus discharges the LOFIC 232. Accordingly, in accordance with the teachings of the present disclosure, in operation, both the first and second metal electrodes (e.g., CTM and CBM) of the LOFIC 232 are locally shorted together and to the same bias voltage source 248 through the reset transistor RST 234, the double floating diffusion transistor 224, the first floating diffusion region FD1 218, the transfer transistor 216, and the low transfer gain transistor 230 during the idle period of the pixel circuit 204, which forces the LOFIC 232 to discharge to reduce image lag issues.

[0044] As Figure 2AAs illustrated in the examples, during idle periods, bias voltage source 248 is configured to provide a bias voltage VCAP, which in various embodiments may have values ​​ranging from low capacitor bias voltage to high capacitor bias voltage, and may also be referred to in this disclosure as VCAP_lo to VCAP_hi. In one embodiment, the bias voltage VCAP may have a value between 0 V and 3.5 V. It should be understood that in various embodiments, the voltage level of the bias voltage VCAP may be determined given the stability range of the high-k material. In this example, during the idle period, the reset control signal RSTG 244 may have a value sufficient to turn on the reset transistor RST 234 (e.g., a value between 2.5 V and 4 V), the dual floating diffusion control signal DFD 238 may have a high voltage value in the range of 2.5 V to 4 V, the low conversion gain control signal LFG 242 may have a value between 0 V and 4 V, the transfer control signal TX 236 may have a value between 0 V and 3 V, and the overflow control signal OFG 256 may have a negative voltage value (e.g., a value between -1 V and -2 V) to form a barrier to prevent any charge from flowing from the photodiode 214 to the LOFIC 232. It should be understood that, since the overflow control signal OFG 256 has a negative voltage value during the idle period, excess charge generated in photodiode 214 in response to bright light (e.g., IR or LED light) is configured not to flow into LFOIC 232, but instead overflows into the first floating diffusion region FD1 218 via transfer transistor 216, which is then discharged through reset transistor 234 during the idle period. Configuring the voltage level transfer control signal TX 236 to a positive voltage or zero voltage provides a leakage path for excess charge to overflow from photodiode 214 into the first floating diffusion region FD1 218 and be discharged through reset transistor 234.

[0045] Figure 2B The illustration shows a cross-sectional view of an example of a pixel circuit 204 including a lateral overflow integrated capacitor (LOFIC) during an idle period according to the teachings of this disclosure. It should be understood that... Figure 2B The pixel circuit 204 may be included in Figure 1 The example shown is of one of the pixel circuits 104 in the pixel array 102, and similarly named and numbered elements are similarly coupled and function in the following text. It should also be understood that... Figure 2B The pixel circuit 204 depicted above can be described in detail. Figure 2A A cross-sectional example of the pixel circuit 204 depicted in the figure.

[0046] For example, such as Figure 2BAs shown in the illustrated example, pixel circuit 204 includes a photodiode PD 214 disposed in a semiconductor material 215 (e.g., silicon, substrate, silicon-germanium alloy, germanium, silicon carbide alloy, indium gallium arsenide alloy, any other alloy formed of group III-V compounds, other suitable semiconductor materials or alloys, combinations thereof, their bulk substrates or wafers). The photodiode 214 is configured to generate image charge in response to incident light. In the illustrated example, pixel circuit 204 also includes a first floating diffusion region FD1 218 coupled to receive image charge from photodiode PD 214 via transfer transistor 216. As will be explained below... Figure 2E The example depicted further illustrates that the transfer gate of transfer transistor 216 is configured to be coupled to a sufficiently low bias voltage (e.g., a voltage between -2.0 V and -0.5 V) to forcefully disconnect transfer transistor 216 during the integration period for accumulating photogenerated charge in photodiode 214, causing excess photogenerated charge from photodiode 214 to overflow into LOFIC 232 through overflow transistor 254 in response to strong light. However, in Figure 2B During the idle period illustrated, transfer transistor 216 is coupled to a voltage (e.g., 0 to 2.7 V) to provide a leakage path between photodiode 214 and the first floating diffusion region FD1 218 to prevent photogenerated charge from overflowing into LOFIC 232, thus preventing stress-induced MIM delay during the idle period. A control bias voltage (e.g., high bias, intermediate bias, or low bias) that biases the transfer gate of transfer transistor 216 is provided by transfer control signal TX 236.

[0047] exist Figure 2BIn the example illustrated, a double-floated diffusion (DFD) transistor 224 is coupled between the first floating diffusion region FD1 218 and the second floating diffusion region FD2 226. The second floating diffusion region FD2 can be coupled to a capacitor (e.g., second capacitor 228) that provides additional charge storage. In an example, the gate of the double-floated diffusion transistor 224 is coupled to receive a high bias voltage, e.g., in response to a double-floated diffusion control signal DFD 238 having a high voltage level, such that the double-floated diffusion transistor 224 is turned on during an idle period, as shown. The high voltage level of the double-floated diffusion control signal DFD 238 can be greater than the high bias voltage applied to the transfer gate of the transfer transistor 216. In one example, the high voltage level of the double-floated diffusion control signal DFD 238 can be in a range between 3 to 4 volts. A reset transistor 234 is coupled between a bias voltage source 248 and the double-floated diffusion transistor 224. The reset transistor 234 is turned on during an idle period, such that excess photo-generated charge can overflow to the first floating diffusion region FD1 218, the second floating diffusion region FD2 226, and drain through the reset transistor 234 to the bias voltage source 248, as shown. In an example, the gate of the reset transistor 234 is coupled to receive a high bias voltage, e.g., in response to a reset control signal RSTG 244 having a high voltage level. In one example, the high voltage level of the reset control signal RSTG 244 can be in a range between 3 to 4 volts.

[0048] As Figure 2BAs shown in the depicted example, overflow transistor 254 is coupled to photodiode 214, and LOFIC 232 is coupled between bias voltage source 248 and overflow transistor 254. In an example, the gate of overflow transistor 254 is coupled to receive a negative bias voltage (e.g., overflow control signal OFG 256 having a low voltage level) such that overflow transistor 254 operates in an off state and disables any charge flow path between photodiode 214 and LOFIC 232. The low or negative bias voltage level of overflow control signal OFG 256 can be in a range between -1 V to -2 V. In an example, low conversion gain transistor 230 is coupled between LOFIC 232 and first floating diffusion region FD1 218. In an example, the gate of low conversion gain transistor 230 is coupled to receive a high bias voltage (e.g., low conversion gain control signal LFG 242 having a high voltage level during an idle period) such that low conversion gain transistor 230 is turned on, as shown. As such, LOFIC 232 is coupled between bias voltage source 248 and low conversion gain transistor 230 as well as bias voltage source 248 and overflow transistor 254. Accordingly, it should be appreciated that LOFIC 232 is selectively coupled to first floating diffusion region FD1 218 through low conversion gain transistor 230, which is selectively coupled to reset transistor 234 through double floating diffusion transistor 224 and second floating diffusion region FD2 226.

[0049] In operation, bias voltage source 248 is configured to provide a bias voltage VCAP to the drain RSTD of reset transistor RST 234 as well as the first metal electrode CTM of LOFIC 232. Further, in Figure 2BDuring the idle period shown in the depicted example, the reset transistor RST 234 is configured to turn on when a high bias voltage is received by the gate of the reset transistor 234, the double floating diffusion transistor 224 is configured to turn on in response to a high bias voltage being received by the gate of the double floating transistor 224, and the low conversion gain transistor 230 is configured to turn on in response to a high bias voltage being received by the gate of the low conversion gain transistor 230. Thus, in accordance with the teachings of the present disclosure, the second metal electrode CBM of the LOFIC 232 is also coupled to the bias voltage source 248 through the first floating diffusion region FD1 218, through the low conversion gain transistor 230, and through the double floating diffusion transistor 224, which results in a special forced bias or auto-zero across the LOFIC 232 during the idle period and thus discharges the LOFIC 232. Accordingly, in operation, during the idle period of the pixel circuit 204, both the first and second metal electrodes (e.g., CTM and CBM) of the LOFIC 232 are locally shorted together and to the same bias voltage source 248 through the reset transistor RST 234, the second floating diffusion region FD2 226, the double floating diffusion transistor 224, the first floating diffusion region FD1 218, and the low conversion gain transistor 230, which forces the LOFIC 232 to discharge to mitigate the image lag issue. It should be appreciated that the gate of the overflow transistor 254 receives a sufficiently negative bias voltage, while the transfer gate of the transfer transistor 216 receives a bias voltage greater than the bias voltage applied to the gate of the overflow transistor 254 (e.g., zero bias voltage or a positive bias voltage), thereby providing a leakage path between the photodiode 214 and the first floating diffusion region FD1 218 during the idle period such that excess charge photo-generated in the photodiode 214 in response to bright light (e.g., IR or LED light) is configured to not flow into the LOFIC 232, but rather to overflow into the first floating diffusion region FD1 218 through the transfer transistor 216, which is then drained through the reset transistor 234 during the idle period.

[0050] In Figure 2B In the example described in the foregoing, it should be noted that the gate oxide layer 217 is disposed between the gate electrodes of the overflow transistor 254, the transfer transistor 216, the double floating diffusion transistor 224, the reset transistor 234, and the low conversion gain transistor 230 and the surface of the semiconductor material 215.

[0051] Figure 2C A schematic diagram of one example of a pixel circuit 204 including a LOFIC during a pre-charge period in accordance with the teachings of the present disclosure is illustrated. It should be appreciated that the pixel circuit 204 of FIG. 2B can be included in a CMOS image sensor 200 in accordance with the teachings of the present disclosure. Figure 2C The pixel circuit 204 of FIG. 2B can be included in a CMOS image sensor 200 in accordance with the teachings of the present disclosure. Figure 1An example of one of the pixel circuits 104 in the pixel array 102 shown in FIG. 1 is shown in FIG. 2, and like-named and numbered elements are coupled and function similarly below. It should also be appreciated that, Figure 2C The pixel circuit 204 depicted in FIG. 2 is substantially similar to the pixel circuit 104 discussed in detail above, except that Figure 2A to 2B The pixel circuit 204 depicted in FIG. 2 is substantially similar to the pixel circuit 104 discussed in detail above, except that Figure 2C The pixel circuit 204 illustrated in FIG. 2 is depicted during a pre-charge period, which occurs after the idle period and before the integration period and the readout period. Figure 2A The pixel circuit 204 illustrated in FIG. 2 is depicted during a pre-charge period, which occurs after the idle period and before the integration period and the readout period.

[0052] To illustrate, Figure 2C The pixel circuit 204 shown in FIG. 2 includes a photodiode 214 configured to photo generate image charge in response to incident light. In the depicted example, the pixel circuit 204 also includes a first floating diffusion region FD1 218 coupled to receive image charge from the photodiode 214 through a transfer transistor 216. In an example, the transfer transistor 216 is coupled to be controlled in response to a transfer control signal TX 236 to transfer image charge from the photodiode 214 to the first floating diffusion region FD1 218. A source follower transistor 220 has a gate coupled to the first floating diffusion region FD1 218, and a row select transistor 222 is coupled to the source follower transistor SF 220, such that the source follower transistor 220 and the row select transistor 222 are coupled between a power supply line and a bit line 212 to output an image signal from the pixel circuit 204 in response to a row select control signal RS 246 and an amount of charge at the gate of the source follower transistor 220.

[0053] In the example illustrated in FIG. 2, a dual floating diffusion DFD transistor 224 is coupled between the first floating diffusion region FD1 218 and a second capacitor 228. The drain of the dual floating diffusion DFD transistor 224 coupled to the second capacitor 228 can also be referred to as a second floating diffusion region FD2 226. The second capacitor 228 has one end coupled to the source of a reset transistor and has another end coupled to receive a floating diffusion capacitor signal FDC 240 for facilitating transfer of charge during a readout period that occurs after the integration period. A reset transistor 234 is coupled between a bias voltage source 248 and the dual floating diffusion transistor 224. The dual floating diffusion transistor 224 is coupled to be controlled in response to a dual floating diffusion control signal DFD 238 and the reset transistor 234 is coupled to be controlled in response to a reset control signal RSTG 244. Figure 2C As

[0054] As Figure 2CAs shown in the depicted example, overflow transistor 254 is coupled to photodiode 214 and LOFIC 232 is coupled between bias voltage source 248 and overflow transistor 254. In an example, overflow transistor 254 is controlled in response to overflow control signal OFG 256. In an example, low conversion gain transistor 230 is coupled between LOFIC 232 and first floating diffusion region FD1 218. In an example, low conversion gain transistor 230 is controlled in response to low conversion gain control signal LFG 242. As such, LOFIC 232 is coupled between bias voltage source 248 and low conversion gain transistor 230 and between bias voltage source 248 and overflow transistor 254. Accordingly, it should be appreciated that LOFIC 232 is selectively coupled to first floating diffusion region FD1 218 through low conversion gain transistor 230, which is selectively coupled to reset transistor 234 through double floating diffusion transistor 224 and second capacitor 228.

[0055] In operation, bias voltage source 248 is configured to provide a bias voltage VCAP to the drain of reset transistor RST 234 and to the first metal electrode CTM of LOFIC 232. Further, in Figure 2CDuring the pre-charge period shown in the depicted example, the reset transistor RST 234 is configured to turn on in response to the reset control signal RSTG 244 (e.g., the reset control signal RSTG 244 has a high voltage level), the double floating diffusion transistor 224 is configured to turn on in response to the double floating diffusion control signal 238 (e.g., the double floating diffusion control signal 238 has a high voltage level), and the low transfer gain transistor 230 is configured to turn on in response to the low transfer gain control signal LFG 242 (e.g., the low transfer gain control signal LFG 242 has a high voltage level). Thus, in accordance with the teachings of the present disclosure, the second metal electrode CBM of the LOFIC 232 is also coupled to the bias voltage source 248 through the first floating diffusion region FD1 218, through the low transfer gain transistor 230, and through the double floating diffusion transistor 224, which results in a special forced bias or auto-zero across the LOFIC 232 during the pre-charge period and thus discharges the LOFIC 232. Accordingly, in operation, during the pre-charge period of the pixel circuit 204, both the first and second metal electrodes (e.g., CTM and CBM) of the LOFIC 232 are locally shorted together and to the same bias voltage source 248 through the reset transistor RST 234, the double floating diffusion transistor 224, the first floating diffusion region FD1 218, and the low transfer gain transistor 230, which forces the LOFIC 232 to discharge to reduce image lag issues. In the depicted example, it should be noted that the transfer transistor 216 is also turned on during the pre-charge period, which also couples the photodiode 214 to the first floating diffusion region FD1 218 and thus to the bias voltage source 248 to reset the photodiode 214 during the pre-charge period. The first floating diffusion region FD1 218 and the second capacitor 228 are also coupled to the bias voltage source 248 and are also reset (e.g., drain the remaining charge to the bias voltage source 248) during the pre-charge period.

[0056] As Figure 2C In the depicted example, during the pre-charge period, the bias voltage source 248 is configured to provide a bias voltage VCAP equal to VCAP hi, the reset control signal RSTG 244 can have a high voltage value that can be in a range between 2.5 V to 4 V, the double floating diffusion control signal DFD 238 can have a high voltage value that can be in a range between 2.5 V to 4 V, the low transfer gain control signal LFG 242 can have a high voltage value that can be in a range between 2.5 V to 4 V, the transfer control signal TX 236 can have a high voltage value that can be in a range from 2.5 V to 3.5 V, and the overflow control signal OFG 256 can have a low voltage value that can be in a range from -1 V to -2 V.

[0057] Figure 2D A diagram illustrating one example of pixel circuit 204 including LOFIC during an integration period in accordance with the teachings of this disclosure is shown. It should be appreciated that, Figure 2D Pixel circuit 204 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in Figure 1 and the above similarly named and numbered elements function similarly below. It should also be appreciated that, Figure 2D Pixel circuit 204 depicted in FIG. 2B is substantially similar to the pixel circuit 204 discussed in detail above, Figure 2A to 2C Pixel circuit 204 depicted in FIG. 2B is substantially similar to the pixel circuit 204 discussed in detail above, Figure 2D Pixel circuit 204 depicted in FIG. 2B is substantially similar to the pixel circuit 204 discussed in detail above, Figure 2C Pixel circuit 204 depicted in FIG. 2B is substantially similar to the pixel circuit 204 discussed in detail above,

[0058] To illustrate, Figure 2D Pixel circuit 204 includes a photodiode 214 configured to photo generate image charge in response to incident light. In the depicted example, pixel circuit 204 also includes a first floating diffusion region FD1 218 coupled to receive image charge from photodiode 214 through a transfer transistor 216. In an example, transfer transistor 216 is coupled to be controlled to transfer image charge from photodiode 214 to first floating diffusion region FD1 218 in response to a transfer control signal TX 236. A source follower transistor 220 has a gate coupled to first floating diffusion region FD1 218, and a row select transistor 222 is coupled to source follower transistor SF 220 such that source follower transistor 220 and row select transistor 222 are coupled between a power supply line and a bit line 212 to output an image signal from pixel circuit 204 in response to a row select control signal RS 246 and an amount of charge at the gate of source follower transistor 220.

[0059] In the example illustrated in FIG. 2A, a double floating diffusion DFD transistor 224 is coupled between first floating diffusion region FD1 218 and a second capacitor 228. The drain of double floating diffusion DFD transistor 224 coupled to second capacitor 228 can also be referred to as a second floating diffusion region FD2 226. Second capacitor 228 is coupled to receive a floating diffusion capacitor signal FDC 240 for facilitating charge readout. A reset transistor 234 is coupled between a bias voltage source 248 and double floating diffusion transistor 224. Double floating diffusion transistor 224 is coupled to be controlled in response to a double floating diffusion control signal DFD 238 and reset transistor 234 is coupled to be controlled in response to a reset control signal RSTG 244. Figure 2D As

[0060] Figure 2D ​As shown in the depicted example, overflow transistor 254 is coupled to photodiode 214 and LOFIC 232 is coupled between bias voltage source 248 and overflow transistor 254. In an example, overflow transistor 254 is controlled in response to overflow control signal OFG 256. In an example, low conversion gain transistor 230 is coupled between LOFIC 232 and first floating diffusion region FD1 218. In an example, low conversion gain transistor 230 is controlled in response to low conversion gain control signal LFG 242. As such, LOFIC 232 is coupled between bias voltage source 248 and low conversion gain transistor 230 and between bias voltage source 248 and overflow transistor 254. Accordingly, it should be appreciated that LOFIC 232 is selectively coupled to first floating diffusion region FD1 218 through low conversion gain transistor 230, which is selectively coupled to reset transistor 234 through double floating diffusion transistor 224. In operation, bias voltage source 248 is configured to provide a bias voltage VCAP to the drain of reset transistor RST 234 and to the first metal electrode CTM of LOFIC 232.

[0061] In the depicted example, transfer transistor 216, overflow transistor 254, and low conversion gain transistor 230 are configured to be open in response to transfer control signal TX 236, overflow control signal OFG 256, and low conversion gain control signal LFG 242, respectively, during the integration period. As such, it should be appreciated that LOFIC 232 is in a charge storage mode during integration. For example, as shown in FIG. 2, when the integration period is complete, transfer control signal TX 236 is asserted, which causes transfer transistor 216 to close, thereby transferring the charge from photodiode 214 to LOFIC 232. As such, it should be appreciated that LOFIC 232 is in a charge storage mode during integration. For example, as shown in FIG. 2, when the integration period is complete, transfer control signal TX 236 is asserted, which causes transfer transistor 216 to close, thereby transferring the charge from photodiode 214 to LOFIC 232. Figure 2DIn the example depicted in FIG. 2, during a bright light integration period, the bias voltage source 248 is configured to provide a bias voltage VCAP equal to VCAP lo (e.g., 1 to 2 V), the reset control signal RSTG 244 can have a value of 0 V, the double floating diffusion control signal DFD 238 can have a value of 0 V, the low conversion gain control signal LFG 242 can have a value of 0 V, the transfer control signal TX 236 can have a low voltage value (e.g., a negative bias signal in a range between -1 V to -2 V), and the overflow control signal OFG 256 can have a negative voltage value in a range of -1 V to -2 V. In the depicted example, it should be appreciated that the transfer transistor 216 and the overflow transistor 254 are biased such that excess image charge photo-generated by the photodiode 214 in response to bright light during the integration period is overflowed through the overflow transistor 254 to the LOFIC 232, rather than through the transfer transistor 216 to the first floating diffusion region FD1 218. It should be appreciated that the overflow transistor 254 can be configured to leak more readily than the transfer transistor 216. In one example, the overflow transistor 254 is configured with an additional n-type channel implant (e.g., with an implant of the same conductivity type as the photodiode 214) under the gate of the overflow transistor 254 proximate to the associated channel region, such that during the integration period, excess image charge is overflowed or leaked from the photodiode 214 through the overflow transistor 254 to the LOFIC 232.

[0062] To illustrate, Figure 2E The diagram represents a cross-section of one example of a pixel circuit 204 including a lateral overflow integrated capacitor (LOFIC) during a bright light integration period, in accordance with the teachings of this disclosure. It should be appreciated that the pixel circuit 204 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1, and the above similarly named and numbered elements are coupled and function similarly below. It should also be appreciated that the pixel circuit 204 depicted in FIG. 2 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1, and the above similarly named and numbered elements are coupled and function similarly below. Figure 2E The pixel circuit 204 depicted in FIG. 2 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1, and the above similarly named and numbered elements are coupled and function similarly below. Figure 1 The diagram represents a cross-section of one example of a pixel circuit 204 including a lateral overflow integrated capacitor (LOFIC) during a bright light integration period, in accordance with the teachings of this disclosure. It should be appreciated that the pixel circuit 204 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1, and the above similarly named and numbered elements are coupled and function similarly below. It should also be appreciated that the pixel circuit 204 depicted in FIG. 2 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1, and the above similarly named and numbered elements are coupled and function similarly below. Figure 2E The pixel circuit 204 depicted in FIG. 2 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1, and the above similarly named and numbered elements are coupled and function similarly below. Figure 2D The diagram represents a cross-section of one example of a pixel circuit 204 including a lateral overflow integrated capacitor (LOFIC) during a bright light integration period, in accordance with the teachings of this disclosure. It should be appreciated that the pixel circuit 204 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1, and the above similarly named and numbered elements are coupled and function similarly below. It should also be appreciated that the pixel circuit 204 depicted in FIG. 2 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1, and the above similarly named and numbered elements are coupled and function similarly below.

[0063] For example, as Figure 2EAs shown in the depicted example, the pixel circuit 204 includes a photodiode PD 214 disposed in a semiconductor material 215 (e.g., silicon) that is configured to photo generate image charge in response to incident light. In the depicted example, the pixel circuit 204 also includes a first floating diffusion region FD1 218 coupled to receive image charge from the photodiode PD 214 through a transfer transistor 216. In an example, the gate of the transfer transistor 216 is configured to be coupled to receive a negative bias voltage of -1.4 V during the integration period shown, which turns off the transfer transistor 216, as shown.

[0064] In Figure 2E In the depicted example, a double floating diffusion DFD transistor 224 is coupled between the first floating diffusion region FD1 218 and a second floating diffusion region FD2 226. In an example, the gate of the double floating diffusion region 224 is coupled to receive a high bias voltage (which can be in a range between 2.5 V to 3.5 V) during the integration period, as shown. A reset transistor 234 is coupled between a bias voltage source 248 and the double floating diffusion transistor 224. In an example, the gate of the reset transistor 234 is coupled to receive a high voltage in a range between 2.5 V to 4 V during the integration period, as shown.

[0065] As Figure 2E As shown in the depicted example, an overflow transistor 254 is coupled to the photodiode 214 and a LOFIC 232 is coupled between a bias voltage source 248 and the overflow transistor 254. In an example, the gate of the overflow transistor 254 is coupled to receive a negative voltage (e.g., a value between -1 V to -2 V) during the integration period, which turns off the overflow transistor 254, but the overflow transistor 254 is configured to provide a disconnected leakage path (e.g., with an additional channel implant 254CH) between the photodiode 214 and the LOFIC 232, as shown. In an example, a low conversion gain transistor 230 is coupled between the LOFIC 232 and the first floating diffusion region FD1 218. In an example, the gate of the low conversion gain transistor 230 is coupled to receive a low bias voltage of 0 V during the integration period, which turns off the low conversion gain transistor 230, as shown.

[0066] Thus, it should be appreciated that during integration, the LOFIC 232 is in a charge storage mode. As mentioned, in one example, it should be appreciated that the overflow transistor 254 can be configured with an additional n-type channel implant (e.g., channel implant 254CH) disposed between the photodiode 214 and the LOFIC 232 under the gate of the overflow transistor 254, such that during the integration period, excess image charge overflows or leaks from the photodiode 214 through the overflow transistor 254 to the LOFIC 232, as shown.

[0067] In the example illustrated in Figure 2E In the example illustrated in

[0068] Figure 3 A timing diagram illustrating example signal values in an example pixel circuit including LOFIC during idle, pre-charge, integration, and readout periods in accordance with the teachings of this disclosure is illustrated in Figure 3 The signals depicted in Figure 2A to 2E An example of the signals used to control the operation of an example pixel circuit, such as pixel circuit 204, is depicted in

[0069] Referring now to the depicted example, Figure 3 Reset control signal RST 344, bias voltage VCAP 348, double floating diffusion control signal DFD 338, low conversion gain control signal LFG 342, transfer control signal TX 336, overflow control signal OFG 356, floating diffusion capacitor signal FDC 340, and row select control signal RS 346 are illustrated, which are configured to control the respective circuit elements discussed above Figure 2A to 2E in detail. Figure 3 The example depicted in

[0070] As Figure 3During the idle period depicted, the reset control signal RST 344 turns on the reset transistor 234, and the bias voltage VCAP 348 provided by the bias voltage source 248 equals a high value (e.g., VCAP hi) coupled to the first metal electrode CTM of the LOFIC 232 and the drain of the reset transistor 234. The double-float diffusion control signal DFD 338 turns on the double-float diffusion transistor 224, which is thus coupled to the first float diffusion region FD1 218 to receive the bias voltage VCAP 348 through the reset transistor 234. The low transfer gain control signal LFG 342 having a high voltage level turns on the low transfer gain transistor 230, which couples the second metal electrode CBM of the LOFIC 232 to the first float diffusion region FD1 218. Thus, it should be appreciated that, in accordance with the teachings of the present disclosure, during the idle period, both the first and second metal electrodes CTM and CBM of the LOFIC 232 are coupled to the bias voltage VCAP 348 through the reset transistor 234, the double-float diffusion transistor 224, the first float diffusion region FD1 218, and the low gain transfer transistor 230. By shorting both the first and second metal electrodes CTM and CBM of the LOFIC 232 to the bias voltage VCAP 348, the LOFIC 232 is locally auto-zeroed or forced to discharge by the pixel circuit 204 to initiate a discharge operation, which reduces image lag, in accordance with the teachings of the present disclosure. The illustrated example also shows that, during the idle period, the transfer control signal TX 336 turns on the transfer transistor 216 and the overflow control signal OFG 356 turns off the overflow transistor 254. In one example, it should be appreciated that the overflow transistor 254 is negatively biased while the transfer control signal TX turns on the transfer transistor 216 or configures the transfer gate 216 to leak more readily than the overflow transistor 254 in the idle period, which prevents excess image charge photo-generated by the photodiode 214 during the idle period from flowing into the LOFIC 232. Conversely, excess image charge photo-generated by the photodiode 214 during the idle period in response to bright light flows through the transfer transistor 216 to the first float diffusion region FD1 218, which is then drained through the reset transistor 234 during the idle period.

[0071] Figure 3The example depicted in the middle shows that during the pre-charge period that occurs after the idle period, the double float diffusion control signal DFD 338, the low conversion gain control signal LFG 342, and the transfer control signal TX 336 remain on. Next, the row select signal RS 346 turns on the row select transistor 222 and then the reset control signal 344 turns on and the bias voltage VCAP 348 transitions to a high capacitor bias value (e.g., VCAP_hi). Thus, it should be appreciated that in accordance with the teachings of the present disclosure, during the pre-charge period, both the first and second metal electrodes CTM and CBM of the LOFIC 232 are coupled through the reset transistor 234, the double float diffusion transistor 224, the first float diffusion region FD1 218, and the low gain conversion transistor 230 to the high bias voltage provided by the bias voltage VCAP 348. In accordance with the teachings of the present disclosure, by continuing to short both the first and second metal electrodes CTM and CBM of the LOFIC 232 to the bias voltage VCAP 348, the LOFIC 232 is locally auto-zeroed or discharged, which reduces image lag. In addition, it should be appreciated that the photodiode 214 and the first float diffusion region FD1 218 are also discharged through the transfer transistor 216 and through the first float diffusion region FD1 218, the double float diffusion transistor 224, the reset transistor 234, and are reset to the high bias voltage provided by the bias voltage VCAP 348 during the pre-charge period.

[0072] Next, the transfer control signal TX 336 turns off the transfer transistor 216 and then the reset control signal RST 344 turns off the reset transistor 234, and then the bias voltage source 348 transitions to a low capacitor bias value or VCAP_lo (e.g., 0 volts), and then the low conversion gain control signal LFG 342 transitions to a low voltage level to turn off the low conversion gain transistor 230, and then the row select signal RS 346 turns off the row select transistor 222.

[0073] Figure 3 The example depicted in the middle shows that during the integration period that occurs after the pre-charge period, all signals are low except for the double float diffusion control signal 338 which remains high, and integration occurs during which the photodiode 214 generates image charge in response to incident light.

[0074] Figure 3The depicted example shows that during a readout period that occurs after the integration period, the double floating diffusion control signal DFD 338 remains high and the row select signal RS 346 turns on the row select transistor 222. Next, the reset control signal 344 turns on the reset transistor 234 and the bias voltage VCAP 348 transitions to a high capacitor bias value (e.g., VCAP hi). In an example, the floating diffusion capacitor signal FDC 340 can be pulsed to adjust the bias across the second capacitor 226 and the voltage of the first floating diffusion region FD1 218 to facilitate signal readout from the photodiode 214 during operation of the high conversion gain and mid conversion gain signal readouts.

[0075] Next, a double conversion gain (DCG) readout of the photodiode occurs during which the reset control signal RST 344 transitions to a low value and then a mid conversion gain (MCG) readout of the reset value (R) from the photodiode 214 occurs. Next, the floating diffusion capacitor signal FDC 340 is pulsed while the double floating diffusion control signal DFD 338 turns off the double floating diffusion transistor 224. Next, a high conversion gain (HCG) readout of the reset value (R) from the photodiode 214 occurs. Next, the floating diffusion capacitor signal FDC 340 transitions to a high value and the transfer control signal TX 336 turns on the transfer transistor 216 during which image charge in the photodiode 214 is transferred to the first floating diffusion region FD1 218. Next, a high conversion gain (HCG) readout of the signal value (S) can occur after the transfer control signal TX 236 and the floating diffusion capacitor signal FDC 340 transition to a low value. Next, the double floating diffusion control signal DFD 338 turns on the double floating diffusion transistor 224, the floating diffusion capacitor signal FDC 340 transitions to a high value, and the transfer control signal TX 336 turns on the transfer transistor 216 during which image charge in the photodiode 214 is transferred to the first floating diffusion region FD1 218 and the second capacitor 228. Next, a mid conversion gain (MCG) readout of the signal value (S) can occur after the transfer control signal TX 236 and the floating diffusion capacitor signal FDC 340 transition to a low value.

[0076] Next, LOFIC readout of the photodiode 214 and the LOFIC 232 occurs during which the low conversion gain control signal LFG 342 turns on the low conversion gain transistor 230 and then the transfer control signal TX 336 turns on the transfer transistor 216 during which image charge in the photodiode 214 is transferred to the first floating diffusion region FD1 218, the second capacitor 228 and the LOFIC 232. Next, low conversion gain (LCG) readout of the signal value (S) can occur. Next, the reset control signal RST 344 turns on the reset transistor 234 during which the photodiode 214, the first floating diffusion region FD1 218, the second capacitor 228 and the LOFIC 232 are all reset through the reset transistor 234, the second floating diffusion region FD2 226, the dual floating diffusion transistor 224, the first floating diffusion region FD1 218, the transfer transistor 216 and the low gain conversion transistor 230 with the bias voltage VCAP 348 set to a high capacitor bias value (e.g., VCAP_hi). Next, the reset transistor 234 is turned off and then low conversion gain (LCG) readout of the reset value (R) occurs.

[0077] Next, in accordance with the teachings of the present disclosure, Figure 3 The process cycle depicted in FIG. 4B loops back to the idle period during which the LOFIC 232 can again be automatically zeroed or discharged to reduce image lag and the cycle repeats.

[0078] Figure 4A A schematic diagram of another example of a pixel circuit 404 including a lateral overflow integrated capacitor (LOFIC) during an idle period in accordance with the teachings of the present disclosure is illustrated. It should be appreciated that the pixel circuit 404 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1A, and the similarly named and numbered elements described above are coupled and function similarly below. It should also be appreciated that the pixel circuit 404 depicted in FIG. 4B shares some similarities with the pixel circuit 204 discussed in detail above. Figure 4A The pixel circuit 404 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in FIG. 1A, and the similarly named and numbered elements described above are coupled and function similarly below. It should also be appreciated that the pixel circuit 404 depicted in FIG. 4B shares some similarities with the pixel circuit 204 discussed in detail above. Figure 1 The pixel circuit 404 depicted in FIG. 4B shares some similarities with the pixel circuit 204 discussed in detail above. Figure 4A Figure 2A to 2E For example, as

[0079] For example, as Figure 4A ​As shown in the depicted example, pixel circuit 404 includes a plurality of photodiodes configured to photo generate image charge in response to incident light. In the depicted example, the plurality of photodiodes includes a set of photodiodes 414-L1, 414-L2, and 414-L3 configured to collectively function as a large photodiode (e.g., 3LPD) having three photodiodes. Additionally, the plurality of photodiodes also includes a photodiode 414-S configured to individually function as a small photodiode (e.g., 1SPD). In some embodiments, the large photodiode can have a greater incident light sensitivity than the small photodiode. In the depicted example, pixel circuit 404 also includes a first floating diffusion region FD1 418 coupled to receive image charge from photodiodes 414-L1, 414-L2, 414-L3, and 414-S through transfer transistors 416-S, 416-L1, 416-L2, and 414-L3, respectively. In the example, transfer transistors 416-S, 416-L1, 416-L2, and 414-L3 are coupled to be controlled to transfer image charge from photodiodes 414-L1, 414-L2, 414-L3, and 414-S to first floating diffusion region FD1 418 in response to transfer control signals LTX1 436-L1, LTX2 436-L2, LTX3 436-L3, and STX 436-S, respectively. A source follower transistor 420 has a gate coupled to first floating diffusion region FD1 418 and a row select transistor 422 is coupled to source follower transistor SF 420, such that source follower transistor 420 and row select transistor 422 are coupled between a power supply line and a bit line 412A to output an image signal from pixel circuit 404 in response to a row select control signal RS 446 and an amount of charge at the gate of source follower transistor 420. In one example, it is noted that pixel circuits 404 included in even rows can be coupled to bit line 412A, while pixel circuits 404 included in odd rows can be coupled to bit line 412B.

[0080] In the depicted example, the second capacitor 428 is coupled to the first floating diffusion region FD1 418 and is coupled to receive a floating diffusion capacitor signal FDC 440. The second capacitor 428 can be a junction capacitor in combination with a metal capacitor or a metal-oxide-semiconductor capacitor (MOSCAP) for additional charge storage. In an example, a reset transistor 434 is coupled between a power line (e.g., a reset voltage source) and the first floating diffusion region FD1 418. The reset transistor 434 is coupled to be controlled in response to a reset control signal RSTG 444. In the illustrated example, a dual floating diffusion transistor 424 is coupled between the first floating diffusion region FD1 418 and a LOFIC 432, which is coupled between a bias voltage source 448 and the first floating diffusion region FD1 418. In an example, the LOFIC 432 includes an insulating material disposed between a first metal electrode (e.g., a CTM) and a second metal electrode (e.g., a CBM). The dual floating diffusion transistor 424 is coupled to be controlled in response to a dual floating diffusion control signal DFD 438.

[0081] In an example, the LOFIC 432 is implemented with a metal-insulator-metal capacitor including an insulating material having a high dielectric constant or a high-k insulating material disposed between a first metal electrode and a second metal electrode. In various examples, the insulating material disposed between the first metal electrode and the second metal electrode of the LOFIC 432 can be formed from a single layer of high-k material or a stack of multiple layers of high-k material. The exact composition and total thickness of the high-k material can depend on the desired LOFIC capacitance. In various examples, the high-k material can include one of aluminum oxide (AI2O3), zirconium dioxide (ZrO2), hafnium oxide (HfO), or combinations thereof.

[0082] As Figure 4A As shown in the example depicted in FIG. 4, the overflow transistor 454 is coupled between the photodiode 414-S and the LOFIC 432. In an example, the overflow transistor 454 is controlled in response to an overflow control signal OFG 456. As such, the LOFIC 432 is coupled between the bias voltage source 448 and the dual floating diffusion transistor 424 and between the bias voltage source 448 and the overflow transistor 454. Accordingly, it should be appreciated that the LOFIC 432 is selectively coupled to the first floating diffusion region FD1 418 through the dual floating diffusion transistor 424. As such, the LOFIC 432 is selectively coupled to the reset transistor 434 through the dual floating diffusion transistor 424.

[0083] In operation, the bias voltage source 448 is configured to provide a bias voltage VCAP to the first metal electrode CTM of the LOFIC 432 and the power supply line is configured to provide a power supply voltage to the drain of the reset transistor 434. In one example, the bias voltage VCAP and the power supply voltage of the power supply line are configured as the same voltage. In another example, it should be appreciated that the bias voltage source 448 can also be configured to provide the bias voltage VCAP to the drain of the reset transistor 434. In Figure 4A During the idle period shown in the example depicted in FIG. 4, the reset transistor 434 is configured to turn on in response to the reset control signal RSTG 444 having a high value. In one example, the double floating diffusion transistor 424 is also configured to turn on in response to the double floating diffusion control signal 438 having a high value. Thus, in accordance with the teachings of the present disclosure, the second metal electrode CBM of the LOFIC 432 is also coupled to receive the power supply voltage through the double floating diffusion transistor 424, the first floating diffusion region FD1 418, and through the reset transistor 434, while the first metal electrode CTM of the LOFIC 432 is coupled to the bias voltage source 448, which results in a special forced bias or auto-zeroing across the LOFIC 432 during the idle period and thus discharging the LOFIC 432. Accordingly, in accordance with the teachings of the present disclosure, in operation, both the first and second metal electrodes (e.g., CTM and CBM) of the LOFIC 432 are locally shorted coupled to a high reset voltage through the reset transistor RST 434, the first floating diffusion region FD1 418, and the double floating diffusion transistor 424 during the idle period, which forces the LOFIC 432 to discharge to reduce image lag issues.

[0084] In the depicted example, it should be noted that the transfer transistor 416-S is biased with a transfer control signal STX 436-S equal to 0 V and the overflow transistor 454 is biased with an overflow control signal OFG 456 equal to a negative voltage value that can be in the range between -1 V to -2 V. Thus, it should be appreciated that the bias of the transfer transistor 416-S is much higher than the bias of the overflow transistor 454, such that excess image charge photo-generated in the photodiode 414-S is overflowed through the transfer transistor 416-S to the first floating diffusion region FD1 418 during the idle period, rather than through the overflow transistor 454 to the LOFIC 432. In the example, it should also be noted that excess image charge photo-generated in the photodiodes 414-L1, 414-L2, and 414-L3 can also be overflowed through the transfer transistors 416-L1, 416-L2, and 416-L3, respectively, to the first floating diffusion region FD1 418, which is then drained through the reset transistor 434 during the idle period.

[0085] Figure 4BThis diagram illustrates another example of a pixel circuit including a lateral overflow integrated capacitor (LOFIC) during the integration period according to the teachings of this disclosure. It should be understood that... Figure 4B The pixel circuit 404 may be included in Figure 1 The example shown is of one of the pixel circuits 104 in the pixel array 102, and similarly named and numbered elements are similarly coupled and function in the following text. It should also be understood that... Figure 4B The pixel circuit 404 depicted is essentially similar to the one discussed in detail above. Figure 4A The pixel circuit 404 depicted in the image is only... Figure 4B The pixel circuit 404 described herein is depicted during the integration period, which occurs when... Figure 4A This refers to the idle cycle, the precharge cycle, and the read cycle as described in the text.

[0086] To illustrate, such as Figure 4B As illustrated in the example, pixel circuit 404 includes a plurality of photodiodes configured to generate image charge in response to incident light. In the illustrated example, the plurality of photodiodes includes a set of photodiodes 414-L1, 414-L2, and 414-L3 configured to collectively function as a large photodiode (e.g., 3LPD) having three photodiodes. Additionally, the plurality of photodiodes also includes a photodiode 414-S configured to individually function as a small photodiode (e.g., 1 SPD). In some embodiments, the large photodiode may have a greater incident light sensitivity than the small photodiode. In the illustrated example, pixel circuit 404 also includes a first floating diffusion region FD1 418 coupled to receive image charge from photodiodes 414-L1, 414-L2, 414-L3, and 414-S respectively via transfer transistors 416-S, 416-L1, 416-L2, and 414-L3. In this example, transfer transistors 416-S, 416-L1, 416-L2, and 414-L3 are coupled to be controlled in response to transfer control signals LTX1 436-L1, LTX2 436-L2, LTX3 436-L3, and STX 436-S, respectively, to transfer image charge from photodiodes 414-L1, 414-L2, 414-L3, and 414-S to the first floating diffusion region FD1 418. A source follower transistor 420 has a gate coupled to the first floating diffusion region FD1 418, and a row select transistor 422 is coupled to the source follower transistor SF 420, such that the source follower transistor 420 and the row select transistor 422 are coupled between the power line and the bit line 412A to output an image signal from the pixel circuit 404 in response to the row select control signal RS 446 and the amount of charge at the gate of the source follower transistor 420.

[0087] In the depicted example, the second capacitor 428 is coupled to the first floating diffusion region FD1 418 and coupled to receive a floating diffusion capacitor signal FDC 440. In an example, a reset transistor 434 is coupled between a power supply line and the first floating diffusion region FD1 418. The reset transistor 434 is coupled to be controlled in response to a reset control signal RSTG 444. In the illustrated example, a dual floating diffusion transistor 424 is coupled between the first floating diffusion region FD1 418 and a LOFIC 432, which is coupled between a bias voltage source 448 and the first floating diffusion region FD1 418. In an example, the LOFIC 432 includes an insulating material (e.g., an insulating material having a high dielectric constant) disposed between a first metal electrode (e.g., a CTM) and a second metal electrode (e.g., a CBM). The dual floating diffusion transistor 424 is coupled to be controlled in response to a dual floating diffusion control signal DFD 438. As Figure 4B In the depicted example shown in FIG. 4, the overflow transistor 454 is coupled between the photodiode 414-S and the LOFIC 432. In an example, the overflow transistor 454 is controlled in response to an overflow control signal OFG 456.

[0088] In operation, the bias voltage source 448 is configured to provide a bias voltage VCAP to the first metal electrode CTM of the LOFIC 432 and the power supply line is configured to provide a power supply voltage to the drain of the reset transistor 434. In the depicted example, the reset control signal RSTG 444 is asserted to a high value to turn on the reset transistor 434 and the dual floating diffusion control signal DFD 438 is asserted to a low value to turn off the dual floating diffusion transistor 424. In the depicted example, the transfer control signal STX 436-S is asserted to a negative voltage value (e.g., between -1 V and -2 V) to bias the transfer transistor 416-S and the overflow control signal OFG 456 is asserted to a voltage value (e.g., 0 V to -2 V) to bias the overflow transistor 454. Figure 4B In the depicted example shown in FIG. 4, the reset transistor 434 is configured to turn on in response to the reset control signal RSTG 444 having a high value during the integration period. Additionally, it should be noted that the transfer transistor 416-S is biased with the transfer control signal STX 436-S equal to a negative voltage value (e.g., between -1 V and -2 V) and the overflow transistor 454 is biased with the overflow control signal OFG 456 equal to a voltage value (e.g., 0 V to -2 V). In the depicted example, it should be appreciated that the photodiode profile of the photodiode 414-S is shifted by the process such that excess image charge photo-generated in the photodiode 414-S is overflowed to the LOFIC 432 through the overflow transistor 454 during the integration period. In an example, it should also be noted that excess image charge photo-generated in the photodiodes 414-L1, 414-L2, and 414-L3 is overflowed to the first floating diffusion region FD1 418 through the transfer transistors 416-L1, 416-L2, and 416-L3, respectively, during the integration period.

[0089] Figure 5A A schematic diagram illustrating yet another example of a pixel circuit 504 including a lateral overflow integrated capacitor (LOFIC) during an integration period in accordance with the teachings of this disclosure is illustrated. It should be appreciated that, Figure 5AThe pixel circuit 504 may be included in Figure 1 The example shown is of one of the pixel circuits 104 in the pixel array 102, and similarly named and numbered elements are similarly coupled and function in the following text. It should also be understood that... Figure 5A The pixel circuit 504 depicted in the image is the same as the one discussed in detail above. Figure 2A to 2E The pixel circuit 204 and depicted in Figure 4A to 4B The pixel circuit 404 depicted in the diagram shares some similarities.

[0090] For example, such as Figure 5A As shown in the illustrated example, pixel circuit 504 includes a photodiode 514 configured to generate image charge in response to incident light. In the illustrated example, pixel circuit 504 also includes a first floating diffusion region FD1 518 coupled to receive image charge from photodiode 514.

[0091] Figure 5A Pixel circuit 504 and Figure 2A to 2E Pixel circuit 204 and / or Figure 4A to 4B One difference between the pixel circuits 404 and the others is that: [the following is a list of components] Figure 5A The transfer transistor in pixel circuit 504 comprises or is implemented using a multi-gate transistor structure. Figure 5A In a specific example depicted, the multi-gate transistor structure is a three-gate transistor structure comprising a photodiode gate 516-P, a floating diffused gate 516-F, and a LOFIC gate 516-L. In this example, the photodiode gate 516-P is coupled to a photodiode 514, the floating diffused gate 516-F is coupled to a first floating diffused region FD1518 and the photodiode gate 516-P, and the LOFIC gate 516-F is coupled to a LOFIC 532, the photodiode gate 516-P, and the floating diffused gate 516-F, as shown. The photodiode gate 516-P is coupled to be controlled in response to a photodiode transfer control signal TXP 536-P, the floating diffused gate 516-F is coupled to be controlled in response to a floating diffused transfer control signal TXF 536-F, and the LOFIC gate 516-L is coupled to be controlled in response to a LOFIC transfer control signal TXL 536-L. The photodiode gate 516-P, the floating diffused gate 516-F, and the LOFIC gate 516-L are individually disposed and electrically isolated. In one example, an insulating material of sufficient thickness is disposed between the photodiode gate 516-P, the floating diffused gate 516-F, and the LOFIC gate 516-L.

[0092] As will be discussed, in operation, image charge is configured to be transferred from photodiode 514 through photodiode gate 516-P and through floating diffusion gate 516-F to first floating diffusion region FD1 518 during a readout period, and excess image charge photo-generated by photodiode 514 during an idle period is configured to overflow from photodiode 514 through photodiode gate 514-P and through floating diffusion gate 516-F into first floating diffusion region FD1 518.

[0093] Source follower transistor 520 has a gate coupled to first floating diffusion region FD1 518 and row select transistor 522 is coupled to source follower transistor SF 520, such that source follower transistor 520 and row select transistor 522 are coupled between a power supply line and bit line 512 to output an image signal from pixel circuit 504 in response to row select control signal RS 546 and the amount of charge at the gate of source follower transistor 520.

[0094] In the example described in Figure 5A In the example described in

[0095] As mentioned above, the LOFIC gate 516-L is coupled to the LOFIC 532, the photodiode gate 516-P is coupled to the photodiode 514, and the floating diffusion gate 516-F is coupled to the first floating diffusion region FD1 518. Thus, the LOFIC gate 516-L and the photodiode gate 516-P are coupled between the LOFIC 532 and the photodiode 514, the floating diffusion gate 516-F and the photodiode gate 516-P are coupled between the first floating diffusion region FD1 518 and the photodiode 514, and the LOFIC gate 516-L and the floating diffusion gate 516-F are coupled between the LOFIC 532 and the first floating diffusion region FD1 518. Accordingly, it should be appreciated that the LOFIC 532 is selectively coupled to the first floating diffusion region FD1 518 by the LOFIC gate 516-L and the floating diffusion gate 516-F, the LOFIC gate 516-L and the floating diffusion gate 516-F are selectively coupled to the reset transistor 534 by the dual floating diffusion transistor 524. In addition, the LOFIC 532 is coupled between the bias voltage source 548 and the LOFIC gate 516-L.

[0096] In an example, the LOFIC 532 is implemented with a metal-insulator-metal capacitor including an insulating material with a high dielectric constant or a high-k insulating material disposed between a first metal electrode and a second metal electrode. In one example, it should be appreciated that the first metal electrode of the LOFIC 532 can be referred to as a capacitor top metal (CTM) coupled to the bias voltage source 548 and the second metal electrode of the LOFIC 532 can be referred to as a capacitor bottom metal (CBM) coupled to the LOFIC gate 516-L.

[0097] As Figure 5A As shown in the example depicted in FIG. 5B, during an idle period, the bias voltage source 548 is configured to provide a bias voltage VCAP which can have a value of VCAP lo to VCAP hi in various examples. In an example, during an idle period, the reset control signal RSTG 544 can have a high voltage value of 2.5 V to 4 V, the dual floating diffusion control signal DFD 538 can have a high voltage value of between 2.5 V to 4 V, the LOFIC transfer control signal TXL 536-L can have a value of -1 V to -2 V, the floating diffusion transfer control signal TXF 536-F can have a value of 2.5 V to 4 V, and the photodiode transfer control signal TXP 536-P can have a value of 0 V to 3 V. It should be appreciated that during an idle period, the LOFIC gate 516-L can have a voltage value of 0 V to 3 V, the photodiode gate 516-P can have a voltage value of 0 V to 3 V, and the floating diffusion gate 516-F can have a voltage value of 0 V to 3 V. Figure 5AIn the example depicted, the LOFIC 532 is isolated from the overflow prevention path from the photodiode 514, such that the LOFIC gate 516-L, the photodiode gate 516-P, and the floating diffusion gate 516-F are biased to prevent overflow of excess image charge photogenerated by the photodiode 514 during an idle period into the LOFIC 532. Conversely, as shown in the example depicted, in accordance with the teachings of this disclosure, excess image charge photogenerated by the photodiode 514 during an idle period is configured to overflow through the photodiode gate 516-P and the floating diffusion gate 516-F into the first floating diffusion region FD1 518, which then drains through the reset transistor 534 to the bias voltage source 548 during the idle period.

[0098] Figure 5B A schematic diagram illustrating yet another example of a pixel circuit 504 including a lateral overflow integrated capacitor (LOFIC) during a pre-charge period in accordance with the teachings of this disclosure is illustrated. It will be appreciated that the pixel circuit 504 can be an example of one of the pixel circuits 104 included in the pixel array 102 shown in Figure 5B Figure 1 The pixel circuit 504 depicted in Figure 5B The pixel circuit 504 depicted in Figure 5A The pixel circuit 504 depicted in Figure 5B The pixel circuit 504 illustrated in Figure 5A The pixel circuit 504 illustrated in

[0099] As Figure 5B ​As shown in the depicted example, pixel circuit 504 includes a photodiode 514 configured to photo generate image charge in response to incident light. In the depicted example, pixel circuit 504 also includes a first floating diffusion region FD1 518 coupled to receive image charge from photodiode 514. Pixel circuit 504 also includes a multi-gate transistor structure including a photodiode gate 516-P, a floating diffusion gate 516-F, and a LOFIC gate 516-L. In an example, photodiode gate 516-P is coupled to photodiode 514, floating diffusion gate 516-F is coupled to first floating diffusion region FD1 518 and photodiode gate 516-P, and LOFIC gate 516-F is coupled to LOFIC 532, photodiode gate 516-P, and floating diffusion gate 516-F, as shown. Photodiode gate 516-P is coupled to be controlled in response to a photodiode transfer control signal Txp 536-P, floating diffusion gate 516-F is coupled to be controlled in response to a floating diffusion transfer control signal TXF 536-F, and LOFIC gate 516-L is coupled to be controlled in response to a LOFIC transfer control signal TXL 536-L.

[0100] Source follower transistor SF 520 has a gate coupled to first floating diffusion region FD1 518 and row select transistor 522 is coupled to source follower transistor SF 520, such that source follower transistor 520 and row select transistor 522 are coupled between a power supply line and bit line 512 to output an image signal from pixel circuit 504 in response to a row select control signal RS 546 and an amount of charge accumulated at the gate of source follower transistor SF 520. Double floating diffusion DFD transistor 524 is coupled between first floating diffusion region FD1 518 and second capacitor 528. The drain of double floating diffusion DFD transistor 524 coupled to second capacitor 528 can also be referred to as second floating diffusion region FD2 526. Second capacitor 528 is coupled to receive a floating diffusion capacitor signal FDC 540. Reset transistor 534 is coupled between a bias voltage source 548 and double floating diffusion transistor 524. Double floating diffusion transistor 524 is coupled to be controlled in response to a double floating diffusion control signal DFD 538 and reset transistor 534 is coupled to be controlled in response to a reset control signal RSTG 544.

[0101] As mentioned above, the LOFIC gate 516-L is coupled to the LOFIC 532, the photodiode gate 516-P is coupled to the photodiode 514, and the floating diffusion gate 516-F is coupled to the first floating diffusion region FD1 518. Thus, the LOFIC gate 516-L and the photodiode gate 516-P are coupled between the LOFIC 532 and the photodiode 514, the floating diffusion gate 516-F and the photodiode gate 516-P are coupled between the first floating diffusion region FD1 518 and the photodiode 514, and the LOFIC gate 516-L and the floating diffusion gate 516-F are coupled between the LOFIC 532 and the first floating diffusion region FD1 518. Accordingly, it should be appreciated that the LOFIC 532 is selectively coupled to the first floating diffusion region FD1 518 by the LOFIC gate 516-L and the floating diffusion gate 516-F, and the LOFIC gate 516-L and the floating diffusion gate 516-F are selectively coupled to the reset transistor 534 by the dual floating diffusion transistor 524. In addition, the LOFIC 532 is coupled between the bias voltage source 548 and the LOFIC gate 516-L. In an example, the LOFIC 532 is implemented with a metal-insulator-metal capacitor including an insulating material or high-k insulating material having a high dielectric constant disposed between a first metal electrode (e.g., a CTM) and a second metal electrode (e.g., a CBM).

[0102] As Figure 5BIn the example depicted in FIG. 5B, during the pre-charge period, the bias voltage source 548 is configured to provide a bias voltage VCAP, which in the example has a value of VCAP hi (e.g., a value between 2.5 V and 4 V). In the example, during the pre-charge period, the reset control signal RSTG 544 can have a high voltage value between 2.5 V and 3.5 V, the double floating diffusion control signal DFD 538 can have a high voltage value between 2.5 V and 4 V, the LOFIC transfer control signal TXL 536-L can have a high voltage value between 2.5 V and 4 V, the floating diffusion transfer control signal TXF 536-F can have a high voltage value between 2.5 V and 3.5 V, and the photodiode transfer control signal TXP 536-P can have a value between 2.5 V and 3.5 V. In one example, the reset control signal RSTG 544 is configured to be greater than the bias voltage VCAP to properly drive the reset transistor RST 534 to reset the first floating diffusion region FD1 518, the second floating diffusion region FD2 526, the photodiode 514, while automatically zeroing the LOFIC 532. Thus, it should be appreciated that during the pre-charge period, the first metal electrode (e.g., CTM) of the LOFIC 532 is coupled to the bias voltage source 548 and the second metal electrode (e.g., CBM) is also locally coupled to the bias voltage source 548 through the LOFIC gate 516-L, through the floating diffusion gate 516-F, through the first floating diffusion region FD1 518, through the double floating diffusion transistor 524, through the second floating diffusion region FD2 526, and through the reset transistor 534 to reset during the pre-charge period. In the example, it should be appreciated that the photodiode 514, the first floating diffusion region FD1 518, and the second capacitor 528 are also coupled to the bias voltage source 548 to reset during the pre-charge period.

[0103] Figure 5C A schematic diagram illustrating yet another example of the pixel circuit 504 including a lateral overflow integrated capacitor (LOFIC) during an integration period in accordance with the teachings of this disclosure is illustrated in FIG. 5C. It should be appreciated that the pixel circuit 504 can be an example of one of the pixel circuits 104 included in the pixel array 102 illustrated in FIG. 1, and the similarly named and numbered elements described above are coupled and function similarly below. It should also be appreciated that the pixel circuit 504 depicted in FIG. 5C is substantially similar to the pixel circuit 504 discussed in detail above with respect to FIG. 5B, except that the pixel circuit 504 illustrated in FIG. 5C is depicted during an integration period, which occurs after the pre-charge period illustrated in FIG. 5B and before the readout period illustrated in FIG. 5D. Figure 5C Figure 1 It should be appreciated that the pixel circuit 504 depicted in FIG. 5C is substantially similar to the pixel circuit 504 discussed in detail above with respect to FIG. 5B, except that the pixel circuit 504 illustrated in FIG. 5C is depicted during an integration period, which occurs after the pre-charge period illustrated in FIG. 5B and before the readout period illustrated in FIG. 5D. Figure 5C Figure 5A to 5B It should be appreciated that the pixel circuit 504 depicted in FIG. 5C is substantially similar to the pixel circuit 504 discussed in detail above with respect to FIG. 5B, except that the pixel circuit 504 illustrated in FIG. 5C is depicted during an integration period, which occurs after the pre-charge period illustrated in FIG. 5B and before the readout period illustrated in FIG. 5D. Figure 5C Figure 5B It should be appreciated that the pixel circuit 504 depicted in FIG. 5C is substantially similar to the pixel circuit 504 discussed in detail above with respect to FIG. 5B, except that the pixel circuit 504 illustrated in FIG. 5C is depicted during an integration period, which occurs after the pre-charge period illustrated in FIG. 5B and before the readout period illustrated in FIG. 5D.

[0104] As​​​Figure 5C As shown in the depicted example, pixel circuit 504 includes a photodiode 514 configured to photo generate image charge in response to incident light. In the depicted example, pixel circuit 504 also includes a first floating diffusion region FD1 518 coupled to receive image charge from photodiode 514. Pixel circuit 504 also includes a multi-gate transistor structure including a photodiode gate 516-P, a floating diffusion gate 516-F, and a LOFIC gate 516-L. In examples, photodiode gate 516-P is coupled to photodiode 514, floating diffusion gate 516-F is coupled to first floating diffusion region FD1 518 and photodiode gate 516-P, and LOFIC gate 516-F is coupled to LOFIC 532, photodiode gate 516-P, and floating diffusion gate 516-F, as shown. Photodiode gate 516-P is coupled to be controlled in response to a photodiode transfer control signal TXP 536-P, floating diffusion gate 516-F is coupled to be controlled in response to a floating diffusion transfer control signal TXF 536-F, and LOFIC gate 516-L is coupled to be controlled in response to a LOFIC transfer control signal TXL 536-L.

[0105] Source follower transistor SF 520 has a gate coupled to first floating diffusion region FD1 518 and row select transistor 522 is coupled to source follower transistor SF 520, such that source follower transistor SF 520 and row select transistor 522 are coupled between a power supply line and bit line 512 to output an image signal from pixel circuit 504 in response to a row select control signal RS 546 and an amount of charge at the gate of source follower transistor 520. Double floating diffusion DFD transistor 524 is coupled between first floating diffusion region FD1 518 and second capacitor 528. The drain of double floating diffusion DFD transistor 524 coupled to second capacitor 528 can also be referred to as second floating diffusion region FD2 526. Second capacitor 528 is coupled to a source of reset transistor 534 and is further coupled to receive a floating diffusion capacitor signal FDC 540. Reset transistor 534 is coupled between a bias voltage source 548 and double floating diffusion transistor 524. Double floating diffusion transistor 524 is coupled to be controlled in response to a double floating diffusion control signal DFD 538 and reset transistor 534 is coupled to be controlled in response to a reset control signal RSTG 544.

[0106] As mentioned above, the LOFIC gate 516-L is coupled to the LOFIC 532, the photodiode gate 516-P is coupled to the photodiode 514, and the floating diffusion gate 516-F is coupled to the first floating diffusion region FD1 518. Thus, the LOFIC gate 516-L and the photodiode gate 516-P are coupled between the LOFIC 532 and the photodiode 514, the floating diffusion gate 516-F and the photodiode gate 516-P are coupled between the first floating diffusion region FD1 518 and the photodiode 514, and the LOFIC gate 516-L and the floating diffusion gate 516-F are coupled between the LOFIC 532 and the first floating diffusion region FD1 518. Accordingly, it should be appreciated that the LOFIC 532 is selectively coupled to the first floating diffusion region FD1 518 by the LOFIC gate 516-L and the floating diffusion gate 516-F, and the LOFIC gate 516-L and the floating diffusion gate 516-F are selectively coupled to the reset transistor 534 by the dual floating diffusion transistor 524. In addition, the LOFIC 532 is coupled between the bias voltage source 548 and the LOFIC gate 516-L. In an example, the LOFIC 532 is implemented with a metal-insulator-metal capacitor including an insulating material or high-k insulating material having a high dielectric constant disposed between a first metal electrode (e.g., a CTM) and a second metal electrode (e.g., a CBM).

[0107] As Figure 5C In the example depicted in FIG. 6B, during the integration period, the bias voltage source 548 is configured to provide a bias voltage VCAP, which in an example has a value of VCAP lo. In an example, during the integration period, the reset control signal RSTG 544 can have a value of 0 V, the dual floating diffusion control signal DFD 538 can have a value of 0 V, the LOFIC transfer control signal TXL 536-L can have a value of 0 V to 1.0 V, the floating diffusion transfer control signal TXF 536-F can have a value of 0 V, and the photodiode transfer control signal TXP 536-P can have a negative voltage value between -1 V and -2 V. Thus, it should be appreciated that during the integration period, excess image charge photo-generated by the photodiode 514 in response to bright light is configured to overflow through the LOFIC gate 516-L to the LOFIC 532, rather than through the floating diffusion gate 516-F into the first floating diffusion region FD1 518.

[0108] Figure 6 A timing diagram illustrating example signal values in another example pixel circuit including a LOFIC during an idle, a pre-charge, an integration, and a readout period in accordance with the teachings of this disclosure is illustrated. It should be appreciated that the signals depicted in Figure 6 The signals depicted in FIG. 6B can be Figure 5A to 5CThe depicted example signals, and like-named and numbered elements in the following description, are meant to be examples and are not limiting.

[0109] Referring now to the depicted example, Figure 6 Reset control signal RST 644, bias voltage VCAP 648, double floating diffusion control signal DFD 638, LOFIC transfer control signal TXL 636-L, photodiode transfer control signal TXP 636-P, floating diffusion transfer control signal TXF 636-F, floating diffusion capacitor signal FDC 640, and row select control signal RS 646 are configured to control the above-described pixel circuit 500 in the following manner. Figure 5A to 5C The corresponding circuit elements are discussed in detail in the following description. Figure 6 The depicted example also illustrates the idle, pre-charge, integration, and readout periods through which the pixel circuit sequentially cycles when generating image data.

[0110] As Figure 6 As shown during the idle period in the depicted example, reset control signal RST 644 turns on reset transistor 534, and bias voltage VCAP 648 equals a high capacitor bias value (e.g., VCAP_hi) coupled to the first metal electrode CTM of LOFIC 532 and the drain of reset transistor 534. Double floating diffusion control signal DFD 638 turns on double floating diffusion transistor 524, which thus couples first floating diffusion region FD1 518 to receive bias voltage VCAP 548 through reset transistor 534. In the example, LOFIC transfer control signal TXL 636-L equals a low value, photodiode transfer control signal TXP 636-P equals a low value, and floating diffusion transfer control signal TXF 636-F equals a high value. As such, it should be appreciated that, in accordance with the teachings of the present disclosure, excess image charge photo-generated in photodiode 514 during the idle period is configured to overflow through floating diffusion gate 516-F into first floating diffusion region FD1 518, which is then drained through reset transistor 534 during the idle period. Continuing with the depicted example, floating diffusion capacitor signal FDC 640 and row select signal RS 646 are configured to equal low values during the idle period.

[0111] Figure 6The depicted example shows that during a pre-charge period occurring after the idle period, the bias voltage VCAP 648 remains at a high value, and the LOFIC transfer control signal TXL 636-L turns on the LOFIC gate 516-L, and then the row select control signal RS 646 turns on the row select transistor 522. Next, the double float diffusion control signal DFD 638 turns on the double float diffusion transistor 524, and then the reset control signal RST 644 turns on the reset transistor 534, and then the photodiode transfer control signal TXP 636-P turns on the photodiode gate 516-P, and then the float diffusion transfer control signal TXF 636-F turns on the float diffusion gate 516-F, which resets the LOFIC 532, the photodiode 514, the first float diffusion region FD1 518, and the second capacitor 528 during the pre-charge period.

[0112] Next, the photodiode transfer control signal TXP 636-P turns off the photodiode gate 516-P, and then the reset control signal RST 644 turns off the reset transistor 534, and then the bias voltage VCAP 648 transitions to a low capacitor bias value (e.g., VCAP lo), and then the LOFIC transfer control signal TXL 636-L turns off the LOFIC gate 516-L, and then the float diffusion transfer control signal TXF 636-F turns off the float diffusion gate 516-F, and then the row select signal RS 646 turns off the row select transistor 522.

[0113] Figure 6 The depicted example shows that during an integration period occurring after the pre-charge period, all signals are low except the double float diffusion control signal 638, which remains high, and integration occurs during which the photodiode 514 generates image charge in response to incident light. It should be appreciated that in accordance with the teachings of the present disclosure, excess image charge photo-generated by the photodiode 514 is configured to overflow into the LOFIC 532 through the LOFIC gate 516-1 during the integration period.

[0114] Figure 6 The depicted example shows that during a readout period occurring after the integration period, the double float diffusion control signal DFD 638 remains high, the float diffusion transfer control signal TXF 636-F turns on the float diffusion gate 516-F, and the row select signal RS 646 turns on the row select transistor 522. Next, the reset control signal 644 turns on the reset transistor 534 and the bias voltage VCAP 648 transitions to a high capacitor bias value (e.g., VCAP hi).

[0115] Next, a double conversion gain (DCG) readout of the photodiode occurs during which the reset control signal RST 644 transitions to a low value and then a reset (R) from middle conversion gain (MCG) readout of the photodiode 514 occurs. Next, the floating diffusion capacitor signal FDC 640 is pulsed while the double floating diffusion control signal DFD 638 turns off the double floating diffusion transistor 524. Next, a reset (R) from high conversion gain (HCG) readout of the photodiode 514 occurs. Next, the floating diffusion capacitor signal FDC 640 transitions to a high value and the photodiode transfer control signal TXP 636-P turns on the photodiode transfer gate 516-P during which image charge in the photodiode 514 is transferred to the first floating diffusion region FD1 518. Next, a high conversion gain (HCG) readout of the signal (S) can occur after the photodiode transfer control signal TXP 636-P and the floating diffusion capacitor signal FDC 640 transition to a low value. Next, the double floating diffusion control signal DFD 638 turns on the double floating diffusion transistor 524, the floating diffusion capacitor signal FDC 640 transitions to a high value, and the photodiode transfer control signal TXP 536-P turns on the photodiode transfer gate 516-P during which image charge in the photodiode 514 is transferred to the first floating diffusion region FD1 518 and the second capacitor 528. Next, a middle conversion gain (MCG) readout of the signal (S) can occur after the photodiode transfer control signal TXP 536-P and the floating diffusion capacitor signal FDC 540 transition to a low value.

[0116] Next, LOFIC readout occurs for photodiode 514 and LOFIC 532. During this period, the LOFIC transfer control signal TXL 636-L turns on the LOFIC transfer gate 516-L, and then the photodiode transfer control signal TXP 636-P turns on the photodiode transfer gate 516-P. During this period, the image charge in photodiode 514 is transferred to the first floating diffusion region FD1 518, the second capacitor 528, and LOFIC 532. Following this, low conversion gain (LCG) readout of the signal value (S) can occur. Next, the reset control signal RST 644 turns on the reset transistor 534. During this period, the photodiode 514, the first floating diffusion region FD1 518, the second capacitor 528, and the LOBIC 532 are all reset through the reset transistor 534, the second floating diffusion region FD2 526, the dual floating diffusion transistor 524, the first floating diffusion region FD1 518, the photodiode transfer gate 516-P, and the LOBIC transfer gate 516-L, wherein the bias voltage VCAP 648 is set to a high capacitor bias value (e.g., VCAP_hi). Next, the reset transistor 534 turns off, and then a low conversion gain (LCG) readout of the reset value (R) occurs.

[0117] Next, according to the teachings of the present invention, Figure 6 The process described in the text returns to the idle period, at which point the loop repeats.

[0118] The above description of the illustrative examples of the present invention (including those described in the abstract) is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Although specific examples of the invention have been described herein for illustrative purposes, those skilled in the art will recognize that various modifications can be made within the scope of the invention.

[0119] These modifications can be made to the invention in light of the above detailed description. The terminology used in the appended claims should not be construed as limiting the invention to the specific instances disclosed in the specification. Rather, the scope of the invention will be fully defined by the appended claims, which will be interpreted according to established principles of claim interpretation.

Claims

1. A pixel circuit comprising: a photodiode configured to photo generate image charge during a period of time in response to incident light; a floating diffusion region coupled to receive the image charge; a transfer transistor coupled between the photodiode and the floating diffusion region, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion region; a reset transistor coupled between a reset voltage source and the floating diffusion region, wherein the reset transistor is configured to switch in response to a reset control signal; a lateral overflow integrated capacitor (LOFIC) including an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to a bias voltage source, wherein the second metal electrode is selectively coupled to the floating diffusion region, wherein excess image charge photo generated by the photodiode during an idle period is configured to overflow from the photodiode into the floating diffusion region through the transfer transistor; and an overflow transistor coupled between the photodiode and the second metal electrode, wherein excess image charge photo generated by the photodiode during an integration period is configured to overflow from the photodiode into the LOFIC through the overflow transistor, and not into the floating diffusion region through the transfer transistor.

2. The pixel circuit of claim 1, wherein the idle period occurs before the integration period.

3. The pixel circuit of claim 2, wherein the reset control signal is configured to turn on the reset transistor during the idle period to discharge the LOFIC through the floating diffusion region during the idle period.

4. The pixel circuit of claim 3, wherein the reset voltage source is the bias voltage source, wherein the reset control signal is configured to turn on the reset transistor to couple the first and second metal electrodes to the bias voltage source to discharge the LOFIC during the idle period and during a pre-charge period, wherein the pre-charge period occurs after the idle period and before the integration period.

5. The pixel circuit of claim 4, wherein a bias voltage provided by the bias voltage source is configured to equal a second bias voltage during the idle period, during the pre-charge period, and during a readout period that occurs after the integration period, wherein the bias voltage is configured to equal a first bias voltage during the integration period.

6. The pixel circuit of claim 5, wherein the first bias voltage is a low capacitor bias voltage, wherein the second bias voltage is a high capacitor bias voltage, wherein the low capacitor bias voltage is less than the high capacitor bias voltage.

7. The pixel circuit of claim 3, further comprising a double floating diffusion (DFD) transistor coupled between the floating diffusion region and the second metal electrode, wherein the DFD transistor is configured to switch in response to a DFD control signal.

8. The pixel circuit of claim 7, wherein the excess image charge photo-generated by the photodiode during the idle period is configured to overflow from the photodiode through the transfer transistor into the floating diffusion region, rather than through the overflow transistor into the LOFIC.

9. The pixel circuit of claim 6, wherein the LOFIC is a first capacitor, wherein the pixel circuit further comprises: a second capacitor coupled to the reset transistor; and a double floating diffusion (DFD) transistor coupled between the floating diffusion region and the second capacitor, wherein the DFD transistor is configured to switch in response to a DFD control signal.

10. The pixel circuit of claim 9, further comprising: a source follower transistor having a gate coupled to the floating diffusion region; and a row select transistor coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between a power supply line and a bit line.

11. The pixel circuit of claim 10, further comprising a low- conversion-gain (LFG) transistor coupled between the floating diffusion region and the second metal electrode, wherein the LFG transistor is configured to switch in response to an LFG control signal.

12. The pixel circuit of claim 11, wherein the second metal electrode is configured to be coupled to the reset transistor through the DFD transistor, the floating diffusion region, and the LFG transistor during the idle period and during the pre-charge period.

13. The pixel circuit of claim 12, wherein the excess image charge photo-generated by the photodiode during the idle period is configured to overflow from the photodiode through the transfer transistor into the floating diffusion region, rather than through the overflow transistor into the LOFIC.

14. The pixel circuit of claim 1, wherein the transfer transistor and the overflow transistor are included in a bypass transistor having a dual gate structure, the dual gate structure including an overflow gate coupled between the LOFIC and the photodiode and a transfer gate coupled between the photodiode and the floating diffusion region.

15. The pixel circuit of claim 1, wherein the transfer transistor comprises a multi-gate transistor structure, the multi-gate transistor structure including the overflow transistor, wherein the multi-gate transistor structure comprises: a photodiode gate coupled to the photodiode; a floating diffusion gate coupled to the floating diffusion region and the photodiode gate; and a LOFIC gate coupled to the LOFIC, the photodiode gate, and the floating diffusion gate, wherein image charge is configured to transfer from the photodiode to the floating diffusion region through the photodiode gate and through the floating diffusion gate during a readout period, ​ wherein the excess image charge photogenerated by the photodiode during the idle period is configured to overflow from the photodiode through the photodiode gate and through the floating diffusion gate into the floating diffusion region.

16. The pixel circuit of claim 15, wherein the second metal electrode is coupled to the reset transistor through the floating diffusion region, the floating diffusion gate, and the LOFIC gate to discharge the LOFIC during the idle period and during a pre-charge period.

17. The pixel circuit of claim 16, wherein the excess image charge photogenerated by the photodiode during the integration period is configured to overflow from the photodiode through the photodiode gate and through the LOFIC gate into the LOFIC.

18. An imaging system comprising: a pixel array including a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns, wherein each of the pixel circuits includes: a photodiode configured to photogenerate image charge in response to incident light; a floating diffusion region coupled to receive the image charge; a transfer transistor coupled between the photodiode and the floating diffusion region, wherein the transfer transistor is configured to transfer the image charge from the photodiode to the floating diffusion region; a reset transistor coupled between a reset voltage source and the floating diffusion region, wherein the reset transistor is configured to switch in response to a reset control signal; a lateral overflow integrated capacitor (LOFIC) including an insulating region disposed between a first metal electrode and a second metal electrode, wherein the first metal electrode is coupled to a bias voltage source, wherein the second metal electrode is selectively coupled to the floating diffusion region, wherein excess image charge photogenerated by the photodiode during an idle period is configured to overflow from the photodiode through the transfer transistor into the floating diffusion region, wherein the idle period occurs before a pre-charge period, the pre-charge period occurs before an integration period, the integration period occurs before a readout period; and an overflow transistor coupled between the photodiode and the second metal electrode, wherein the excess image charge photogenerated by the photodiode during the integration period is configured to overflow from the photodiode through the overflow transistor into the LOFIC instead of through the transfer transistor into the floating diffusion region; control circuitry coupled to the pixel array to control operation of the pixel array; and readout circuitry coupled to the pixel array to read out image data from the plurality of pixel circuits.

19. The imaging system of claim 18, wherein the reset control signal is configured to turn on the reset transistor during the idle period to discharge the LOFIC through the floating diffusion region during the idle period.

20. The imaging system of claim 19, wherein the reset voltage source is the bias voltage source, wherein the reset control signal is configured to turn on the reset transistor to couple the first and second metal electrodes to the bias voltage source during the idle period and during a pre-charge period to discharge the LOFIC.

21. The imaging system of claim 20, wherein a bias voltage provided by the bias voltage source is configured to equal a second bias voltage during the idle period, during the pre-charge period, and during the readout period, wherein the bias voltage is configured to equal a first bias voltage during the integration period, wherein the first bias voltage is a low capacitor bias voltage, wherein the second bias voltage is a high capacitor bias voltage, wherein the low capacitor bias voltage is less than the high capacitor bias voltage.

22. The imaging system of claim 19, wherein each of the pixel circuits further comprises a double floating diffusion (DFD) transistor coupled between the floating diffusion region and the second metal electrode, wherein the DFD transistor is configured to switch in response to a DFD control signal.

23. The imaging system of claim 22, wherein the excess image charge photogenerated by the photodiode during the idle period is configured to overflow from the photodiode into the floating diffusion region through the transfer transistor, rather than through the overflow transistor into the LOFIC.

24. The imaging system of claim 21, wherein the LOFIC is a first capacitor, wherein the pixel circuit further comprises: a second capacitor coupled to the reset transistor; and a double floating diffusion (DFD) transistor coupled between the floating diffusion region and the second capacitor, wherein the DFD transistor is configured to switch in response to a DFD control signal.

25. The imaging system of claim 24, wherein each of the pixel circuits further comprises: a source follower transistor having a gate coupled to the floating diffusion region; and a row select transistor coupled to the source follower transistor, wherein the source follower transistor and the row select transistor are coupled between a power supply line and a bit line.

26. The imaging system of claim 25, wherein each of the pixel circuits further comprises a low conversion gain (LFG) transistor coupled between the floating diffusion region and the second metal electrode, wherein the LFG transistor is configured to switch in response to an LFG control signal.

27. The imaging system of claim 26, wherein the second metal electrode is configured to be coupled to the reset transistor through the DFD transistor, the floating diffusion region, and the LFG transistor during the idle period and during the pre-charge period. ​ ​ 28. The imaging system of claim 27, wherein the excess image charge photo-generated by the photodiode during the idle period is configured to overflow from the photodiode through the transfer transistor into the floating diffusion region, rather than through the overflow transistor into the LOFIC.

29. The imaging system of claim 18, wherein the transfer transistor is included in a bypass transistor having a dual gate structure including an overflow gate coupled between the LOFIC and the photodiode and a transfer gate coupled between the photodiode and the floating diffusion region.

30. The imaging system of claim 18, wherein the transfer transistor comprises a multi-gate transistor structure including the overflow transistor, wherein the multi-gate transistor structure comprises: a photodiode gate coupled to the photodiode; a floating diffusion gate coupled to the floating diffusion region and the photodiode gate; and a LOFIC gate coupled to the LOFIC, the photodiode gate, and the floating diffusion gate, wherein image charge is configured to be transferred from the photodiode to the floating diffusion region through the photodiode gate and through the floating diffusion gate during the readout period, wherein the excess image charge photo-generated by the photodiode during the idle period is configured to overflow from the photodiode through the photodiode gate and through the floating diffusion gate into the floating diffusion region.

31. The imaging system of claim 30, wherein the second metal electrode is coupled to the reset transistor through the floating diffusion region, the floating diffusion gate, and the LOFIC gate to discharge the LOFIC during the idle period and during the pre-charge period.

32. The imaging system of claim 31, wherein the excess image charge photo-generated by the photodiode during the integration period is configured to overflow from the photodiode through the photodiode gate and through the LOFIC gate into the LOFIC. ​

Images