Chip Processing Method, Apparatus, Device, Storage Medium and Program Product

Abstract

The present application provides a chip processing method, apparatus, electronic device, computer-readable storage medium, computer program product, and quantum chip; the method includes: determining an initial intrinsic frequency of a chip substrate; based on a comparison result between the initial intrinsic frequency and a quantum operating frequency, performing a pattern etching process on a first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface; the quantum operating frequency is the operating frequency of qubits of a quantum circuit, the second surface and the first surface are opposite, and the target pattern is the pattern when the difference between the intrinsic frequency and the quantum operating frequency of the chip substrate is the largest; performing a preparation process for the quantum circuit on the second surface of the chip substrate that has undergone the pattern etching process to obtain a quantum chip. Through the present application, the influence of the intrinsic frequency of the chip substrate on the coherence of qubits can be reduced, the coherence time of the quantum chip can be extended, and the computing power of the quantum chip can be increased.

Description

Technical Field

[0001] This application relates to chip processing technology, and in particular, to a chip processing method, apparatus, electronic device, computer-readable storage medium, computer program product, and quantum chip. Background Art

[0002] Since quantum computing uses the principle of superposition states for computing, quantum computing has attracted great interest in the academic and industrial communities due to its more powerful computing ability than traditional computers for specific problems. The computing ability of quantum computing mainly depends on the relaxation time and scalability. To achieve good scalability, superconducting materials are usually selected to fabricate non-linear circuits on a substrate to construct quantum bits. At this time, an important factor affecting the relaxation time of quantum bits is the substrate eigenmode.

[0003] Due to the influence of the substrate eigenmode on the coherence of quantum bits, the relaxation time is short, thus limiting the computing ability of quantum computing. There is no effective solution to this problem in the related art. Summary of the Invention

[0004] Embodiments of this application provide a chip processing method, apparatus, electronic device, computer-readable storage medium, computer program product, and quantum chip, which can reduce the influence of the eigenfrequency of the chip substrate on the coherence of quantum bits, extend the coherence time of the quantum chip, and increase the computing ability of the quantum chip.

[0005] The technical solution of the embodiments of this application is implemented as follows:

[0006] Embodiments of this application provide a chip processing method, including:

[0007] Determine the initial eigenfrequency of the chip substrate;

[0008] Based on the comparison result between the initial eigenfrequency and the quantum working frequency, perform pattern etching treatment on the first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface;

[0009] Wherein, the quantum working frequency is the working frequency of the quantum bits of the quantum circuit, the second surface and the first surface are opposite, and the target pattern is the pattern when the difference between the eigenfrequency of the chip substrate and the quantum working frequency is the largest;

[0010] Perform preparation processing for the quantum circuit on the second surface of the chip substrate after the pattern etching treatment to obtain a quantum chip.

[0011] Embodiments of this application provide a chip processing apparatus, including:.

[0012] A determination module, configured to determine the initial intrinsic frequency of the chip substrate;

[0013] An etching module, configured to perform a pattern etching process on the first surface of the chip substrate based on a comparison result between the initial intrinsic frequency and the quantum operating frequency, so as to obtain a chip substrate with a complete second surface and a target pattern on the first surface;

[0014] Wherein, the quantum operating frequency is the operating frequency of qubits of the quantum circuit, the second surface is opposite to the first surface, and the target pattern is the pattern when the difference between the intrinsic frequency of the chip substrate and the quantum operating frequency is the largest;

[0015] A preparation module, configured to perform a preparation process for the quantum circuit on the second surface of the chip substrate that has undergone the pattern etching process, so as to obtain a quantum chip.

[0016] In the above solution, the determination module is further configured to: when the first surface of the chip substrate is rectangular, obtain the length and width of the first surface; and determine the initial intrinsic frequency of the chip substrate based on the length and width of the first surface.

[0017] In the above solution, the determination module is further configured to: square the length to obtain a first squared result, and square the width to obtain a second squared result; determine a first ratio of the squared result of the pi constant to the first squared result and a second ratio of the squared result of the pi constant to the second squared result; perform a square root operation on the sum result of the first ratio and the second ratio to obtain a square root result; and use the ratio of the square root result to the substrate constant as the initial intrinsic frequency, where the substrate constant is obtained based on the magnetic permeability of the chip substrate and the dielectric constant of the chip substrate.

[0018] In the above solution, the etching module is further configured to: before performing a pattern etching process on the first surface of the chip substrate based on a comparison result between the initial intrinsic frequency and the quantum operating frequency to obtain a chip substrate with a complete second surface and a target pattern on the first surface, when the initial intrinsic frequency is less than the quantum operating frequency, obtain the target pattern of the first surface when the intrinsic frequency of the chip substrate reaches the minimum value; and when the initial intrinsic frequency is not less than the quantum operating frequency, obtain the target pattern of the first surface when the intrinsic frequency of the chip substrate reaches the maximum value.

[0019] In the above solution, when the initial intrinsic frequency is less than the quantum operating frequency, the target pattern has a cubic depression at the center position of the first surface. When the initial intrinsic frequency is not less than the quantum operating frequency, the target pattern has a cubic protrusion at the center position of the first surface.

[0020] In the above solution, the etching module is further configured to: obtain the geometric parameters of the chip substrate, the material of the chip substrate, and multiple candidate patterns of the chip substrate; call a first neural network model to perform the following processing: obtain the geometric features corresponding to the geometric parameters, the material features corresponding to the material, and the pattern features of each candidate pattern; for each candidate pattern, perform a fusion process on the geometric features, the material features, and the pattern features of the candidate pattern to obtain a first fusion feature, and perform a first mapping process on the first fusion feature to obtain the predicted intrinsic frequency of the candidate pattern; sort the predicted intrinsic frequencies of the multiple candidate patterns from small to large, and use the candidate pattern corresponding to the predicted intrinsic frequency ranked first as the target pattern.

[0021] In the above solution, the etching module is further configured to: obtain the geometric parameters of the chip substrate, the material of the chip substrate, and multiple candidate patterns of the chip substrate; call a first neural network model to perform the following processing: obtain the geometric features corresponding to the geometric parameters, the material features corresponding to the material, and the pattern features of each candidate pattern; for each candidate pattern, perform a fusion process on the geometric features, the material features, and the pattern features of the candidate pattern to obtain a first fusion feature, and perform a first mapping process on the first fusion feature to obtain the predicted intrinsic frequency of the candidate pattern; sort the predicted intrinsic frequencies of the multiple candidate patterns from large to small, and use the candidate pattern corresponding to the predicted intrinsic frequency ranked first as the target pattern.

[0022] In the above solution, the first surface of the chip substrate is a plane, and the etching module is further configured to: before obtaining the target pattern of the first surface when the intrinsic frequency of the chip substrate reaches the minimum value, perform multiple simulated cutting processes on the first surface of the chip substrate until the first surface of the chip substrate becomes a plane again; for the first surface of the chip substrate obtained by each simulated cutting process, perform the following processing: simulate the propagation of electromagnetic waves on the first surface of the chip substrate, and obtain the transmission frequency of the electromagnetic waves when resonance occurs during the propagation process; sort the transmission frequencies corresponding to each simulated cutting process from small to large, and determine the transmission frequency ranked first as the intrinsic frequency that reaches the minimum value.

[0023] In the above solution, the first surface of the chip substrate is a plane, and the etching module is further configured to: before obtaining the target pattern of the first surface when the intrinsic frequency of the chip substrate reaches the maximum value, perform multiple simulated cutting processes on the first surface of the chip substrate until the first surface of the chip substrate becomes a plane again; for the first surface of the chip substrate obtained by each simulated cutting process, perform the following processes: simulate the propagation of electromagnetic waves on the first surface of the chip substrate, and obtain the transmission frequency of the electromagnetic waves when resonance occurs during the propagation process; sort the transmission frequencies corresponding to each simulated cutting process from largest to smallest, and determine the transmission frequency ranked first as the intrinsic frequency that reaches the maximum value.

[0024] In the above solution, any one of the simulated cutting processes is any one of the following processes: obtaining a grinding wheel cutting unit, and performing simulated cutting on the first surface of the chip substrate based on the grinding wheel cutting unit; obtaining the moving trajectory of the simulated light beam on the first surface of the chip substrate and the residence time of the simulated light beam at each position during the movement, and performing simulated cutting processing on the first surface of the chip substrate based on the moving trajectory and the residence time.

[0025] An embodiment of the present application provides a quantum chip, where the chip substrate of the quantum chip includes opposite first and second surfaces;

[0026] The first surface has a target pattern, where the target pattern is the pattern when the difference between the intrinsic frequency of the chip substrate and the quantum working frequency is the largest;

[0027] The second surface is configured with a quantum circuit, where the working frequency of the quantum bits of the quantum circuit is the quantum working frequency.

[0028] An embodiment of the present application provides an electronic device, including:

[0029] A memory for storing executable instructions;

[0030] A processor, configured to implement the chip processing method provided by the embodiment of the present application when executing the executable instructions stored in the memory.

[0031] An embodiment of the present application provides a computer-readable storage medium, storing executable instructions, which are used to implement the chip processing method provided by the embodiment of the present application when being executed by a processor.

[0032] An embodiment of the present application provides a computer program product, including a computer program or instruction, where the computer program or instruction implements the chip processing method provided by the embodiment of the present application when being executed by a processor.

[0033] The embodiments of the present application have the following beneficial effects:

[0034] Based on the comparison result between the initial intrinsic frequency and the quantum operating frequency, perform a patterning etching process on the first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface. The target pattern is the pattern when the difference between the intrinsic frequency and the quantum operating frequency of the chip substrate is the largest, eliminating the influence of the intrinsic frequency of the chip substrate on the qubit coherence, thereby increasing the computing power of the quantum chip. Perform a preparation process for the quantum circuit on the second surface of the chip substrate that has undergone the patterning etching process to obtain a quantum chip. Since the pattern is etched on the first surface of the chip substrate, it does not affect the morphology and size of the second surface of the chip substrate, so the quantum circuit can be prepared normally. Description of the Drawings

[0035] Figure 1 is a schematic structural diagram of a chip processing system provided by an embodiment of the present application;

[0036] Figure 2 is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0037] Figures 3A - 3B is a schematic flowchart of a chip processing method provided by an embodiment of the present application;

[0038] Figure 4 is a schematic flowchart of a chip processing method provided by an embodiment of the present application;

[0039] Figure 5 is a cutting schematic diagram of a chip processing method provided by an embodiment of the present application;

[0040] Figure 6 is a cutting schematic diagram of a chip processing method provided by an embodiment of the present application;

[0041] Figure 7 is a schematic diagram of the change in the intrinsic frequency of a chip processing method provided by an embodiment of the present application;

[0042] Figure 8 is a cutting schematic diagram of a chip processing method provided by an embodiment of the present application;

[0043] Figure 9 is a cutting schematic diagram of a chip processing method provided by an embodiment of the present application;

[0044] Figure 10 is a schematic diagram of the change in the intrinsic frequency of a chip processing method provided by an embodiment of the present application. Detailed Embodiments

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following will further describe this application in detail in conjunction with the accompanying drawings. The described embodiments should not be regarded as limitations of this application. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

[0046] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict.

[0047] In the following description, the terms "first / second / third" are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged in a specific order or sequence when allowed, so that the embodiments of this application described here can be implemented in an order other than that illustrated or described here.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0049] Before further elaborating on the embodiments of this application, the nouns and terms involved in the embodiments of this application are described. The nouns and terms involved in the embodiments of this application are subject to the following explanations.

[0050] 1) Chip substrate eigenmode: Since the substrate of the chip is usually square, it is equivalent to forming a two-dimensional resonant cavity in the microwave band on the chip substrate, thus having its own eigenmode.

[0051] 2) Quantum computing: Quantum computing is a new computing mode that follows the laws of quantum mechanics to regulate quantum information units for computing. In contrast to traditional general-purpose computers, its theoretical model is the universal Turing machine; for a general quantum computer, its theoretical model is the universal Turing machine reinterpreted by the laws of quantum mechanics.

[0052] 3) Quantum circuit: A set of quantum gates that are non-cyclically connected (through input and output lines). The size and depth of the circuit are the number of nodes and the depth of the bottom connection graph.

[0053] 4) Quantum chip: A quantum chip is to integrate quantum circuits on a substrate, thereby carrying the function of quantum information processing.

[0054] 5) Quantum superposition state: It refers to the state in which a quantum system can be in a superposition of different quantum states.

[0055] 6) Relaxation time: The time required for a qubit to degenerate from a quantum superposition state to a classical state.

[0056] 7) Relaxation rate: The rate at which a qubit degenerates from a quantum superposition state to a classical state.

[0057] A traditional computer can only manipulate the definite state of one bit at a time, while quantum computing can manipulate superposition states using the principle of state superposition, thus greatly improving computing power. However, the superposition state based on quantum mechanics is easily disturbed by the environment and depolarizes to the classical state. The time taken for depolarization is called the relaxation time, and the length of the relaxation time directly affects the computing power of the quantum computer. In addition to the relaxation time, scalability is also an important indicator affecting quantum computing, and scalability directly determines the number of computer bits. The quantum computing scheme based on superconductivity can achieve good scalability. Usually, superconducting materials such as aluminum and tantalum are selected to prepare non-linear inductance circuits on a silicon wafer or a sapphire substrate to construct qubits.

[0058] At this time, in addition to the losses brought by the material and the substrate, the eigenmode of the substrate also affects the relaxation time of the qubit. Since the substrate is generally square, there will also be electromagnetic standing waves inside the substrate, which can form the eigenmode of the substrate. The working frequency of superconducting qubits generally works between 4 GHz and 6 GHz, while the eigenfrequency of the 8 mm * 8 mm silicon substrate often used to prepare quantum chips is 7.7 GHz, and the eigenfrequency of the 8 mm * 8 mm sapphire substrate is about 8.4 GHz. This is relatively close to the working frequency of the qubit. When the number of bits on the chip increases, the size of the chip needs to be increased. For example, 10 mm * 10 mm silicon wafers and sapphire wafers are used. At this time, the eigenfrequency of the 10 mm * 10 mm silicon wafer is 6.1 GHz, and the eigenfrequency of the 10 mm * 10 mm sapphire substrate is 6.7 GHz. At this time, the chip eigenfrequency and the qubit working frequency will be closer.

[0059] When implementing the embodiments of the present application, the applicant found that for a superconducting qubit chip, the relaxation rate caused by the substrate mode can be seen in formula (1):

[0060]

[0061] where g represents the coupling strength between the qubit and the chip substrate mode, Δ represents the frequency difference between the working frequency of the qubit and the eigenfrequency of the substrate, and κ represents the attenuation rate of the electromagnetic field mode near the qubit.

[0062] As can be seen from Equation (1), when the eigenfrequency of the substrate is close to the operating frequency of the qubit, i.e., when Δ is very small, the relaxation rate of the qubit caused by the substrate mode is very fast, significantly affecting the coherence of the qubit. Therefore, an important way to improve the coherence of the qubit is to increase the difference between the eigenfrequency of the substrate and the operating frequency of the qubit.

[0063] For a silicon substrate, in related technologies, a deep silicon etching process is used to etch periodic vias on the silicon substrate. When the period of the small holes is less than the wavelength of the electromagnetic wave, the presence of the small holes can significantly suppress the eigenmode of the chip substrate. Since the loss of the sapphire substrate is lower than that of the silicon substrate, the sapphire substrate is more widely used in quantum chips. However, for sapphire, there is no mature via process yet.

[0064] For a sapphire substrate, in related technologies, the size of the sapphire is changed. Since the operating frequency of the quantum chip is lower than the eigenfrequency of the sapphire substrate, reducing the size of the sapphire substrate can shift the eigenfrequency of the substrate to a higher frequency. For example, when the operating frequency of the quantum chip is 5 GHz, when the size of the substrate is 10 mm × 10 mm, its eigenfrequency is 6.7 GHz, and at this time Δ is 1.7 GHz. When a substrate with a size of 8 mm × 8 mm is selected, its eigenfrequency is 8.4 GHz, and at this time Δ is 3.4 GHz. A chip size of 6 mm × 6 mm can be selected, and its eigenfrequency is 11.2 GHz, and at this time Δ is 6.5 GHz. It can be seen that reducing the substrate size can significantly increase the distance between the eigenfrequency of the chip substrate and the operating frequency of the qubit. However, this method can only be used when the number of qubits is small, such as only a few qubits. When the number of qubits increases, such as hundreds of qubits, due to the sharp increase in the circuits on the chip, a large-size substrate must be selected, and the substrate size cannot be easily changed.

[0065] In summary, due to the influence of the substrate eigenmode on the coherence of the qubit, the relaxation time is short, thus limiting the computing power of quantum computing. There is no effective solution to this problem in related technologies.

[0066] The embodiments of the present application provide a chip processing method, device, electronic device, computer-readable storage medium, computer program product, and quantum chip, which can reduce the influence of the eigenfrequency of the chip substrate on the coherence of the qubit, extend the coherence time of the quantum chip, and increase the computing power of the quantum chip.

[0067] The following describes the exemplary applications of the electronic device provided in the embodiments of the present application. The device provided in the embodiments of the present application can be implemented as various types of user terminals such as laptop computers, tablet computers, desktop computers, set-top boxes, mobile devices (e.g., mobile phones, portable music players, personal digital assistants, dedicated messaging devices, portable gaming devices), etc., or can also be implemented as a server. Below, the exemplary applications when the device is implemented as a server will be described.

[0068] See Figure 1 , Figure 1 is a schematic structural diagram of the chip processing system provided in the embodiments of the present application. The terminal 400 is connected to the server 200 through the network 300. The network 300 can be a wide area network, a local area network, or a combination of both.

[0069] In some embodiments, the chip processing method provided in the embodiments of the present application can be jointly implemented by the terminal and the server. The server 200 determines the initial intrinsic frequency of the chip substrate. The server 200 compares the initial intrinsic frequency of the chip substrate with the quantum operating frequency. The server 200 determines the target pattern based on the comparison result and sends the target pattern to the terminal 400. The terminal 400 performs pattern etching on the first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface. The quantum operating frequency is the operating frequency of the qubits of the quantum circuit. The second surface is opposite to the first surface. The target pattern is the pattern when the difference between the intrinsic frequency and the quantum operating frequency of the chip substrate is the largest. The terminal 400 performs the preparation process for the quantum circuit on the second surface of the chip substrate after the pattern etching process to obtain a quantum chip.

[0070] In some embodiments, the chip processing method provided in the embodiments of the present application can also be implemented independently by the terminal or the server. Taking the independent implementation by the terminal as an example, the terminal 400 determines the initial intrinsic frequency of the chip substrate. The terminal 400 compares the initial intrinsic frequency of the chip substrate with the quantum operating frequency. The terminal 400 determines the target pattern based on the comparison result and sends the target pattern to the terminal 400. The terminal 400 performs pattern etching on the first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface. The quantum operating frequency is the operating frequency of the qubits of the quantum circuit. The second surface is opposite to the first surface. The target pattern is the pattern when the difference between the intrinsic frequency and the quantum operating frequency of the chip substrate is the largest. The terminal 400 performs the preparation process for the quantum circuit on the second surface of the chip substrate after the pattern etching process to obtain a quantum chip.

[0071] In some embodiments, the server 200 may be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It may also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, as well as big data and artificial intelligence platforms. The terminal 400 may be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, a smart voice interaction device, a smart home appliance, a vehicle terminal, an aircraft, etc., but is not limited thereto. The terminal and the server may be directly or indirectly connected through wired or wireless communication means, which are not limited in the embodiments of the present application.

[0072] In some embodiments, the terminal or the server may implement the chip processing method provided in the embodiments of the present application by running a computer program. For example, the computer program may be a native program or software module in an operating system; it may be a local (Native) application (APP, Application), that is, a program that needs to be installed in the operating system to run, such as a maintenance APP for industrial equipment; it may also be a small program, that is, a program that only needs to be downloaded to a browser environment to run; it may also be a small program that can be embedded into any APP. In short, the above computer program may be any form of application program, module or plug-in.

[0073] See Figure 2 , Figure 2 is a schematic structural diagram of an electronic device provided in the embodiments of the present application. Figure 2 The terminal 400 shown in the figure includes: at least one processor 410, a memory 450, at least one network interface 420, and a user interface 430. Each component in the terminal 400 is coupled together through a bus system 440. It can be understood that the bus system 440 is used to realize the connection and communication between these components. In addition to including a data bus, the bus system 440 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clear illustration, in Figure 2 all kinds of buses are labeled as the bus system 440.

[0074] The processor 410 may be an integrated circuit chip with signal processing capabilities, such as a general-purpose processor, a digital signal processor (DSP, Digital Signal Processor), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or any conventional processor, etc.

[0075] The user interface 430 includes one or more output devices 431 that enable the presentation of media content, including one or more speakers and / or one or more visual display screens. The user interface 430 also includes one or more input devices 432, including user interface components that facilitate user input, such as a keyboard, a mouse, a microphone, a touch screen display, a camera, and other input buttons and controls.

[0076] The memory 450 can be removable, non-removable, or a combination thereof. Exemplary hardware devices include solid state memory, hard disk drives, optical disk drives, etc. The memory 450 optionally includes one or more storage devices that are physically remote from the processor 410.

[0077] The memory 450 includes volatile memory or non-volatile memory, and may also include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), and the volatile memory can be random access memory (RAM). The memory 450 described in the embodiments of the present application is intended to include any suitable type of memory.

[0078] In some embodiments, the memory 450 is capable of storing data to support various operations. Examples of such data include programs, modules, and data structures, or subsets or supersets thereof, which are described below by way of example.

[0079] An operating system 451, including system programs for processing various basic system services and performing hardware-related tasks, such as a framework layer, a core library layer, a driver layer, etc., for implementing various basic services and processing hardware-based tasks;

[0080] A network communication module 452 for reaching other computing devices via one or more (wired or wireless) network interfaces 420. Exemplary network interfaces 420 include: Bluetooth, Wi-Fi (Wireless Fidelity), and USB (Universal Serial Bus), etc.;

[0081] A presentation module 453 for enabling the presentation of information (such as a user interface for operating peripheral devices and displaying content and information) via one or more output devices 431 associated with the user interface 430 (such as a display screen, a speaker, etc.);

[0082] An input processing module 454 for detecting and translating one or more user inputs or interactions from one or more of one or more input devices 432.

[0083] In some embodiments, the device provided by the embodiments of the present application may be implemented in software. Figure 2 Shown in the memory 450 is a chip processing device 455, which may be software in the form of a program and a plug-in, etc., including the following software modules: a determination module 4551, an etching module 4552, and a preparation module 4553. These modules are logical, and thus can be arbitrarily combined or further split according to the functions to be implemented. The functions of each module will be described below.

[0084] The chip processing method provided by the embodiments of the present application will be described in combination with the exemplary applications and implementations of the terminals provided by the embodiments of the present application.

[0085] See Figure 3A , Figure 3A is a schematic flowchart of the chip processing method provided by the embodiments of the present application, which will be described in combination with Figure 3A the steps 101 to 103 shown.

[0086] In step 101, determine the initial intrinsic frequency of the chip substrate.

[0087] In some embodiments, the initial intrinsic frequency of the chip substrate determined in step 101 can be achieved through the following technical solution: when the first surface of the chip substrate is rectangular, obtain the length and width of the first surface. For example, when the first surface is rectangular, obtain the length and width of the rectangle. Based on the length and width of the first surface, determine the initial intrinsic frequency of the chip substrate. Since the thickness of the chip substrate is much smaller than the length and width of the chip substrate, the chip substrate can be regarded as a two-dimensional resonant cavity to calculate the initial intrinsic frequency.

[0088] In some embodiments, the above-mentioned determination of the initial intrinsic frequency of the chip substrate based on the length and width of the first surface can be achieved through the following technical solution: square the length to obtain a first squared result, and square the width to obtain a second squared result; determine a first ratio of the squared result of the pi constant to the first squared result, and a second ratio of the squared result of the pi constant to the second squared result; take the square root of the sum result of the first ratio and the second ratio to obtain a square root result; use the ratio of the square root result to the substrate constant as the initial intrinsic frequency, where the substrate constant is obtained based on the magnetic permeability of the chip substrate and the dielectric constant of the chip substrate. Through the embodiments of the present application, the chip substrate can be regarded as a two-dimensional resonant cavity to calculate the initial intrinsic frequency, so that the initial intrinsic frequency can be accurately and effectively determined.

[0089] As an example, when regarding the chip substrate as a two-dimensional resonant cavity to calculate the initial intrinsic frequency, the calculation of the initial intrinsic frequency can refer to formula (2):

[0090]

[0091] wherein, μ and ε are the permeability and permittivity of the chip substrate respectively, l and w are the length and width of the chip substrate respectively, f is the initial eigenfrequency, and the substrate constant is

[0092] In step 102, based on the comparison result between the initial eigenfrequency and the quantum working frequency, pattern etching treatment is performed on the first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface.

[0093] As an example, the quantum working frequency is the working frequency of the qubits of the quantum circuit, the second surface is opposite to the first surface, and the target pattern is the pattern when the difference between the eigenfrequency of the chip substrate and the quantum working frequency is the largest.

[0094] As an example, before step 102, etching treatment needs to be performed on the chip substrate. The initial chip substrate is a cube, and the thickness (height) of the cube is much smaller than the length and width of the cube. The initial chip substrate has two surfaces determined by the long side and the wide side (two opposite faces of the cube). The first surface is any one of the two surfaces, and the second surface is the other surface. The surface to be pattern-etched is regarded as the back of the chip substrate, and the surface that is not pattern-etched and remains intact during the etching process is regarded as the front of the chip substrate.

[0095] In step 103, preparation treatment for the quantum circuit is performed on the second surface of the chip substrate after pattern etching treatment to obtain a quantum chip.

[0096] In some embodiments, referring to Figure 3B , Figure 3B is a schematic flowchart of the chip processing method provided by the embodiments of the present application. Before performing pattern etching treatment on the first surface of the chip substrate based on the comparison result between the initial eigenfrequency and the quantum working frequency in step 102 to obtain a chip substrate with a complete second surface and a target pattern on the first surface, perform Figure 3B the steps 104 to 105 shown.

[0097] In step 104, when the initial eigenfrequency is less than the quantum working frequency, obtain the target pattern of the first surface when the eigenfrequency of the chip substrate reaches the minimum value.

[0098] In step 105, when the initial eigenfrequency is not less than the quantum working frequency, obtain the target pattern of the first surface when the eigenfrequency of the chip substrate reaches the maximum value.

[0099] As an example, according to the comparison result of whether the quantum working frequency is less than or not less than the intrinsic frequency, the substrate etching method is determined. Specifically, the target pattern to be etched is determined. When the quantum working frequency is less than the intrinsic frequency of the chip substrate, the target pattern should be etched so that the intrinsic frequency of the chip substrate moves to a higher frequency, that is, the target pattern on the first surface when the intrinsic frequency of the chip substrate reaches the maximum value is obtained. When the quantum working frequency is not less than the intrinsic frequency of the chip substrate, the target pattern should be etched so that the intrinsic frequency of the chip substrate moves to a lower frequency, that is, the target pattern on the first surface when the intrinsic frequency of the chip substrate reaches the minimum value is obtained.

[0100] In some embodiments, when the initial intrinsic frequency is less than the quantum working frequency, the target pattern has a cubic depression at the center position of the first surface. When the initial intrinsic frequency is not less than the quantum working frequency, the target pattern has a cubic boss at the center position of the first surface. Through the embodiments of the present application, the minimization or maximization of the intrinsic frequency can be achieved through a simple target pattern, effectively improving the pattern etching efficiency.

[0101] As an example, when the intrinsic frequency of the substrate is not less than the working frequency of the qubit, refer to Figures 5 - 6 , Figures 5 - 6 which schematically shows a method of processing a groove on the back surface of the chip substrate using a dicing machine grinding wheel. When cutting, the cutting depth of the grinding wheel on the chip substrate can be set to 330 microns. At this time, the remaining thickness of the chip substrate is 100 microns. When the dicing machine grinding wheel cuts from one side of the chip substrate to the other side, the lateral removal amount is 200 microns. That is, each time of cutting can cut out a groove with a width of 200 microns and a depth of 330 microns, and the back surface of the chip substrate can be processed into a boss shape as shown in Figure 5 . Further, the periphery of the back surface of the chip substrate can be removed in sequence to be processed into a boss shape with a central protrusion as shown in Figure 6 . Figure 7 shows the relationship between the intrinsic frequency of the substrate and the material removal amount of the chip substrate. As the removal amount of both sides or the periphery of the back surface of the chip substrate increases, the intrinsic frequency of the chip substrate will increase significantly. Then, as the removal amount continues to increase, the intrinsic frequency of the chip substrate will start to decrease until the 330-micron-thick material on the back surface is completely removed. At this time, the side length of the chip substrate is 10 mm, and the thickness of the chip substrate is 100 microns, which is equivalent to obtaining the target pattern corresponding to the maximum value of the intrinsic frequency in Figure 7 , that is, the central protrusion cubic boss as shown in Figure 6 .

[0102] As an example, when the intrinsic frequency of the substrate is less than the working frequency of the qubit, refer to Figure 8 , Figure 8Schematically shows a way to process grooves on the back surface of a sapphire substrate using a dicing machine grinding wheel. At this time, the cutting parameters of the dicing machine grinding wheel can be set. For example, grooves are etched in the middle part. Similarly, each cut can obtain a groove with a width of 200 microns and a depth of 330 microns. By precisely controlling the number of cuts, the shape shown in Figure 8 can be obtained after multiple cuts. It is also possible to only process the central area. However, since the dicing machine can only completely cut from one side of the chip to the other side. Refer to Figure 10 , Figure 10 shows the relationship between the intrinsic frequency of the sapphire substrate and the removal amount of the sapphire substrate. As the material removal amount increases, the intrinsic frequency of the chip substrate first decreases significantly, and then as the removal amount continues to increase, the intrinsic frequency of the chip substrate begins to rise, and finally reaches a situation very close to the intrinsic frequency of the initial chip substrate. Therefore, in actual processing, it is also necessary to precisely control the material removal amount to reach the maximum value of the difference between the intrinsic frequency of the chip substrate and the working frequency of the qubit, which is equivalent to obtaining the target pattern corresponding to the minimum intrinsic frequency in Figure 10 , that is, the cube depression with a central protrusion shown in Figure 8 .

[0103] In some embodiments, the above-mentioned obtaining of the target pattern of the first surface when the intrinsic frequency of the chip substrate obtains the minimum value can be achieved through the following technical solutions: obtaining the geometric parameters of the chip substrate, the material of the chip substrate, and multiple candidate patterns of the chip substrate; calling a first neural network model to perform the following processing: obtaining geometric features corresponding to the geometric parameters, material features corresponding to the material, and pattern features of each candidate pattern; for each candidate pattern, fusing the geometric features, material features, and pattern features of the candidate pattern to obtain a first fusion feature, and performing a first mapping process on the first fusion feature to obtain the predicted intrinsic frequency of the candidate pattern; sorting the predicted intrinsic frequencies of multiple candidate patterns from small to large, and using the candidate pattern corresponding to the predicted intrinsic frequency ranked first as the target pattern, so that the target pattern of the chip substrate when the intrinsic frequency is the smallest can be obtained.

[0104] In some embodiments, the target pattern of the first surface when the intrinsic frequency of the chip substrate obtains the maximum value can be achieved through the following technical solution: obtaining the geometric parameters of the chip substrate, the material of the chip substrate, and multiple candidate patterns of the chip substrate; calling a first neural network model to perform the following processing: obtaining the geometric features corresponding to the geometric parameters, the material features corresponding to the material, and the pattern features of each candidate pattern; for each candidate pattern, performing a fusion process on the geometric features, the material features, and the pattern features of the candidate pattern to obtain a first fusion feature, and performing a first mapping process on the first fusion feature to obtain the predicted intrinsic frequency of the candidate pattern; sorting the predicted intrinsic frequencies of the multiple candidate patterns from largest to smallest, and using the candidate pattern corresponding to the predicted intrinsic frequency ranked first as the target pattern, so that the target pattern of the chip substrate when the intrinsic frequency is the largest can be obtained.

[0105] Predict the intrinsic frequency of each candidate pattern by means of artificial intelligence, so as to select the candidate pattern corresponding to the maximum intrinsic frequency as the target pattern or select the candidate pattern corresponding to the minimum intrinsic frequency as the target pattern, improving the acquisition efficiency of the target pattern to improve the pattern etching efficiency.

[0106] As an example, obtain the sample geometric parameters of the sample chip substrate, the sample material of the sample chip substrate, and multiple sample candidate patterns of the sample chip substrate; call the initialized first neural network model to perform the following processing: obtain the sample geometric features corresponding to the sample geometric parameters, the sample material features corresponding to the sample material, and the sample pattern features of each sample candidate pattern; for each sample candidate pattern, perform a fusion process on the sample geometric features, the sample material features, and the sample pattern features of the sample candidate pattern to obtain a first sample fusion feature, and perform a first mapping process on the first sample fusion feature to obtain the predicted intrinsic frequency of the sample candidate pattern, determine the error between the predicted intrinsic frequency of the sample candidate pattern and the marked intrinsic frequency of the sample candidate pattern, update the parameters of the first neural network model based on the error, and use the first neural network model updated when the error converges to the minimum value as the first neural network model to be called subsequently.

[0107] In some embodiments, the first surface of the chip substrate is a plane. Before obtaining the target pattern of the first surface when the intrinsic frequency of the chip substrate obtains the minimum value, perform multiple simulated cutting processes on the first surface of the chip substrate until the first surface of the chip substrate becomes a plane again; for the first surface of the chip substrate obtained by each simulated cutting process, perform the following processing: simulate the propagation of electromagnetic waves on the first surface of the chip substrate, and obtain the transmission frequency of the electromagnetic waves when resonance occurs during the propagation process; sort the transmission frequencies corresponding to each simulated cutting process from smallest to largest, and determine the transmission frequency ranked first as the intrinsic frequency that obtains the minimum value.

[0108] As an example, the chip substrate is a cuboid with an initial thickness. Multiple simulated cutting processes are performed on the first surface of the chip substrate, that is, it is not a real cut on the chip substrate, but a simulated cut, to obtain the first surface of the chip substrate after cutting until the first surface of the chip substrate becomes a plane again, which is equivalent to the chip substrate becoming a cuboid again, except that the thickness is reduced compared to the initial one. For each simulated cut, a first surface with different patterns can be obtained. The electromagnetic wave is simulated to propagate on the first surface of the chip substrate. Through simulation software, the simulation propagation of the electromagnetic wave on the first surfaces with various patterns can be realized, and the transmission frequency of the electromagnetic wave when resonance occurs during the propagation process is obtained as the eigenfrequency of the corresponding pattern. The transmission frequencies corresponding to each simulated cutting process are sorted from small to large, and the transmission frequency ranked first is determined as the eigenfrequency with the minimum value, that is, the pattern corresponding to the transmission frequency ranked first is used as the target pattern.

[0109] In some embodiments, the first surface of the chip substrate is a plane. Before obtaining the target pattern of the first surface when the eigenfrequency of the chip substrate reaches the maximum value, multiple simulated cutting processes are performed on the first surface of the chip substrate until the first surface of the chip substrate becomes a plane again. For the first surface of the chip substrate obtained by each simulated cutting process, the following processing is performed: The electromagnetic wave is simulated to propagate on the first surface of the chip substrate, and the transmission frequency of the electromagnetic wave when resonance occurs during the propagation process is obtained. The transmission frequencies corresponding to each simulated cutting process are sorted from large to small, and the transmission frequency ranked first is determined as the eigenfrequency with the maximum value.

[0110] As an example, the chip substrate is a cuboid with an initial thickness. Multiple simulated cutting processes are performed on the first surface of the chip substrate, that is, it is not a real cut on the chip substrate, but a simulated cut, to obtain the first surface of the chip substrate after cutting until the first surface of the chip substrate becomes a plane again, which is equivalent to the chip substrate becoming a cuboid again, except that the thickness is reduced compared to the initial one. For each simulated cut, a first surface with different patterns can be obtained. The electromagnetic wave is simulated to propagate on the first surface of the chip substrate. Through simulation software, the simulation propagation of the electromagnetic wave on the first surfaces with various patterns can be realized, and the transmission frequency of the electromagnetic wave when resonance occurs during the propagation process is obtained as the eigenfrequency of the corresponding pattern. The transmission frequencies corresponding to each simulated cutting process are sorted from large to small, and the transmission frequency ranked first is determined as the eigenfrequency with the maximum value, that is, the pattern corresponding to the transmission frequency ranked first is used as the target pattern.

[0111] Through the embodiments of the present application, multiple simulation cuts can be performed to obtain multiple first surfaces with different patterns after simulation cutting. By means of simulation, the eigenfrequencies corresponding to the first surfaces of each pattern are tested, so as to determine the pattern with the maximum or minimum eigenfrequency as the target pattern, and the target pattern can be accurately obtained.

[0112] In some embodiments, any one of the following processes is performed for any one simulation cut: Obtain a grinding wheel cutting unit, and perform simulation cutting on the first surface of the chip substrate based on the grinding wheel cutting unit. For example, use the microscope system built in the dicing machine to measure the position of the chip substrate and determine the height from the chip substrate to the grinding wheel. According to the preset cutting parameters of the grinding wheel for each cut of the chip substrate. Taking a square chip substrate with a side length of 10 mm and a thickness of 430 μm as an example (grinding wheel cutting unit), for a chip substrate with a thickness of 430 μm, when cutting, the cutting depth of the grinding wheel on the chip substrate can be set to 330 μm, and the remaining thickness of the chip substrate at this time is 100 μm. When the dicing machine grinding wheel cuts from one side of the chip substrate to the other side, the lateral removal amount is 200 μm, that is, each cut can cut out a groove with a width of 200 μm and a depth of 330 μm; Obtain the movement trajectory of the simulated light beam on the first surface of the chip substrate and the residence time of the simulated light beam at each position during the movement, and perform simulation cutting on the first surface of the chip substrate based on the movement trajectory and the residence time. For example, a focused plasma or laser can also be used to process the center of the chip. First, accurately control the position of the focused plasma on the chip substrate or the position of the laser beam focus on the chip substrate, and then the program controls the movement trajectory of the focused plasma or laser beam and the residence time at each position on the substrate, so as to remove the material on the chip substrate, and finally process a chip substrate with a groove in the middle as Figure 9 shown.

[0113] In some embodiments, the chip substrate of the quantum chip includes opposite first and second surfaces; the first surface has a target pattern, where the target pattern is the pattern when the difference between the eigenfrequency of the chip substrate and the quantum working frequency is the largest; the second surface is configured with a quantum circuit, where the working frequency of the qubits of the quantum circuit is the quantum working frequency.

[0114] As an example, first determine the initial intrinsic frequency of the chip substrate, and then, based on the comparison result between the initial intrinsic frequency and the quantum operating frequency, perform a patterning etching process on the first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface. The quantum operating frequency is the operating frequency of the qubits of the quantum circuit. The second surface is opposite to the first surface. The target pattern is the pattern when the difference between the intrinsic frequency of the chip substrate and the quantum operating frequency is the largest. Finally, perform a preparation process for the quantum circuit on the second surface of the chip substrate after the patterning etching process to obtain a quantum chip.

[0115] Based on the comparison result between the initial intrinsic frequency and the quantum operating frequency, perform a patterning etching process on the first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface. The target pattern is the pattern when the difference between the intrinsic frequency of the chip substrate and the quantum operating frequency is the largest. Eliminate the influence of the intrinsic frequency of the chip substrate on the qubit coherence, thereby increasing the computing power of the quantum chip. Perform a preparation process for the quantum circuit on the second surface of the chip substrate after the patterning etching process to obtain a quantum chip. Since patterning is etched on the first surface of the chip substrate, it does not affect the morphology and size of the second surface of the chip substrate, so that the quantum circuit can be prepared normally.

[0116] Next, an exemplary application of the embodiments of the present application in a practical application scenario will be described.

[0117] In some embodiments, the chip processing method provided by the embodiments of the present application can be jointly implemented by a terminal and a server. The server determines the initial intrinsic frequency of the chip substrate, the server compares the initial intrinsic frequency of the chip substrate with the quantum operating frequency, the server determines the target pattern based on the comparison result, and sends the target pattern to the terminal. The terminal performs a patterning etching process on the first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface. The quantum operating frequency is the operating frequency of the qubits of the quantum circuit. The second surface is opposite to the first surface. The target pattern is the pattern when the difference between the intrinsic frequency of the chip substrate and the quantum operating frequency is the largest. The terminal performs a preparation process for the quantum circuit on the second surface of the chip substrate after the patterning etching process to obtain a quantum chip.

[0118] The embodiments of the present application adjust the intrinsic frequency of the substrate by etching a pattern on the back of the substrate to change the overall shape of the substrate, increasing the distance between the qubit operating frequency and the intrinsic frequency of the substrate, which can significantly reduce the influence of the substrate mode on the qubit coherence and extend the qubit coherence time.

[0119] The chip processing method provided by the embodiments of the present application is to use the pattern etched on the back of the substrate to change the eigenfrequency of the intrinsic mode of the substrate, so as to increase the difference between the working frequency of the qubit and the eigenfrequency of the substrate. In this way, the influence of the intrinsic mode of the chip substrate on the coherence of the qubit can be reduced, and the coherence time can be extended.

[0120] See Figure 4 , Figure 4 is a schematic flow chart of the chip processing method provided by the embodiments of the present application. In step 201, the initial eigenfrequency of the chip substrate is calculated. Specifically, since the thickness of the chip substrate is much smaller than the length and width of the chip, the chip substrate can be regarded as a two-dimensional resonant cavity. The calculation of the initial eigenfrequency can refer to formula (3):

[0121]

[0122] where μ and ε are the magnetic permeability and dielectric constant of the chip substrate respectively, and l and w are the length and width of the chip substrate respectively.

[0123] The eigenfrequency of the chip substrate can also be output by using simulation software. After obtaining the eigenfrequency of the chip substrate, the initial eigenfrequency is compared with the working frequency of the qubit.

[0124] In step 202, according to the comparison result of whether the working frequency of the quantum chip is higher than or lower than the eigenfrequency, the substrate etching method is determined. Specifically, the target pattern to be etched is determined. When the working frequency of the qubit is less than the eigenfrequency of the chip substrate, the target pattern should be etched to move the eigenfrequency of the chip substrate to a higher frequency. When the working frequency of the qubit is not less than the eigenfrequency of the chip substrate, the target pattern should be etched to move the eigenfrequency of the chip substrate to a lower frequency.

[0125] In step 203, ion cutting, laser cutting or mechanical dicing is used to etch the chip substrate. Specifically, ion cutting, laser cutting or mechanical dicing is used to etch the target pattern on the back of the chip substrate, such as etching a groove structure or a boss structure, and precisely controlling the size of the groove or boss so that the difference between the eigenfrequency of the chip substrate and the working frequency of the qubit reaches the maximum.

[0126] In step 204, a quantum circuit is fabricated on the front of the chip substrate to obtain a quantum chip. Specifically, since the front size and morphology are not affected by the pattern etching, a qubit circuit can be fabricated on the front. The qubit circuit includes structures such as a readout circuit, a filter, a resonator, and a Josephson junction.

[0127] In step 205, the quantum chip is encapsulated and cryogenic test processing is performed on the quantum chip. Specifically, the quantum chip is placed in a refrigerator and the quantum algorithm is run.

[0128] In some embodiments, when the intrinsic frequency of the substrate is not less than the operating frequency of the qubit, refer to Figures 5 - 6 , Figures 5 - 6 Schematically shows the way of using a dicing machine grinding wheel to process grooves on the back of the sapphire substrate. This process can be directly completed using a commercial dicing machine. First, the front of the sapphire is attached to a special iron ring with a blue film, and then the back of the sapphire is placed in the dicing machine facing the direction of the grinding wheel. Then, the position of the sapphire is measured using the microscope system built into the dicing machine to determine the height of the sapphire from the grinding wheel. According to the set cutting parameters for the sapphire calibrated in advance for each cut of the grinding wheel. Taking a square sapphire with a side length of 10 mm and a thickness of 430 μm as an example, for a 430-μm-thick sapphire substrate, when cutting, the cutting depth of the grinding wheel on the sapphire can be set to 330 μm, and at this time the remaining thickness of the sapphire is 100 μm. When the dicing machine grinding wheel cuts from one side of the sapphire to the other side, the lateral removal amount is 200 μm, that is, each cut can cut out a groove with a width of 200 μm and a depth of 330 μm, and the back of the sapphire can be processed into a Figure 5 shown boss shape. Further, the periphery of the back of the sapphire can also be removed in turn to be processed into a Figure 6 shown boss shape with a central protrusion.

[0129] In some embodiments, Figure 7 shows the relationship between the intrinsic frequency of the sapphire substrate and the removal amount of the sapphire substrate. As the removal amount on both sides or the periphery of the back of the sapphire increases, the intrinsic frequency of the sapphire will increase significantly. After that, as the removal amount continues to increase, the structure of the sapphire is getting closer and closer to a thinner complete sapphire, and then the intrinsic frequency of the sapphire will start to decrease until the 330-μm-thick sapphire on the back is completely removed. At this time, the size of the sapphire is 10 mm in side length and 100 μm in thickness. At this time, the difference in the intrinsic frequency of the sapphire and the intrinsic frequency when the thickness is 430 μm is relatively small. Therefore, in actual operation, it is necessary to accurately select the appropriate removal amount to make the difference between the intrinsic frequency of the sapphire and the operating frequency of the qubit the largest.

[0130] In some embodiments, when the intrinsic frequency of the substrate is not higher than the operating frequency of the qubit, the intrinsic frequency of the substrate can be further reduced. Figure 8 Schematically shows the way of using a dicing machine grinding wheel to process grooves on the back of the sapphire substrate. At this time, the cutting parameters of the dicing machine grinding wheel can be set. For example, grooves are etched in the middle part. Similarly, each cut can obtain a groove with a width of 200 μm and a depth of 330 μm. By precisely controlling the number of cuts, after multiple cuts, the following can be obtainedFigure 8 The shape shown.

[0131] In some embodiments, it is also possible to process only the central region. However, since the dicing machine can only completely cut from one side of the chip to the other side of the chip. Therefore, if only the central region of the chip is processed, the dicing machine cannot be used. See Figure 9 , at this time, a focused plasma or laser can be used to process the center of the chip. First, precisely control the position of the focused plasma on the chip substrate or the position of the laser beam focus on the chip substrate, and then control the movement trajectory of the focused plasma or laser beam and the residence time at each position on the substrate by a program, so as to remove the material on the chip substrate, and finally process a chip substrate with a groove in the middle as Figure 9 shown.

[0132] In some embodiments, see Figure 10 , Figure 10 shows the relationship between the intrinsic frequency of the sapphire substrate and the removal amount of the sapphire substrate. As the material removal amount increases, the intrinsic frequency of the chip substrate will first decrease significantly, and then as the removal amount continues to increase, the intrinsic frequency of the chip substrate begins to rise, and finally reaches a situation very close to the intrinsic frequency of the initial chip substrate. Therefore, in actual processing, it is also necessary to precisely control the material removal amount to reach the maximum value of the difference between the intrinsic frequency of the chip substrate and the working frequency of the qubit.

[0133] By etching a convex or concave pattern on the back of the chip substrate in the embodiments of the present application, the intrinsic frequency of the chip substrate can be significantly increased or decreased, and the difference between the intrinsic frequency of the chip substrate and the working frequency of the qubit can be increased, thereby extending the coherence time. Since etching the pattern on the back of the chip substrate does not affect the front surface morphology and size of the chip substrate, it has no impact on the subsequent processing of the quantum chip. And there is no requirement for the type of the chip substrate. In addition to the sapphire substrate, it can also be used for silicon substrates or silicon carbide substrates, with good compatibility.

[0134] Next, continue to describe the exemplary structure of the implementation of the chip processing device 455 provided in the embodiments of the present application as a software module. In some embodiments, such as Figure 4As shown, the software modules stored in the chip processing device 455 of the memory 450 may include: a determination module 4551 for determining the initial intrinsic frequency of the chip substrate; an etching module 4554 for performing a pattern etching process on the first surface of the chip substrate based on the comparison result between the initial intrinsic frequency and the quantum working frequency, to obtain a chip substrate with a complete second surface and a target pattern on the first surface; wherein, the quantum working frequency is the working frequency of the qubits of the quantum circuit, the second surface and the first surface are opposite, and the target pattern is the pattern when the difference between the intrinsic frequency and the quantum working frequency of the chip substrate is the largest; a preparation module 4553 for performing a preparation process for the quantum circuit on the second surface of the chip substrate that has undergone the pattern etching process, to obtain a quantum chip.

[0135] In some embodiments, the determination module 4551 is further configured to: when the first surface of the chip substrate is rectangular, obtain the length and width of the first surface; and determine the initial intrinsic frequency of the chip substrate based on the length and width of the first surface.

[0136] In some embodiments, the determination module 4551 is further configured to: square the length to obtain a first squared result, and square the width to obtain a second squared result; determine a first ratio of the squared result of the pi constant to the first squared result and a second ratio of the squared result of the pi constant to the second squared result; take the square root of the sum result of the first ratio and the second ratio to obtain a square root result; and use the ratio of the square root result to the substrate constant as the initial intrinsic frequency, where the substrate constant is obtained based on the magnetic permeability and the dielectric constant of the chip substrate.

[0137] In some embodiments, the etching module 4554 is further configured to: before performing a pattern etching process on the first surface of the chip substrate based on the comparison result between the initial intrinsic frequency and the quantum working frequency to obtain a chip substrate with a complete second surface and a target pattern on the first surface, when the initial intrinsic frequency is less than the quantum working frequency, obtain the target pattern of the first surface when the intrinsic frequency of the chip substrate reaches the minimum value; and when the initial intrinsic frequency is not less than the quantum working frequency, obtain the target pattern of the first surface when the intrinsic frequency of the chip substrate reaches the maximum value.

[0138] In some embodiments, when the initial intrinsic frequency is less than the quantum working frequency, the target pattern is a cube depression at the center position of the first surface. When the initial intrinsic frequency is not less than the quantum working frequency, the target pattern is a cube protrusion at the center position of the first surface.

[0139] In some embodiments, the etching module 4554 is further configured to: before obtaining the target pattern on the first surface when the intrinsic frequency of the chip substrate reaches the minimum value, obtain the geometric parameters of the chip substrate, the material of the chip substrate, and multiple candidate patterns of the chip substrate; call the first neural network model to perform the following processing: obtain the geometric features corresponding to the geometric parameters, the material features corresponding to the material, and the pattern features of each candidate pattern; for each candidate pattern, perform a fusion process on the geometric features, the material features, and the pattern features of the candidate pattern to obtain a first fusion feature, and perform a first mapping process on the first fusion feature to obtain the predicted intrinsic frequency of the candidate pattern; sort the predicted intrinsic frequencies of the multiple candidate patterns from small to large, and use the candidate pattern corresponding to the predicted intrinsic frequency ranked first as the target pattern.

[0140] In some embodiments, the etching module 4554 is further configured to: before obtaining the target pattern on the first surface when the intrinsic frequency of the chip substrate reaches the maximum value, obtain the geometric parameters of the chip substrate, the material of the chip substrate, and multiple candidate patterns of the chip substrate; call the first neural network model to perform the following processing: obtain the geometric features corresponding to the geometric parameters, the material features corresponding to the material, and the pattern features of each candidate pattern; for each candidate pattern, perform a fusion process on the geometric features, the material features, and the pattern features of the candidate pattern to obtain a first fusion feature, and perform a first mapping process on the first fusion feature to obtain the predicted intrinsic frequency of the candidate pattern; sort the predicted intrinsic frequencies of the multiple candidate patterns from large to small, and use the candidate pattern corresponding to the predicted intrinsic frequency ranked first as the target pattern.

[0141] In some embodiments, the first surface of the chip substrate is a plane, and the etching module 4554 is further configured to: before obtaining the target pattern on the first surface when the intrinsic frequency of the chip substrate reaches the minimum value, perform multiple simulated cutting processes on the first surface of the chip substrate until the first surface of the chip substrate becomes a plane again; for the first surface of the chip substrate obtained by each simulated cutting process, perform the following processing: simulate the propagation of electromagnetic waves on the first surface of the chip substrate, and obtain the transmission frequency of the electromagnetic waves when resonance occurs during the propagation process; sort the transmission frequencies corresponding to each simulated cutting process from small to large, and determine the transmission frequency ranked first as the intrinsic frequency that reaches the minimum value.

[0142] In some embodiments, the first surface of the chip substrate is a plane. The etching module 4554 is further configured to: before obtaining the target pattern of the first surface when the intrinsic frequency of the chip substrate reaches the maximum value, perform multiple simulated cutting processes on the first surface of the chip substrate until the first surface of the chip substrate becomes a plane again; for each simulated cutting process on the first surface of the chip substrate, perform the following processes: simulate the propagation of electromagnetic waves on the first surface of the chip substrate, and obtain the transmission frequency of the electromagnetic waves when resonance occurs during the propagation; sort the transmission frequencies corresponding to each simulated cutting process from largest to smallest, and determine the transmission frequency ranked first as the intrinsic frequency that reaches the maximum value.

[0143] In some embodiments, any one of the simulated cutting processes is any one of the following processes: obtaining a grinding wheel cutting unit, and performing simulated cutting on the first surface of the chip substrate based on the grinding wheel cutting unit; obtaining the moving trajectory of the simulated light beam on the first surface of the chip substrate and the residence time of the simulated light beam at each position during the movement, and performing simulated cutting on the first surface of the chip substrate based on the moving trajectory and the residence time.

[0144] An embodiment of the present application provides a quantum chip. The chip substrate of the quantum chip includes opposite first and second surfaces; the first surface has a target pattern, where the target pattern is the pattern when the difference between the intrinsic frequency of the chip substrate and the quantum working frequency is the largest; the second surface is configured with a quantum circuit, where the working frequency of the quantum bits of the quantum circuit is the quantum working frequency.

[0145] An embodiment of the present application provides a computer program product or a computer program. The computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device executes the chip processing method described above in the embodiments of the present application.

[0146] An embodiment of the present application provides a computer-readable storage medium storing executable instructions, where the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be caused to execute the chip processing method provided in the embodiments of the present application. For example, Figures 3A - 3B the chip processing method shown.

[0147] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disc, or CD-ROM; or it may be various devices including one or any combination of the above memories.

[0148] In some embodiments, the executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including being deployed as a stand-alone program or being deployed as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0149] As an example, the executable instructions may or may not correspond to a file in a file system, may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, stored in a single file dedicated to the program in question, or, stored in multiple cooperating files (such as files that store one or more modules, subroutines, or portions of code).

[0150] As an example, the executable instructions may be deployed to execute on one computing device, or on multiple computing devices located at one site, or, on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0151] In summary, according to the embodiments of the present application, based on the comparison result between the initial intrinsic frequency and the quantum operating frequency, the first surface of the chip substrate is subjected to a patterning etching process to obtain a chip substrate with a complete second surface and a target pattern on the first surface, where the target pattern is the pattern when the difference between the intrinsic frequency and the quantum operating frequency of the chip substrate is the largest, eliminating the influence of the intrinsic frequency of the chip substrate on the coherence of qubits, thereby ensuring that the quantum circuit can operate normally. The second surface of the chip substrate after the patterning etching process is subjected to a preparation process for the quantum circuit to obtain a quantum chip. Since the pattern is etched on the first surface of the chip substrate, it does not affect the morphology and size of the second surface of the chip substrate, so that a quantum circuit can be prepared to obtain a normally operating quantum chip.

[0152] The above is only the embodiments of the present application and is not intended to limit the protection scope of the present application. Any modifications, equivalent replacements, and improvements made within the spirit and scope of the present application are all included in the protection scope of the present application.

Claims

1. A chip processing method, characterized in that, The method includes: Determining an initial intrinsic frequency of the chip substrate; Based on a comparison result between the initial intrinsic frequency and a quantum operating frequency, performing a pattern etching process on a first surface of the chip substrate to obtain a chip substrate with a complete second surface and a target pattern on the first surface; Wherein, the quantum operating frequency is the operating frequency of qubits of a quantum circuit, the second surface is opposite to the first surface, and the target pattern is the pattern of the first surface when the initial intrinsic frequency is less than the quantum operating frequency and the intrinsic frequency of the chip substrate obtains a minimum value, or when the initial intrinsic frequency is not less than the quantum operating frequency, the pattern of the first surface when the intrinsic frequency of the chip substrate obtains a maximum value; Performing a preparation process for the quantum circuit on the second surface of the chip substrate after the pattern etching process to obtain a quantum chip.

2. The method according to claim 1, wherein The determining the initial intrinsic frequency of the chip substrate includes: When the first surface of the chip substrate is rectangular, obtaining the length and width of the first surface; Based on the length and width of the first surface, determining the initial intrinsic frequency of the chip substrate.

3. The method according to claim 2, characterized in that The based on the length and width of the first surface, determining the initial intrinsic frequency of the chip substrate includes: Squaring the length to obtain a first squared result, and squaring the width to obtain a second squared result; Determining a first ratio of the squared result of the pi constant to the first squared result, and a second ratio of the squared result of the pi constant to the second squared result; Taking the square root of the sum result of the first ratio and the second ratio to obtain a square root result; Taking the ratio of the square root result to a substrate constant as the initial intrinsic frequency, where the substrate constant is obtained based on the magnetic permeability of the chip substrate and the dielectric constant of the chip substrate.

4. The method according to claim 1, characterized in that, When the intrinsic frequency of the chip substrate obtains a minimum value, the method further includes: Obtaining geometric parameters of the chip substrate, the material of the chip substrate, and multiple candidate patterns of the chip substrate; Invoking a first neural network model to perform the following process: Obtaining geometric features corresponding to the geometric parameters, material features corresponding to the material, and pattern features of each candidate pattern; For each candidate pattern, performing a fusion process on the geometric features, the material features, and the pattern features of the candidate pattern to obtain a first fusion feature, and performing a first mapping process on the first fusion feature to obtain a predicted intrinsic frequency of the candidate pattern; Sorting the predicted intrinsic frequencies of the multiple candidate patterns from small to large, and taking the candidate pattern corresponding to the predicted intrinsic frequency ranked first as the target pattern.

5. The method according to claim 1, wherein When the intrinsic frequency of the chip substrate obtains a maximum value, the method further includes: Obtaining geometric parameters of the chip substrate, the material of the chip substrate, and multiple candidate patterns of the chip substrate; Invoking a first neural network model to perform the following process: Obtain the geometric features corresponding to the geometric parameters, the material features corresponding to the material, and the pattern features of each of the candidate patterns; For each of the candidate patterns, perform a fusion process on the geometric features, the material features, and the pattern features of the candidate pattern to obtain a first fusion feature, and perform a first mapping process on the first fusion feature to obtain the predicted eigenfrequency of the candidate pattern; Sort the predicted eigenfrequencies of the multiple candidate patterns from largest to smallest, and use the candidate pattern corresponding to the predicted eigenfrequency ranked first as the target pattern.

6. The method according to claim 1, characterized in that The first surface of the chip substrate is a plane, and the method further includes: Perform multiple simulated cutting processes on the first surface of the chip substrate until the first surface of the chip substrate becomes a plane again; For the first surface of the chip substrate obtained by each simulated cutting process, perform the following process: Simulate the propagation of electromagnetic waves on the first surface of the chip substrate, and obtain the transmission frequency of the electromagnetic waves when resonance occurs during the propagation process; Sort the transmission frequencies corresponding to each simulated cutting process from smallest to largest, and determine the transmission frequency ranked first as the eigenfrequency that obtains the minimum value.

7. The method according to claim 1, wherein The first surface of the chip substrate is a plane, and the method further includes: Perform multiple simulated cutting processes on the first surface of the chip substrate until the first surface of the chip substrate becomes a plane again; For the first surface of the chip substrate obtained by each simulated cutting process, perform the following process: Simulate the propagation of electromagnetic waves on the first surface of the chip substrate, and obtain the transmission frequency of the electromagnetic waves when resonance occurs during the propagation process; Sort the transmission frequencies corresponding to each simulated cutting process from largest to smallest, and determine the transmission frequency ranked first as the eigenfrequency that obtains the maximum value.

8. The method according to claim 6 or 7, characterized in that, Any one of the simulated cutting processes is any one of the following processes: Perform simulated cutting on the first surface of the chip substrate based on a grinding wheel cutting unit; Obtain the movement trajectory of the simulated light beam on the first surface of the chip substrate and the residence time of the simulated light beam at each position during the movement process, and perform a simulated cutting process on the first surface of the chip substrate based on the movement trajectory and the residence time.

9. The method according to claim 1, wherein When the initial eigenfrequency is less than the quantum operating frequency, the target pattern has a cubic depression at the center position of the first surface; When the initial eigenfrequency is not less than the quantum operating frequency, the target pattern has a cubic protrusion at the center position of the first surface.

10. A quantum chip, characterized in that The chip substrate of the quantum chip includes a first surface and a second surface opposite to each other; The first surface has a target pattern, wherein when the initial eigenfrequency is less than the quantum operating frequency, the target pattern is the pattern of the first surface when the eigenfrequency of the chip substrate obtains the minimum value, or when the initial eigenfrequency is not less than the quantum operating frequency, the target pattern is the pattern of the first surface when the eigenfrequency of the chip substrate obtains the maximum value; The second surface is configured with a quantum circuit, wherein the operating frequency of the qubits of the quantum circuit is the quantum operating frequency.

11. A chip processing device, characterized in that, The device includes: a determination module configured to determine an initial intrinsic frequency of a chip substrate; an etching module configured to perform a patterned etching process on a first surface of the chip substrate based on a comparison result between the initial intrinsic frequency and the quantum operating frequency, so as to obtain a chip substrate with a complete second surface and a target pattern on the first surface; wherein the quantum operating frequency is the operating frequency of the qubits of the quantum circuit, the second surface and the first surface are opposite to each other, and the target pattern is the pattern of the first surface when the intrinsic frequency of the chip substrate reaches the minimum value when the initial intrinsic frequency is less than the quantum operating frequency, or the pattern of the first surface when the intrinsic frequency of the chip substrate reaches the maximum value when the initial intrinsic frequency is not less than the quantum operating frequency; a preparation module configured to perform a preparation process for the quantum circuit on the second surface of the chip substrate that has undergone the patterned etching process, so as to obtain a quantum chip.

12. An electronic device, characterized in that, The electronic device includes: a memory configured to store executable instructions; a processor configured to implement the chip processing method according to any one of claims 1 to 9 when executing the executable instructions stored in the memory.

13. A computer-readable storage medium storing executable instructions, characterized in that, The executable instructions, when executed by the processor, implement the chip processing method according to any one of claims 1 to 9.

14. A computer program product, comprising a computer program or instructions, characterized in that, The computer program or instructions, when executed by the processor, implement the chip processing method according to any one of claims 1 to 9.

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