Memory device and zq calibration method

Abstract

The embodiment of the present disclosure relates to the field of semiconductor circuit design, in particular to a memory device and a ZQ calibration method, comprising: two calibration resistance interfaces connected with the same ZQ calibration resistance; a first master chip, a plurality of cascaded first slave chips, a second master chip and a plurality of cascaded second slave chips connected with the ZQ calibration resistance, and a first transmission end and a second transmission end used for transmitting a ZQ flag signal; a recognition module used for recognizing a priority calibration chip, a delay calibration chip, a master-slave chip cascaded with the priority calibration chip, and a secondary slave chip cascaded with the delay calibration chip; in a command mode, the priority calibration chip starts calibration based on a ZQ calibration command, the delay calibration chip starts calibration based on a delayed ZQ calibration command, and after calibration is completed, the ZQ flag signal is sent through the second transmission end; and the master-slave chip and the secondary slave chip start calibration based on the ZQ flag signal, so as to realize theoretically unlimited number of multi-chip sharing the ZQ calibration resistance.

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