Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: a substrate, wherein a shallow trench isolation structure is formed in the substrate; an interlayer dielectric layer, formed on the substrate, wherein the interlayer dielectric layer covers the shallow trench isolation structure; and a second conductive interconnection structure, wherein the second conductive interconnection structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure. The technical solution of the present invention can reduce the manufacturing cost of a capacitor and improve the utilization rate of the area.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Under the existing process, MIM (Metal Insulator Metal) capacitors are made by stacking metal layer-dielectric layer-metal layer. However, the current manufacturing process of MIM capacitors is complicated, requiring 4 separate photomasks and corresponding photolithography / etching processes to complete the production, which makes it difficult to control the quality of MIM capacitors and leads to increased costs; at the same time, the MIM capacitor area and the device area (such as MOS tube) cannot overlap in the vertical direction. If a large-capacity capacitor is required, the area share of the MIM capacitor will inevitably increase, resulting in low area utilization.

[0003] Therefore, how to reduce the manufacturing cost of capacitors and improve the area utilization is an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a manufacturing method thereof, which can reduce the manufacturing cost of a capacitor and improve the utilization rate of the area.

[0005] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0006] A substrate having a shallow trench isolation structure formed therein;

[0007] An interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer covers the shallow trench isolation structure;

[0008] A second conductive interconnect structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure.

[0009] Optionally, the semiconductor device includes at least two second conductive interconnect structures.

[0010] Optionally, the second conductive interconnect structure includes a second contact plug, a second metal interconnect layer and a second through-hole plug, the second contact plug extends from the interlayer dielectric layer at least into the shallow trench isolation structure, the second metal interconnect layer is electrically connected to the second contact plug, and the adjacent second metal interconnect layer is electrically connected through the second through-hole plug.

[0011] Optionally, the semiconductor device also includes a transistor and a first conductive interconnect structure, the transistor is formed in an active area surrounded by the shallow trench isolation structure, the first conductive interconnect structure penetrates the interlayer dielectric layer and is electrically connected to the transistor; the first conductive interconnect structure includes a first contact plug, a first metal interconnect layer and a first through-hole plug, the first metal interconnect layer is electrically connected to the transistor through the first contact plug, the adjacent first metal interconnect layer is electrically connected through the first through-hole plug, the first contact plug and the second contact plug are located on the same layer, the first metal interconnect layer and the second metal interconnect layer are located on the same layer, and the first through-hole plug and the second through-hole plug are located on the same layer.

[0012] Optionally, at least one of the second contact plug, the second metal interconnection layer and the second via plug is a plate-shaped structure.

[0013] Optionally, the substrate is an SOI substrate, which includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, and the shallow trench isolation structure is formed in the semiconductor layer and contacts the insulating buried layer; or, the substrate is a single-layer semiconductor substrate, and the shallow trench isolation structure is formed in the single-layer semiconductor substrate.

[0014] Optionally, the second conductive interconnect structure extends into the buried insulating layer; or, the second conductive interconnect structure extends into the shallow trench isolation structure.

[0015] Optionally, the semiconductor device further includes:

[0016] An etch stop layer is formed between the interlayer dielectric layer, the shallow trench isolation structure and the substrate.

[0017] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0018] Providing a substrate, wherein a shallow trench isolation structure is formed in the substrate;

[0019] An interlayer dielectric layer and a second conductive interconnect structure are formed, wherein the interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the shallow trench isolation structure, and the second conductive interconnect structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure.

[0020] Optionally, the second conductive interconnect structure includes a second contact plug, a second metal interconnect layer and a second through-hole plug, the second contact plug extends from the interlayer dielectric layer at least into the shallow trench isolation structure, the second metal interconnect layer is electrically connected to the second contact plug, and the adjacent second metal interconnect layer is electrically connected through the second through-hole plug.

[0021] Optionally, a transistor is formed in the active area surrounded by the shallow trench isolation structure, and the manufacturing method of the semiconductor device also includes forming a first conductive interconnect structure, which runs through the interlayer dielectric layer and is electrically connected to the transistor; the first conductive interconnect structure includes a first contact plug, a first metal interconnect layer and a first through-hole plug, the first metal interconnect layer is electrically connected to the transistor through the first contact plug, and the adjacent first metal interconnect layer is electrically connected through the first through-hole plug; wherein the first contact plug and the second contact plug are formed simultaneously, the first metal interconnect layer and the second metal interconnect layer are formed simultaneously, and the first through-hole plug and the second through-hole plug are formed simultaneously.

[0022] Optionally, at least one of the second contact plug, the second metal interconnection layer and the second via plug is a plate-shaped structure.

[0023] Optionally, the substrate is an SOI substrate, which includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, and the shallow trench isolation structure is formed in the semiconductor layer and contacts the insulating buried layer; or, the substrate is a single-layer semiconductor substrate, and the shallow trench isolation structure is formed in the single-layer semiconductor substrate.

[0024] Optionally, the second conductive interconnect structure extends into the buried insulating layer; or, the second conductive interconnect structure extends into the shallow trench isolation structure.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] 1. The semiconductor device of the present invention comprises: a substrate having a shallow trench isolation structure formed therein; an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer covering the shallow trench isolation structure; and a second conductive interconnect structure, the second conductive interconnect structure penetrating the interlayer dielectric layer and at least extending into the shallow trench isolation structure, so that the manufacturing cost of the capacitor can be reduced and the area utilization rate can be improved.

[0027] 2. The manufacturing method of the semiconductor device of the present invention comprises providing a substrate in which a shallow trench isolation structure is formed; forming an interlayer dielectric layer and a second conductive interconnection structure, wherein the interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the shallow trench isolation structure, and the second conductive interconnection structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure, so that the manufacturing cost of the capacitor can be reduced and the area utilization rate can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

[0029] Figure 2 yes Figure 1 A perspective view of an electrode plate in the semiconductor device shown;

[0030] Figure 3 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0031] Figure 4a to Figure 4i yes Figure 3 A schematic diagram of a device in a method for manufacturing a semiconductor device is shown.

[0032] Among them, Figure 1 to Figure 4i The reference numerals are described as follows:

[0033] 11-substrate; 111-lower substrate; 112-buried insulating layer; 113-semiconductor layer; 12-shallow trench isolation structure; 13-interlayer dielectric layer; 131-first interlayer dielectric layer; 132-second interlayer dielectric layer; 133-third interlayer dielectric layer; 14-first conductive interconnect structure; 141-first contact plug; 1411-first contact hole; 142-first metal interconnect layer; 1421-first trench; 143-first via plug; 1431-first via; 15-second conductive interconnect structure; 151-second contact plug; 1511-second contact hole; 152-second metal interconnect layer; 1521-second trench; 153-second via plug; 1531-second via; 16-metal silicide layer; 17-etching stop layer. DETAILED DESCRIPTION

[0034] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0035] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, in which a shallow trench isolation structure is formed; an interlayer dielectric layer, formed on the substrate, the interlayer dielectric layer covering the shallow trench isolation structure; and a second conductive interconnect structure, the second conductive interconnect structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure.

[0036] See below Figure 1 and Figure 2 The semiconductor device provided by this embodiment is described in detail.

[0037] A shallow trench isolation structure 12 is formed in the substrate 11. The area surrounded by the shallow trench isolation structure 12 is an active area, and a transistor is formed in the active area. The shallow trench isolation structure 12 can be used to isolate the transistor. In other embodiments, other device structures can also be formed in the active area.

[0038] The top surface of the shallow trench isolation structure 12 may be flush with, slightly lower than, or slightly higher than the top surface of the substrate 11 .

[0039] exist Figure 1 In the cross-sectional view shown, an active region may be formed in the substrate 11 surrounded by the shallow trench isolation structure 12, and the transistor (not shown) may include a gate structure formed on the active region and a source region and a drain region formed in the active region on both sides of the gate structure; the gate structure includes a gate layer and a sidewall located on the sidewall of the gate layer. A gate dielectric layer is also formed between the gate structure and the substrate 11.

[0040] The substrate 11 may be a single-layer semiconductor substrate, in which case the shallow trench isolation structure 12 is formed in a portion of the thickness of the single-layer semiconductor substrate; or Figure 1 As shown, the substrate 11 is an SOI substrate, which includes a lower substrate 111, an insulating buried layer 112 and a semiconductor layer 113 from bottom to top, the shallow trench isolation structure 12 is formed in the semiconductor layer 113, and the bottom of the shallow trench isolation structure 12 can be in contact with the insulating buried layer 112, and the source region and the drain region can be formed in the entire thickness or partial thickness of the semiconductor layer 113.

[0041] The single-layer semiconductor substrate, the lower substrate 111 and the semiconductor layer 113 may be made of any appropriate semiconductor material, including but not limited to silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide and other semiconductors. The insulating buried layer 112 is, for example, a silicon oxide layer.

[0042] The interlayer dielectric layer 13 is formed on the substrate 11 , and the interlayer dielectric layer 13 covers the shallow trench isolation structure 12 and the transistor.

[0043] The semiconductor device may further include:

[0044] An etch stop layer 17 formed between the interlayer dielectric layer 13, the shallow trench isolation structure 12 and the transistor;

[0045] The metal silicide layer 16 may be formed on the surfaces of the gate structure, the source region and the drain region.

[0046] The semiconductor device further includes a first conductive interconnect structure 14 , which penetrates the interlayer dielectric layer 13 and is electrically connected to the transistor, and a second conductive interconnect structure 15 penetrates the interlayer dielectric layer 13 and at least extends into the shallow trench isolation structure 12 .

[0047] The first conductive interconnect structure 14 is used to electrically lead out the transistor, and the first conductive interconnect structure 14 may be formed on the gate structure, the source region, and the drain region.

[0048] If the metal silicide layer 16 and the etch stop layer 17 are formed on the transistor, the first conductive interconnect structure 14 penetrates the interlayer dielectric layer 13 and the etch stop layer 17 and is electrically connected to the metal silicide layer 16, so that the first conductive interconnect structure 14 is electrically connected to the gate layer, source region or drain region of the transistor.

[0049] If the etch stop layer 17 is formed on the shallow trench isolation structure 12, then when the substrate 11 is a single-layer semiconductor substrate, the second conductive interconnect structure 15 penetrates the interlayer dielectric layer 13 and the etch stop layer 17 and extends into the shallow trench isolation structure 12, but does not penetrate the shallow trench isolation structure 12.

[0050] If the etch stop layer 17 is formed on the shallow trench isolation structure 12, then when the substrate 11 is an SOI substrate, the second conductive interconnect structure 15 can penetrate the interlayer dielectric layer 13 and the etch stop layer 17 and extend into the shallow trench isolation structure 12, but does not penetrate the shallow trench isolation structure 12; or, the second conductive interconnect structure 15 can penetrate the interlayer dielectric layer 13 and the etch stop layer 17 and extend into the shallow trench isolation structure 12, and just penetrate the shallow trench isolation structure 12; or, the second conductive interconnect structure 15 can penetrate the interlayer dielectric layer 13, the etch stop layer 17 and the shallow trench isolation structure 12 and extend into the insulating buried layer 112, but does not penetrate the insulating buried layer 112.

[0051] The semiconductor device includes at least two of the second conductive interconnect structures 15. In each of the shallow trench isolation structures 12 (i.e. Figure 1Each of the shallow trench isolation structures 12 in the cross-section shown can be formed with at least one of the second conductive interconnect structures 15; when one of the second conductive interconnect structures 15 is formed in each of the shallow trench isolation structures 12, the second conductive interconnect structures 15 in two adjacent shallow trench isolation structures 12 can serve as two electrode plates of a MIM capacitor; when at least two of the second conductive interconnect structures 15 are formed in each of the shallow trench isolation structures 12, the two adjacent second conductive interconnect structures 15 in each of the shallow trench isolation structures 12 can serve as two electrode plates of a MIM capacitor, and the second conductive interconnect structures 15 in two adjacent shallow trench isolation structures 12 can also serve as two electrode plates of a MIM capacitor.

[0052] Furthermore, when the second conductive interconnect structure 15 extends into the shallow trench isolation structure 12, two adjacent second conductive interconnect structures 15 and the interlayer dielectric layer 13, etch stop layer 17 and shallow trench isolation structure 12 therebetween may constitute a MIM capacitor; or, when the second conductive interconnect structure 15 extends into the insulating buried layer 112, two adjacent second conductive interconnect structures 15 and the interlayer dielectric layer 13, etch stop layer 17, shallow trench isolation structure 12 and insulating buried layer 112 therebetween may also constitute a MIM capacitor.

[0053] The two electrode plates of the MIM capacitor are located in the STI region and do not occupy the area of ​​the device region, that is, the MIM capacitor does not occupy any additional new area, so that the utilization rate of the chip area is improved while not affecting the area of ​​the transistor and the shallow trench isolation structure 12.

[0054] The first conductive interconnect structure 14 includes a first contact plug 141, a first metal interconnect layer 142 and a first through-hole plug 143. The first metal interconnect layer 142 is electrically connected to the transistor through the first contact plug 141, and the first metal interconnect layer 142 in an adjacent layer is electrically connected through the first through-hole plug 143. The second conductive interconnect structure 15 includes a second contact plug 151, a second metal interconnect layer 152 and a second through-hole plug 153. The second contact plug 151 extends from the interlayer dielectric layer 13 into the shallow trench isolation structure 12 or the insulating buried layer 112 at the bottom of the shallow trench isolation structure 12. The second metal interconnect layer 152 is electrically connected to the second contact plug 151, and the second metal interconnect layer 152 in an adjacent layer is electrically connected through the second through-hole plug 153.

[0055] The interlayer dielectric layer 13 is a multi-layer stacked structure, the first conductive interconnect structure 14 may include multiple layers of the first metal interconnect layers 142 and the first through-hole plugs 143 that are alternately stacked, the second conductive interconnect structure 15 may include multiple layers of the second metal interconnect layers 152 and the second through-hole plugs 153 that are alternately stacked, the first contact plugs 141, the first metal interconnect layers 142 of different layers, and the first through-hole plugs 143 of different layers are located in the interlayer dielectric layer 13 of different layers, and the second contact plugs 151, the second metal interconnect layers 152 of different layers, and the second through-hole plugs 153 of different layers are located in the interlayer dielectric layer 13 of different layers.

[0056] Preferably, the first contact plug 141 and the second contact plug 151 are located at the same layer, the first metal interconnection layer 142 and the second metal interconnection layer 152 are located at the same layer, and the first via plug 143 and the second via plug 153 are located at the same layer.

[0057] exist Figure 1 In the illustrated embodiment, the interlayer dielectric layer 13 includes a first interlayer dielectric layer 131, a second interlayer dielectric layer 132, and a third interlayer dielectric layer 133 stacked from bottom to top, the first contact plug 141 and the second contact plug 151 are located in the first interlayer dielectric layer 131, the two first metal interconnection layers 142 and the two second metal interconnection layers 152 are respectively located in the two second interlayer dielectric layers 132, and the first through-hole plug 143 and the second through-hole plug 153 are located in the third interlayer dielectric layer 133.

[0058] Since the first contact plug 141 and the second contact plug 151 are located at the same layer, the first metal interconnection layer 142 and the second metal interconnection layer 152 are located at the same layer, and the first through-hole plug 143 and the second through-hole plug 153 are located at the same layer, the first contact plug 141 and the second contact plug 151 can be formed at the same time, the first metal interconnection layer 142 and the second metal interconnection layer 152 can be formed at the same time, and the first through-hole plug 143 and the second through-hole plug 153 can be formed at the same time, that is, the first conductive interconnection structure 14 and the second conductive interconnection structure 15 can be formed at the same time, then, it is only necessary to adjust the photomask for forming the first contact plug 141 and the photomask for forming the first metal interconnection layer 15. The mask design of the layer 142 and the mask used to form the first through-hole plug 143 allows the first contact plug 141 and the second contact plug 151 to share the same mask, the first metal interconnection layer 142 and the second metal interconnection layer 152 to share the same mask, and the first through-hole plug 143 and the second through-hole plug 153 to share the same mask, that is, the first conductive interconnection structure 14 and the second conductive interconnection structure 15 share the same mask, and no additional mask is needed to manufacture the MIM capacitor, and the process of forming the first conductive interconnection structure 14 and the process of forming the second conductive interconnection structure 15 are basically the same, thereby simplifying the process steps, making the quality of the MIM capacitor easier to control, and reducing the cost.

[0059] Furthermore, since the first contact plug 141 and the second contact plug 151 are located on the same layer, the first metal interconnection layer 142 and the second metal interconnection layer 152 are located on the same layer, and the first through-hole plug 143 and the second through-hole plug 153 are located on the same layer, the second conductive interconnection structure 15 and the first conductive interconnection structure 14 can both extend to the surface of the interlayer dielectric layer 13, that is, can both extend to the surface of the semiconductor device. Therefore, the length of the second conductive interconnection structure 15 in the direction perpendicular to the substrate 11 can be made very long, so that the area of ​​the electrode plate can be made very large, and the area of ​​the electrode plate is not limited by the chip area, thereby significantly increasing the capacitance value of the MIM capacitor.

[0060] Preferably, Figure 2As shown, at least one of the second contact plug 151, the second metal interconnection layer 152 and the second through-hole plug 153 is a plate-like structure, that is, the cross-sectional shape of at least one of the second contact plug 151, the second metal interconnection layer 152 and the second through-hole plug 153 is a rectangular structure, so that the area of ​​the second conductive interconnection structure 15 as an electrode plate is increased, thereby increasing the capacitance value of the capacitor. It should be noted that the plate surfaces (i.e., the surfaces with increased areas) of adjacent plate-like structures are arranged oppositely; and the more the number of plate-like structures in each layer structure of the second conductive interconnection structure 15 is, and the longer the length of the plate surface of the plate-like structure in the direction parallel to the substrate 11 is, the larger the area of ​​the electrode plate is.

[0061] Among them, Figure 2 In the illustrated embodiment, the second contact plug 151 and the second metal interconnection layer 152 are plate-shaped structures, that is, the cross-sectional shape of the two electrode plates facing each other is a rectangle.

[0062] In summary, the present invention provides a semiconductor device, comprising: a substrate, a shallow trench isolation structure formed in the substrate; an interlayer dielectric layer formed on the substrate, the interlayer dielectric layer covering the shallow trench isolation structure; a second conductive interconnect structure, the second conductive interconnect structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure. The semiconductor device provided by the present invention can reduce the manufacturing cost of the capacitor and improve the area utilization.

[0063] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 3 ,from Figure 3 It can be seen that the method for manufacturing the semiconductor device includes:

[0064] Step S1, providing a substrate, wherein a shallow trench isolation structure is formed in the substrate;

[0065] Step S2, forming an interlayer dielectric layer and a second conductive interconnect structure, wherein the interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the shallow trench isolation structure, and the second conductive interconnect structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure.

[0066] See below Figure 2 and Figure 4a to Figure 4i The method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0067] Follow step S1, refer to Figure 4a, a substrate 11 is provided, and a shallow trench isolation structure 12 is formed in the substrate 11. The area surrounded by the shallow trench isolation structure 12 is an active area, and a transistor is formed in the active area. The shallow trench isolation structure 12 can be used to isolate the transistor. In other embodiments, other device structures can also be formed in the active area.

[0068] The top surface of the shallow trench isolation structure 12 may be flush with, slightly lower than, or slightly higher than the top surface of the substrate 11 .

[0069] exist Figure 4a In the cross-sectional view shown in , an active region may be formed in the substrate 11 surrounded by the shallow trench isolation structure 12, and the transistor (not shown) may include a gate structure formed on the active region and a source region and a drain region formed in the active region on both sides of the gate structure; the gate structure includes a gate layer and a sidewall located on the sidewall of the gate layer. A gate dielectric layer is also formed between the gate structure and the substrate 11.

[0070] The substrate 11 may be a single-layer semiconductor substrate, in which case the shallow trench isolation structure 12 is formed in a portion of the thickness of the single-layer semiconductor substrate; or Figure 4a As shown, the substrate 11 is an SOI substrate, which includes a lower substrate 111, an insulating buried layer 112 and a semiconductor layer 113 from bottom to top, the shallow trench isolation structure 12 is formed in the semiconductor layer 113, and the bottom of the shallow trench isolation structure 12 can be in contact with the insulating buried layer 112, and the source region and the drain region can be formed in the entire thickness or partial thickness of the semiconductor layer 113.

[0071] The single-layer semiconductor substrate, the lower substrate 111 and the semiconductor layer 113 may be made of any appropriate semiconductor material, including but not limited to silicon, germanium, silicon germanium, silicon germanium carbide, silicon carbide and other semiconductors. The insulating buried layer 112 is, for example, a silicon oxide layer.

[0072] See also Figure 4b Before subsequently forming the interlayer dielectric layer 13 and the second conductive interconnect structure 15, the method for manufacturing the semiconductor device may further include:

[0073] Forming a metal silicide layer 16 on the surface of the transistor, wherein the metal silicide layer 16 may be formed on the surfaces of the gate structure, the source region, and the drain region;

[0074] An etch stop layer 17 is formed, and the etch stop layer 17 covers the surface of the shallow trench isolation structure 12 and the metal silicide layer 16 .

[0075] According to step S2, refer to Figure 4c to Figure 4i, forming an interlayer dielectric layer 13 and a second conductive interconnect structure 15, wherein the interlayer dielectric layer 13 is formed on the substrate 11, the interlayer dielectric layer 13 covers the shallow trench isolation structure 12, and the second conductive interconnect structure 15 penetrates the interlayer dielectric layer 13 and at least extends into the shallow trench isolation structure 12.

[0076] The method for manufacturing a semiconductor device further includes forming a first conductive interconnect structure 14 , wherein the first conductive interconnect structure 14 penetrates the interlayer dielectric layer 13 and is electrically connected to the transistor.

[0077] The first conductive interconnect structure 14 is used to electrically lead out the transistor, and the first conductive interconnect structure 14 may be formed on the gate structure, the source region, and the drain region.

[0078] If the metal silicide layer 16 and the etch stop layer 17 are formed on the transistor, the first conductive interconnect structure 14 penetrates the interlayer dielectric layer 13 and the etch stop layer 17 and is electrically connected to the metal silicide layer 16, so that the first conductive interconnect structure 14 is electrically connected to the gate layer, source region or drain region of the transistor.

[0079] If the etch stop layer 17 is formed on the shallow trench isolation structure 12, then when the substrate 11 is a single-layer semiconductor substrate, the second conductive interconnect structure 15 penetrates the interlayer dielectric layer 13 and the etch stop layer 17 and extends into the shallow trench isolation structure 12, but does not penetrate the shallow trench isolation structure 12.

[0080] If the etch stop layer 17 is formed on the shallow trench isolation structure 12, then when the substrate 11 is an SOI substrate, the second conductive interconnect structure 15 can penetrate the interlayer dielectric layer 13 and the etch stop layer 17 and extend into the shallow trench isolation structure 12, but does not penetrate the shallow trench isolation structure 12; or, the second conductive interconnect structure 15 can penetrate the interlayer dielectric layer 13 and the etch stop layer 17 and extend into the shallow trench isolation structure 12, and just penetrate the shallow trench isolation structure 12; or, the second conductive interconnect structure 15 can penetrate the interlayer dielectric layer 13, the etch stop layer 17 and the shallow trench isolation structure 12 and extend into the insulating buried layer 112, but does not penetrate the insulating buried layer 112.

[0081] The number of the second conductive interconnect structures 15 is at least two. Figure 4iEach of the shallow trench isolation structures 12 in the cross-section shown can be formed with at least one of the second conductive interconnect structures 15; when one of the second conductive interconnect structures 15 is formed in each of the shallow trench isolation structures 12, the second conductive interconnect structures 15 in two adjacent shallow trench isolation structures 12 can serve as two electrode plates of a MIM capacitor; when at least two of the second conductive interconnect structures 15 are formed in each of the shallow trench isolation structures 12, the two adjacent second conductive interconnect structures 15 in each of the shallow trench isolation structures 12 can serve as two electrode plates of a MIM capacitor, and the second conductive interconnect structures 15 in two adjacent shallow trench isolation structures 12 can also serve as two electrode plates of a MIM capacitor.

[0082] Furthermore, when the second conductive interconnect structure 15 extends into the shallow trench isolation structure 12, two adjacent second conductive interconnect structures 15 and the interlayer dielectric layer 13, etch stop layer 17 and shallow trench isolation structure 12 therebetween may constitute a MIM capacitor; or, when the second conductive interconnect structure 15 extends into the insulating buried layer 112, two adjacent second conductive interconnect structures 15 and the interlayer dielectric layer 13, etch stop layer 17, shallow trench isolation structure 12 and insulating buried layer 112 therebetween may also constitute a MIM capacitor.

[0083] The two electrode plates of the MIM capacitor are located in the STI region and do not occupy the area of ​​the device region, that is, the MIM capacitor does not occupy any additional new area, so that the utilization rate of the chip area is improved while not affecting the area of ​​the transistor and the shallow trench isolation structure 12.

[0084] The first conductive interconnect structure 14 includes a first contact plug 141, a first metal interconnect layer 142 and a first through-hole plug 143. The first metal interconnect layer 142 is electrically connected to the transistor through the first contact plug 141, and the first metal interconnect layer 142 in an adjacent layer is electrically connected through the first through-hole plug 143. The second conductive interconnect structure 15 includes a second contact plug 151, a second metal interconnect layer 152 and a second through-hole plug 153. The second contact plug 151 extends from the interlayer dielectric layer 13 into the shallow trench isolation structure 12 or the insulating buried layer 112 at the bottom of the shallow trench isolation structure 12. The second metal interconnect layer 152 is electrically connected to the second contact plug 151, and the second metal interconnect layer 152 in an adjacent layer is electrically connected through the second through-hole plug 153.

[0085] The interlayer dielectric layer 13 is a multi-layer stacked structure, the first conductive interconnect structure 14 may include multiple layers of the first metal interconnect layers 142 and the first through-hole plugs 143 that are alternately stacked, the second conductive interconnect structure 15 may include multiple layers of the second metal interconnect layers 152 and the second through-hole plugs 153 that are alternately stacked, the first contact plugs 141, the first metal interconnect layers 142 of different layers, and the first through-hole plugs 143 of different layers are located in the interlayer dielectric layer 13 of different layers, and the second contact plugs 151, the second metal interconnect layers 152 of different layers, and the second through-hole plugs 153 of different layers are located in the interlayer dielectric layer 13 of different layers.

[0086] exist Figure 4i In the illustrated embodiment, the interlayer dielectric layer 13 includes a first interlayer dielectric layer 131, a second interlayer dielectric layer 132, and a third interlayer dielectric layer 133 stacked from bottom to top, the first contact plug 141 and the second contact plug 151 are located in the first interlayer dielectric layer 131, the two first metal interconnection layers 142 and the two second metal interconnection layers 152 are respectively located in the two second interlayer dielectric layers 132, and the first through-hole plug 143 and the second through-hole plug 153 are located in the third interlayer dielectric layer 133.

[0087] Preferably, the first contact plug 141 and the second contact plug 151 are formed simultaneously, the first metal interconnection layer 142 and the second metal interconnection layer 152 are formed simultaneously, and the first through-hole plug 143 and the second through-hole plug 153 are formed simultaneously, that is, the first conductive interconnection structure 14 and the second conductive interconnection structure 15 are formed simultaneously. Then, it is only necessary to adjust the mask used to form the first contact plug 141, the mask used to form the first metal interconnection layer 142, and the mask used to form the first through-hole plug 143 so that the first contact plug 141 and the second conductive interconnection structure 15 can be formed simultaneously. The second contact plug 151 shares the same photomask, the first metal interconnection layer 142 and the second metal interconnection layer 152 share the same photomask, and the first through-hole plug 143 and the second through-hole plug 153 share the same photomask, that is, the first conductive interconnection structure 14 and the second conductive interconnection structure 15 share the same photomask, and no additional photomask is required to manufacture the MIM capacitor, and the process of forming the first conductive interconnection structure 14 and the process of forming the second conductive interconnection structure 15 are basically the same, thereby simplifying the process steps, making the quality of the MIM capacitor easier to control, and reducing the cost.

[0088] Furthermore, since the first conductive interconnect structure 14 and the second conductive interconnect structure 15 are formed simultaneously, and the first conductive interconnect structure 14 is used to electrically lead out the transistor, the second conductive interconnect structure 15 and the first conductive interconnect structure 14 can both extend to the surface of the interlayer dielectric layer 13, that is, can both extend to the surface of the semiconductor device. Therefore, the length of the second conductive interconnect structure 15 in a direction perpendicular to the substrate 11 can be made very long, thereby making the area of ​​the electrode plate very large, and the area of ​​the electrode plate is not limited by the chip area, thereby significantly increasing the capacitance value of the MIM capacitor.

[0089] Preferably, Figure 2 As shown, at least one of the second contact plug 151, the second metal interconnection layer 152 and the second through-hole plug 153 is a plate-like structure, that is, the cross-sectional shape of at least one of the second contact plug 151, the second metal interconnection layer 152 and the second through-hole plug 153 is a rectangular structure, so that the area of ​​the second conductive interconnection structure 15 as an electrode plate is increased, thereby increasing the capacitance value of the capacitor. It should be noted that the plate surfaces (i.e., the surfaces with increased areas) of adjacent plate-like structures are arranged oppositely; and the more the number of plate-like structures in each layer structure of the second conductive interconnection structure 15 is, and the longer the length of the plate surface of the plate-like structure in the direction parallel to the substrate 11 is, the larger the area of ​​the electrode plate is.

[0090] Among them, Figure 2 In the illustrated embodiment, the second contact plug 151 and the second metal interconnection layer 152 are plate-shaped structures, that is, the cross-sectional shape of the two electrode plates facing each other is a rectangle.

[0091] Taking the simultaneous formation of the first conductive interconnect structure 14 and the second conductive interconnect structure 15, and the substrate 11 is an SOI substrate as an example, the steps of forming the interlayer dielectric layer 13, the first conductive interconnect structure 14 and the second conductive interconnect structure 15 may include: first, Figure 4cAs shown, a first interlayer dielectric layer 131 is formed to cover the etch stop layer 17, and the first interlayer dielectric layer 131 and the etch stop layer 17 above the transistor are etched, and the first interlayer dielectric layer 131, the etch stop layer 17, and the shallow trench isolation structure 12 above the shallow trench isolation structure 12 are etched, or the insulating buried layer 112 is further etched to form a first contact hole 1411 and a second contact hole 1511, the first contact hole 1411 penetrates the first interlayer dielectric layer 131 and the etch stop layer 17 above the transistor to expose the metal silicide layer 16, and the second contact hole 1511 penetrates the first interlayer dielectric layer 131, the etch stop layer 17 and the shallow trench isolation structure 12 above the shallow trench isolation structure 12 and enters the insulating buried layer 112, or the second contact hole 1511 penetrates the first interlayer dielectric layer 131 and the etch stop layer 17 to enter the shallow trench isolation structure 12; then, as shown in FIG. Figure 4d As shown, metal material is filled in the first contact hole 1411 and the second contact hole 1511 to form a first contact plug 141 in the first contact hole 1411 and a second contact plug 151 in the second contact hole 1511; then, as shown in Figure 4e As shown, a second interlayer dielectric layer 132 is formed to cover the first interlayer dielectric layer 131, and the second interlayer dielectric layer 132 is etched to form a first trench 1421 exposing the first contact plug 141 and a second trench 1521 exposing the second contact plug 151; then, as shown Figure 4f As shown, metal material is filled in the first trench 1421 and the second trench 1521 to form a first metal interconnection layer 142 in the first trench 1421 and a second metal interconnection layer 152 in the second trench 1521; then, as shown Figure 4g As shown, a third interlayer dielectric layer 133 is formed to cover the second interlayer dielectric layer 132, and the third interlayer dielectric layer 133 is etched to form a first through hole 1431 exposing the first metal interconnection layer 142 and a second through hole 1531 exposing the second metal interconnection layer 152; then, as shown Figure 4h As shown, metal material is filled in the first through hole 1431 and the second through hole 1531 to form a first through hole plug 143 in the first through hole 1431 and a second through hole plug 153 in the second through hole 1531; then, a plurality of alternately stacked first metal interconnection layers 142 and the first through hole plug 143 are formed on the first contact plug 141, and a plurality of alternately stacked second metal interconnection layers 152 and the second through hole plug 153 are formed on the second contact plug 151, as shown in FIG. Figure 4iFIG. 4 schematically shows two layers of the first metal interconnection layer 142 and the second metal interconnection layer 152 , and one layer of the first via plug 143 and the second via plug 153 .

[0092] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, wherein a shallow trench isolation structure is formed in the substrate; forming an interlayer dielectric layer and a second conductive interconnect structure, wherein the interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the shallow trench isolation structure, and the second conductive interconnect structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure. The method for manufacturing a semiconductor device provided by the present invention can reduce the manufacturing cost of a capacitor and improve the area utilization rate.

[0093] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate having a shallow trench isolation structure formed therein; An interlayer dielectric layer is formed on the substrate, and the interlayer dielectric layer covers the shallow trench isolation structure; a second conductive interconnect structure, the second conductive interconnect structure penetrating the interlayer dielectric layer and extending at least into the shallow trench isolation structure, the second conductive interconnect structure serving as an electrode plate of the MIM capacitor; The second conductive interconnect structure includes a second contact plug, and the second contact plug extends from the interlayer dielectric layer at least into the shallow trench isolation structure.

2. The semiconductor device according to claim 1, wherein The semiconductor device includes at least two of the second conductive interconnect structures.

3. The semiconductor device according to claim 1, wherein The second conductive interconnect structure further includes a second metal interconnect layer and a second via plug, the second metal interconnect layer is electrically connected to the second contact plug, and adjacent second metal interconnect layers are electrically connected through the second via plug.

4. The semiconductor device according to claim 3, characterized in that The semiconductor device also includes a transistor and a first conductive interconnect structure, wherein the transistor is formed in an active area surrounded by the shallow trench isolation structure, and the first conductive interconnect structure penetrates the interlayer dielectric layer and is electrically connected to the transistor; the first conductive interconnect structure includes a first contact plug, a first metal interconnect layer and a first through-hole plug, the first metal interconnect layer is electrically connected to the transistor through the first contact plug, the first metal interconnect layer in an adjacent layer is electrically connected through the first through-hole plug, the first contact plug and the second contact plug are located on the same layer, the first metal interconnect layer and the second metal interconnect layer are located on the same layer, and the first through-hole plug and the second through-hole plug are located on the same layer.

5. The semiconductor device according to claim 3, wherein: At least one of the second contact plug, the second metal interconnection layer and the second via plug is a plate-shaped structure.

6. The semiconductor device according to claim 1, wherein: The substrate is an SOI substrate, which includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, and the shallow trench isolation structure is formed in the semiconductor layer and contacts the insulating buried layer; or, the substrate is a single-layer semiconductor substrate, and the shallow trench isolation structure is formed in the single-layer semiconductor substrate.

7. The semiconductor device according to claim 6, wherein: The second conductive interconnect structure extends into the buried insulating layer; or, the second conductive interconnect structure extends into the shallow trench isolation structure.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The semiconductor device further comprises: An etch stop layer is formed between the interlayer dielectric layer, the shallow trench isolation structure and the substrate.

9. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, wherein a shallow trench isolation structure is formed in the substrate; forming an interlayer dielectric layer and a second conductive interconnect structure, wherein the interlayer dielectric layer is formed on the substrate, the interlayer dielectric layer covers the shallow trench isolation structure, the second conductive interconnect structure penetrates the interlayer dielectric layer and at least extends into the shallow trench isolation structure, and the second conductive interconnect structure serves as an electrode plate of the MIM capacitor; The second conductive interconnect structure includes a second contact plug, and the second contact plug extends from the interlayer dielectric layer at least into the shallow trench isolation structure.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The second conductive interconnect structure further includes a second metal interconnect layer and a second via plug, the second metal interconnect layer is electrically connected to the second contact plug, and adjacent second metal interconnect layers are electrically connected through the second via plug.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: A transistor is formed in the active area surrounded by the shallow trench isolation structure. The manufacturing method of the semiconductor device also includes forming a first conductive interconnect structure, which runs through the interlayer dielectric layer and is electrically connected to the transistor; the first conductive interconnect structure includes a first contact plug, a first metal interconnect layer and a first through-hole plug, the first metal interconnect layer is electrically connected to the transistor through the first contact plug, and the adjacent first metal interconnect layer is electrically connected through the first through-hole plug; wherein the first contact plug and the second contact plug are formed simultaneously, the first metal interconnect layer and the second metal interconnect layer are formed simultaneously, and the first through-hole plug and the second through-hole plug are formed simultaneously.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: At least one of the second contact plug, the second metal interconnection layer and the second via plug is a plate-shaped structure.

13. The method for manufacturing a semiconductor device according to claim 9, wherein: The substrate is an SOI substrate, which includes a lower substrate, an insulating buried layer and a semiconductor layer from bottom to top, and the shallow trench isolation structure is formed in the semiconductor layer and contacts the insulating buried layer; or, the substrate is a single-layer semiconductor substrate, and the shallow trench isolation structure is formed in the single-layer semiconductor substrate.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The second conductive interconnect structure extends into the buried insulating layer; or, the second conductive interconnect structure extends into the shallow trench isolation structure.

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