A power combining network and a design method thereof

Abstract

The application provides a power combining network and a design method thereof. The power combining network comprises N pieces of A microstrip lines arranged in sequence along a first direction and M pieces of B microstrip lines arranged in sequence along a second direction, N is an even number greater than 3, the N pieces of A microstrip lines are of the same size and correspond to N power amplifiers one by one, the first ends of the N pieces of A microstrip lines are connected to the output ends of the corresponding power amplifiers respectively, the second ends of the N pieces of A microstrip lines are connected to the first side of the first piece of B microstrip line in sequence, and the connection positions of the second ends of the jth piece of A microstrip line and the first piece of B microstrip line and the connection positions of the (N+1-j)th piece of A microstrip line and the first piece of B microstrip line are symmetrical to the midpoint of the first side of the first piece of B microstrip line. The power combining network provided by the application can guarantee the optimal output power and the lowest combining loss of each power amplifier link, and meanwhile, each power amplifier link has good amplitude and phase consistency.

Description

Technical Field

[0001] This invention relates to the field of chip design, and more particularly to a power combining network and a design method for a power combining network. Background Technology

[0002] In high-frequency circuit design, transistors generally have low power output. When a power amplifier composed of a single power transistor cannot meet the need for high power output, power combining is required to achieve the required power output. A power combining network combines the outputs of multiple power amplifiers through a network to increase the output power.

[0003] In power combining networks, low insertion loss and good amplitude-phase consistency are required. Low insertion loss prevents excessive power loss from the amplifier's output in the combining network, while good amplitude-phase consistency ensures the efficiency and reliability of the combining process. Traditional power combining networks, such as binary Wilkinson power dividers and quadrature couplers with double-balanced configurations, suffer from drawbacks such as large area, low combining efficiency, and high losses, failing to meet the high-power, high-capacity requirements of power amplifiers in radar and communication systems.

[0004] To address the aforementioned problems, this invention proposes a power combining network and a design method for such a network. Summary of the Invention

[0005] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0006] To overcome the above-mentioned defects, the present invention aims to provide a power combining network that ensures the optimal output power and the lowest combining loss of each power amplifier link, while also having good amplitude and phase consistency in each power amplifier link.

[0007] According to one aspect of the present invention, a power combining network is provided for combining the output signals of N power amplifiers into a single combined signal. The power combining network includes N A-microstrip lines arranged sequentially along a first direction and N B microstrip lines are arranged sequentially along the second direction, where N is an even number greater than 3. N A microstrip lines are of the same size and each corresponds to one of the N power amplifiers. The first ends of the N A microstrip lines are connected to the output terminals of their respective power amplifiers. The second ends of the N A microstrip lines are sequentially connected to the first side of the first B microstrip line. The connection position between the second end of the j-th A microstrip line and the first B microstrip line is symmetrical to the connection position between the (N+1-j)-th A microstrip line and the first B microstrip line with respect to the midpoint of the first side of the first B microstrip line. The second side of the preceding B microstrip line contacts the first side of the following B microstrip line. The midpoint of the second side of the last B microstrip line serves as the output point of the combined signal. The length of the first side of the i-th B microstrip line is greater than D. i+1 And less than D i , No. Open-circuit stubs are provided at both ends of the second side of microstrip line B. Among them, , D i Indicates the distance from the second end of the i-th microstrip line to the... The distance between the second ends of microstrip line A, where the second side of the microstrip line is the side opposite to its first side.

[0008] In one embodiment, the second ends of N A microstrip lines are connected at equal intervals to the first side of the first B microstrip line.

[0009] In one embodiment, the spacing is larger than the size of the power amplifier tubes adapted to the power combining network.

[0010] In one embodiment, the length of the second side of a plurality of B microstrip lines is less than the length of its first side.

[0011] In one embodiment, the power combining network along the first... The perpendicular bisector of the second side of microstrip line B is symmetrical.

[0012] In one embodiment, the open branch starts from the first The two ends of the second side of the B microstrip line move away from the first The direction of the B microstrip line extends.

[0013] The better ones have fan-shaped branches.

[0014] Furthermore, the angle between the central axis of the sector and the second direction is 45°.

[0015] In one embodiment, the first side of the first B microstrip line further includes N-3 grooves, the kth groove is disposed on the first side of the first B microstrip line between the (k+1)th and (k+2)th A microstrip lines, and the depth of the N-3 grooves gradually decreases from the perpendicular bisector of the first side of the first B microstrip line to both sides, wherein 1≤k≤N-3.

[0016] In one embodiment, a grounding capacitor is connected to the midpoint of the first side of the first B microstrip line.

[0017] Ideally, N should be 4.

[0018] According to another aspect of the present invention, a method for designing a power combining network is provided. The power combining network is used to combine the output signals of N power amplifiers into a single combined signal. The power combining network includes N A-microstrip lines arranged sequentially along a first direction and... N B microstrip lines are arranged sequentially along the second direction, where N is an even number greater than 3. Each of the N A microstrip lines corresponds one-to-one with one of the N power amplifiers, and their first ends are connected to the output terminals of the corresponding power amplifiers. The second ends of the N A microstrip lines are connected sequentially and at equal intervals to the first side of the first B microstrip line. The second side of the preceding B microstrip line is in contact with the first side of the following B microstrip line. The second side of the B microstrip line has open-circuit stubs at both ends. The midpoint of the second side of the B microstrip line is used as the output point of the combined signal. The second side of the microstrip line is the side opposite to its first side. The design method includes: determining the optimal load impedance of the N-channel power amplifier using the load pulling method; and adjusting the N A microstrip lines, the... The dimensions of the B microstrip line and the open stub are such that the impedance of the power combining network is equal to the optimal load impedance.

[0019] In an embodiment of a preferred design approach, the open branch is fan-shaped, and the dimensions of the open branch include the radius and arc length of the fan shape.

[0020] In one embodiment, the first side of the first B microstrip line further includes N-3 grooves, and the k-th groove is provided on the first side of the first B microstrip line located between the second end of the (k+1)-th A microstrip line and the second end of the (k+2)-th A microstrip line. The design method also includes adjusting the depth of the k-th groove to maintain the amplitude and phase consistency of the multi-channel signals associated with the groove.

[0021] In one embodiment, after determining the optimal load impedance of the N power amplifiers, the method further includes: in response to the optimal load impedance being less than a preset load threshold, setting an impedance matching unit on the output link of the combined signal of the power combining network to improve the impedance matching target of the power combining network, and using the real and imaginary parts of the improved impedance matching target as the adjustment targets for the N A microstrip lines and the open stub, respectively.

[0022] This invention provides a novel power combining network structure that constructs an all-in-one structure with excellent symmetry, optimal output power, and extremely low combining loss, while suppressing second harmonics. During the design phase of the power combining network, the amplitude and phase consistency of multiple signals can be ensured by adjusting the dimensions of the microstrip lines and open stubs. Attached Figure Description

[0023] The above-described features and advantages of the present invention will be better understood after reading the detailed description of the embodiments of this disclosure in conjunction with the following accompanying drawings.

[0024] Figure 1 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0025] Figure 2 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0026] Figure 3 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0027] Figure 4 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0028] Figure 5 This is a schematic diagram illustrating the shape of a microstrip line in one embodiment according to one aspect of the present invention;

[0029] Figure 6 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0030] Figure 7 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0031] Figure 8 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0032] Figure 9 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0033] Figure 10 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0034] Figure 11 This is a schematic diagram of a power combining network structure according to one aspect of the present invention;

[0035] Figure 12 This is a schematic diagram of the harmonic suppression effect curve of the power combining network structure according to an embodiment of the present invention;

[0036] Figure 13 This is a schematic diagram of the power enhancement effect curve of the power combining network structure according to an embodiment of the present invention;

[0037] Figure 14 This is a flowchart illustrating a design method for a power combining network according to another aspect of the present invention;

[0038] Figure 15 This is a flowchart illustrating a design method for a power combining network according to another aspect of the present invention;

[0039] Figure 16 This is a schematic diagram illustrating the structure of the output link of a power combining network according to one aspect of the present invention. Detailed Implementation

[0040] The following description is provided to enable those skilled in the art to implement and use the invention and adapt it to specific application contexts. Various modifications and uses in different applications will be readily apparent to those skilled in the art, and the general principles defined herein are applicable to a wide range of embodiments. Therefore, the invention is not limited to the embodiments given herein, but should be granted the broadest scope consistent with the principles and novel features disclosed herein.

[0041] In the following detailed description, numerous specific details are set forth to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that practice of the invention is not necessarily limited to these specific details. In other words, well-known structures and devices are shown in block diagram form without being depicted in detail to avoid obscuring the invention.

[0042] Unless otherwise expressly stated, all features disclosed in this specification (including any appended claims, abstract, and drawings) may be replaced by alternative features for the same, equivalent, or similar purpose. Therefore, unless explicitly stated otherwise, each disclosed feature is merely one example of a set of equivalent or similar features.

[0043] Note that, where used, the markings left, right, front, back, top, bottom, front, back, clockwise, and counterclockwise are merely for convenience and do not imply any specific fixed direction. In fact, they are used to reflect the relative position and / or orientation between different parts of an object. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0044] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be understood as directly connected. Connection points, connection locations, and output points should not be understood as points with infinitely small coverage areas, but rather as areas that meet the dimensional requirements for electrical signal transmission and electrical connection relationships.

[0045] Note that, in practice, "further," "preferably," "even further," and "more preferably" are simply starting points for describing another embodiment based on the foregoing embodiments. The combination of these "further," "preferably," "even further," or "more preferably" followed by the foregoing embodiments constitutes the complete structure of another embodiment. Between several "further," "preferably," "even further," or "more preferably" settings following the same embodiment... Another embodiment of the composition that can be arbitrarily combined.

[0046] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the aspects described below with reference to the accompanying drawings and specific embodiments are merely exemplary and should not be construed as limiting the scope of protection of the present invention in any way.

[0047] According to one aspect of the present invention, a power combining network is provided to ensure optimal output power and minimum combining loss for each power amplifier link.

[0048] Figure 1 A schematic diagram of a power combining network structure in one embodiment is shown, such as... Figure 1 As shown, the power combining network includes N class A microstrip lines A1~AN arranged sequentially along the first direction. Type B microstrip lines B1~B1 arranged sequentially along the second direction , where N is an even number greater than 3.

[0049] The first ends of N microstrip lines A1~AN are respectively connected to the output terminals of the corresponding power amplifier tubes (not shown), and the second ends of N microstrip lines A1~AN are sequentially connected to the first side of microstrip line B1. The connection positions of the second ends of microstrip lines Ai and B1 and AN-i+1 and B1 are symmetrical with respect to the midpoint M of the first side of microstrip line B1, where N≥i≥1.

[0050] That is, the connection positions of the second end of microstrip line A1 and microstrip line B1 are symmetrical with respect to the midpoint M of the first side of microstrip line B1, the connection positions of the second end of microstrip line A2 and microstrip line B1 are symmetrical with respect to the midpoint M of the first side of microstrip line B1, and so on. The connection position of the second end with microstrip line B1 and microstrip line A The connection point of the second end with microstrip line B1 is symmetrical with respect to the midpoint M of the first side of microstrip line B1.

[0051] microstrip lines B1~B They are connected sequentially. For example... Figure 1 As shown, the first side of microstrip line B1 is connected to the second end of microstrip lines A1~AN, the second side of microstrip line B1 is in contact with the first side of microstrip line B2, the second side of microstrip line B2 is in contact with the first side of microstrip line B3 (when N≥6), and so on.

[0052] The last microstrip line B is microstrip line B. The midpoint M' of the second side is used as the output point of the combined signal.

[0053] It can be understood that the first and second sides of a microstrip line refer to the two opposite sides of the microstrip line, generally referring to two sides that are parallel (not necessarily of the same length). For example, the two long sides or the two short sides of a rectangular microstrip line, or the two base sides of a trapezoidal structure.

[0054] Sequential arrangement generally refers to arranging in a certain direction. In this invention, it is limited to the midpoints of microstrip lines being arranged sequentially along a certain direction. For example, sequential arrangement of microstrip lines A1~AN along the first direction means that the midpoints of microstrip lines A1~AN are arranged sequentially along the first direction; sequential arrangement of microstrip lines B1~BN / 2 along the second direction means that the midpoints of microstrip lines B1~BN / 2 are arranged sequentially along the second direction.

[0055] Furthermore, for design convenience, generally speaking, Class A microstrip lines are of the same size and are all connected to the first side of microstrip line B1. Therefore, the line connecting the midpoints of microstrip lines A1 to AN is parallel to the first side of microstrip line B1. Also, the midpoints of microstrip lines B1 to BN / 2 are arranged sequentially along the second direction, so the line connecting the midpoints of microstrip lines B1 to BN / 2 is perpendicular to the first side of microstrip line B1, meaning the first and second directions are perpendicular.

[0056] Furthermore, the i-th microstrip line B i The length of the first side is greater than D i And less than D i-1 , D i Indicates microstrip line A i The second end to microstrip line A N+1-i The distance from the second end. Figure 1Taking the power combining network shown as an example, assuming the distance between the second end of microstrip line A1 and the second end of microstrip line AN (which can be considered as the distance from the connection point of microstrip line A1 and microstrip line B1 to the connection point of microstrip line AN and microstrip line B1) is D1, and the distance between the second end of microstrip line A2 and the second end of microstrip line AN-1 (which can be considered as the distance from the connection point of microstrip line A2 and microstrip line B1 to the connection point of microstrip line AN-1 and microstrip line B1) is D2, then the length of the first side of microstrip line B2 must be greater than D2 and less than D1.

[0057] It is understandable that, due to the multiple power amplification branches of the all-in-one circuit structure, they pass through the corresponding microstrip lines A1~AN and sequentially through microstrip lines B1~B1. The output is at point M', therefore there are multiple power amplification branches with inherent asymmetry.

[0058] As in Figure 1 In the symmetrical structure shown, the structure is symmetrical with respect to the connection of MM'. Therefore, the transmission paths of the power amplification branches corresponding to A1 and AN are the same, the transmission paths of the power amplification branches corresponding to A2 and AN-1 are the same, and so on, thus satisfying the condition that "microstrip line A..." The connection position of the second end with microstrip line B1 and microstrip line A The requirement is that the connection position of the second end to the microstrip line B1 is symmetrical with respect to the midpoint M of the first side of the microstrip line B1.

[0059] exist Figure 2 In the illustrated embodiment, to maximize chip area utilization, power amplifier transistors M1~MN are arranged along a slanted side, resulting in staggered placement and thus avoiding the minimum spacing requirement between transistors. In this embodiment, since microstrip lines A1~AN have the same dimensions, while microstrip lines B1~B... The resulting structure is symmetrical with respect to the perpendicular bisector of the structure. Therefore, the transmission paths of the power amplification branches corresponding to A1 and AN can be considered to be basically the same, the transmission paths of the power amplification branches corresponding to A2 and AN-1 can be considered to be basically the same, and so on, which also satisfies the condition that "microstrip line A..." The connection position of the second end with microstrip line B1 and microstrip line A The requirement is that the connection position of the second end to the microstrip line B1 is symmetrical with respect to the midpoint M of the first side of the microstrip line B1.

[0060] But Figure 1 or Figure 2 In the illustrated embodiment, due to the asymmetry of the connection positions of microstrip lines A1 and A2 on microstrip line B1, the transmission paths of the power amplification branches corresponding to microstrip lines A1 and A2, or the transmission paths of the power amplification branches corresponding to microstrip lines AN-1 and AN (excluding microstrip line A) are different. and microstrip line A The transmission paths corresponding to adjacent microstrip lines A have inherent asymmetry characteristics. To improve the symmetry of the transmission paths corresponding to adjacent microstrip lines A, in addition to the combining of microstrip lines B1, paths B2~B1 are also set. Among them, microstrip line B2 is used to improve the equivalence of the transmission paths of the power amplification branches corresponding to microstrip lines A1 and A2, and so on, microstrip line B... Used to improve microstrip line A -1 and microstrip line A The equivalence of the transmission paths of the corresponding power amplification branches. Meanwhile, B1~B Impedance matching was also achieved through high- and low-impedance transformation lines.

[0061] To further improve the symmetry of the transmission paths of multiple power amplification branches, microstrip lines A1~A2 are of the same size, and microstrip lines B1~B2 are of the same size. The microstrip lines B1~B have the same shape and are arranged in the same way. The resulting structure is symmetrical about the extension of MM'.

[0062] Furthermore, microstrip line B The second side also has open-circuit stubs E1 and E2 at its two ends. It can be understood that, to improve symmetry, open-circuit stubs E1 and E2 are the same size, and their arrangement and direction are relative to the microstrip line B. The perpendicular bisector of the second side is symmetrical.

[0063] Ideally, the open branch originates from microstrip line B. The two ends of the second side move away from microstrip line B. Extending in the direction of. Here, "away from" refers to the open branch at microstrip line B. The area formed by the extensions of two adjacent sides of the setting position.

[0064] In one specific embodiment, such as Figure 4 As shown, in this embodiment, open-circuit stubs E1 and E2 are fan-shaped and located in region C, which is far from microstrip line B2.

[0065] It is understandable that open-circuit stubs can be of any shape. To reduce chip area and meet the isolation requirements with the signal output line (the subsequent line of output point M'), it is preferable that the open-circuit stub be set as a fan shape.

[0066] The angles between the central axis N1 of the fan-shaped open branch E1 and the central axis N2 of the fan-shaped open branch E2 in area C and the second direction can be arbitrary. More preferably, such as Figure 4As shown, the angle between the central axis N1 of the fan-shaped open branch E1 and the central axis N2 of the fan-shaped open branch E2 and the second direction is 45°.

[0067] It is conceivable that the symmetry requirement of the transmission path of the multi-power amplifier branch restricts the size and arrangement of the microstrip lines on one side of MM' to be symmetrical with those on the other side, but does not restrict the arrangement of the Class A microstrip lines on the same side to be the same.

[0068] To give a simple example, the distance between the second end of microstrip line A1 and the second end of microstrip line A2 can be the same as or different from the distance between the second end of microstrip line A2 and the second end of microstrip line A3. That is, the distance between microstrip lines A1 and A2... +1 can be connected to the first side of microstrip line B1 at unequal intervals.

[0069] Optionally, to simplify the simulation and calculation process, the arrangement of the Class A microstrip lines on the same side can also be set to be the same. Figure 3 It shows Figure 1 A schematic diagram of the power combining network when N is 4. Figure 3 In the illustrated embodiment, the second ends of microstrip lines A1 to A4 are connected at equal intervals to the first side of microstrip line B1, and the spacing between adjacent Class A microstrip lines is greater than the sum of the arrangement size of the power amplifier tubes and the minimum spacing between the power amplifier tubes. Here, the arrangement size of the power amplifier tubes refers to the dimensions of the power amplifier tubes along their arrangement direction, and the minimum spacing between the power amplifier tubes refers to the minimum distance required to meet the isolation requirements between multiple power amplifier tubes. That is, the overall structure of the power combining network is along microstrip line B1. The perpendicular bisector MM' of the second side is symmetrical.

[0070] The actual shape of a Class B microstrip line can be any shape symmetrical along the connection line MM', such as... Figure 5 The rectangle shown in A Figure 5 Type B microstrip lines are elongated strips with curved ends or other regular or irregular shapes with an axis of symmetry. To reduce the reflection loss caused by Type B microstrip lines, it is preferable that the length of the second side of the Type B microstrip line is less than the length of its first side.

[0071] Figure 6 A schematic diagram of the power combining network structure in a specific embodiment is shown, such as... Figure 6 As shown, the microstrip line B1 is an isosceles trapezoid, and the length of the second side is smaller than that of the first side.

[0072] Figure 7 A schematic diagram of the power combining network structure in another embodiment is shown. Figure 7 The illustrated embodiments are relative to Figure 6 The difference in the embodiment shown is that the sandwiched edge between the first and second sides of the microstrip line B1 is an inwardly concave curve.

[0073] Figure 8 A schematic diagram of the power combining network structure in another embodiment is shown. Figure 8 The illustrated embodiments are relative to Figure 6 The difference in the embodiment shown is that the sandwiched edge between the first and second sides of the microstrip line B1 is an outwardly convex curve.

[0074] Understandable. Figures 6-8 Other Class B microstrip lines in the illustrated embodiments can also be used. Figures 6-8 The shape of the microstrip line B1 in any of the embodiments.

[0075] To further improve the equivalence of the transmission paths corresponding to the power amplification branches on the same side, a groove can be provided on the first side of the microstrip line B1 to effectively extend the transmission paths of the Class A microstrip lines on both sides of the groove.

[0076] The first side of microstrip line B1 can be provided with N-3 grooves H1 to HN-3. The N-3 grooves H1 to HN-3 are distributed from the midpoint of the first side of microstrip line B1 along both sides, and the depth of the grooves gradually decreases. Among them, the k-th (1≤k≤N-3) groove is provided on the first side of microstrip line B1 located between microstrip lines Ak+1 and Ak+2. The N-3 grooves are symmetrical with respect to the perpendicular bisector of the first side of microstrip line B1.

[0077] Figure 9 A schematic diagram of a power combining network in one embodiment is shown. In this embodiment, N=4, and a groove H1 is provided on the first side of microstrip line B1. The groove H1 is located on the first side of microstrip line B1 between microstrip line A2 and microstrip line A3.

[0078] Figure 10 A schematic diagram of the power combining network in another embodiment is shown. In this embodiment, N=6, and three grooves H1~H3 are provided on the first side of microstrip line B1. Groove H1 is located on the first side of microstrip line B1 between microstrip lines A2 and A3, groove H2 is located on the first side of microstrip line B1 between microstrip lines A3 and A4, and groove H3 is located on the first side of microstrip line B1 between microstrip lines A4 and A5. The depth a of groove H2 gradually decreases to the depth b of grooves H2 and H3 on both sides, i.e., a>b.

[0079] Optionally, to improve the power combining network's ability to suppress second harmonics, an LC filter circuit can be placed at the midpoint of the first side of the microstrip line B1.

[0080] When power combining networks are used in high-frequency scenarios, the transmission line is equivalent to an inductor. Figure 11A schematic diagram of a power combining network in a high-frequency scenario is shown. The midpoint of the first side of the microstrip line B1 is connected to a ground capacitor C1, and the connection line of the ground capacitor C1 is equivalent to an inductor L.

[0081] Furthermore, symmetrical LC filter circuits can be placed at both ends of microstrip line B1 to improve the suppression of second harmonics, and these circuits can be placed on the other side of microstrip line B1 (the side opposite to the Class A microstrip line), such as... Figure 11 The LC filter circuit shown is configured at both ends of microstrip line B1.

[0082] It is understandable that the LC filter structure with the capacitor and transmission line connected in series resonates at the operating frequency of the power amplifier transistor, which can be regarded as an open circuit. However, under the second harmonic, it behaves as a short circuit, thereby controlling the second harmonic impedance and second harmonic power of the output transistor. Controlling the second harmonic can effectively improve the output power and efficiency.

[0083] Furthermore, in some embodiments, the two ends of the microstrip line B1 (such as...) Figure 11 The location indicated by VDD can also be connected to a bias circuit to provide bias voltage for the power amplifier tube connected to the first end of the Class A microstrip line.

[0084] Figure 12 The diagram shows the harmonic suppression curve of the power combining network in one embodiment, as follows: Figure 12 As shown, in the coordinate axis, the horizontal axis represents frequency, and the vertical axis represents harmonic insertion loss. Curve L1 shows the harmonic suppression curve of the power combining network in an embodiment with N=4 and no LC filter circuit, while curve L2 shows the harmonic suppression curve of the power combining network in an embodiment with N=4 and an LC filter circuit. Clearly, adding an LC filter circuit can significantly suppress the second harmonic.

[0085] Figure 13 An output power curve of a power combining network in one embodiment is shown, such as... Figure 13 As shown, in the coordinate axis, the horizontal axis represents frequency and the vertical axis represents output power. Curve L3 shows the output power curve of the power combining network in an embodiment with N=4 and no LC filter circuit, while curve L4 shows the output power curve of the power combining network in an embodiment with N=4 and an LC filter circuit. Clearly, adding an LC filter circuit can significantly improve the combining efficiency and output power.

[0086] According to one aspect of the present invention, a design method for a power combining network is provided to ensure optimal output power and minimum combining loss of each power amplifier link, while also ensuring good amplitude and phase consistency in each power amplifier link.

[0087] Figure 14An embodiment of a design method for a power combining network is shown, wherein the power combining network can be referred to the power combining network in the foregoing embodiment. The definitions of terms involved in the design method are the same as those in the foregoing power combining network embodiments, and will not be repeated.

[0088] Specifically, the power combining network includes N class A microstrip lines A1~AN arranged sequentially along the first direction. Type B microstrip lines B1~B1 arranged sequentially along the second direction Where N is an even number greater than 3. N Class A microstrip lines correspond one-to-one with N power amplifiers, with their first ends connected to the output terminals of the corresponding amplifiers. The second ends of the N Class A microstrip lines are sequentially connected at equal intervals to the first side of the first B microstrip line. The second side of the preceding B microstrip line is in contact with the first side of the following B microstrip line. The second side of the B microstrip line has open-circuit stubs at both ends. The midpoint of the second side of the B microstrip line is used as the output point of the combined signal.

[0089] like Figure 14 As shown, the design method of the power combining network includes steps S1 to S2.

[0090] Step S1 involves determining the optimal load impedance of the N-channel power amplifier using a load-pulling method.

[0091] Load pulling is an impedance-related measurement technique aimed at detecting the load impedance supplied to the device under test (DUT) at its fundamental frequency f0 or any harmonic frequencies (primarily 2f0 and 3f0). The load pulling method finds the input-output matching impedance that maximizes the output power of the active device by continuously adjusting the impedances at the input and output terminals. Similarly, it can also obtain the matching impedance that maximizes the efficiency of the power transistors, i.e., the optimal load impedance. It is understood that those skilled in the art can use any existing or future load pulling method or tool to determine the optimal load impedance for an N-channel power amplifier.

[0092] Step S2 is: Adjust N A microstrip lines, The dimensions of the B microstrip line and open stubs are such that the impedance of the power combining network is equal to the optimal load impedance.

[0093] The optimal load impedance generally includes the real and imaginary parts. Power combining networks also include the balance between different signals. In practice, power combining networks not only need to meet the optimal load impedance, but also need to meet the balance requirements of each signal.

[0094] It is understandable that power combining networks include various parameters, such as the dimensions of the N A microstrip lines, The dimensions of the B microstrip line, the dimensions and locations of open stubs, and other parameters have varying degrees of correlation with the final impedance of the power combining network, as well as with its balance or other circuit performance. Therefore, in the actual design process, some parameters with low correlation can be set first, and then appropriate parameters can be selected as variables for adjustment, so that the impedance and balance of the power combining network meet the design requirements.

[0095] For example, in the process of implementing the present invention, it was found that under the structure of the power combining network shown in the present invention, the size of the Class A microstrip line is most related to the real impedance of the power combining network, and the size of the open stub is most related to the virtual impedance of the power combining network.

[0096] Furthermore, the first side of the first B microstrip line in the power combining network may also include N-3 grooves, with the k-th groove located on the first side of the first B microstrip line between the (k+1)-th and (k+2)-th A microstrip lines. .

[0097] exist Figure 15 In the embodiment shown, Figure 15 The design method shown is in Figure 14 Based on the design method shown, a groove design step S3 is added. Step S3 is: adjust the depth of the k-th groove to maintain the amplitude and phase consistency among the multi-channel signals associated with the groove.

[0098] Furthermore, in any of the aforementioned embodiments of the power combining network and its design method, the target or adjustment objective for the structure and parameters of the power combining network is to achieve the optimal load impedance for each power amplifier. However, in some cases, when the optimal load impedance corresponding to the N power amplifiers is too low, the size of the power combining network formed for this low optimal load impedance will be very large. Therefore, an impedance matching unit can be set on the output link after the output point M' of the power combining network to adjust the impedance matching target of the power combining network to be greater than the optimal load impedance of the power amplifier, thereby reducing the size required for the power combining network.

[0099] Figure 16 A schematic diagram of the output link of the combined signal in a specific embodiment is shown, as follows: Figure 16 As shown, a DC blocking capacitor C2 is set on the output link (the shape of the capacitor in the layout is not easy for non-layout engineers to understand, so it is replaced by a circuit symbol). When this network is applied to high-frequency signals, the pads PAD1 and PAD2 of the DC blocking capacitor C2 can be equivalent to inductors, that is, it is equivalent to setting a low-pass network as an impedance matching unit on the output link, realizing low-impedance transformation, thereby raising the load impedance of the output point M', that is, raising the impedance matching target of the power combining network.

[0100] The design method for the corresponding power combining network may also include the step of setting an impedance matching unit. In response to the optimal load impedance being less than a preset load threshold, an impedance matching unit is set on the output link of the combined signal of the power combining network to improve the impedance matching target of the power combining network.

[0101] It is understood that the power combining network comprises multiple microstrip lines, and therefore is highly dependent on size. An area threshold can be set for the power combining network based on the overall chip area. The power combining network within this area has a corresponding achievable impedance matching range, i.e., a preset load threshold. When the optimal load impedance is less than this preset load threshold, impedance matching units can be set to raise the impedance matching target of the power combining network. The real and imaginary parts of the raised impedance matching target are then used as the adjustment targets for the N A microstrip lines and the open-circuit stubs, respectively.

[0102] materialization Figure 16 The impedance matching unit shown can adjust the parameters of the DC blocking capacitor C2 and the dimensions of the pads PAD1 and PAD2 across the DC blocking capacitor so that the load impedance of the output point M' becomes the matching impedance target allowed by the area threshold of the power combining network.

[0103] To facilitate design implementation, the target matching impedance can be set to the matching impedance value corresponding to a standard power combining network, i.e., the preset matching impedance value. When setting up the impedance matching unit, it is only necessary to adjust the load impedance of the output point M' to this preset matching impedance value. In the subsequent design process of the power combining network, the standard power combining network can be easily adopted.

[0104] Although the methods described above are illustrated and depicted as a series of actions for the sake of simplicity, it should be understood and appreciated that these methods are not limited by the order of the actions, as some actions may occur in a different order and / or concurrently with other actions from the illustrations and descriptions herein or not illustrated and described herein but which may be understood by those skilled in the art, according to one or more embodiments.

[0105] The preceding description is provided to enable any person skilled in the art to practice the various aspects described herein. However, it should be understood that the scope of protection of this invention should be determined by the appended claims and should not be limited to the specific structures and components of the embodiments described above. Various changes and modifications can be made to the embodiments by those skilled in the art within the spirit and scope of this invention, and these changes and modifications also fall within the scope of protection of this invention.

Claims

1. A power combining network for combining the output signals of N power amplifiers into a single combined signal, the power combining network comprising N A-microstrip lines arranged sequentially along a first direction and B microstrip lines are arranged sequentially along the second direction, where N is an even number greater than 3. N identical A-microstrip lines are connected to N power amplifiers. The first ends of each of the N A-microstrip lines are connected to the output of their respective amplifiers. The second ends of each of the N A-microstrip lines are sequentially connected to the first side of a first B-microstrip line. The connection point between the second end of the j-th A-microstrip line and the first B-microstrip line is symmetrical to the connection point between the (N+1)-j-th A-microstrip line and the first B-microstrip line relative to the midpoint of the first side of the first B-microstrip line. The second side of the preceding B-microstrip line is connected to the first side of the following B-microstrip line, and the midpoint of the second side of the last B-microstrip line serves as the output point of the combined signal. The length of the first side of the i-th microstrip line B is greater than D. i And less than D i-1 , No. The second side of microstrip line B has open-circuit stubs at both ends. in, , D i Indicates the distance from the second end of the i-th microstrip line to the... The distance between the second ends of microstrip line A, where the second side of the microstrip line is the side opposite to its first side.

2. The power combining network as described in claim 1, characterized in that, The second ends of the N A microstrip lines are connected at equal intervals to the first side of the first B microstrip line.

3. The power combining network as described in claim 2, characterized in that, The spacing is greater than the sum of the arrangement size of the power amplifier tubes adapted by the power combining network and the minimum spacing between the power amplifier tubes.

4. The power combining network as described in claim 1, characterized in that, In several B-microstrip lines, the length of the second side is less than the length of the first side.

5. The power combining network as described in claim 4, characterized in that, The power combining network along the first The perpendicular bisector of the second side of microstrip line B is symmetrical.

6. The power combining network as described in claim 1, characterized in that, The open branch is from the first The two ends of the second side of the B microstrip line move away from the first... The direction of the B microstrip line extends.

7. The power combining network as described in claim 6, characterized in that, The open branch is fan-shaped.

8. The power combining network as described in claim 7, characterized in that, The angle between the central axis of the sector and the second direction is 45°.

9. The power combining network as described in any one of claims 1 to 8, characterized in that, The first side of the first B microstrip line also includes N-3 grooves. The k-th groove is located on the first side of the first B microstrip line between the (k+1)-th and (k+2)-th A microstrip lines. The depth of the N-3 grooves gradually decreases from the perpendicular bisector of the first side of the first B microstrip line to both sides, where 1≤k≤N-3.

10. The power combining network as described in any one of claims 1 to 8, characterized in that, A grounding capacitor is connected to the midpoint of the first side of the first B microstrip line.

11. The power combining network as described in any one of claims 1 to 8, characterized in that, N is 4.

12. The power combining network as described in any one of claims 1 to 8, characterized in that, An impedance matching unit is set on the output link of the combined signal output point to reduce the impedance matching target of the power combining network.

13. The power combining network as described in claim 12, characterized in that, The impedance matching unit includes a capacitor connected in series with the output link and the capacitor's pads.

14. A design method for a power combining network, wherein the power combining network is used to combine the output signals of N power amplifiers into a single combined signal, the power combining network comprising N A-microstrip lines arranged sequentially along a first direction and N B microstrip lines are arranged sequentially along the second direction, where N is an even number greater than 3. Each of the N A microstrip lines corresponds one-to-one with one of the N power amplifiers, and their first ends are connected to the output terminals of the corresponding power amplifiers. The second ends of the N A microstrip lines are sequentially connected at equal intervals to the first side of the first B microstrip line. The second side of the preceding B microstrip line is in contact with the first side of the following B microstrip line. The second side of the B microstrip line has open-circuit stubs at both ends. The midpoint of the second side of the B-microstrip line is used as the output point of the combined signal. The second side of the microstrip line is the side opposite to its first side. The design method includes: The optimal load impedance of the N-channel power amplifier was determined using the load-pulling method. as well as Adjust the N A microstrip lines, the The dimensions of the B microstrip line and the open stub are such that the impedance of the power combining network is equal to the optimal load impedance.

15. The design method of the power combining network as described in claim 14, characterized in that, The open branch is fan-shaped, and the dimensions of the open branch include the radius and arc length of the fan shape.

16. The design method of the power combining network as described in claim 14, characterized in that, The first side of the first B microstrip line also includes N-3 grooves. The k-th groove is provided on the first side of the first B microstrip line located between the second end of the (k+1)-th A microstrip line and the second end of the (k+2)-th A microstrip line. The design method includes: The depth of the k-th groove is adjusted to maintain the amplitude and phase consistency of the multi-channel signals associated with the k-th groove.

17. The design method of the power combining network as described in claim 14, characterized in that, After determining the optimal load impedance for the N-channel power amplifier, the following steps are also included: In response to the optimal load impedance being less than a preset load threshold, an impedance matching unit is set on the output link of the combined signal of the power combining network to improve the impedance matching target of the power combining network, and the real and imaginary parts of the improved impedance matching target are used as the adjustment targets for the N A microstrip lines and the open stub, respectively.

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