A chip-on-chip system and its power state configuration, feedback and control method

Abstract

The present invention discloses a wafer-based system and its power state configuration, feedback, and control method, and relates to the field of wafer-level processors. The key points of its technical solution are: including a main controller and a plurality of slave controllers arranged one by one with module groups, the main controller is used to obtain the power state configuration data of each module group through an external interface connected to the main controller for communication, and send it to the corresponding slave controller, or to receive power state feedback data and send it through an external interface; the slave controller is used to send the power state configuration information to the corresponding core grain, or to receive the power state feedback information uploaded by the core grain; the core grain is used to set the power state according to the power state configuration information, or upload the power state feedback information to the slave controller. It is characterized in that it can accurately control the power state of each core grain of the wafer-based system and complete the state feedback, which is safe and convenient, saves hardware resource overhead, reduces system power consumption, and improves the efficiency of power state configuration.

Description

Technical Field

[0001] The present invention relates to the field of wafer-level processors, and in particular to an on-wafer system and a power state configuration, feedback and control method thereof. Background Art

[0002] At present, the number of transistors that can be accommodated per unit area in a chip is increasing, yield control is becoming more and more difficult, power consumption issues are becoming more and more prominent, and manufacturing and design costs are soaring exponentially. The performance improvement of a single chip has reached its limit. In order to break the boundary conditions of the existing large-scale infrastructure system, solve the current dilemma of stacked development of large-scale infrastructure, and maintain sustainable development in the field of integrated circuits in the post-Moore era, upgrading the system on chip SoC (System on Chip) to the wafer-level heterogeneous integration technology of the system on wafer SoW (System on Wafer) has gradually become a research hotspot in the field of integrated circuits.

[0003] On-wafer systems need to adapt to different application scenarios, such as high-performance computing, artificial intelligence, data communication, and signal processing. The on-wafer system components of these application scenarios can be roughly divided into two categories, one containing general-purpose processors, such as high-performance computing and artificial intelligence; the other does not contain general-purpose processors, such as data communication and signal processing. Therefore, it will be necessary to integrate core particles of different structures on a circular silicon substrate on a large scale to meet different application scenarios. Compared with traditional single-chip or small-scale chip integration, large-scale chip integration has the following fundamental problems: 1. Large-scale chip integration on the same wafer (on-wafer systems generally contain hundreds of chiplets). If all chiplets are powered on at once without control, it is easy to generate surges that damage the circuit structure and cause short circuits, which will cause all or part of the chiplets to fail to work properly; 2. Since the on-wafer system can be adapted to different application scenarios, the functions required in different scenarios are also different. If all chiplets are operated at the same time every time under the premise of ensuring safe power-on operation, it will not only increase power consumption and cause energy waste, but also cause performance loss; 3. If the control protocol for the interactive use of configuration data adopts traditional IIC, SPI and other bus protocols, it will face the problems of a large number of buses and dense bus connections. Using traditional buses to configure all chiplets requires each chiplet to send configuration signals one by one according to the address. Because the number of chiplets to be configured is large and the bus transmission rate is low, this method is too inefficient. If the JTAG daisy chain bus protocol is used, it will be affected by the yield of the internal circuits of the chip and the silicon substrate itself. Once a node in the daisy chain fails, the entire link cannot be properly controlled. Summary of the invention

[0004] In response to the problems existing in the prior art, the first object of the present invention is to provide an on-chip system, which is characterized by being able to accurately control the power status of each chip in the on-chip system and complete status feedback, which is safe and convenient, saves hardware resource overhead, reduces system power consumption, and improves the efficiency of power status configuration.

[0005] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: an on-chip system, including multiple module groups and a power control component, wherein the module group includes multiple core particles with the same function; the power control component includes a master controller and multiple slave controllers corresponding to the module groups, the master controller is connected to the multiple slave controllers through a first communication bus, and each slave controller is connected to each core particle in the corresponding module group; wherein the master controller is used to obtain power state configuration data of each module group through an external interface connected to the master controller, and send the power state configuration data to the corresponding slave controller, or to receive power state configuration data of each module group. The power status feedback data of the module group is uploaded by the slave controller and sent through the external interface; the slave controller is used to receive the power status configuration data, obtain the power status configuration information of each chip in the corresponding module group from the power status configuration data, and send the power status configuration information to the corresponding chip, or to receive the power status feedback information uploaded by the chip and generate power status feedback data to send, and upload the power status feedback data to the main controller; the chip is used to receive the power status configuration information and set the power status according to the power status configuration information, or to upload the power status feedback information to the slave controller according to the instruction of the slave controller.

[0006] Preferably, the controller compares the power status configuration information of each chip in the corresponding module group with the power status feedback information of each chip one by one, or compares the power status configuration information of each chip in the corresponding module group with the power status configuration information acquired last time one by one, obtains the chip whose power status needs to be adjusted, and sends the corresponding power status configuration information to the chip whose power status needs to be adjusted.

[0007] Preferably, the main controller compares the power status configuration data of each module group with the power status configuration data obtained last time, or compares the power status configuration data of each module group with the power status feedback data of each module group one by one, so as to obtain the module group whose power status needs to be adjusted; the main controller sends the corresponding power status configuration data to the slave controller corresponding to the module group whose power status needs to be adjusted.

[0008] Preferably, the first communication bus protocol includes a start bit, a target address, a read / write flag, a response bit, a data field, a check field and a stop bit, which are responsible for data communication between the master controller and each slave controller; the target address includes the slave controller address, and the data field includes power status configuration data or power status feedback data; each slave controller has a unique slave controller address.

[0009] Another object of the present invention is to provide a power state configuration method in a wafer system, which is characterized in that it can complete the independent configuration of the power state of each chip in the wafer system, is safe and convenient, and improves the efficiency of power state configuration.

[0010] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a power state configuration method in a crystal system, which is used to configure the power state of a chip in the above-mentioned crystal system, and includes the following steps: a main controller receives a power state configuration message from an external interface; the main controller parses the power state configuration message to obtain power state configuration data; the main controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data; the slave controller obtains the power state configuration information of the chip in the corresponding module group from the power state configuration data; the slave controller sends the power state configuration information to the corresponding chip; the chip receives the power state configuration information sent by the slave controller, and sets the power state according to the power state configuration information.

[0011] Specifically, the master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data; including: the master controller sends a start bit, and sends the target address to the slave controller in a set order in a serial manner through the first communication bus; the slave controller receives the target address through the first communication bus, compares it with the local address and sends a response bit; after the master controller receives the correct response bit, it prepares to write data, and the master controller writes the power state configuration data to the first communication bus in serial bit by bit; the slave controller receives the power state feedback data and sends the response bit, if the master controller does not receive the correct response bit, it resends the data, if the master controller receives the correct response bit, the master controller calculates the check value and sends the check value as the check field, the slave controller calculates the check value and compares it with the received check field and sends the response bit; if the master controller receives an incorrect response bit, it resends the data, if the master controller receives the correct response bit, the master controller sends a stop signal and switches the target address to be sent to the slave controller address corresponding to the next module group; repeat the above steps until all slave controllers in the set order receive the power state configuration data.

[0012] Specifically, the slave controller obtains the power status configuration information of the corresponding chip in the module group from the power status configuration data, including: the binary valid part of the power status configuration data corresponds bit by bit to the power status configuration information of each chip in the module group, and the slave controller parses the power status configuration data bit by bit to extract the power status configuration information.

[0013] Another object of the present invention is to provide a power status feedback method in a chip system, which is characterized by being able to complete the feedback of the power status of each chip in the chip system for external users to make analysis and decisions, which is safe and convenient and improves the efficiency of power status configuration.

[0014] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a power status feedback method in a crystal system, which is used to feedback the power status of a core particle in the above-mentioned crystal system, comprising the following steps: the core particle uploads power status feedback information to the slave controller according to the instruction of the slave controller; the slave controller receives the power status feedback information uploaded by the core particle; the slave controller generates power status feedback data according to the power status feedback information and stores it in a register; the slave controller uploads the power status feedback data to the main controller, and the main controller receives the power status feedback data uploaded by the slave controller of each module group; the main controller packages the power status feedback data to generate a power status feedback message, and sends the power status feedback message through an external interface according to external instructions.

[0015] Specifically, the slave controller receives power status feedback information uploaded by the chiplet, generates power status feedback data according to the power status feedback information and stores it in a register, including combining the power status feedback information of the chiplets in the current module group into power status feedback data and writing it into the register of the slave controller in a bit-by-bit manner so that each chiplet corresponds to the binary valid part of the power status feedback data.

[0016] Specifically, the slave controller uploads the power status feedback data to the main controller, and the main controller receives the power status feedback data uploaded by the slave controllers of each module group, which specifically includes: the main controller sends a start bit and sends the target address to the slave controller in serial via the first communication bus; the slave controller receives the target address via the first communication bus, compares it with the local address and sends a response bit; after receiving the correct response bit, the main controller prepares to read the data, the slave controller reads the power status feedback data in the register, and writes the power status feedback data serially to the first communication bus, the main controller receives the power status feedback data and sends the response bit, if the slave controller does not receive the correct response bit, it resends the data, if the slave controller receives the correct response bit, the slave controller calculates the check value and sends the check value as the check field, the main controller calculates the check value and compares it with the received check field and sends the response bit; the main controller sends a stop signal and switches to the address of the slave controller in the next module group; repeat the above steps until the slave controllers corresponding to all module groups have completed sending the power status feedback data in the set order.

[0017] Another object of the present invention is to provide a power state control method in a chip system, which is characterized by being able to accurately control the power state of each chip in the chip system and complete state feedback, which is safe and convenient, saves hardware resource overhead, reduces system power consumption, and improves the efficiency of power state configuration.

[0018] To achieve the above-mentioned purpose, the technical solution adopted by the present invention is: a power state control method in a crystal system, which is used to control the power state of the core particles in the above-mentioned crystal system, including the above-mentioned power state configuration method and feedback method in the crystal system, and also includes the following steps: the main controller receives the power state configuration message, parses the power state configuration message to obtain the power state configuration data of each module group, compares the power state configuration data with the power state configuration data of each module group obtained last time, and obtains the power state configuration data of the module group in the module group that needs to change the power state; the main controller sends the power state configuration data of the module group that needs to change the power state to the corresponding slave controller, and receives the power state configuration data from the slave controller; the slave controller obtains the power state configuration information of the core particles in the corresponding module group from the power state configuration data; the slave controller sends the power state configuration information to the corresponding core particles; the core particles receive the power state configuration information sent by the slave controller, and set the power state according to the power state configuration information.

[0019] Specifically, power state configuration data is received from the controller, and after parsing the power state configuration data to obtain power state configuration information of each chip, the power state configuration information is compared with the power state configuration information of each chip obtained last time to obtain the power state configuration information of the chip in the module group whose power state needs to be changed.

[0020] The beneficial effects of the present invention are: (1) It has the ability to control the power state of the chip of the on-chip system according to the pre-configuration, and the chip startup is not all started at once, but the chip is started in the module group according to the issued system configuration plan. In this way, the data processing of the power state is clearer and easier to encode, and at the same time, it can avoid the large current caused by the simultaneous power-on startup of a large number of chiplets and the destruction of the circuit structure, reducing the configuration difficulty, safe and convenient. (2) The applicable chip or the chip that is not applicable to the scene can be started or shut down according to the functional configuration, so that the on-chip system can provide the best performance with the lowest power consumption, save hardware resource overhead, and reduce system power consumption. (3) The custom bus communication method introduced in the present invention only exchanges data in a serial manner between the module group and the main controller, and the module group interacts in a parallel manner between the chiplets, thereby solving the high line connection density and high processing difficulty caused by the dense wiring brought by the use of traditional bus connection and configuration of all chiplets, and at the same time can avoid the problem of signal crosstalk caused by dense wiring. (4) By adding a verification mechanism and a retransmission mechanism to the protocol, the reliability of data transmission is further guaranteed, and the signal flipping caused by line problems or other reasons during the transmission process, which results in the configuration result being different from the expectation, is avoided. Therefore, the present invention provides an efficient and reliable on-chip system chip power state control method. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a structural schematic diagram of the on-wafer system of the present invention;

[0022] Figure 2 It is a schematic diagram of the structure of the module group of the on-wafer system of the present invention;

[0023] Figure 3 A first communication bus protocol diagram of the present invention;

[0024] Figure 4 A flow chart of the power state configuration method of the present invention;

[0025] Figure 5 A flowchart of step 103 of the power state configuration method of the present invention;

[0026] Figure 6 It is a flow chart of the power supply state feedback method of the present invention;

[0027] Figure 7 is a flow chart of step 304 of the power supply status feedback method of the present invention;

[0028] Figure 8 It is a flow chart of the power state control method of the present invention;

[0029] Fig. 9 The slave controller address list format of the present invention;

[0030] Fig.10 The format of the chiplet address list of a specific embodiment of the present invention;

[0031] Fig.11 It is a structural schematic diagram of an on-wafer system according to a specific embodiment of the present invention;

[0032] Fig.12 A first communication bus protocol diagram of a specific embodiment of the present invention;

[0033] Fig.13 A state machine diagram of a main controller according to a specific embodiment of the present invention;

[0034] Fig.14 A first communication bus timing diagram of a specific embodiment of the present invention;

[0035] Fig.15 A state machine diagram of a slave controller according to a specific embodiment of the present invention;

[0036] Fig.16 A chiplet address list of a specific embodiment of the present invention;

[0037] Fig.17 A slave controller address list according to a specific embodiment of the present invention;

[0038] Fig.18 It is a schematic diagram of the power supply status structure of the on-chip system according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0040] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the drawings, and the words "bottom" and "top", "inner" and "outer" refer to directions toward or away from the geometric center of a specific component, respectively.

[0042] The present invention provides a chip-on-chip system, including multiple module groups and power control components, such as Figure 1 , 2 As shown, the module group includes multiple cores with the same function. Specifically, each core has a unique core address. Allocating cores with the same function to the same module group is conducive to improving the efficiency of power management, because the communication processing between homogeneous cores will be simpler and the data processing will be more efficient, while the communication between heterogeneous cores does not have this advantage. And it can simplify the encoding of power control data by the main controller. And in most cases, the switching of the on-chip system working mode (that is, the control of the power status of each core) always turns on one or several types of cores at the same time, or turns off one or several types of cores at the same time, that is, the control of the core power is always controlled by category, and only in a few cases will part of the same type of cores be controlled to be turned on or off.

[0043] The power control component includes a main controller and a plurality of slave controllers corresponding to the module groups. The main controller is connected to the plurality of slave controllers through a first communication bus, and each slave controller is connected to each chip in the corresponding module group; wherein,

[0044] The main controller is used to obtain the power state configuration data of each module group through an external interface connected to the main controller, and send the power state configuration data to the corresponding slave controller, or to receive the power state feedback data uploaded by the slave controller of each module group and send it through the external interface. Specifically, the power state configuration data of each module group contains the power state configuration information of each core particle in the module group, and the power state feedback data of each module group contains the power state feedback information of each core particle in the module group. Usually, the system on the crystal is equipped with a power supply PCB board, and a main control device is set on the power supply PCB board. The above-mentioned main controller can be built into the main control device. An external interface is also provided on the main control device, and the external interface is connected to the main controller for communication, so as to realize the communication between the main controller and the external control host. Optionally, the external interface includes but is not limited to a proximal serial port or a remote TCP network port, and the external interface can be connected to an external control host. The external user can input a power state configuration file containing the power state configuration data on the external control host, and can also display the power state feedback data through the external control host to know the power state of each module group and its internal core particles in the crystal system.

[0045] It should be noted that the external user referred to in the present invention includes but is not limited to a user and a computing system. The second communication bus protocol includes a target address and an information field, the target address is the core address of the target core or the address of the slave controller, and the information field includes power state configuration information or power state feedback information.

[0046] The slave controller is used to receive the power state configuration data of the corresponding module group, obtain the power state configuration information of each core in the corresponding module group, and send the power state configuration information to the corresponding core, or to receive the power state feedback information uploaded by the core, and generate power state feedback data to send, and upload the power state feedback data to the main controller. Specifically, the slave controller disassembles the received power state configuration data into the power state configuration information of each core, and sends it to the corresponding core. Alternatively, the slave controller splices the received power state feedback information into power state feedback information, and uploads it to the main controller.

[0047] Optionally, the slave controller may be disposed in one of the core particles of the corresponding module group, and the core particle provided with the slave controller and other core particles of the module group are communicatively connected via a second communication bus, so as to realize the communication connection between the slave controller and each core particle in the module group. Figure 2 As shown, there are k*m cores in the module group, and the slave controller is set in core 0. Core 0 and other k*m-1 cores are connected to each other through the second communication bus. Figure 1As shown, in the wafer-on-wafer system of the present invention, the module groups are distributed on the wafer, and the master controller is connected to the core particles with built-in slave controllers in each module group through a first communication bus including a clock line SCL and a data line SDA. The first communication bus also includes multiple address lines ADDR. The N address lines ADDR can be up to 2 N Each chip provides a different address.

[0048] The power state configuration information is used to indicate the power state required by the chip with different contents. In actual use, the content of the power state configuration information can be specifically set according to the actual situation of the power state required by the chip. For example, the power state configuration information of "0" indicates that the chip needs to be configured to a non-working or low-power consumption mode; the power state configuration information of "1" indicates that the chip needs to be configured to a normal working mode. Similarly, the power state feedback information is used to indicate the power state of the chip when it is giving feedback, and indicates the power state fed back by the chip with different contents. In actual use, the content of the power state feedback information can be specifically set according to the actual situation of the power state of the chip when it is giving feedback. In this embodiment, the two chip states that need to be configured, namely, the non-working mode and the low-power consumption mode, are set to correspond to the same power state configuration information content because the non-working or low-power consumption mode of the chip is determined by the power design of the chip, and the same power signal is sent, and the chip may be in a non-working mode or a low-power consumption mode.

[0049] The chip is used to receive power state configuration information sent from the controller and set the power state according to the power state configuration information, or to upload power state feedback information to the slave controller according to the instruction of the slave controller. Specifically, the chip can adjust its own power state according to the power state configuration information after receiving the power state configuration information, and can also upload its own power state after receiving the instruction of the slave controller, that is, the power state request signal from the slave controller. The optional way for the chip to realize the above functions is as follows: each chip has a chip power-on control circuit, and after receiving the power state configuration information, the chip power-on control circuit sends a corresponding power enable signal to the power enable port of the chip, so that the power state of the chip is consistent with the required power state displayed by the power state configuration information. For example, if the power enable signal that puts the chip in a non-working or low-power mode is "0", and the power enable signal that puts the chip in a normal working mode is "1", and the power status configuration information is "0" indicating that the chip needs to be configured to a non-working or low-power mode, and the power status configuration information is "1" indicating that the chip needs to be configured to a normal working mode, that is, the content of the power status configuration information is consistent with the power enable signal of the chip; then the chip power-on control circuit sends the power status configuration information to the power enable port of the chip to complete the setting of the power status of the chip. If the power enable signal that puts the chip in non-operating or low-power mode is "1", and the power enable signal that puts the chip in normal operating mode is "0", and the power state configuration information is "0" indicating that the chip needs to be configured in non-operating or low-power mode, and the power state configuration information is "1" indicating that the chip needs to be configured in normal operating mode, that is, the content of the power state configuration information is inverted from the power enable signal of the chip; then the chip power-on control circuit sends the inverted signal of the power state configuration information to the power enable port of the chip to complete the setting of the chip power state. It should be noted that, according to actual needs, the above-mentioned chip power-on control circuit can be set in the chip or integrated in the slave controller; those skilled in the art can also use conventional technical means to implement the above functions.

[0050] This setting can realize accurate control of the power-on status of each chip in the on-chip system, and can avoid the problem that the surge caused by all-at-on power-on startup damages the circuit structure and causes all or part of the chips to fail to work properly. At the same time, according to different application scenarios, the power-on status of different chips in the system can be adaptively set to adjust the power consumption of the entire on-chip system and reduce unnecessary energy consumption. At the same time, it can also feedback the power status of all chips in the on-chip system for external users to make analysis and decisions.

[0051] Preferably, the slave controller compares the power state configuration information of each core particle in the corresponding module group with the power state feedback information of each core particle one by one, or compares the power state configuration information of each core particle in the corresponding module group with the power state configuration information obtained last time one by one, obtains the core particle whose power state needs to be adjusted, and sends the corresponding power state configuration information to the core particle whose power state needs to be adjusted. With this arrangement, the slave controller can obtain the core particle whose power state needs to be adjusted in two ways. One way is that the slave controller obtains the core particle whose power state needs to be adjusted by comparing the obtained power state configuration information with the power state feedback information uploaded by the core particle. Another way is that the slave controller obtains the core particle whose power state needs to be adjusted by comparing the power state configuration information obtained this time or the power state configuration information of the core particle obtained last time. Therefore, the slave controller does not need to send power state configuration information to all the chiplets in the module group. It only needs to send configuration information to some chiplets that need to adjust their current power state to change their power state, thereby achieving accurate configuration from the controller to the chiplets, saving hardware resource overhead, reducing system power consumption, and improving the efficiency of power state configuration.

[0052] Preferably, the main controller compares the power state configuration data of each module group with the power state configuration data obtained last time, or compares the power state configuration data of each module group with the power state feedback data of each module group, so as to obtain the module group that needs to adjust the power state, and sends the corresponding power state configuration data to the slave controller corresponding to the module group that needs to adjust the power state. In this way, the main controller obtains the module group that needs to adjust the power state and the corresponding slave controller in two ways. One way is that the main controller compares the power state configuration data currently obtained with the power state configuration data obtained last time. Another way is that the main controller compares the power state configuration data currently obtained with the power state feedback data uploaded by the slave controller. Therefore, the main controller does not need to send the power state configuration data to all slave controllers, but only needs to send the configuration data to the slave controllers corresponding to some module groups that need to adjust the current power state, thereby realizing accurate data transmission from the main controller to the slave controller, saving hardware resource overhead, reducing system power consumption, and improving the efficiency of power state configuration.

[0053] Preferably, if Figure 3As shown, the first communication bus protocol includes a start bit, a target address, a read / write flag, a response bit, a data field, a check field and a stop bit, which are responsible for data communication between the master controller and each slave controller. The target address includes the slave controller address, and the data field includes power state configuration data or power state feedback data. Each slave controller has a unique slave controller address. The first communication bus protocol includes a response mechanism and a check mechanism to ensure that the data is correctly received by the slave controller. The response bit is used to ensure the reliability and correctness of the communication between the master controller and the slave controller. After receiving a target address or data field or check field, the slave controller feeds back the correct response bit to notify the master controller or the slave controller. If the master controller or the slave controller does not receive a response or receives an incorrect response within the specified time, the master controller or the slave controller starts the retransmission mechanism and repeatedly sends the data. If the preset number of times cannot get a correct response, it is judged that the core is damaged and the retransmission ends; if the response is correct, the retransmission ends. The external user can read the core state table on the master controller through the network to know the working status of the core and whether it is damaged. The number of bits of the response bit includes but is not limited to one. The above-mentioned check field is used to check the correctness and integrity of the data field transmission. The check field is generated using a check algorithm, and the check algorithm used includes but is not limited to CRC, MD5 or SHA algorithms. After the main controller or the slave controller receives the check data, it checks the register address and data content. If the check result is correct, it returns the correct response bit. If the check result is wrong, it returns the wrong response bit. After the main controller or the slave controller receives the wrong response bit, it starts the retransmission mechanism. If the response is correct, the retransmission ends. The retransmission ends after the preset number of consecutive retransmissions fails. A custom bus communication method is introduced, and data is only exchanged in serial mode between the module group and the main controller, while the module group interacts in parallel mode between the core particles, thereby solving the high line connection density and high processing difficulty caused by the dense wiring brought about by the use of traditional bus connections and the configuration of all core particles, and also avoiding the problem of signal crosstalk caused by dense lines.

[0054] The present invention also provides a power state configuration method in a wafer system, which is used to configure the power state of a chip in the wafer system, such as Figure 4 As shown, the following steps are included:

[0055] Step 101: The main controller receives a power state configuration message from an external interface;

[0056] Step 102: The main controller parses the power state configuration message to obtain power state configuration data;

[0057] Step 103: the master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data;

[0058] Step 104: The controller obtains the power state configuration information of the chip in the corresponding module group from the power state configuration data;

[0059] Step 105: Sending power state configuration information from the controller to the corresponding chip;

[0060] Step 106: The chip receives the power state configuration information sent from the controller, and sets the power state according to the power state configuration information.

[0061] Specifically, the power state configuration message contains the power state configuration data of all module groups in the on-chip system. After the main controller receives the power state configuration message from the external interface, it can parse the power state configuration data of each module group from the power state configuration message, and package it and send it to the slave controller corresponding to the module group. In addition, the power state configuration data of each module group contains the power state configuration information of all core particles in the module group. After receiving the power state configuration data from the slave controller, the power state configuration information of each core particle can be extracted from the power state configuration data. The slave controller sends the power state configuration information to the corresponding core particle. After receiving the power state configuration information, the core particle can set its own power state according to the power state configuration information, thereby completing the power state configuration. This setting can realize the precise control of the power-on state of each core particle in the on-chip system, and can avoid the problem of all or part of the core particles not being able to work properly due to the surge generated by all-on startup. At the same time, according to different application scenarios, the power-on state of different core particles in the system can be adaptively set to adjust the power consumption of the entire on-chip system and reduce unnecessary energy consumption.

[0062] Specifically, in the above step 102, the main controller parses the power configuration message to obtain the power configuration data; including, the main controller searches the module group-slave controller address mapping table, splits the data of the power configuration message by module group, and obtains the power state configuration data of each module group; each of the slave controllers has a unique slave controller address. The module group-slave controller address mapping table has a built-in correspondence between the module group and the corresponding slave controller address, which is stored in the internal memory of the main controller.

[0063] Specifically, Figure 5 As shown, in the above step 103, the master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data; specifically,

[0064] Step 201: the master controller sends a start bit and sends a target address to the slave controller in a serial manner via a first communication bus;

[0065] Step 202: The slave controller receives the target address via the first communication bus, compares it with the local address and sends a response bit;

[0066] Step 203: After receiving the correct response bit, the main controller prepares to write data, and the main controller writes the power state configuration data bit by bit serially into the first communication bus;

[0067] Step 204: The slave controller receives the power status feedback data and sends a response bit. If the master controller does not receive the correct response bit, the data is resent. If the master controller receives the correct response bit, the master controller calculates the check value and sends the check value as the check field. The slave controller calculates the check value and compares it with the received check field and sends the response bit. If the master controller receives an incorrect response bit, the data is resent. If the master controller receives the correct response bit, the master controller sends a stop signal and switches the target address to be sent to the slave controller address corresponding to the next module group.

[0068] Step 205: Repeat the above steps 201-204 until all slave controllers in the set order receive the power state configuration data.

[0069] As described above, if the main controller does not receive a response or receives an incorrect response within the specified time, the main controller starts the retransmission mechanism and repeatedly sends the data. If the preset number of retransmissions fails to get a correct response, it is determined that the slave controller or the chip where the slave controller is located is damaged and the retransmission ends; if the response is correct, the retransmission ends. The external user object can read the chip status table on the main controller through the network to know the working status of the chip and whether it is damaged. If the verification result is correct, the correct response bit is returned afterwards. If the verification result is wrong, the wrong response bit is returned afterwards. After the main controller receives the wrong response bit, it starts the retransmission mechanism. If the response is correct, the retransmission ends. The retransmission ends after the preset number of consecutive retransmissions fail to verify. The above setting order can be in accordance with the address order of the slave controller, or it can be another order specified by the external user object.

[0070] Specifically, the above step 104, from the controller, obtains the power state configuration information of the chip in the corresponding module group from the power state configuration data; specifically includes that the binary valid part of the power state configuration data corresponds to the power state configuration information of each chip in the module group bit by bit, and the controller parses the power state configuration data bit by bit to extract the power state configuration information. The power state configuration data is converted into binary form, the number of bits of the valid part of the binary form of the power state configuration data is the same as the number of chip in the module group, and each valid bit of the binary form of the power state configuration data corresponds to the power state configuration information of a chip. For example, there are chip No. 0, chip No. 1, chip No. 2, and chip No. 3 in a module group, a total of four chips, the power state configuration data is "0101b", and the binary valid part of the power state configuration data is "0101", then the power state configuration information of chip No. 0 is "1", the power state configuration information of chip No. 1 is "0", the power state configuration information of chip No. 2 is "1", and the power state configuration information of chip No. 3 is "0".

[0071] Specifically, the above step 105, sending the power state configuration information from the controller to the corresponding chiplet, includes sending the power state configuration information from the controller to the corresponding chiplet through the second communication bus.

[0072] Specifically, in the above step 106, the chip receives the power state configuration information sent from the controller and sets the power state according to the power state configuration information, including, as described above, after the chip power-on control circuit receives the power state configuration information, sending a corresponding power enable signal to the chip, so that the power state of the chip is consistent with the required power state displayed by the power state configuration information.

[0073] The present invention also provides a power supply status feedback method in a wafer system, which is used to feedback the power supply status of the chip in the wafer system, such as Figure 6 As shown, the following steps are included:

[0074] Step 301: the chip uploads power status feedback information to the slave controller according to the instruction of the slave controller;

[0075] Step 302: receiving power status feedback information uploaded by the chip from the controller;

[0076] Step 303: The slave controller generates power state feedback data according to the power state feedback information and stores the data in a register;

[0077] Step 304: the slave controller uploads the power status feedback data to the main controller, and the main controller receives the power status feedback data uploaded by the slave controllers of each module group;

[0078] Step 305: The main controller packages the power state feedback data to generate a power state feedback message, and sends the power state feedback message through the external interface according to the external instruction.

[0079] This setting can provide feedback on the power status of all chiplets in the on-wafer system for external users to make analysis and decisions.

[0080] Specifically, the chip uploads the power state feedback information to the slave controller according to the instruction of the slave controller, including sending a feedback request instruction from the slave controller to all the chiplets in the module group, and after each chip receives the feedback instruction, it sends the power state feedback information corresponding to the power state at the time of its feedback to the slave controller. The corresponding relationship between the power state feedback information and the power state is as described above.

[0081] Specifically, the above steps 302 and 303, receive the power state feedback information uploaded by the chip from the slave controller, generate the power state feedback data according to the power state feedback information and store it in the register; including, the slave controller combines the power state feedback information of the chip in the current module group into the power state feedback data in a bit-by-bit correspondence manner between each chip and the binary effective part of the power state feedback data and writes it into the register of the slave controller. As described above, for example, there are four chip No. 0, No. 1, No. 2, and No. 3 in a module group, the power state feedback information of chip No. 0 is "1", the power state feedback information of chip No. 1 is "0", the power state feedback information of chip No. 2 is "1", and the power state feedback information of chip No. 3 is "0", then the binary effective part of the power state feedback data generated by the combination is "0101", and the complete power state feedback data of the module group is "0101b".

[0082] Specifically, in the above step 304, the slave controller uploads the power status feedback data to the main controller, and the main controller receives the power status feedback data uploaded by the slave controllers of each module group; Figure 7 As shown, including:

[0083] Step 401: the master controller sends a start bit and sends a target address to the slave controller in a serial manner via a first communication bus;

[0084] Step 402: The slave controller receives the target address via the first communication bus, compares it with the local address and sends a response bit;

[0085] Step 403: After receiving the correct response bit, the master controller prepares to read data, reads the power status feedback data in the register from the slave controller, and serially writes the power status feedback data into the first communication bus. The master controller receives the power status feedback data and sends the response bit. If the slave controller does not receive the correct response bit, it resends the data. If the slave controller receives the correct response bit, the slave controller calculates the check value and sends the check value as the check field. The master controller calculates the check value and compares it with the received check field and sends the response bit.

[0086] Step 404: the master controller sends a stop signal and switches to the address of the slave controller in the next module group;

[0087] Step 405: repeat the above steps 401-404 until all slave controllers corresponding to all module groups have sent the power status feedback data in the set order.

[0088] As described above, if the slave controller does not receive a response or receives an incorrect response within the specified time, the retransmission mechanism is started and the data is sent repeatedly. If the preset number of retransmissions fails to get a correct response, the retransmission ends; if the response is correct, the retransmission ends. If the verification result is correct, the correct response bit is returned afterwards. If the verification result is wrong, the wrong response bit is returned afterwards. After the slave controller receives the wrong response bit, the retransmission mechanism is started. If the response is correct, the retransmission ends. If the verification fails for the preset number of consecutive retransmissions, the retransmission ends. The above setting order can be in accordance with the address order of the slave controller, or it can be another order specified by the external user object.

[0089] Specifically, in the above step 305, the main controller packages the power status feedback data to generate a power status feedback message, and sends the power status feedback message through the external interface according to the external instruction; including that the main controller combines and packages the power status feedback data sent by all corresponding slave controllers in a set order to generate a power status feedback message.

[0090] The present invention also provides a power state control method in a wafer system, which is used to control the power state of a chip in the wafer system, including the power state configuration method and feedback method in the wafer system. Figure 8 As shown, the following steps are also included:

[0091] Step 501: the main controller receives a power state configuration message, parses the power state configuration message to obtain power state configuration data of each module group, compares the power state configuration data with the power state configuration data of each module group obtained last time, and obtains the power state configuration data of the module group whose power state needs to be changed in the module group;

[0092] Step 502: the master controller sends the power state configuration data of the module group whose power state needs to be changed to the corresponding slave controller, and the slave controller receives the power state configuration data;

[0093] Step 503: the slave controller obtains the power state configuration information of the chiplets in the corresponding module group from the power state configuration data; and the slave controller sends the power state configuration information to the corresponding chiplets;

[0094] Step 504: The chip receives the power state configuration information sent from the controller, and sets the power state according to the power state configuration information.

[0095] The above-mentioned main controller receives the power status configuration message, parses the power status configuration message to obtain the power status configuration data of each module group, compares the power status configuration data with the power status configuration data of each module group obtained last time, and obtains the power status configuration data of the module group in the module group that needs to change the power status; the main controller sends the power status configuration data of the module group that needs to change the power status to the corresponding slave controller, and receives the power status configuration data from the slave controller. Specifically, the main controller parses the power status configuration message to obtain the power status data of each module group, and then binds the power status configuration data with the unique address of the slave controller corresponding to the module group to generate a slave controller routing list. After receiving the power status feedback data, the main controller can also bind the power status feedback data with the unique address of the slave controller corresponding to the module group to generate a slave controller routing list. The format of the slave controller routing list is as follows: Fig. 9As shown, the content includes the slave controller address, the power status data of the module group, and the valid-invalid bit. During initialization, the power status of each chip in each module group in the slave controller routing list generated by the master controller is set to 0. After all the steps of each configuration method are executed, all the steps of the feedback method are executed. The master controller compares the slave controller routing list generated by the analysis with the slave controller routing list generated last time. If the power status data of the module group is the same, the routing item in the slave controller routing list generated this time is invalidated by setting the valid-invalid bit of the routing item in the slave controller routing list generated this time. After comparing the routing items one by one and adjusting the valid-invalid bit, the slave controller routing list of this time is generated. The target address to be sent by the master controller is set to the slave controller address of the valid routing item in the slave controller routing list generated this time, and the data field to be sent is set to the power status configuration data of the module group in the valid routing item in the slave controller routing list generated this time. The master controller sends the power status configuration data of the valid routing items in the slave controller routing list generated this time in the set order until all slave controllers corresponding to the valid routing items receive the power status configuration data. As described above, with this configuration, the master controller does not need to send power status configuration data to all slave controllers, but only needs to send configuration data to the slave controllers corresponding to some module groups that need to adjust the current power status, thereby achieving accurate data transmission from the master controller to the slave controllers, saving hardware resource overhead, reducing system power consumption, and improving the efficiency of power status configuration.

[0096] Preferably, after receiving power state configuration data from the controller and parsing the power state configuration data to obtain the power state configuration information of each chip, the power state configuration information is compared with the power state configuration information of each chip obtained last time, and the power state configuration information of the chip in the module group that needs to change the power state is obtained. Specifically, after receiving the power state configuration data from the controller, the power state configuration data is parsed bit by bit and bound to the corresponding chip address to form a chip routing list. After receiving the power state feedback information from the controller, the power state feedback information can also be bound to the unique address of the corresponding chip to generate a chip routing list. The format of the chip routing list is as follows: Fig.10As shown, the content includes the chip address, the power status information of the chip, and the valid-invalid bit. During initialization, the power status information of the chip in the chip routing list generated by the slave controller is set to 0. The slave controller compares the parsed chip routing list with the chip routing list generated last time. If the power status information of the chip is the same, the valid-invalid bit of the routing item in the chip routing list generated this time is set to make the routing item invalid. After comparing the routing items one by one and adjusting the valid-invalid bit, the slave controller routing list is generated this time. The target address to be sent from the slave controller is set to the chip address of the valid routing item in the chip routing list generated this time, and the power status configuration information is set to the power status configuration information of the chip in the valid routing item in the chip routing list generated this time. The slave controller sends the power status configuration information of the valid routing items in the chip routing list generated this time in the set order until the chip corresponding to all valid routing items receive the power status configuration information. As described above, with this configuration, the slave controller does not need to send power state configuration information to all the chiplets in the module group. It only needs to send configuration information to some chiplets that need to adjust their current power state to change their power state, thereby achieving accurate configuration from the controller to the chiplets, saving hardware resource overhead, reducing system power consumption, and improving the efficiency of power state configuration.

[0097] The above is the core idea of ​​the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application. The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention.

[0098] Specific embodiment: A system on a wafer, such as Fig.11 As shown, it includes a wafer with multiple core particles integrated and a main controller. The circular area in the figure represents a wafer. There are 16 module groups on the wafer, and each module group has 4 core particles with the same function. A power supply network (VDD) and a ground network (GND) are provided on the wafer, and each core particle is connected to the power supply network (VDD) and the ground network (GND). In the figure, a slave controller is provided in the core particle 0 of each module group. The main controller communicates and connects with the core particle 0 with the slave controller in each module group through the first communication bus, that is, the main controller is connected to the core particle 0 of each module group. There is 1 clock line (SCL), 1 data line (SDA), and 4 address lines (ADDR).

[0099] like Fig.12 As shown, in this embodiment, the protocol of the first communication bus includes a bus message format, including a start bit (S), an 8-bit target address, a read / write flag ( R represents the read signal, Indicates write signal), 8-bit data field, 4-bit check field, one stop bit (P) and several acknowledge bits. The acknowledge bit includes acknowledge signal (A) and non-acknowledge signal

[0100] The start bit (S) is the start flag of bus communication, which notifies the slave device to start communication. When SCL is high, a falling edge on SDA indicates the start bit;

[0101] 8-bit target address: represents the target module group to which the power state configuration data is to be sent or the target module group to which the power state feedback data needs to be read. Since the module group corresponds to the slave controller one by one, the 8-bit target address is set as the slave controller address, that is, the 8-bit target address is set as the register address of the chip where the slave controller is located. In this embodiment, the slave controller addresses of the 16 slave controllers corresponding to the 16 module groups on the wafer are: 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0f.

[0102] Read / write flag: indicates the read / write type of the message. If it is marked as a write signal, the corresponding data field is written to the register address of the chip where the corresponding slave controller is located. If it is marked as a read signal, the slave controller returns the data in the corresponding register address to the master controller.

[0103] 8-bit data field: can read and write one byte of power state configuration data or power state feedback data.

[0104] 4-bit check field: Checks the correctness and integrity of the data field. Uses a check algorithm (CRC, SHA or MD5, etc.). The master controller or slave controller calculates the check result of the data respectively, and compares the calculated check result with the data in the received check field. If the check result is correct, the correct response bit is then fed back. Otherwise, an incorrect response bit is fed back.

[0105] Stop bit: It is the end mark of bus communication, which notifies the slave to end the communication. When SCL is at a high level, a rising edge on SDA indicates a stop bit.

[0106] Several response bits: "A" or The field indicates the response bit. After receiving the data of a field, the chip where the slave controller is located feeds back a response signal (A) to inform the master controller. If the master controller does not receive a response within the specified time or receives a non-response signal The main controller starts the retransmission mechanism and sends the data repeatedly. If the response is correct, the retransmission ends. If the correct response is not obtained after three retransmissions (i.e. the preset number of times mentioned above), the main controller ends the retransmission and determines that the chip is damaged.

[0107] The main controller is set in the main control device on the power supply PCB board outside the wafer. It contains message retransmission logic circuit, verification algorithm circuit, etc. Its logic function mainly includes a main controller state machine, such as Figure 13-14 shown.

[0108] The master controller state machine includes the following states: IDLE state, Ready state, Slave_ADDR state, Read_DATA state, Write_DATA state, Check state, Calc state, Acq_State state, and P_State state, a total of 9 states.

[0109] The idle state is the IDLE state: that is, the initial state, which is responsible for detecting whether the power state configuration message is received and parsing the power state configuration message. In the IDLE state processing logic of the main controller, it waits for the power state configuration message to be sent to the external interface. When the power state configuration message is received, it starts to parse the power state configuration message, extracts the power state configuration data from the message, binds the power state configuration data with the unique address of the slave controller corresponding to the module group to generate a slave controller routing list, and compares the power state data of each module group in the slave controller routing list generated last time. If there is a similarity, the routing item is invalidated, that is, the valid-invalid bit of the routing item is set to 0. In this embodiment, the valid-invalid bit is 1 to indicate that the routing item is valid, and the valid-invalid bit is 0 to indicate that the routing item is invalid. The power state of the core particles in each module group is represented by 0 and 1, and the target address to be sent is set to the first valid item in the routing table, that is, the power state configuration information of the core particles in each module group is represented by 0 and 1. The target address to be sent is set to the slave controller address of the first valid routing item, and the power status data is set to the first valid routing item after parsing, which is the power status configuration data corresponding to the first module group in this embodiment. After completion, it enters the ready state.

[0110] Ready state: responsible for starting the data transmission from the master controller to the slave controller corresponding to the target address when writing configuration data. In the Ready state processing logic of the master controller, a start signal is sent, that is, SCL and SDA are set to high level at the same time, and SDA is set to low level during this period. After completion, the target address is sent, that is, the Slave_ADDR state is entered.

[0111] The state of sending the target address is the Slave_ADDR state: responsible for sending the target address and the read / write flag to the target slave controller. In the Slave_ADDR state processing logic of the master controller, when SCL is pulled low, SDA is changed to the highest bit 0b of the target address value to be sent, and after the SDA change is completed, SCL is pulled high to keep SDA unchanged, and then SCL is pulled low to complete the sending of the highest bit address. According to this method, the target address 0x00 is sent bit by bit in serial mode. Case 1: When the previous state is the Ready state, after the target address is sent, a write signal (0) is sent as a read / write flag. When the master controller receives the response signal (A), the state switches to the write data state, i.e., the Write_DATA state; if the master controller does not receive the response signal in the Slave_ADDR state, it resends the target address until the response signal is received, or sends a stop signal (P) after the number of resends reaches the set number of times and still no response signal is received. At this time, if the current target address is not the address of the last valid routing item in the slave controller routing list, the target address to be sent is set to the slave controller address of the next valid routing item in the slave controller routing list, and the power state configuration data is set to the power state data of the module group of the next valid routing item in the slave controller routing table after parsing. After completion, it enters the Ready state, i.e., the Ready state. If the current target address is the address of the last valid routing item in the slave controller routing list, the master controller enters the feedback acquisition state, i.e., the Acq_State state. Case 2: When the previous state is the Acq_State state, after the target address is sent, a read signal, i.e., (1), is sent as a read / write flag. When the master controller receives the response signal (A), the state switches to the data reading state, i.e., the Read_DATA state, and is ready to read data, while controlling SCL to switch between high and low levels; if the master controller does not receive the response signal in the Slave_ADDR state, it resends the target address until the response signal is received, or sends a stop signal (P) after the number of resends reaches the set number of times and still no response signal is received. At this time, if the current target address is not the address of the last valid routing item in the slave controller routing list, the target address to be sent is set to the slave controller address of the next valid routing item in the slave controller routing list, and the power state configuration data is set to the power state data of the module group of the next valid routing item in the slave controller routing table after parsing. After completion, it enters the Ready state, i.e., the Ready state. If the current target address is the address of the last valid routing item in the slave controller routing list, the master controller enters the feedback acquisition state, i.e., the Acq_State state.

[0112] Read data state, i.e., Read_DATA state: is responsible for receiving data from the slave controller. In the Read_DATA state processing logic of the master controller, after receiving the data field, i.e., the power state feedback data, the master controller sends a response signal (A) and switches the state to the verification state, i.e., the Check state.

[0113] Write data state, i.e. Write_DATA state: responsible for sending power state configuration data to the target slave controller. In the Write_DATA state processing logic of the master controller, when SCL is pulled low, SDA is changed to the power state configuration data to be sent. After the SDA change is completed, SCL is pulled high to keep SDA unchanged, and then SCL is pulled low to complete the sending of the highest bit address. According to this method, the power state configuration data is sent serially bit by bit. If the master controller receives a response signal (A), it switches to the calculation verification state, i.e. Calc state; if the master controller does not receive a response signal (A) in the Write_DATA state, it re-configures the power state data until the response signal (A) is received, or sends a stop signal (P) after the number of retransmissions reaches the set number of times and still no response signal is received. At this time, if the current target address is not the address of the last valid routing item in the slave controller routing list, the target address to be sent is set to the slave controller address of the next valid routing item in the slave controller routing list, and the power state configuration data is set to the power state data of the module group of the next valid routing item in the slave controller routing table after parsing. After completion, it enters the ready state, i.e. Ready state. If the current target address is the address of the last valid routing item in the slave controller routing list, the master controller enters the feedback acquisition state, namely, the Acq_State state.

[0114] The check state is the Check state: responsible for checking whether the received check field value matches the check value calculated by the check algorithm. In the Check state processing logic of the main controller, the main controller receives the check field, and then calculates the received power supply status feedback data according to the same check algorithm, and then compares the calculated check value with the received check field value. If they completely match, it means that the data transmission is correct, and the main controller sends a response signal (A); if they do not match, it means that the data transmission has an error, and the main controller sends a non-response signal The master controller receives the stop signal (P). At this time, if the current target address is not the address of the last valid routing item in the slave controller routing list, the target address to be sent is set to the slave controller address of the next valid routing item in the slave controller routing list, and the power state configuration data is set to the power state configuration data of the module group of the next valid routing item in the slave controller routing table after parsing. After completion, it enters the continue configuration state, i.e., the Acq_State state. If the current target address is the address of the last valid routing item in the slave controller routing list, the master controller enters the feedback sending state, i.e., the P_State state.

[0115] Calculation state, i.e., Calc state: responsible for calculating the value of the check field according to the value of the data field. In the Calc state processing logic of the main controller, the CRC-4 / ITU check algorithm is used in this embodiment to calculate the check value, i.e., the check field value, for the power state configuration data of the data field, and send it bit by bit through the serial bus. If the main controller receives a response signal (A), it sends a stop signal (P). At this time, if the current target address is not the address of the last valid routing item in the slave controller routing list, the target address to be sent is set to the slave controller address of the next valid routing item in the slave controller routing list, and the power state configuration data is set to the power state data of the module group of the next valid routing item in the slave controller routing table after parsing. After completion, it enters the ready state, i.e., the Ready state. If the current target address is the address of the last valid routing item in the slave controller routing list, the main controller enters the feedback acquisition state, i.e., the Acq_State state. If the main controller receives an unanswered signal Then it returns to the write data state, i.e., Write_DATA state, to resend the power state configuration data, or sends a stop signal (P) after the number of resends reaches the set number and still no response signal is received. At this time, if the current target address is not the address of the last valid routing item in the slave controller routing list, the target address to be sent is set to the slave controller address of the next valid routing item in the slave controller routing list, and the power state configuration data is set to the power state data of the module group of the next valid routing item in the slave controller routing table after parsing. After completion, it enters the ready state, i.e., Ready state. If the current target address is the address of the last valid routing item in the slave controller routing list, the master controller enters the feedback acquisition state, i.e., Acq_State state.

[0116] The feedback acquisition state, i.e., the Acq_State state, is responsible for starting the data transmission from the master controller to the slave controller corresponding to the target address when reading feedback data. In the Acq_State state processing logic of the master controller, the target address to be sent is set to the slave controller address of the routing item in the slave controller routing list, and then the start signal is sent, i.e., SCL and SDA are pulled high at the same time, and SDA is pulled low during this period. After completion, the target address sending state, i.e., the Slave_ADDR state, is entered.

[0117] Feedback sending state is P_State state: all module group power state feedback data is encapsulated into the message format used for external interaction and the power state feedback of all current core particles is sent out.

[0118] The slave controller is located inside the chip, and its logic functions mainly include a slave controller state machine, such as Figure 14-15 shown.

[0119] The slave controller state machine includes the following states: IDLE state, Read_DATA state, Write_DATA state, Check state, Calc state, CTRL state, Get_PState state, a total of 7 states.

[0120] Idle state IDLE state: that is, the initial state, that is, the initial state, responsible for detecting whether the target address, power state configuration data, matching target address, response and verification are received. In the IDLE state processing logic of the slave controller, it waits to receive the target address and read-write flag, receives the target address, and compares it with the local address. If the address matches, it sends a response signal (A signal, that is, SDA is pulled low), and the slave controller simultaneously switches to the read data state, that is, the Read_DATA state (when the read-write flag is 0) or switches to the write data state, that is, the Write_DATA state (when the read-write flag is 1); if the address does not match, it maintains the IDLE state. For example, when the target slave controller of the master controller is the slave controller of module 0, the slave controller receives the target address through the bus and compares it with the local address. Only the slave controller in module group 0 is completely matched. The slave controller in module group 0 sends a response signal (A) and simultaneously switches to the read data state, i.e., the Read_DATA state (when the read-write flag is 0) or switches to the write data state, i.e., the Write_DATA state (when the read-write flag is 1). If the other slave controllers do not match the address comparison, they remain in the IDLE state.

[0121] Read data state, i.e., Read_DATA state: is responsible for receiving the data field from the master controller. In the slave controller's Read_DATA state processing logic, after receiving the data field, i.e., the power state configuration data, the slave controller saves it into the register, sends a response signal (A), and switches the state to the verification state, i.e., the Check state.

[0122] Write data state, i.e. Write_DATA state: responsible for sending power state configuration data to the master controller. In the Write_DATA state processing logic of the slave controller, when SCL is pulled low, SDA is changed to the power state feedback data to be sent. After the SDA change is completed, SCL is pulled high to keep SDA unchanged, and then SCL is pulled low to complete the transmission of the highest bit data. According to this method, the power state feedback data is sent bit by bit in serial mode. If the slave controller receives a response signal (A), it switches to the calculation verification state, i.e. Calc state; if the slave controller does not receive a response signal (A) in the Write_DATA state, the power state feedback data is resent until a response signal (A) is received.

[0123] The check state is the Check state: responsible for checking whether the received check field value matches the check value calculated by the check algorithm. In the Check state processing logic of the slave controller, the slave controller receives the check field, and then calculates the received power state configuration data according to the same check algorithm, and then compares the calculated check value with the received check field value. If they completely match, it means that the data transmission is correct, and the slave controller sends a response signal (A); if they do not match, it means that the data transmission has an error, and the slave controller sends a non-response signal After the slave controller detects the stop signal (P), it enters the control state, namely the CTRL state.

[0124] Calculation state, i.e. Calc state: responsible for calculating the value of the check field according to the value of the data field, i.e. the power status feedback data sent. In the Calc state processing logic of the slave controller, a specific check algorithm (such as CRC, MD5, SHA, etc.) is used to calculate the check value, i.e. the check field value, for the power status feedback data of the data field, and send it bit by bit through the serial bus. If a response signal (A) is received from the slave controller, a stop signal (P) is sent and the slave controller switches to the idle state, i.e. the IDLE state. If a non-response signal is received from the slave controller, Then it returns to the data writing state, that is, the Write_DATA state, and resends the power status feedback data.

[0125] The control state is the CTRL state: responsible for setting the power state of each chip in the module group according to the power state configuration data. From the CTRL state processing logic of the slave controller, each bit of the received power state configuration data corresponds to a chip in the current module group, and the power state configuration data is parsed bit by bit into power state configuration information, and the power state configuration information is used as the power state information of the chip and bound to the corresponding chip address to form the chip routing list format of the current module group, and compared with the power state of each chip in the last generated chip routing list item by item. If there is a similarity, the routing item is invalidated, that is, the valid-invalid bit of the routing item is set to 0. In this embodiment, the valid-invalid bit is 1 to indicate that the routing item is valid, and the valid-invalid bit is 0 to indicate that the routing item is invalid. Then, according to the routing table, the power state configuration signal is sent to the chip of the corresponding address through the second communication bus item by item (valid item) to change the current power state (0: not working or low power consumption mode; 1: normal working mode), and after completion, it is switched from the controller state to the Get_PState state. In this embodiment, the current chip routing list format of module 0 from the controller is as follows Fig.16 As shown, each bit of the power state configuration data 1111b corresponds to a chip in the current module group.

[0126] Get feedback sending state, i.e. Get_PState state: responsible for obtaining the power state feedback information fed back by each chip, forming power state feedback data and writing it into the register. In the Get_PState state processing logic of the slave controller, the slave controller sends a power state request signal through the second communication bus according to the valid routing items in the current chip routing list to obtain the current power state of each chip, and combines the power state feedback information of the chip in the current module group into power state feedback data and writes it into the register in a bit-by-bit correspondence between each chip and the binary valid part of the power state feedback data, and returns to the IDLE state after completion.

[0127] In this embodiment, the chip can adjust its own power state according to the power state configuration information after receiving the power state configuration information, and can also upload its own power state after receiving an instruction from the controller, that is, a power state request signal from the controller.

[0128] Assuming that the power status configuration information of each chip in the 16 module groups is parsed as {1111b, 1110b, 1100b, 1000b, 1011b, 0011b, 0111b, 0001b, 1111b, 1111b, 1111b, 1111b, 0001b, 0010b, 0100b, 1000b}, the corresponding slave controller routing list is as follows: Fig.17 The working mode of this embodiment is as follows.

[0129] (1) Initialization: the power status data of each module group in the slave controller routing list in the master controller are all 0000b, and the valid and invalid bits are all 1; the power status information of each chip in the chip routing list in each slave controller is all 0, and the valid and invalid bits are all 1.

[0130] (2) The master controller enters the IDLE state and waits for the power state configuration message to be sent to the external interface. After receiving the power state configuration message, it starts to parse the power state configuration message, binds the power state configuration data with the unique address of the slave controller corresponding to the module group to generate a slave controller routing list, and compares the power state data of each module group in the slave controller routing list generated last time. If there is a similarity, the routing item is invalidated, that is, the valid-invalid bit of the routing item is set to 0. The target address to be sent is set to the slave controller address 0x00 of the first valid routing item, and the data field is set to the power state data of the module group of the first valid routing item after parsing, that is, in this embodiment, the power state configuration data 1111b corresponding to the first module group. After completion, it enters the ready state.

[0131] (3) After the master controller enters the Ready state, it sends a start signal, that is, sets SCL and SDA to high levels at the same time, and sets SDA to low level during this period. After completion, it enters the state of sending the target address, that is, the Slave_ADDR state. At this time, the slave controller remains in the IDLE state.

[0132] (4) After the master controller enters the Slave_ADDR state, it controls SCL to be pulled low to change SDA to the highest bit 0b of the target address value to be sent, and pulls SCL high to keep SDA unchanged after the SDA change is completed, and then pulls SCL low to complete the sending of the highest bit address. According to this method, the target address 0x00 is sent bit by bit in serial mode. After the target address is sent, a write signal (0) is sent. At this time, each slave controller receives the target address through the bus and compares it with the local address. Only the slave controller in module group 0 is completely matched. The slave controller in module group 0 sends a response signal (A) and switches to the read data state, that is, Read_DATA state at the same time. If the other slave controllers do not match the address, they will ignore it and keep the IDLE state.

[0133] (5) When the master controller receives the response signal (A), the state switches to the write data state, i.e., the Write_DATA state, and similarly sends the power state configuration data 1111b of the corresponding module group in a bit-serial manner. If the master controller does not receive the response signal (A) in the Slave_ADDR state, the target address is resent. When the master controller receives the response signal (A), the state switches to the calculation verification state, i.e., the Calc state. After the slave controller receives the power state configuration data 1111b in the Read_DATA state, it saves it in the register, sends the response signal (A) at the same time, and switches the state to the verification state, i.e., the Check state.

[0134] (6) The master controller uses the CRC-4 / ITU checksum algorithm in the Calc state to calculate the checksum field value of the power state configuration data 1111b to be 0110b, and sends it bit by bit through the serial bus. At this time, the slave controller is in the Check state, receives the checksum field from the slave controller, and then calculates the received power state configuration data according to the same checksum algorithm, and then compares the calculated checksum value with the received checksum field value. If they completely match, it means that the data transmission is correct, and the slave controller sends a response signal (A); if they do not match, it means that the data transmission has an error, and the slave controller sends a non-response signal At this time, after receiving the check code 0110b, the slave controller calculates the check code 0110b for the received power state configuration data 1111b according to the same algorithm. If they match completely, it means that the data transmission is correct and a response signal (A) is sent at the same time. Then resend the power status data. When the master controller receives the response signal (A), it sends a stop signal (P). At this time, the master controller sets the target address to be sent to the slave controller address of the next valid routing item in the slave controller routing list, that is, 01, and the power status data is set to the power status data of the module group of the next valid routing item in the slave controller routing list, that is, 1110b. After completion, it enters the Ready state.

[0135] (7) After the slave controller of module 0 detects the stop signal (P), it enters the control state, i.e., the CTRL state, and parses the power state configuration data bit by bit into the power state configuration information. The power state configuration information is used as the power state information of the core particle and is bound to the corresponding core particle address to form the core particle routing list format of the current module group. The power state of each core particle in the core particle routing list generated last time is compared item by item. If there is a similarity, the routing item is invalidated, i.e., the valid-invalid bit of the routing item is set to 0. Then, according to the routing table, the power state configuration signal is sent to the core particle of the corresponding address through the second communication bus item by item (valid item) to change the current power state, so that core particles 1-4 are all set to the normal working mode. After completion, the controller state is switched to the Get_PState state.

[0136] (8) In the Get_PState state, the slave controller sends a power state request signal through the second communication bus to obtain the current power state of each chip according to the valid routing items in the current chip routing list, and combines the power state feedback information of the chip in the current module group into power state feedback data 1111b in a bit-by-bit manner according to the binary valid part of each chip corresponding to the power state feedback data (i.e., the lowest bit data corresponds to chip 0, and the highest bit data corresponds to chip 3) and writes it into the register. After completion, the slave controller returns to the IDLE state.

[0137] (9) The main controller repeats steps 3 to 8 until all module groups have completed data transmission and enters the Acq_State state.

[0138] (10) In the feedback sending state, i.e., Acq_State state, the master controller sets the target address to be sent to the address 0x00 of the slave controller of the first module group in the first slave controller routing list, and then sends a start signal, i.e., pulls up SCL and SDA at the same time, pulls down SDA during this period, and enters the sending target address state, i.e., Slave_ADDR state after completion; at this time, the slave controller remains in IDLE state.

[0139] (11) In the Slave_ADDR state, the master controller changes SDA to the highest bit of the target address value to be sent when SCL is pulled low, and pulls SCL high to keep SDA unchanged after the SDA change is completed, and then pulls SCL low to complete the sending of the highest bit address. According to this method, the target address 0x00 is sent bit by bit in serial mode, and after the target address is sent, a read signal (1) is sent; at this time, each slave controller receives the target address through the bus and compares it with the local address. Only the slave controller in module group 0 is completely matched. The slave controller in module group 0 sends a response signal (A) and switches to the read data state, that is, Write_DATA state at the same time. If the other slave controllers do not match the address, they ignore it and remain in IDLE state.

[0140] (12) When the master controller receives the response signal (A), the state switches to the data reading state, that is, the Read_DATA state, to prepare to read data, and at the same time controls SCL to switch between high and low levels. After the slave controller at address 0x00 enters the Write_DATA state, it reads the value 1111b of the power status feedback data stored in the register, and modifies SDA bit by bit to write serially to the bus when SCL is low. When the master controller receives the data, it sends a response signal (A) and switches to the Check state at the same time. The slave controller detects whether the response signal (A) is received. If the response signal (A) is not received, the data is resent; if the slave controller receives the response signal (A), the slave controller will switch to the Calc state;

[0141] (13) In the Calc state, the slave controller uses the CRC-4 / ITU check algorithm to calculate the check field value of the power configuration data 1111b to be 0110b, and sends it bit by bit through the serial bus. At this time, the slave controller is in the Check state, receives the check field from the slave controller, and then calculates the received power status configuration data according to the same check algorithm, and compares the calculated check value with the received check field value. If they match completely, it means that the data transmission is correct, and the slave controller sends a response signal (A); if they do not match, it means that the data transmission has an error, and the slave controller sends a non-response signal If the host controller receives a no-response signal Then the power status data is resent. When the master controller receives the response signal (A), it sends a stop signal (P), switches the state to Acq_State state, and sets the target address to be sent to the address 0x01 of the slave controller of the next module group. After the slave controller detects the stop signal, it switches the state to IDLE state.

[0142] (14) Repeat steps 10 to 13 until the power status of all module groups is updated. The main controller switches the state to P_State, encapsulates the power status feedback data of all module groups into the message format used for external interaction, and sends out the power status feedback of all current core particles. After completion, the main controller switches the state to IDLE state.

[0143] After completing the above 14 steps, the power status of all the chips in the chip system can be controlled. Fig.18 As shown, the current status of all chip power supplies after the preset configuration can be obtained.

[0144] In summary, the on-chip system and its power state configuration, feedback, and control method of the present invention can accurately and efficiently control the startup process of each chip in the on-chip system, avoiding the large current damage to the circuit structure caused by the large number of chips powered on at the same time, and providing better performance with less power consumption by accurately controlling the startup of the corresponding chip according to the startup configuration. At the same time, an improved version of the serial bus protocol is adopted and managed in the form of module groups. Only serial bus communication is used between the main controller and the module group, and high-speed parallel bus communication between chips is used within the module group. Compared with the traditional bus, the efficiency of data communication is accelerated, and the efficiency and reliability of power configuration are improved, so that the system can be quickly switched to the specified working mode while ensuring the safety of the on-chip system.

[0145] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the invention may be modified or replaced by equivalents without departing from the scope of the technical solutions of the present invention, which should all be covered by the scope of the claims of the present invention.

Claims

1. A wafer-based system, characterized in that: It includes multiple module groups and power control components, among which: A module group includes multiple cores with the same function; A power control component includes a main controller and a plurality of slave controllers arranged in one-to-one correspondence with a module group, wherein the main controller is connected to the plurality of slave controllers through a first communication bus, and each slave controller is connected to each chip in the corresponding module group; the slave controller can be arranged in one of the chips in the corresponding module group, and the chip in which the slave controller is arranged is connected to the other chips in the module group through a second communication bus to realize the communication connection between the slave controller and each chip in the module group; wherein, The main controller is used to obtain the power state configuration data of each module group through an external interface connected to the main controller, and send the power state configuration data to the corresponding slave controller, or to receive the power state feedback data uploaded by the slave controller of each module group and send it through the external interface; A slave controller is used to receive the power state configuration data, obtain the power state configuration information of each chip in the corresponding module group from the power state configuration data, and send the power state configuration information to the corresponding chip, or to receive the power state feedback information uploaded by the chip and generate power state feedback data to send, and upload the power state feedback data to the master controller; The core particle is used to receive the power state configuration information and set the power state according to the power state configuration information, or to upload power state feedback information to the slave controller according to the instruction of the slave controller.

2. The on-wafer system according to claim 1, characterized in that: The controller compares the power status configuration information of each chip in the corresponding module group with the power status feedback information of each chip one by one, or compares the power status configuration information of each chip in the corresponding module group with the power status configuration information obtained last time one by one, obtains the chip that needs to adjust the power status, and sends the corresponding power status configuration information to the chip that needs to adjust the power status.

3. The on-wafer system according to claim 1, characterized in that: The main controller compares the power status configuration data of each module group with the power status configuration data obtained last time, or compares the power status configuration data of each module group with the power status feedback data of each module group one by one to obtain the module group whose power status needs to be adjusted; the main controller sends the corresponding power status configuration data to the slave controller corresponding to the module group whose power status needs to be adjusted.

4. The on-wafer system according to claim 1, characterized in that: The first communication bus protocol includes a start bit, a target address, a read / write flag, a response bit, a data field, a check field and a stop bit, and is responsible for data communication between the master controller and each slave controller; the target address includes the slave controller address, and the data field includes power status configuration data or power status feedback data; each slave controller has a unique slave controller address.

5. A power state configuration method in a wafer system, used to configure the power state of a chip in the wafer system according to claims 1-4, characterized in that: The following steps are involved: The main controller receives a power state configuration message from an external interface; The main controller parses the power state configuration message to obtain the power state configuration data; The master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data; The slave controller obtains the power state configuration information of the chip in the corresponding module group from the power state configuration data; Sending power state configuration information from the controller to the corresponding chip; The chip receives power state configuration information sent from the controller and sets the power state according to the power state configuration information.

6. The power state configuration method according to claim 5, characterized in that: The master controller sends the power state configuration data to the corresponding slave controller, and the slave controller receives the power state configuration data; specifically including: The master controller sends a start bit and sends a target address to the slave controller via the first communication bus in a serial manner; The slave controller receives the target address via the first communication bus, compares it with the local address and sends a response bit; After receiving the correct response bit, the main controller prepares to write data, and the main controller writes the power state configuration data bit by bit serially into the first communication bus; The slave controller receives power status feedback data and sends a response bit. If the master controller does not receive the correct response bit, it resends the data. If the master controller receives the correct response bit, the master controller calculates the check value and sends the check value as the check field. The slave controller calculates the check value and compares it with the received check field and sends the response bit. If the master controller receives an incorrect response bit, it resends the data. If the master controller receives the correct response bit, the master controller sends a stop signal and switches the target address to be sent to the slave controller address corresponding to the next module group. The above steps are repeated until all slave controllers in the set order receive the power state configuration data.

7. The power state configuration method according to claim 5, characterized in that: The slave controller obtains the power status configuration information of the corresponding core particles in the module group from the power status configuration data, specifically including: the binary valid part of the power status configuration data corresponds bit by bit to the power status configuration information of each core particle in the module group, and the slave controller parses the power status configuration data bit by bit to extract the power status configuration information.

8. A power status feedback method in a wafer system, used to feedback the power status of a chip in the wafer system according to claims 1-4, characterized in that: The following steps are involved: The chip uploads power status feedback information to the slave controller according to the instruction of the slave controller; Receive power status feedback information uploaded by the chip from the controller; The slave controller generates power state feedback data according to the power state feedback information and stores it in a register; The slave controller uploads the power status feedback data to the master controller, and the master controller receives the power status feedback data uploaded by the slave controllers of each module group; The main controller packages the power state feedback data to generate a power state feedback message, and sends the power state feedback message through an external interface according to an external instruction.

9. The power supply status feedback method according to claim 8, characterized in that: The slave controller receives the power status feedback information uploaded by the chiplets; the slave controller generates power status feedback data according to the power status feedback information and stores it in the register; specifically, the slave controller combines the power status feedback information of the chiplets in the current module group into power status feedback data in a bit-by-bit manner so that each chiplet corresponds to the binary valid part of the power status feedback data, and writes the power status feedback data into the register of the slave controller.

10. The power supply status feedback method according to claim 8, characterized in that: The slave controller uploads the power status feedback data to the master controller, and the master controller receives the power status feedback data uploaded by the slave controllers of each module group, specifically including: The master controller sends a start bit and sends a target address to the slave controller via the first communication bus in a serial manner; The slave controller receives the target address via the first communication bus, compares it with the local address and sends a response bit; After receiving the correct response bit, the master controller prepares to read the data, reads the power status feedback data in the register from the slave controller, and writes the power status feedback data serially to the first communication bus. The master controller receives the power status feedback data and sends the response bit. If the slave controller does not receive the correct response bit, the data is resent. If the slave controller receives the correct response bit, the slave controller calculates the check value and sends the check value as the check field. The master controller calculates the check value and compares it with the received check field and sends the response bit. The master controller sends a stop signal and switches to the address of the slave controller in the next module group; Repeat the above steps until all slave controllers corresponding to all module groups have sent the power status feedback data in the set order.

11. A power state control method in a wafer system, used to control the power state of a chip in the wafer system according to claims 1-4, comprising the power state configuration method and feedback method in the wafer system, characterized in that: The following steps are also included: The main controller receives the power state configuration message, parses the power state configuration message to obtain the power state configuration data of each module group, compares the power state configuration data with the power state configuration data of each module group obtained last time, and obtains the power state configuration data of the module group whose power state needs to be changed in the module group; The master controller sends the power state configuration data of the module group whose power state needs to be changed to the corresponding slave controller, and the slave controller receives the power state configuration data; The slave controller obtains power state configuration information of the chip in the corresponding module group from the power state configuration data; and the slave controller sends the power state configuration information to the corresponding chip; The chip receives power state configuration information sent from the controller and sets the power state according to the power state configuration information.

12. The power state control method according to claim 11, characterized in that: After receiving power state configuration data from the controller and parsing the power state configuration data to obtain power state configuration information of each chip, the power state configuration information is compared with the power state configuration information of each chip obtained last time to obtain the power state configuration information of the chip in the module group whose power state needs to be changed.

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