Linear voltage regulator circuit and power supply device

Abstract

This application relates to the field of linear voltage regulator circuit technology, and discloses a linear voltage regulator circuit applied to a multi-power-domain system, where the multi-power-domain system includes N power supplies, where N is an integer greater than 1. The linear voltage regulator circuit includes: N parallel power transistor branches, each power transistor branch including a transmission gate and a power transistor connected in series, and the source of each power transistor being connected to a power supply; a control circuit including N control signal output terminals, each control signal output terminal being connected to the control terminal of a transmission gate; the N control signal output terminals output control signals for selecting power transistors; wherein, the transmission gates of the N power transistor branches receive the control signals output by the control circuit and turn on the selected power transistors according to the control signals. The linear voltage regulator circuit provided in this disclosure can prevent the current generated in the power transistor from flowing through the control circuit, thereby reducing the voltage difference between the input and output terminals of the control circuit. This application also discloses a power supply device.

Description

Technical Field

[0001] This application relates to the field of linear regulator circuit technology, and for example to a linear regulator circuit and power supply device. Background Technology

[0002] In power supply systems, linear regulators are typically required to provide a stable voltage source for circuits such as digital circuits and flash memory circuits. Linear regulators (low dropout regulators, LDOs) offer advantages such as low cost, small size, low output noise, and simple structure, making them an important type of circuit in power management chips. The essence of an LDO is to obtain a stable output voltage through a bias current generated by a bandgap reference, a reference voltage, and a negative feedback control loop. This output voltage remains largely unchanged regardless of variations in process technology, temperature, and power supply voltage. In power management chip applications, there are usually two or more power domains, such as a battery domain, a contact power domain, and a non-contact power domain. Therefore, a power selection circuit is needed to select the power supply according to the rules of the power management system, serving as the error amplifier power supply voltage and the source voltage of the power transistor in the LDO.

[0003] In traditional power selection circuits, multiple power domains pass through the power selection circuit and then become the power supply voltage for the power transistor circuit of the linear regulator.

[0004] In the process of implementing the embodiments of this disclosure, at least the following problems were found in the related art:

[0005] In power management chips, LDOs are typically used to power digital circuits. As the scale of digital circuits gradually increases, power consumption increases, and the current flowing through the power transistor of the LDO also gradually increases. This leads to a gradual increase in the current flowing through the switching transistor of the power selection circuit, resulting in a larger voltage difference across the switching transistor.

[0006] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This disclosure provides a linear regulator circuit and a power supply device to reduce the voltage difference between the input and output terminals of a switching transistor in a power selection circuit.

[0009] In some embodiments, the linear regulator circuit is applied to a multi-power-source domain, the multi-power-source domain including N power sources, where N is an integer greater than 1; characterized in that the linear regulator circuit includes: N parallel power transistor branches, each power transistor branch including a transmission gate and a power transistor connected in series, the source of each power transistor being connected to a power source; a control circuit including N control signal output terminals, each control signal output terminal being connected to the control terminal of a transmission gate; the N control signal output terminals output control signals for selecting power transistors; wherein, the transmission gates of the N power transistor branches receive the control signals output by the control circuit and turn on the selected power transistors according to the control signals.

[0010] Optionally, the linear regulator circuit further includes an error amplifier and a negative feedback circuit; the inputs of all transmission gates are connected in parallel to the output of the error amplifier; the output of each transmission gate is connected to the gate of a power transistor; and the drains of all power transistors are connected in parallel to the input of the negative feedback circuit.

[0011] Optionally, each transmission gate includes a PMOS transistor, an NMOS transistor, and an inverter; the gate of the PMOS transistor is connected in parallel with the input of the inverter, serving as the control terminal of the transmission gate; the drain of the PMOS transistor is connected in parallel with the drain of the NMOS transistor, serving as the input terminal of the transmission gate; the source of the PMOS transistor is connected in parallel with the source of the NMOS transistor, serving as the output terminal of the transmission gate; and the gate of the NMOS transistor is connected to the output terminal of the inverter.

[0012] Optionally, the control circuit further includes N power input terminals and one voltage output terminal; each power input terminal is connected to a power supply; the voltage output terminal is connected to the power supply terminal of the error amplifier to provide power to the error amplifier; wherein, the voltage output by the voltage output terminal is the power supply voltage connected to one of the N power input terminals.

[0013] Optionally, the control circuit includes N parallel control branches, each control branch including a branch signal input terminal, a branch power input terminal, and a branch voltage output terminal; each branch signal input terminal is connected to a control signal output terminal of the control circuit; each branch power input terminal serves as a power input terminal; and all branch voltage output terminals are connected in parallel as a voltage output terminal.

[0014] Optionally, each control branch includes: a switching transistor, the drain of which serves as the branch power input terminal; the gate of which serves as the branch signal input terminal; and the source of which serves as the branch voltage output terminal.

[0015] Optionally, the branch signal input terminal of the i-th control branch in the control circuit and the control terminal of the transmission gate in the i-th power transistor branch are connected in parallel to the i-th control signal output terminal of the control circuit; and the branch power supply input terminal of the i-th control branch in the control circuit, the source of the power transistor in the i-th power transistor branch, and the i-th power supply input terminal in the control circuit are connected to the same power supply; where i = 1, ..., N.

[0016] Optionally, the negative input terminal of the error amplifier is connected to the reference voltage; the positive input terminal of the error amplifier is connected to the output terminal of the negative feedback circuit.

[0017] Optionally, the negative feedback circuit includes: a first voltage divider element, the input terminal of which serves as the input terminal of the negative feedback circuit; the output terminal of which serves as the output terminal of the negative feedback circuit; a second voltage divider element, the input terminal of which is connected to the output terminal of the first voltage divider element; and the output terminal of the second voltage divider element is grounded.

[0018] In some embodiments, the power supply device includes N power supplies, where N is an integer greater than 1; the power supply device also includes a linear regulator circuit as described above.

[0019] The linear regulator circuit and linear regulator provided in this disclosure can achieve the following technical effects:

[0020] In this embodiment, the power selection circuit is improved into a control circuit, and the source of each power transistor is connected to a separate power supply. The control signal of the control circuit selectively turns on the power transistors, preventing current from flowing through the control circuit and thus reducing the current in the control circuit. This, in turn, reduces the voltage drop across the switching transistor in the control circuit, thereby lowering the voltage difference between the input and output terminals of the switching transistor. Furthermore, compared to conventional circuits, the linear regulator circuit provided in this embodiment reduces the area occupied by the LDO's power transistors and the area required for the power selection circuit's switching transistors to reduce voltage drop, thus lowering production costs and improving circuit performance.

[0021] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0023] Figure 1 This is a circuit diagram of a traditional linear regulator circuit used in multiple power domains;

[0024] Figure 2 This is a circuit diagram of a linear regulator circuit for multiple power domains provided in an embodiment of this disclosure;

[0025] Figure 3 This is a circuit diagram of a transmission gate in a linear regulator circuit for multiple power domains provided in an embodiment of this disclosure;

[0026] Figure 4 This is a circuit diagram of a control circuit in a linear regulator circuit for multiple power domains provided in an embodiment of this disclosure;

[0027] Figure 5 This is a circuit diagram of another control circuit in a linear regulator circuit for multiple power domains provided in an embodiment of this disclosure;

[0028] Figure 6 This is a circuit diagram of an error amplifier in a linear regulator circuit for multiple power domains provided in an embodiment of the present disclosure. Detailed Implementation

[0029] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0030] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0031] Unless otherwise stated, the term "multiple" means two or more.

[0032] The term "correspondence" can refer to an association or binding relationship. The correspondence between A and B means that there is an association or binding relationship between A and B.

[0033] Combination Figure 1As shown, taking a multi-power-domain LDO circuit with two power supplies, VCC10 and VCC20, as an example, the circuit includes a bandgap reference source VREF0, an error amplifier EA0, a power transistor PM0, a first resistor R1, a second resistor R2, and a power selection circuit PWR_SW. The power supply voltage of the error amplifier EA0 is the same as the source voltage of the power transistor PM0, which is the voltage VCC0 output by the power selection circuit PWR_SW. In the application scenarios of power management chips, there are usually two or more power domains, such as battery domain, contact power domain, and unconnected power domain. Therefore, the power selection circuit PWR_SW needs to select the power supply according to the rules of the power management system to serve as the power supply voltage of the LDO's error amplifier EA0 and the source voltage of the power transistor PM0.

[0034] In the power selection circuit PWR_SW, the current flowing through the switching transistor is the sum of the current flowing through the LDO's power transistor PM0 and the current flowing through the error amplifier EA0. This results in a large current flowing through the switching transistor in the power selection circuit PWR_SW, leading to a large voltage difference across the switching transistor. Consequently, the voltage difference between the input and output terminals of the power selection circuit PWR_SW increases. This structure requires both the power selection circuit PWR_SW and the LDO's power transistor PM0 circuit to have large areas, which is highly disadvantageous in low-voltage power management systems.

[0035] Combination Figure 2 As shown, this embodiment of the present disclosure provides a linear regulator circuit applied to multiple power supply domains, the multiple power supply domains including N power supplies (VCC1, ..., VCCN), where N is an integer greater than 1; the linear regulator circuit includes N parallel power transistor branches (TP1, ..., TPN) and a control circuit K.

[0036] Each power transistor branch includes a transmission gate and a power transistor connected in series. For example, the i-th power transistor branch TPi includes a transmission gate TGi and a power transistor PMi, i = 1, ..., N. The source of each power transistor is connected to a power supply. The control circuit K includes N control signal output terminals; each control signal output terminal is connected to the control terminal of a transmission gate; the N control signal output terminals output control signals (VG_VCC1, ..., VG_VCCN) for selecting the power transistor. The transmission gates of the N power transistor branches receive the control signals output by the control circuit and turn on the selected power transistor according to the control signals.

[0037] In the linear regulator circuit provided in this embodiment, the power selection circuit is improved into a control circuit K, and the source of each power transistor is connected to a power supply. The control signal of the control circuit K selectively turns on the power transistors, preventing current from flowing through the control circuit K and thus reducing the current in the control circuit K. This, in turn, reduces the voltage drop generated when the power supply voltage passes through the switching transistor in the control circuit K, thereby reducing the voltage difference between the input and output terminals of the switching transistor. Furthermore, compared with conventional circuits, the linear regulator circuit provided in this embodiment reduces the area occupied by the LDO's power transistors and the area increased by the switching transistors in the power selection circuit to reduce voltage drop, thus reducing production costs and improving circuit performance.

[0038] Optionally, the linear regulator further includes an error amplifier EA and a negative feedback circuit F; the inputs of all transmission gates are connected in parallel to the output of the error amplifier EA; the output of each transmission gate is connected to the gate of a power transistor; and the drains of all power transistors are connected in parallel to the input of the negative feedback circuit F.

[0039] The inputs of all transmission gates are connected in parallel to the output of error amplifier EA to receive the output voltage VO_EA of error amplifier EA, applying the same voltage to the inputs of all transmission gates. The output of each transmission gate is connected to the gate of a power transistor. When a transmission gate is turned on, the output voltage of the error amplifier is applied to the gate of the power transistor. The source of the power transistor is connected to a power supply. When a voltage is applied to its gate, the power transistor is turned on, outputting a voltage at its drain. The drains of all power transistors are connected in parallel to the input of negative feedback circuit K. When one power transistor is turned on, a voltage VFB will be output from the input of negative feedback circuit K.

[0040] Optionally, combined Figure 3 As shown, each transmission gate includes a first PMOS transistor P11, a first NMOS transistor N11, and an inverter INV1; the gate of PMOS transistor P11 is connected in parallel with the input terminal of inverter INV1, serving as the control terminal of the transmission gate; the drain of PMOS transistor P11 is connected in parallel with the drain of NMOS transistor N11, serving as the input terminal VIN of the transmission gate; the source of PMOS transistor P11 is connected in parallel with the source of NMOS transistor N11, serving as the output terminal VOUT of the transmission gate; the gate of NMOS transistor N11 is connected to the output terminal of inverter INV1.

[0041] By utilizing the complementarity of PMOS and NMOS transistors, a CMOS transmission gate can be constructed. When the transmission gate needs to be turned on, a low-level input is provided to the gate of PMOS transistor P11, a high-level input to the gate of NMOS transistor N11, and a voltage is applied to the input of the transmission gate. In this case, at least one of PMOS transistors P11 and NMOS transistor N11 will be turned on, and the transmission gate acts as a closed switch, transmitting the voltage at the input terminal VIN to the output terminal VOUT. Conversely, when the transmission gate needs to be turned off, a high-level input is provided to the gate of PMOS transistor P11, and a low-level input to the gate of NMOS transistor N11. In this case, both PMOS transistors P11 and NMOS transistor N11 will be turned off, and the transmission gate will also be turned off. An inverter INV1 is connected in series between the gates of PMOS transistor P11 and NMOS transistor N11. The gate of PMOS transistor P11 is connected in parallel with the input of inverter INV1, serving as the control terminal of the transmission gate. Then, if the control signal VG_VCCA input to the control terminal is low, and VG_VCCB obtained after passing through inverter INV1 is high, then in the transmission gate, the gate of PMOS transistor P11 will have a low input and the gate of NMOS transistor N11 will have a high input, thus turning on the transmission gate.

[0042] Optionally, the control circuit K further includes N power input terminals and a voltage output terminal; each power input terminal is connected to a power supply; the voltage output terminal is connected to the power supply terminal of the error amplifier EA to provide power to the error amplifier EA; wherein, the voltage output by the voltage output terminal is the power supply voltage connected to one of the N power input terminals.

[0043] The control circuit K can also select a power supply voltage from the voltages input from the N power supply input terminals according to the rules of the preset power management system, and use the output voltage VDD as the power supply voltage of the error amplifier EA.

[0044] Optionally, combined Figure 4 As shown, the control circuit K includes: a digital control module LC, which includes N power supply terminals and N signal output terminals; each power supply terminal of the digital control module LC is connected to a power supply; each signal output terminal of the digital control module LC serves as a control signal output terminal of the control circuit K.

[0045] In the digital control module LC, after selecting a power supply voltage according to the rules of the preset power management system, the control terminal of the transmission gate is acted upon by the corresponding control signal output by the selected power supply, thereby turning on the power transistor in a power transistor branch and realizing the normal function of the linear regulator.

[0046] Optionally, combined Figure 5As shown, the control circuit K also includes: N parallel control branches (KP1, ..., KPN), each control branch including a branch signal input terminal, a branch power input terminal and a branch voltage output terminal; each branch signal input terminal is connected to a control signal output terminal of the control circuit K; each branch power input terminal serves as a power input terminal; all branch voltage output terminals are connected in parallel as a voltage output terminal.

[0047] Each branch power input is connected to one of the power sources in the multi-power domain. The branch signal input selects one control branch to be turned on and the other control branches to be turned off according to the received control signal. At this time, the branch voltage output of the selected control branch will have a voltage output, which will act on the power supply terminal of the error amplifier EA to provide power to the error amplifier EA.

[0048] Optionally, each control branch includes a switching transistor. For example, the i-th control branch KPi includes a switching transistor Pi. The drain of the switching transistor serves as the branch power supply input; the gate of the switching transistor serves as the branch signal input; and the source of the switching transistor serves as the branch voltage output.

[0049] A switching transistor, which can be a PMOS transistor, is set in the control branch. The gate of the switching transistor is used to receive the control signal output by the LC of the digital control module. When the control branch needs to be turned on, the gate of the switching transistor will receive a low-level signal, at which time the switching transistor will be turned on, and there will be a voltage output at the voltage output terminal of the control branch.

[0050] Optionally, the branch signal input terminal of the i-th control branch in the control circuit K and the control terminal of the transmission gate TGi in the i-th power transistor branch are connected in parallel to the i-th control signal output terminal of the control circuit K; and the branch power supply input terminal of the i-th control branch in the control circuit K, the source of the power transistor PMi in the i-th power transistor branch, and the i-th power supply input terminal in the control circuit are connected to the same power supply VCCi.

[0051] In this embodiment, to ensure that the voltage output by the control circuit K is the same as the voltage at the source of the power transistor, it is necessary to establish a one-to-one correspondence between the control circuit K and all the output and input terminals of the N power transistor branches. The following explanation assumes that the i-th power supply VCCi in the multi-power-supply domain is selected.

[0052] When the i-th power supply VCCi in the multi-power-supply domain is selected, the i-th signal output terminal in the digital control module LC will output a low-level signal VG_VCCi = 0, while the other signal output terminals will output high-level signals. At this time, the switching transistor Pi of the i-th control branch KPi in the control circuit K is turned on, and the other control branches are turned off, generating a voltage VDD = VCCi at the power supply terminal of the error amplifier EA. After passing through the error amplifier EA, a voltage VO_EA is output at the output terminal of the error amplifier EA, which acts on the N parallel power transistor branches. In the N power transistor branches, the control terminal of the transmission gate TGi on the i-th power transistor branch TPi receives the low-level signal VG_VCCi, while the control terminals of the transmission gates on the other power transistor branches receive high-level signals. At this time, the i-th power transistor branch TPi will be turned on, and a voltage will be generated at the gate of the power transistor PMi on the i-th power transistor branch TPi. The source of the i-th power transistor PMi is connected to the i-th power supply VCCi, making the i-th power transistor PMi turn on. The other power transistors are turned off because no voltage is applied to their gates. A voltage VO will be generated at the output of the N parallel power transistor branches.

[0053] Optionally, the negative input terminal of the error amplifier EA is connected to the reference voltage VREF; the positive input terminal of the error amplifier EA is connected to the output terminal of the negative feedback circuit F.

[0054] The outputs of the N parallel power transistor branches generate a voltage VO. This feedback voltage VFB is applied to the positive input of the error amplifier EA through a negative feedback circuit F, forming a negative feedback control loop. The existence of this negative feedback control loop ensures that the output voltage VO remains a stable value.

[0055] Optionally, combined Figure 6As shown, the error amplifier EA includes a second NMOS transistor N10, a third NMOS transistor N20, a fourth NMOS transistor N30, a fifth NMOS transistor N40, a second PMOS transistor P10, a third PMOS transistor P20, and a current source I1. The source of the second PMOS transistor P10 is connected to the power supply voltage VDD, and its drain is connected to its gate. The source of the third PMOS transistor P20 is connected to the power supply voltage VDD, its gate is connected to the gate of the second PMOS transistor P10, and its drain is connected to the drain of the third NMOS transistor N20, outputting a voltage VO_EA. The gate of the second NMOS transistor N10 is connected to the feedback voltage VFB, its source is connected to the drain of the fourth NMOS transistor N30, and its drain is connected to the drain of the second PMOS transistor P10. The gate of the third NMOS transistor N20 is connected to the reference voltage VREF, and the source of the third NMOS transistor N20 is connected to the source of the second NMOS transistor N10. The gate of the fourth NMOS transistor N30 is connected to the gate of the fifth NMOS transistor N40, the drain of the fourth NMOS transistor N30 is connected to the source of the third NMOS transistor N20, and the source of the fourth NMOS transistor N30 is connected to ground. The gate of the fifth NMOS transistor N40 is connected to the drain of the fifth NMOS transistor N40, and the source of the fifth NMOS transistor N40 is connected to ground. The input of the current source I1 is connected to the power supply voltage VDD, and the output of the current source I1 is connected to the drain of the fifth NMOS transistor N40.

[0056] When the feedback voltage VFB is greater than the reference voltage VREF, the gate-source voltage of the second NMOS transistor N10 increases, increasing its driving capability; the gate voltage of the second PMOS transistor P10 decreases; the gate voltage of the third PMOS transistor P20 decreases, increasing its driving capability; and the VO_EA voltage increases. With the i-th power transistor branch TPi conducting, the gate voltage of power transistor PMi increases, while the source voltage VCC remains constant. Therefore, the gate-source voltage decreases, the current flowing through power transistor PMi decreases, and the current flowing through the negative feedback circuit F decreases, causing the feedback voltage VFB to decrease. This decrease acts on the positive input terminal of the error amplifier EA, forming a negative feedback control loop.

[0057] The error amplifier circuit EA outputs voltage VO_EA when the gate voltage of the second NMOS transistor N10 is inconsistent with the gate voltage of the third NMOS transistor N20. This output voltage controls the current flowing through the negative feedback circuit, thus aligning the gate voltages of the second NMOS transistor N10 and the third NMOS transistor N20. The value of VO_EA corresponds to the difference between the gate voltages of the second NMOS transistor N10 and the third NMOS transistor N20.

[0058] Optionally, the negative feedback circuit F includes: a first voltage divider element R3, the input terminal of which serves as the input terminal of the negative feedback circuit F; the output terminal of which serves as the output terminal of the negative feedback circuit F; a second voltage divider element R4, the input terminal of which is connected to the output terminal of the first voltage divider element R3; and the output terminal of the second voltage divider element R4 is grounded.

[0059] The first voltage divider element R3 and the second voltage divider element R4 can each be set as two resistors. When the current flowing through the negative feedback circuit F in the linear regulator decreases, the resistance value remains unchanged, thereby reducing the feedback voltage VFB to form a negative feedback loop.

[0060] The linear regulator circuit provided in this disclosure, compared to traditional linear regulator circuits, features N parallel power transistor branches. N transmission gates are positioned at the gates of the N power transistors, and the control signals for these gates are provided by the digital control module LC of the control circuit K through a logic control circuit. The sources of the N power transistors are connected to N power supplies, thus reducing the voltage drop caused by the switching transistors of the control circuit K through the N power supply voltages at the sources of the N power transistors. This improves the load-carrying capacity of the power transistors and indirectly reduces the required power transistor area. Furthermore, only one of the N power transistor branches is selected, reducing the possibility of instability issues in the negative feedback control loop caused by sudden increases or decreases in power transistor size. In addition, the linear regulator circuit provided in this disclosure saves the area of ​​the power transistor circuit in a traditional LDO and the area required for the switching transistors in the power selection circuit to reduce voltage drop, thereby reducing production costs and improving circuit performance.

[0061] This disclosure also provides a power supply device including N power domains, where N is an integer greater than 1; the power supply device further includes a linear regulator circuit as described above.

[0062] The power supply device provided in this disclosure can provide a stable voltage source in a multi-power-domain system through a linear regulator circuit. This voltage source remains largely unchanged regardless of variations in process technology, temperature, and power supply voltage. Furthermore, compared to traditional power supply devices, the power supply device provided in this disclosure has a smaller circuit footprint, lower production costs, and better circuit performance.

[0063] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A linear voltage regulator circuit, applied in a multi-power-source domain, wherein the multi-power-source domain includes N power sources, where N is an integer greater than 1; characterized in that, The linear regulator circuit includes: N parallel power transistor branches, each power transistor branch includes a transmission gate and a power transistor connected in series, and the source of each power transistor is connected to a power supply. The control circuit includes N control signal output terminals, each of which is connected to the control terminal of a transmission gate; the N control signal output terminals output control signals for selecting the power transistor. Among them, the transmission gates of N power transistor branches receive the control signals output by the control circuit and turn on the selected power transistors according to the control signals; The linear regulator circuit also includes an error amplifier and a negative feedback circuit; the inputs of all transmission gates are connected in parallel to the output of the error amplifier; the output of each transmission gate is connected to the gate of a power transistor; and the drains of all power transistors are connected in parallel to the input of the negative feedback circuit. The control circuit further includes N power input terminals and one voltage output terminal; each power input terminal is connected to a power source; the voltage output terminal is connected to the power source of the error amplifier to provide power to the error amplifier; wherein, the voltage output by the voltage output terminal is the power source voltage connected to one of the N power input terminals. The negative input terminal of the error amplifier is connected to the reference voltage; the positive input terminal of the error amplifier is connected to the output terminal of the negative feedback circuit.

2. The linear voltage regulator circuit according to claim 1, characterized in that, Each transmission gate includes a PMOS transistor, an NMOS transistor, and an inverter; the gate of the PMOS transistor is connected in parallel with the input of the inverter, serving as the control terminal of the transmission gate; the drain of the PMOS transistor is connected in parallel with the drain of the NMOS transistor, serving as the input terminal of the transmission gate; the source of the PMOS transistor is connected in parallel with the source of the NMOS transistor, serving as the output terminal of the transmission gate; the gate of the NMOS transistor is connected to the output terminal of the inverter.

3. The linear voltage regulator circuit according to claim 1, characterized in that, The control circuit includes: N parallel control branches, each control branch includes a branch signal input terminal, a branch power input terminal, and a branch voltage output terminal; each branch signal input terminal is connected to a control signal output terminal of the control circuit; each branch power input terminal serves as a power input terminal; all branch voltage output terminals are connected in parallel as a voltage output terminal.

4. The linear regulator circuit according to claim 3, characterized in that, Each control branch includes: The drain of the switching transistor is used as the power input terminal of the branch; the gate of the switching transistor is used as the signal input terminal of the branch; and the source of the switching transistor is used as the voltage output terminal of the branch.

5. The linear voltage regulator circuit according to claim 3, characterized in that, The branch signal input terminal of the i-th control branch in the control circuit and the control terminal of the transmission gate in the i-th power transistor branch are connected in parallel to the i-th control signal output terminal of the control circuit; and, The power input terminal of the i-th control branch in the control circuit, the source of the power transistor in the i-th power transistor branch, and the power input terminal of the i-th power transistor in the control circuit are connected to the same power supply. Where i = 1, ..., N.

6. The linear regulator circuit according to claim 1, characterized in that, The negative feedback circuit includes: The first voltage divider element has its input terminal serving as the input terminal of the negative feedback circuit, and its output terminal serving as the output terminal of the negative feedback circuit. The second voltage divider element has its input terminal connected to the output terminal of the first voltage divider element; the output terminal of the second voltage divider element is grounded.

7. A power supply device comprising N power supplies, where N is an integer greater than 1; characterized in that the power supply device further comprises a linear regulator circuit as described in any one of claims 1 to 6.

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