Method for implementing rs decoding hardware, electronic device and storage medium

Abstract

Embodiments of the present application disclose a RS decoding hardware implementation method, an electronic device and a storage medium, comprising obtaining positions of A lost data blocks, positions of A required check blocks and an original coefficient matrix, wherein A is less than or equal to M, and M is the number of original check blocks; extracting corresponding row and column coefficients from the original coefficient matrix according to the positions of the A data blocks and the positions of the A check blocks, generating an M-order coefficient matrix according to the row and column coefficients, and calculating an inverse matrix of the M-order coefficient matrix; generating new M check blocks according to the positions of the A check blocks, and recovering the A lost data blocks according to the new M check blocks, the original M check blocks and the inverse matrix. The present application reduces the original N-order inverse matrix solution to an M-order inverse matrix solution, greatly reducing the hardware implementation complexity.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of RS decoding, in particular to an RS decoding hardware implementation method, an electronic device and a storage medium. BACKGROUND

[0002] With the development and popularity of cloud storage, the amount of data that needs to be stored and processed presents an explosive growth. In order to ensure the security of data, the currently used data storage technologies mainly include multi-backup technology and erasure coding technology. Among them, the multi-backup technology is to backup the same data multiple times, and the commonly used is 3 backup technology, which has the disadvantage of low disk utilization, and the required disk capacity is directly multiplied by 3, which is high in cost. The erasure coding technology is to achieve the effect of data backup by increasing part of the disk, and the utilization rate of the erasure coding disk can reach 1.x (less than 2). The erasure coding storage generates N+M data blocks by increasing M check blocks from N data blocks, and when there are less than or equal to M data blocks missing in the N+M data blocks, the missing data blocks can be recovered. When A (<=M) data blocks are missing and need to be recovered, the inverse matrix of N-A (data blocks) +A (check blocks) needs to be solved to obtain the missing data blocks. When the number of missing blocks is large, the order of the matrix to be solved is also large (usually N order matrix is directly solved), and the hardware complexity is also large. SUMMARY

[0003] Embodiments of the present application provide an RS decoding hardware implementation method, an electronic device and a storage medium, which can reduce the implementation complexity of hardware.

[0004] In a first aspect, embodiments of the present application provide an RS decoding hardware implementation method, which comprises:

[0005] obtaining A missing data block positions, A required check block positions and an original coefficient matrix, wherein A is less than or equal to M, and M is the number of original check blocks;

[0006] extracting corresponding row and column coefficients from the original coefficient matrix according to the A data block positions and the A check block positions, generating an M order coefficient matrix according to the row and column coefficients, and calculating the inverse matrix of the M order coefficient matrix;

[0007] generating new M check blocks according to the A check block positions, and recovering the A missing data blocks according to the new M check blocks, the original M check blocks and the inverse matrix.

[0008] In a second aspect, an electronic device is provided, which comprises a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the RS decoding hardware implementation method as described above when executing the computer program.

[0009] In a third aspect, a computer readable storage medium is provided, which stores computer executable instructions for implementing the RS decoding hardware implementation method as described above.

[0010] The RS decoding hardware implementation method provided by the embodiment of the present application is suitable for the decoding architecture of N data blocks and M check blocks, and does not need to perform the inverse operation of the N-order coefficient matrix, but can determine the coefficients needed to be extracted from the M*N-order original coefficient matrix by losing the data block position and using the check block position, generate an M-order coefficient matrix from the coefficients, perform the inverse operation on the M-order coefficient matrix, and recover the lost data block by using the new and old check codes and the inverse matrix of the M-order coefficient matrix. The embodiment reduces the inverse matrix solving of N order to the inverse matrix solving of M order, and greatly reduces the implementation complexity of the hardware.

[0011] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the present application. The objects and other advantages of the present application can be achieved and obtained by the structure particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the technical scheme of the present application, and constitute a part of the specification, and are used together with the embodiments of the present application to explain the technical scheme of the present application, and do not constitute a limitation on the technical scheme of the present application.

[0013] Figure 1 A flowchart of the RS decoding hardware implementation method provided by an embodiment of the present application is shown in the figure;

[0014] Figure 2 A flowchart of generating the M-order coefficient matrix provided by an embodiment of the present application is shown in the figure;

[0015] Figure 3 A flowchart of recovering the A data blocks provided by an embodiment of the present application is shown in the figure;

[0016] Figure 4 A flowchart of the RS decoding hardware implementation method provided by another embodiment of the present application is shown in the figure;

[0017] Figure 5 A flowchart of recovering the B check blocks provided by an embodiment of the present application is shown in the figure;

[0018] Figure 6 A flowchart of extracting the coefficient matrix provided by an embodiment of the present application is shown in the figure;

[0019] Figure 7A flow chart for decoding a data block is provided for an embodiment of the present application.

[0020] Figure 8 A flow chart for decoding a check block is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and should not be used to limit the present application.

[0022] It should be noted that although the functional modules are divided in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a manner different from the module division in the device or the order in the flow chart. The terms "first", "second", etc. in the specification, claims or above-described drawings are used to distinguish similar objects, and do not necessarily describe a specific order or sequence.

[0023] With the development and popularity of cloud storage, the amount of data that needs to be stored and processed is growing explosively. In order to ensure the security of data, the currently used data storage technologies mainly include multi-backup technology and erasure technology. Among them, the multi-backup technology is to backup the same data multiple times, and the commonly used 3-backup technology has the disadvantage of low disk utilization, and the required disk capacity is directly multiplied by 3, which is relatively high in cost. The erasure technology achieves the effect of data backup by increasing part of the disk, and the utilization rate of the erasure disk can reach 1.x (less than 2). The erasure storage generates N+M data blocks by increasing M check blocks from N data blocks, and when less than or equal to M data blocks are lost in the N+M data blocks, the lost data blocks can be recovered. When A data blocks are lost (A<=M) and need to be recovered, the inverse matrix of N-A (data blocks) + A (check blocks) needs to be solved to obtain the lost data blocks. When the number of lost blocks is large, the order of the matrix to be solved is also large (usually N-order matrix is directly solved), and the hardware complexity is also large.

[0024] In order to solve the above-mentioned defects, the present application can determine the coefficients that need to be extracted from the M*N order original coefficient matrix by using the lost data block position and the check block position, generate an M order coefficient matrix from the coefficients, perform an inverse operation on the M order coefficient matrix, and then perform a finite field matrix multiplication on the difference between the new and old check codes and the inverse matrix of the M order coefficient matrix, so as to recover the lost data block. The inverse matrix solving of N order is reduced to the inverse matrix solving of M order, which greatly reduces the implementation complexity of the hardware.

[0025] And through the application, the whole data block can be obtained by splicing the original data block and the recovered data block, and the lost check block can be recovered by performing the matrix multiplication of the whole data block and the coefficient matrix of the lost check block in the finite field.

[0026] An embodiment of the present application provides an RS decoding hardware implementation method, which can be executed in an electronic device. The electronic device can be a mobile electronic device, a non-mobile electronic device or a server. The mobile electronic device can be a mobile phone, a tablet computer, a notebook computer, a palm computer, a vehicle-mounted electronic device, a wearable device, an ultra-mobile personal computer, a netbook, a personal digital assistant, etc.; the non-mobile electronic device can be a personal computer, a television, a teller machine or a self-service machine, etc.; and the present application is not limited in specific embodiments. The electronic device can include a processor, an external memory interface, an internal memory, a universal serial bus (USB) interface, a charging management module, a power management module, a battery, an antenna, a mobile communication module, a wireless communication module, an audio module, a loudspeaker, a receiver, a microphone, a headset interface, a sensor module, a key, a motor, an indicator, a camera, a display screen, and a Subscriber Identification Module (SIM) card interface, etc. The server can be a stand-alone server or a cloud server providing cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, Content-Delivery Network (CDN), and basic cloud computing services such as big data and artificial intelligence platforms.

[0027] The embodiments of the present application are further described below with reference to the accompanying drawings.

[0028] Referring to Figure 1 An embodiment of the present application provides an RS (Reed-solomon) decoding hardware implementation method, which includes the following steps:

[0029] In step S101, the positions of A lost data blocks, the positions of A required check blocks and an original coefficient matrix are obtained, wherein A is less than or equal to M, and M is the number of original check blocks.

[0030] In step S102, corresponding row and column coefficients are extracted from the original coefficient matrix according to the positions of the A data blocks and the positions of the A check blocks, an M-order coefficient matrix is generated according to the row and column coefficients, and an inverse matrix of the M-order coefficient matrix is calculated.

[0031] Step S103: Generate M new check blocks based on the positions of the A check blocks, and recover the lost A data blocks based on the new M check blocks, the original M check blocks, and the inverse matrix.

[0032] This method is applicable to decoding architectures with N original data blocks and M original parity blocks, where M is much smaller than N. When A data blocks are lost from the original N data blocks, this method can effectively recover these A data blocks and significantly reduce the hardware implementation complexity during the recovery process.

[0033] In step S101, the locations of A data blocks lost from the original N data blocks, the locations of A parity blocks required from the original M parity blocks, and the original coefficient matrix of order M*N are known. The required A parity block locations are pre-configured based on the locations of the lost A data blocks, which will not be detailed here. In some embodiments, the original coefficient matrix of order M*N uses a configurable intrinsic polynomial, such as a Cauchy matrix or a van der Montgomery matrix (this embodiment uses a Cauchy matrix as an example), ensuring that any submatrix of the coefficient matrix is ​​invertible. The expression for the Cauchy matrix is ​​as follows:

[0034]

[0035] Where, x i and y i All are elements GF(2) in the Galohua Domain w ), that is, x i ∈GF(2 w ), y i ∈GF(2 w And x i ≠y i .

[0036] The following describes the underlying principles of this method embodiment:

[0037] Suppose there are n data blocks W = (w1, w2, ..., w n ), the coefficient matrix β = (β) of n*m 1,1 ,...,β m,n After performing matrix multiplication on the data block and the coefficient matrix within a finite field, m check blocks Q = (q1, q2, ..., q3) are obtained. m ).

[0038] When k data blocks out of n data blocks are lost, the data blocks corresponding to these k positions are filled with 0 values, resulting in W' = (w'1, w'2, ..., w'). n Then, combine the n data blocks padded with zeros with the n*m ​​coefficient matrix β = (β 1,1 ,...,β m,n) and the new check blocks Q' = (q'1, q'2,..., q' m) are obtained by performing the matrix multiplication of the finite field. m ) and the new check blocks Q' = (q'1, q'2,..., q' m) are obtained by performing the matrix multiplication of the finite field.

[0039] ) and the new check blocks Q' = (q'1, q'2,..., q' m) are obtained by performing the matrix multiplication of the finite field.

[0040] ) and the new check blocks Q' = (q'1, q'2,..., q' m) are obtained by performing the matrix multiplication of the finite field. When k < M, it is necessary to pad it to M order before starting the inverse operation of the matrix β. Only 1 is padded on the diagonal, and 0 is padded on the rest of the positions. The k*k matrix is padded to the M*M order coefficient matrix. Then the inverse operation is performed on the extracted coefficient matrix to obtain

[0041] The inverse matrix obtained by solving is The value Q-Q' after the subtraction of the check blocks is subjected to the matrix multiplication of the finite field to obtain the lost data blocks. The first k data blocks in the m data blocks are the lost data blocks.

[0042] Therefore, in step S102, the lost data block position and the required verification block position are directly used to determine the corresponding coefficients that need to be extracted from the original coefficient matrix. The coefficients are used to generate an M order coefficient matrix, and the inverse operation is performed on the M order coefficient matrix.

[0043] Referring to Figure 2 In some embodiments, the step S102 of extracting the corresponding row and column coefficients from the original coefficient matrix according to the A data block positions and the A check block positions, and generating an M order coefficient matrix according to the row and column coefficients, comprises:

[0044] Step S1021, extracting A column coefficients from the original coefficient matrix according to A data block positions.

[0045] Step S1022, extracting A row coefficients from the original coefficient matrix according to A check block positions.

[0046] Step S1023, when A is equal to M, generating an M order coefficient matrix according to the A column coefficients and the A row coefficients.

[0047] Step S1024, when A is less than M, generating an A order coefficient matrix according to the A column coefficients and the A row coefficients, and expanding the A order coefficient matrix to an M order coefficient matrix.

[0048] In step S1024, because A is less than M, the A order coefficient matrix is expanded to an M order coefficient matrix. In some embodiments, step S1024 expands the A order coefficient matrix to an M order coefficient matrix in the following way:

[0049] Step S10241, extend the A-order coefficient matrix to an M-order matrix, and determine a first blank position on the diagonal line and a second blank position on the non-diagonal line in the M-order matrix.

[0050] Step S10242, fill the first blank position with a first value and the second blank position with a second value to obtain an M-order coefficient matrix; wherein the first value is 1 and the second value is 0.

[0051] In steps S10241 and S10242, the A-order coefficient matrix is padded to the M-order coefficient matrix according to the rule of padding 1 to the blank position on the diagonal line of the matrix and padding 0 to the remaining blank positions of the matrix.

[0052] With reference to Figure 3 In step S103, generating the new M check blocks includes:

[0053] Step S1031, obtain the original N data blocks.

[0054] Step S1032, pad 0 to A data block positions in the original N data blocks to generate a 1*N order data matrix.

[0055] Step S1033, select an A*N order data matrix from the original coefficient matrix according to the A check block positions.

[0056] Step S1034, pad 0 to the blank coefficient positions of the A*N order data matrix to pad the A*N order data matrix to an M*N order data matrix.

[0057] Step S1035, multiply the 1*N order data matrix and the M*N order data matrix to obtain the new M check blocks.

[0058] In step S1031, the original N data blocks are known items. In step S1032, since A data blocks are missing in the original N data blocks, 0 needs to be padded to the missing A data block positions to obtain a 1*N order data matrix. In step S1033, A row coefficients (here, the A row coefficients are the extracted A*N order data matrix) corresponding to the positions are extracted from the M*N order original coefficient matrix according to the required A check block positions. In step S1034, the A*N order data matrix obtained in step S1033 is extended to an M*N order data matrix by directly padding 0 to the blank positions in the matrix, as in the extension in step S1024. In step S1035, the 1*N order data matrix obtained in step S1032 and the M*N order data matrix obtained in step S1034 are multiplied in a finite field to obtain the new M check blocks.

[0059] In step S103, after the new M parity blocks are generated, the lost A data blocks are recovered according to the new M parity blocks, the original M parity blocks and the inverse matrix. Refer to Figure 3 In an embodiment, step S103 recovers the A data blocks by the following way:

[0060] Step S1036, calculates a difference matrix between the new M parity blocks and the original M parity blocks.

[0061] Step S1037, multiplies the difference matrix and the inverse matrix to recover the lost A data blocks.

[0062] In step S1036, the new and old M parity blocks are subjected to a subtraction operation in a finite field to obtain a difference matrix, and then the difference matrix and the inverse matrix of the M order coefficient matrix obtained in step S102 are subjected to a matrix multiplication operation in the finite field to obtain N data blocks. The first A data blocks in the N data blocks are the decoded A data blocks (i.e. the lost A data blocks are recovered).

[0063] The RS decoding hardware implementation method provided in the embodiment is suitable for the decoding architecture of N data blocks and M parity blocks. Without performing the inverse operation of the N order coefficient matrix, the coefficients needed to be extracted from the original M*N order coefficient matrix can be determined by using the lost data block position and the parity block position, the coefficients are used to generate an M order coefficient matrix, the inverse operation is performed on the M order coefficient matrix, and then the difference between the new and old parity codes and the inverse matrix are subjected to a finite field matrix multiplication, so that the lost data blocks can be recovered. The inverse matrix solving of N order is reduced to the inverse matrix solving of M order, and the hardware implementation complexity is greatly reduced.

[0064] In the above embodiment, the case that A data blocks in the original N data blocks are lost is mainly involved. Based on the above embodiment, refer to Figure 4 An embodiment of the present application provides an RS decoding hardware implementation method. The method involves the case that A data blocks in the original N data blocks and B parity blocks in the original M parity blocks are lost. The method includes the following steps:

[0065] Step S104, obtains the lost B parity block positions, wherein the sum of A and B is less than or equal to M.

[0066] Step S105, extracts the corresponding parity block coefficient matrix from the original coefficient matrix according to the B parity block positions.

[0067] Step S106, recovers the lost B parity blocks according to the recovered A data blocks and the parity block coefficient matrix.

[0068] Based on the steps S101 to S103, in step S104 of the embodiment, the lost B check block positions are known, in order to recover the lost B check blocks, first, in step S105, the corresponding check block coefficient matrix is extracted from the original M*N order coefficient matrix according to the B check block positions, then in step S106, the lost B check blocks are recovered according to the check block coefficient matrix and the recovered A data blocks.

[0069] With reference to Figure 5 In some embodiments, step S106 specifically comprises the following steps:

[0070] Step S1061, the recovered A data blocks and the remaining N-A data blocks in the original N data blocks are spliced into complete N data blocks.

[0071] Step S1062, the check block coefficient matrix is multiplied by the complete N data blocks to recover the lost B check blocks.

[0072] In step S1061, first, since the original N data blocks have lost A data blocks, the A data blocks recovered in step S103 and the remaining N-A data blocks in the original N data blocks except the lost A data blocks are spliced into complete N data blocks, then the check block coefficient matrix is multiplied by the complete N data blocks in the finite field to obtain M check blocks, and the first B check blocks are the recovered B check blocks.

[0073] The embodiment makes further improvement on the basis of the above method embodiment, adopts the architecture of first restoring the lost data blocks (steps S101 to S103) and then restoring the lost check blocks (steps S103 to S106). By splicing the remaining N-A data blocks in the original N data blocks and the recovered A data blocks, the overall N data blocks are obtained, and the lost check blocks can be obtained by performing finite field matrix multiplication on the check block coefficient matrix extracted from the original M*N order coefficient matrix according to the position of the lost check blocks, so that the data blocks and the check blocks are simultaneously recovered.

[0074] With reference to Figure 6 to Figure 8 In an embodiment of the application, an RS decoding hardware implementation method is provided, and the method implements the decoding operation through the following flow:

[0075] Step S201, confirming parameters.

[0076] Specifically, in the original N data blocks and the original M check blocks, A data blocks are lost, and A∈(0, M], B check blocks are lost, and B∈[0, M], and A+B<=M. The lost data block positions are known Missing check block positions and required check block positions The three positions are configured by a higher layer.

[0077] Step S202, calculate the inverse matrix of the M-order coefficient matrix and select the output check block coefficient.

[0078] Specifically, according to the A missing data block positions The A column positions in the M*N original coefficient matrix, i.e., the first column, can be determined. According to the A required check block positions The A row positions in the M*N coefficient matrix, i.e., the first row, can be determined.

[0079] By confirming the row and column coefficient positions, the coefficient matrix

[0080] When A < M, the A*A-order coefficient matrix needs to be expanded into an M*M-order coefficient matrix. The expansion is to fill 1 in the diagonal position of the matrix and 0 in the other positions. The A*A-order coefficient matrix is filled to an M*M-order coefficient matrix. After expansion, the inverse operation of the M*M-order coefficient matrix is performed to obtain the inverse matrix β'.

[0081] When A = M, the inverse operation of the M*M-order coefficient matrix is directly performed to obtain the inverse matrix β'.

[0082] According to the B missing check block positions in the original M check blocks The coefficient row positions that need to be extracted from the M*N-order coefficient matrix Therefore, the coefficient

[0083] Step S203, collect the data blocks and check blocks that need to be decoded (i.e., the data blocks (N-A) that are not missing in the original N data blocks and the check blocks (M-B) that are not missing in the original M check blocks) and output a 1*N-order data matrix.

[0084] Specifically, M+N memories are required to store the data blocks and check blocks that need to be decoded. During storage, according to the data block and check block loss indication configured by the higher layer, the memory corresponding to the data block that has been lost and the check block that has been lost is directly written as 0 to be emptied. After the data blocks and check blocks are collected, a 1*N data matrix is output synchronously. It should be noted that since there are A data blocks missing in the original N data blocks in step S201, the positions of the A missing data blocks need to be filled with 0 to obtain a 1*N data matrix.

[0085] Step S204, extracting and outputting the M*N coefficient matrix.

[0086] Specifically, according to the A check block positions needed to be used Determining A rows of coefficients in the M*N coefficient matrix corresponding to the positions Then, the extracted A*N matrix is expanded into an M*N matrix (0 is supplemented).

[0087] Step S205, generating new M check blocks.

[0088] Specifically, the 1*N order data matrix β' of step S203 is multiplied with the M*N order coefficient matrix of step S204 in a finite field to obtain a 1*M order check block q'.

[0089] Step S206, recovering data blocks.

[0090] Specifically, the original M check blocks are subtracted from the newly generated M check blocks q' of step S205 in a finite field, and then multiplied with the M*M order inverse matrix calculated in step S202 to obtain a 1*M order data matrix, wherein the first A are the data blocks to be recovered.

[0091] Step S207, recovering check blocks.

[0092] Specifically, the decoded A data blocks are spliced with the original N-A data blocks of step S201 to obtain complete N data blocks. Then, the coefficient matrix β'' extracted in step S202 is multiplied with the complete N data blocks in a finite field to obtain the lost B check blocks.

[0093] Step S208, storing.

[0094] Specifically, the decoded A data blocks and the decoded B check blocks are stored for high-level reading. When A+B

[0095] The method embodiment has the following beneficial effects:

[0096] 1) Supporting decoding and recovery of simultaneous loss of data blocks and check blocks;

[0097] The method adopts an architecture of first restoring lost data blocks and then restoring lost check blocks. The original data blocks are spliced with the restored data blocks to obtain the overall data, and the lost check blocks are multiplied with the coefficients of the lost check blocks in a finite field to obtain the lost check blocks. In this way, it can be ensured that the data blocks and the check blocks can be simultaneously recovered.

[0098] 2) Inverse matrix of a matrix of order M;

[0099] The method optimizes the decoding process. When A (A<=M) order data is lost, only the inverse operation of the A order coefficient matrix is needed to perform the decoding operation, and the inverse operation of the N order coefficient matrix is not needed. The coefficient matrix to be extracted can be determined by the lost data position and the verification code position. The inverse operation is performed on the coefficient matrix, and the difference between the new and old check blocks is multiplied by the finite field matrix to obtain the data to be decoded. In the hardware implementation process, in order to be compatible with the A value, M possible scenarios may be needed at most. Different scenarios occupy different hardware resources. In order to save hardware costs as much as possible, the method combines the matrix of order less than M (order A) and performs the inverse operation of the M order matrix, thereby reducing the hardware resource cost.

[0100] In one embodiment of the present application, an electronic device is provided, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor.

[0101] The processor and the memory can be connected by a bus or other means.

[0102] The memory, as a non-transitory computer readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory can include a high-speed random access memory and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory can optionally include a memory remotely arranged with respect to the processor, and these remote memories can be connected to the processor through a network. Examples of the above-mentioned network include but are not limited to the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0103] The non-transitory software programs and instructions required for the RS decoding hardware implementation method of the above-mentioned embodiments are stored in the memory, and when executed by the processor, the RS decoding hardware implementation method in the above-mentioned embodiments is executed, for example, the method steps S101 to S103 in the above-mentioned Figure 1 , the method steps S1021 to S1024 in the above-mentioned Figure 2 , the method steps S1031 to S1037 in the above-mentioned Figure 3 , the method steps S104 to S106 in the above-mentioned Figure 4 , and the steps S1061 to S1062 in the above-mentioned Figure 5 .

[0104] The terminal embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0105] Furthermore, in one embodiment of the present invention, a computer-readable storage medium is provided that stores computer-executable instructions, which are executed by a processor or controller, for example, by a processor in the above-described terminal embodiment, causing the processor to execute the RS decoding hardware implementation method in the above-described embodiment, for example, to perform the above-described... Figure 1 Method steps S101 to S103 in the text Figure 2 Method steps S1021 to S1024 in the text Figure 3 Method steps S1031 to S1037 in the text Figure 4 Method steps S104 to S106 and Figure 5 Steps S1061 to S1062 in the process.

[0106] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0107] In the description of the application, reference is made to the terms "one embodiment", "some embodiments", "an illustrative embodiment", "an example", "a specific example" or "some examples" means that a particular feature, structure, material or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. The illustrative appearances of the above-mentioned terms in various places in the specification are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0108] The above is a specific description of the preferred embodiment of the present application, but the present application is not limited to the above-mentioned embodiments, and those skilled in the art can make various equivalent modifications or replacements without departing from the spirit of the present application, and these equivalent modifications or replacements are included in the scope defined by the claims of the present application.

Claims

1. A method of RS decoding hardware implementation, characterized in that, The method comprises: obtaining lost A data block positions, required A check block positions and an original coefficient matrix, wherein A is less than or equal to M, and M is the number of original check blocks; generating an M-order coefficient matrix according to A column coefficients corresponding to the A data blocks and A row coefficients corresponding to the A check block positions in the original coefficient matrix, and calculating an inverse matrix of the M-order coefficient matrix; generating new M check blocks according to the A check block positions, and recovering the lost A data blocks according to the new M check blocks, original M check blocks and the inverse matrix; wherein the generating of the new M check blocks according to the A check block positions comprises: filling 0 in the A data block positions in the original N data blocks to generate an N*1-order data matrix; and M is less than N; selecting an A*N-order data matrix from the original coefficient matrix according to the A check block positions; completing the A*N-order data matrix to an M*N-order data matrix according to the rule of filling 0 in the matrix position empty coefficient; multiplying the M*N-order data matrix and the N*1-order data matrix to obtain the new M check blocks.

2. The method of RS decoding hardware implementation according to claim 1, wherein, The generating of the M-order coefficient matrix according to the A column coefficients corresponding to the A data blocks and the A row coefficients corresponding to the A check block positions in the original coefficient matrix comprises: when A is equal to M, generating an M-order coefficient matrix according to the A column coefficients and the A row coefficients; when A is less than M, generating an A-order coefficient matrix according to the A column coefficients and the A row coefficients, and expanding the A-order coefficient matrix to an M-order coefficient matrix.

3. The method of RS decoding hardware implementation according to claim 2, wherein, The expanding of the A-order coefficient matrix to the M-order coefficient matrix comprises: expanding the A-order coefficient matrix to an M-order matrix, and determining a first blank position on a diagonal line and a second blank position on a non-diagonal line in the M-order matrix; filling a first value in the first blank position and a second value in the second blank position to obtain an M-order coefficient matrix; wherein the first value is 1, and the second value is 0.

4. The method of RS decoding hardware implementation according to claim 3, wherein, The recovering of the lost A data blocks according to the new M check blocks, original M check blocks and the inverse matrix comprises: calculating a difference matrix between the new M check blocks and the original M check blocks; multiplying the difference matrix and the inverse matrix to recover the lost A data blocks.

5. The method of RS decoding hardware implementation according to claim 4, wherein, The method further comprises: obtaining lost B check block positions, wherein the sum of A and B is less than or equal to M; extracting a corresponding check block coefficient matrix from the original coefficient matrix according to the B check block positions; recovering the lost B check blocks according to the recovered A data blocks and the check block coefficient matrix.

6. The method of RS decoding hardware implementation according to claim 5, wherein, The recovering of the lost B check blocks according to the recovered A data blocks and the check block coefficient matrix comprises: splicing the recovered A data blocks and remaining N-A data blocks in the original N data blocks into complete N data blocks; multiplying the check block coefficient matrix and the complete N data blocks to recover the lost B check blocks.

7. The method of RS decoding hardware implementation according to claim 6, wherein, After the B check blocks lost are recovered, the method further comprises: writing the A data blocks recovered and the B check blocks recovered into a memory.

8. The method of RS decoding hardware implementation according to any one of claims 1 to 7, characterized in that, The original coefficient matrix is a Cauchy matrix or a Van der Monde matrix.

9. An electronic device, comprising: comprise: a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the RS decoding hardware implementation method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that, computer executable instructions are stored for executing the RS decoding hardware implementation method according to any one of claims 1 to 8.

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