A CLLC converter digitized synchronous rectification control method

Abstract

The application discloses a CLLC converter digital synchronous rectification control method. The method adopts a DSP chip to control the CLLC converter, and comprises the following steps: real-time sampling of output voltage and output current through an ADC module; calculation and processing of the voltage and current sampling signals; calculation of output power control of the secondary side synchronous rectification enable; processing of the secondary side resonant current sampling signal by using a high-speed comparator module; output of the secondary side synchronous rectification control signal through an algorithm; and control of the secondary side switch tube on-off through a secondary side driving circuit. The application determines the working state through the switching frequency of the CLLC converter, carries out different delay processing on the turn-on of the secondary side switch tube, ensures ZVS turn-on and avoids the current backflow problem caused by the false turn-on, and improves the efficiency and reliability of the system.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a digital synchronous rectification control method for a CLLC converter. Background Technology

[0002] With the development of renewable energy, electric vehicles, power electronic transformers, energy storage systems, and other fields, bidirectional isolated DC-DC converters have been widely used and are currently a research hotspot. High power density and high efficiency have always been the research focus of DC-DC converters, especially for resonant converters. Improving their operating efficiency and reducing converter energy loss are among the research directions.

[0003] To reduce conduction losses in the secondary-side network, synchronous rectification control is often employed for the secondary-side switches. This involves applying a drive signal to the gate of the corresponding switch when current flows through it, turning it on and changing the current path from the body diode to a channel, thus reducing losses caused by current flowing through the switch. Currently, commonly used synchronous rectification control methods include analog control and digital control. Analog control requires additional analog circuitry, such as comparators, to process current and other signals, increasing circuit cost; digital control does not require additional analog circuitry, making it more economical. Traditional synchronous rectification methods do not perform turn-on delay processing, resulting in hard turn-on of the secondary-side switches and higher switching losses. Some researchers have proposed delaying turn-on in under-resonant operation, but this does not consider the effects of dead time and parasitic parameters in resonant operation, leading to current backflow problems in CLLC converters caused by incorrect synchronous rectification turn-on. Summary of the Invention

[0004] To address the problems in existing technologies, this invention proposes a digital synchronous rectification control method for CLLC converters, enabling ZVS (Zero-Voltage-Side Response) turn-on of synchronous rectification and preventing backflow of energy on the secondary side. This invention employs a DSP chip to control the CLLC converter, including real-time sampling of output voltage and current via an ADC module; processing of the voltage and current sampling signals; calculating output power to control secondary-side synchronous rectification enable; processing the secondary-side resonant current sampling signal using a high-speed comparator module; and outputting a secondary-side synchronous rectification control signal via an algorithm, which controls the on / off state of the secondary-side switching transistors through a secondary-side drive circuit. This invention determines the operating state by the switching frequency of the CLLC converter and applies different delays to the turn-on of the secondary-side switching transistors, ensuring ZVS turn-on and preventing backflow caused by erroneous turn-on, thereby improving system efficiency and reliability.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A digital synchronous rectification control method for a CLLC converter is implemented through a CLLC converter and a control circuit. The CLLC converter consists of a primary-side network, a secondary-side network, and a resonant cavity. The control circuit includes an output voltage sampling circuit, an output current sampling circuit, a secondary-side resonant current sampling circuit, a DSP controller, a primary-side drive circuit, and a secondary-side drive circuit. The method includes the following steps:

[0007] Step 1: The ADC module of the DSP chip acquires the output signals of the output voltage sampling circuit and the output current sampling circuit in real time;

[0008] Step 2: Process the signal acquired by the ADC module, calculate the output power, and determine whether to enable synchronous rectification;

[0009] Step 3: Determine the circuit operating state based on the switching frequency of the CLLC converter. The circuit operating state includes state A and state B.

[0010] When the switching frequency f of the CLLC converter s Less than or equal to the resonant frequency f r When, it indicates that the operation is in state A;

[0011] When the switching frequency f of the CLLC converter s Greater than the resonant frequency f r When this is the case, it indicates that the system is in state B.

[0012] Step 4: Based on the operating status of the CLLC converter, select the synchronous rectification signal turn-on delay time to obtain the turn-on time of the synchronous rectification signal;

[0013] Step 5: The high-speed comparator module of the DSP chip processes the output signal of the secondary resonant current sampling circuit, compares it with the threshold, and obtains the turn-off time of the synchronous rectified signal.

[0014] Step 6: Based on the turn-on and turn-off times of the synchronous rectification signal, the DSP chip sends a synchronous rectification control signal, which controls the on / off state of the secondary-side switching transistor through the secondary-side drive circuit.

[0015] Furthermore, the output voltage sampling circuit and the output current sampling circuit convert the output voltage and output current into weak electrical signals of 0-3.3V through voltage sensors and current sensors, respectively.

[0016] Furthermore, the ADC module of the DSP chip acquires the output signals of the output voltage sampling circuit and the output current sampling circuit, converting the analog weak electrical signal into a digital signal for the DSP chip to process and calculate.

[0017] Furthermore, before calculating the signal acquired by the ADC module, the signal is first filtered, then the voltage and current values ​​are restored, and then the real-time output power is calculated using the power calculation formula.

[0018] Furthermore, in step 2, determining whether to enable synchronous rectification includes:

[0019] When the output power is less than the power threshold P th1 At that time, the synchronous rectification enable signal SR EN A value of 0 indicates that synchronous rectification is not enabled and the secondary-side switching transistor does not operate.

[0020] When the output power is greater than the power threshold P th2 At that time, the synchronous rectification enable signal SR EN A value of 1 indicates that synchronous rectification is enabled and the secondary-side switch is activated, where the power threshold P... th1 Less than the power threshold P th2 .

[0021] Furthermore, in step 4, selecting the synchronous rectification signal turn-on delay time includes:

[0022] The turn-on delay is a delay based on the turn-on time of the corresponding primary-side switch tube.

[0023] When the CLLC converter operates in state A, the turn-on delay time is fixed at t. o ;

[0024] When the CLLC converter operates in state B, the turn-on delay time varies with the switching frequency in time t. o Based on this, a step-like increment is made, and the delay time reaches its maximum t when the switching frequency is at its maximum. n , i.e. t n It is the maximum delay time, where n represents the number of steps.

[0025] Furthermore, in step 5, the processing of the high-speed comparator module includes:

[0026] The high-speed comparator in the high-speed comparator module samples the output signal V of the secondary resonant current sampling circuit. I_Sec The comparison includes handling the shutdown time for both positive and negative half cycles; the high-speed comparator module includes high-speed comparator CMPSS_H and high-speed comparator CMPSS_L.

[0027] The high-speed comparator CMPSS_H performs a comparison and judgment within the positive half-cycle. When V I_Sec <V th1 When the high-speed comparator outputs 0, it indicates that a turn-off signal has been given to the corresponding switch in the secondary network.

[0028] The high-speed comparator CMPSS_L performs a comparison and judgment during the negative half-cycle. When V I_Sec >V th2 When the high-speed comparator outputs 0, it indicates that a turn-off signal has been given to the corresponding switch in the secondary network.

[0029] Among them, V I_Sec It is the output signal of the secondary resonant current sampling circuit, V th1 and V th2 These are the two threshold values ​​corresponding to when the secondary resonant current is close to 0.

[0030] Furthermore, t o It is set according to the circuit characteristics, t n It is set based on dead time, circuit characteristics, and the worst operating conditions.

[0031] Compared with the prior art, the beneficial effects of the technical solution of the present invention are:

[0032] 1. This invention adopts a digital synchronous rectification control method. By sampling the secondary resonant current in real time and using a DSP high-speed comparator to process the sampling signal, it does not add additional analog circuits, has strong applicability, simplifies the control circuit, and reduces circuit costs.

[0033] 2. This invention addresses the switching frequency of CLLC converters by differentiating their operating states. In state A, a fixed turn-on delay is applied during synchronous rectification to avoid the oscillation process of the drain-source voltage of the secondary-side switch, enabling the switch to turn on at ZVS and thus reducing switching losses. In state B, considering the influence of dead time and circuit parasitic parameters, the turn-on delay time is set in a stepped manner according to the switching frequency. While maximizing the synchronous rectification time, it ensures that the secondary-side current has reversed when the switch is turned on, thereby avoiding the problem of secondary-side energy backflow caused by false turn-on. Attached Figure Description

[0034] Figure 1 This is a control block diagram of the digital synchronous rectification method for CLLC converter in this invention;

[0035] Figure 2 This is a schematic diagram of the steps of the digital synchronous rectification control method for CLLC converter in this invention;

[0036] Figure 3 This is the digital synchronous rectification enable control diagram of the CLLC converter in this invention;

[0037] Figure 4 This is a diagram showing the turn-on delay of the digital synchronous rectification of the CLLC converter in this invention.

[0038] Figure 5 This is the timing diagram of the digital synchronous rectification control drive of the CLLC converter in this invention;

[0039] Figure 6 These are experimental results of the digital synchronous rectification of the CLLC converter in this invention; where (a) is the experimental result of the CLLC converter operating in state A, and (b) is the experimental result of the CLLC converter operating in state B. Detailed Implementation

[0040] To make the technical solution of the present invention clearer, the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0041] This embodiment provides a digital synchronous rectification control method for a CLLC converter. The application topology and control circuit of this method are as follows: Figure 1 As shown. The topology of the CLLC converter consists of a primary-side network, a secondary-side network, and a resonant cavity. The primary-side network is composed of primary-side switches S1-S4; the secondary-side network is composed of secondary-side switches S5-S8; and the resonant cavity is composed of the primary-side resonant inductor L. r1 Primary resonant capacitor C r1 Secondary resonant inductor L r2 Secondary resonant capacitor C r2 It consists of a high-frequency transformer. The control circuit includes an output voltage sampling circuit, an output current sampling circuit, a secondary resonant current sampling circuit, a DSP controller, a primary-side drive circuit, and a secondary-side drive circuit.

[0042] Specifically, such as Figure 2 As shown, a digital synchronous rectification control method for a CLLC converter in this embodiment includes the following steps:

[0043] Step 1: The ADC module of the DSP chip acquires the output signals of the output voltage sampling circuit and the output current sampling circuit in real time;

[0044] The output voltage sampling circuit and the output current sampling circuit convert the output voltage and output current into weak electrical signals of 0-3.3V through voltage sensors and current sensors, respectively. The ADC module collects these signals and converts the analog weak electrical signals into digital signals for the DSP chip to process and calculate.

[0045] Step 2: Process the signal acquired by the ADC module, calculate the output power, and determine whether to enable synchronous rectification;

[0046] Before calculating the signal acquired by the ADC module, the signal is first filtered, then the voltage and current values ​​are restored, and then the real-time output power is calculated using the power calculation formula (1).

[0047] P o =U o I o (1)

[0048] Among them, U o It is the output voltage, I o It is the output current, P o It refers to output power.

[0049] Synchronous rectification enable is used to determine hysteresis settings to prevent system oscillation, such as... Figure 3 As shown, when the output power is less than the power threshold P th1 At that time, the synchronous rectification enable signal SR EN A value of 0 indicates that synchronous rectification is not enabled, and secondary-side switches S5-S8 do not operate; when the output power is greater than the power threshold P... th2 At that time, the synchronous rectification enable signal SR EN A value of 1 indicates that synchronous rectification is enabled, and the secondary-side switches S5-S8 operate, where the power threshold P... th1 Less than the power threshold P th2 .

[0050] Step 3: Determine the circuit operating state, including state A and state B, based on the switching frequency of the CLLC converter;

[0051] When the switching frequency f of the CLLC converter s Less than or equal to the resonant frequency f r When, it indicates that the operation is in state A;

[0052] When the switching frequency f of the CLLC converter s Greater than the resonant frequency f r When this is the case, it indicates that the system is in state B.

[0053] Where the resonant frequency f r Obtained according to formula (2);

[0054]

[0055] Among them, L r1 It is the primary-side resonant inductance, C r1 It is the primary resonant capacitor.

[0056] Step 4: Based on the operating state of the CLLC converter, select the synchronous rectification signal turn-on delay time to obtain the turn-on time of the synchronous rectification signal, such as... Figure 4 As shown, f1 is the first switching frequency threshold, f2 is the second switching frequency threshold, and f... max It is the maximum switching frequency;

[0057] When the CLLC converter operates in state A, the turn-on delay time is fixed at t. o ;

[0058] When the CLLC converter operates in state B, the turn-on delay time varies with the switching frequency in time t.o Based on this, a step-like increment is made, and the delay time reaches its maximum t when the switching frequency is at its maximum. n , i.e. t n It is the maximum delay time, where n represents the number of steps.

[0059] Among them, t o It is set according to the circuit characteristics, t n It is set based on dead time, circuit characteristics, and the worst operating conditions.

[0060] In this embodiment, the resonant frequency is 120kHz and the switching frequency range is 70-200kHz. When the CLLC converter is working in state B, that is, the switching frequency is 120-200kHz, in order to ensure that the synchronous rectification time is as long as possible, a delay is made every 10kHz, as shown in formula (3).

[0061]

[0062] Where t is the activation delay time, t1 is the first delay time, t2 is the second delay time, and t... n That is the maximum delay time.

[0063] Step 5: The high-speed comparator module of the DSP chip processes the output signal of the secondary resonant current sampling circuit and compares it with the threshold to obtain the turn-off time of the synchronous rectified signal; the high-speed comparator module includes high-speed comparator CMPSS_H and high-speed comparator CMPSS_L;

[0064] The high-speed comparator CMPSS_H performs a comparison and judgment within the positive half-cycle. When V I_Sec <V th1 When the high-speed comparator outputs 0, it indicates that a turn-off signal has been given to the corresponding switch in the secondary network.

[0065] The high-speed comparator CMPSS_L performs a comparison and judgment during the negative half-cycle. When V I_Sec >V th2 When the high-speed comparator outputs 0, it indicates that a turn-off signal has been given to the corresponding switch in the secondary network.

[0066] Among them, V I_Sec It is the output signal of the secondary resonant current sampling circuit, V th1 and V th2 These are the two threshold values ​​corresponding to when the secondary resonant current is close to 0.

[0067] Step 6: Based on the turn-on and turn-off times of the synchronous rectification signal, the DSP chip sends a synchronous rectification control signal, which controls the on / off state of the secondary-side switching transistors S5-S8 through the secondary-side drive circuit.

[0068] like Figure 5The diagram shown is a synchronous rectification control drive timing diagram. The drive signals for secondary side switches S5 and S7 are the same, and the drive signals for S6 and S8 are the same. They have a delay relative to the primary side switches when they are turned on.

[0069] Figure 6 This is a graph showing the experimental results of this embodiment, wherein, Figure 6 (a) is the experimental result diagram of the CLLC converter operating in state A. Figure 6 (b) is the experimental result graph showing the operation in state B. From... Figure 6 As can be seen, the secondary-side switch turns on with a delay relative to the primary-side switch, and turns off somewhat earlier. This earlier turn-off is due to the threshold V... th1 and V th2 These correspond to values ​​slightly greater than 0 and slightly less than 0 for the resonant current, respectively, to avoid inaccurate current zero-crossing sampling caused by interference. This invention can effectively achieve ZVS turn-on of the synchronous rectifier switch and prevent secondary-side energy backflow.

Claims

1. A digital synchronous rectification control method for a CLLC converter, implemented through a CLLC converter and a control circuit; the CLLC converter consists of a primary-side network, a secondary-side network, and a resonant cavity; the control circuit includes an output voltage sampling circuit, an output current sampling circuit, a secondary-side resonant current sampling circuit, a DSP controller, a primary-side drive circuit, and a secondary-side drive circuit, characterized in that, Includes the following steps: Step 1: The ADC module of the DSP chip acquires the output signals of the output voltage sampling circuit and the output current sampling circuit in real time; Step 2: Process the signal acquired by the ADC module, calculate the output power, and determine whether to enable synchronous rectification; Step 3: Determine the circuit operating state based on the switching frequency of the CLLC converter. The circuit operating state includes state A and state B. When the switching frequency of the CLLC converter Less than or equal to the resonant frequency When, it indicates that the operation is in state A; When the switching frequency of the CLLC converter Greater than the resonant frequency When this is the case, it indicates that the system is in state B. Step 4: Based on the operating status of the CLLC converter, select the synchronous rectification signal turn-on delay time to obtain the turn-on time of the synchronous rectification signal; Step 5: The high-speed comparator module of the DSP chip processes the output signal of the secondary resonant current sampling circuit, compares it with the threshold, and obtains the turn-off time of the synchronous rectified signal. The high-speed comparator module's processing includes: The high-speed comparator in the high-speed comparator module samples the output signal of the secondary resonant current sampling circuit. The comparison includes handling the shutdown time for both positive and negative half cycles; the high-speed comparator module includes high-speed comparator CMPSS_H and high-speed comparator CMPSS_L. The high-speed comparator CMPSS_H performs a comparison and judgment within the positive half-cycle. When the high-speed comparator outputs 0, it indicates that a turn-off signal has been given to the corresponding switch in the secondary network. The high-speed comparator CMPSS_L performs a comparison and judgment during the negative half-cycle. When the high-speed comparator outputs 0, it indicates that a turn-off signal has been given to the corresponding switch in the secondary network. in, It is the output signal of the secondary resonant current sampling circuit. and These are the two threshold values ​​corresponding to when the secondary resonant current is close to 0; Step 6: Based on the turn-on and turn-off times of the synchronous rectification signal, the DSP chip sends a synchronous rectification control signal, which controls the on / off state of the secondary-side switching transistor through the secondary-side drive circuit.

2. The digital synchronous rectification control method for a CLLC converter according to claim 1, characterized in that, The output voltage sampling circuit and the output current sampling circuit convert the output voltage and output current into weak electrical signals of 0-3.3V through voltage sensors and current sensors, respectively.

3. The digital synchronous rectification control method for a CLLC converter according to claim 1, characterized in that, The ADC module of the DSP chip collects the output signals of the output voltage sampling circuit and the output current sampling circuit, converting the analog weak electrical signals into digital signals for the DSP chip to process and calculate.

4. The digital synchronous rectification control method for a CLLC converter according to claim 1, characterized in that, Before calculating the signal acquired by the ADC module, the signal is first filtered, then the voltage and current values ​​are restored, and finally the real-time output power is calculated using the power calculation formula.

5. The digital synchronous rectification control method for a CLLC converter according to claim 1, characterized in that, Step 2, determining whether to enable synchronous rectification, includes: When the output power is less than the power threshold At that time, synchronous rectification enable signal A value of 0 indicates that synchronous rectification is not enabled and the secondary-side switching transistor does not operate. When the output power is greater than the power threshold At that time, synchronous rectification enable signal A value of 1 indicates that synchronous rectification is enabled and the secondary-side switch is activated, where the power threshold is... Less than the power threshold .

6. The digital synchronous rectification control method for a CLLC converter according to claim 1, characterized in that, In step 4, selecting the synchronous rectification signal activation delay time includes: The turn-on delay is a delay based on the turn-on time of the corresponding primary-side switch tube. When the CLLC converter operates in state A, the turn-on delay time is fixed at... ; When the CLLC converter operates in state B, the turn-on delay time depends on the switching frequency. Based on this, a stepped increase is made, and the delay time reaches its maximum when the switching frequency is at its maximum. ,Right now It is the maximum delay time, where, This indicates the number of steps.

7. The digital synchronous rectification control method for a CLLC converter according to claim 6, characterized in that, It is set according to the circuit characteristics. It is set based on dead time, circuit characteristics, and the worst operating conditions.

Images