Display panel and display device

Abstract

The application discloses a display panel and a display device, the display panel comprising a pixel circuit and a light emitting element, the pixel circuit comprising: a driving transistor, a gate of which is electrically connected with a first node; a first transistor, which is connected in series between the driving transistor and a data line; a second transistor, which is electrically connected between the driving transistor and the light emitting element; a first capacitor, a first plate of which is electrically connected with the first node, and a second plate of which is electrically connected with a first power voltage line; and the first node is located on a side of the second plate away from a substrate. One driving period of the display panel comprises a display scanning area and a front and rear corridor area; a plurality of pixel circuits are arranged in M rows and N columns, N is greater than or equal to 2, and M is greater than or equal to 2; the data line transmits a data signal, at least one data signal in the display scanning area comprises a first level V1, and the data signal in the front and rear corridor area comprises a second level V2, V1 is not equal to V2, and the application improves the problem of the influence of low-frequency Long V mode flicker on the display effect of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to a display panel and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess characteristics such as self-illumination, fast response, wide color gamut, wide viewing angle, and high brightness, enabling the fabrication of thin and flexible display devices, thus gradually becoming a key research focus in the field of display technology. OLEDs require current to drive them. In display applications, driving transistors in the pixel circuits provide driving current to the OLEDs to make them emit light, and a stable driving current is needed to ensure display performance. AMOLED (Active-matrix organic light-emitting diode) display panels offer even wider viewing angles, higher refresh rates, and thinner dimensions, thus becoming a research hotspot in the display technology field.

[0003] The pixels in an AMOLED display panel include a pixel driving circuit. The driving transistor in the pixel driving circuit can generate a driving current, and the light-emitting element emits light in response to the driving current. The driving current generated by the driving transistor is related to the potential of the gate of the driving transistor.

[0004] AMOLED display panels are widely used in various display scenarios. Due to power consumption requirements, some display scenarios with low image quality requirements will use low-frequency display mode to increase battery life. However, AMOLED low-frequency mode has flicker, which can damage eyesight if used for a long time.

[0005] Therefore, there is an urgent need to provide a display panel that can improve the flickering problem of AMOLED in low-frequency mode. Summary of the Invention

[0006] In view of this, the present invention provides a display panel and a display device to improve the problem of flickering in low-frequency mode of the display panel.

[0007] On one hand, the present invention provides a display panel, the display panel including a substrate, a plurality of pixel circuits located on one side of the substrate, and light-emitting elements electrically connected to the pixel circuits:

[0008] The pixel circuit includes:

[0009] A driving transistor, the gate of which is electrically connected to the first node and provides driving current to the light-emitting element;

[0010] The first transistor is connected in series between the driving transistor and the data line, and transmits the data signal to the driving transistor in response to the first scan signal;

[0011] The second transistor is electrically connected between the driving transistor and the light-emitting element, and transmits driving current to the light-emitting element in response to the light-emitting control signal;

[0012] The first capacitor has its first plate electrically connected to the first node and its second plate electrically connected to the first power supply voltage line; the first node is located on the side of the second plate away from the substrate.

[0013] One drive cycle of the display panel includes the display scanning area and the front and rear corridor areas;

[0014] Multiple pixel circuits are arranged in M ​​rows and N columns, where N≥2 and M≥2;

[0015] The data line transmits data signals. In the display scanning area, at least one data signal includes a first level V1, and in the front and rear corridor areas, the data signal includes a second level V2, wherein V1 ≠ V2.

[0016] On the other hand, the present invention also provides a display device including the above-described display panel.

[0017] Compared with the prior art, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0018] In the display panel of the present invention, the pixel circuit includes: a driving transistor, the gate of which is electrically connected to a first node and provides driving current to a light-emitting element; a first transistor connected in series between the driving transistor and a data line, which transmits a data signal to the driving transistor in response to a first scan signal; a second transistor electrically connected between the driving transistor and a light-emitting element, which transmits driving current to the light-emitting element in response to a light-emitting control signal; a first capacitor, the first plate of which is electrically connected to the first node, and the second plate of which is electrically connected to a first power supply voltage line; the first node is located on the side of the second plate away from the substrate; one driving cycle of the display panel includes a display scan area. The system includes front and rear corridor areas; multiple pixel circuits are arranged in M ​​rows and N columns, where N≥2 and M≥2; data lines transmit data signals. In the display scanning area, at least one data signal includes a first level V1, and in the front and rear corridor areas, the data signal includes a second level V2, where V1≠V2. In the front and rear corridor areas, the data lines will be coupled with the first node. The second level V2 of the data signal will affect the potential of the first node, causing the gate-source voltage Vgs of the driving transistor to decrease. At this time, the opening amplitude of the driving transistor decreases, the driving current generated decreases, and thus the brightness of the light-emitting element decreases. This superimposed leakage current effect interferes with the effect of leakage current on flicker, thereby improving the flicker problem.

[0019] Of course, any product implementing this invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0020] Other features and advantages of the invention will become clear from the following detailed description of exemplary embodiments of the invention with reference to the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the invention and, together with their description, serve to explain the principles of the invention.

[0022] Figure 1 This is a schematic diagram of the pixel circuit structure of a display panel in related technologies;

[0023] Figure 2 It is a brightness variation diagram of multiple driving cycles in related technologies;

[0024] Figure 3 This invention provides a display panel;

[0025] Figure 4 yes Figure 3 A schematic diagram of the middle pixel circuit;

[0026] Figure 5 This is a layout diagram of a pixel circuit provided by the present invention;

[0027] Figure 6 This is a driving timing diagram of a display panel provided by the present invention;

[0028] Figure 7 This is a driving timing diagram for another display panel provided by the present invention;

[0029] Figure 8 This is a schematic diagram of another pixel circuit provided by the present invention;

[0030] Figure 9 This is a schematic diagram of the pixel circuit during the reset phase;

[0031] Figure 10 This is a schematic diagram of the pixel circuit during the data signal writing stage;

[0032] Figure 11 This is a schematic diagram of the pixel circuit during the light-emitting stage;

[0033] Figure 12 This invention provides a timing diagram of the working cycle of a pixel circuit.

[0034] Figure 13 This is another working cycle timing diagram of a pixel circuit provided by the present invention;

[0035] Figure 14 This is another working cycle timing diagram of a pixel circuit provided by the present invention;

[0036] Figure 15 This is another working cycle timing diagram of a pixel circuit provided by the present invention;

[0037] Figure 16 This is a schematic diagram of the planar structure of the display device provided in an embodiment of the present invention. Detailed Implementation

[0038] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the invention.

[0039] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0040] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0041] In all the examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0042] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0043] In view of the flickering problem of display panels in related technologies when displaying at low frequencies, the inventors conducted the following research on the display panels of related technologies, referring to... Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the pixel circuit structure of a display panel in related technologies. Figure 2 This is a graph showing the brightness change of a display panel over one driving cycle, as described in related technologies. Figure 1The pixel driving circuit 000 includes: a first transistor T1', whose control terminal is electrically connected to the light emission signal input terminal, its first terminal is electrically connected to the first power supply signal terminal PVDD, and its second terminal is electrically connected to the first terminal of the driving transistor T3'; a second transistor T2', whose control terminal is electrically connected to the second scan signal input terminal S2, its first terminal is electrically connected to the data signal input terminal Vdata, and its second terminal is electrically connected to the first terminal of the driving transistor T3'; a driving transistor T3', whose control terminal is electrically connected to the second terminal of the fourth transistor T5', and its first terminal is electrically connected to the second terminal of the first transistor T1' and the second terminal of the second transistor T2'; a third transistor T4', whose control terminal is electrically connected to the second scan signal input terminal S2, its first terminal is electrically connected to the second terminal of the fourth transistor T5' and the second plate of the storage capacitor Cst', and its second terminal is electrically connected to the second terminal of the driving transistor T3' and the first terminal of the fifth transistor T6'; and a fourth transistor T5', whose control terminal is electrically connected to the first scan signal input terminal S2. Terminal S1 is electrically connected, with its first terminal electrically connected to the reference voltage signal input terminal Vref, and its second terminal electrically connected to the control terminal of the driving transistor T3'; the fifth transistor T6' has its control terminal electrically connected to the light emission signal input terminal Emit, its first terminal electrically connected to the second terminal of the driving transistor T3' and the second terminal of the third transistor T4', and its second terminal electrically connected to the anode of the light emission element O'; the sixth transistor T7' has its control terminal electrically connected to the second scan signal input terminal, its first terminal electrically connected to the reference voltage signal input terminal vref, and its second terminal electrically connected to the first terminal of the light emission element O'; the light emission element O' has its first terminal electrically connected to the second terminal of the fifth transistor T6' and the second terminal of the sixth transistor T7', and its second terminal electrically connected to the second power supply signal terminal PVEE; the storage capacitor Cst' has its first terminal electrically connected to the first power supply signal terminal PVDD, and its second terminal electrically connected to the control terminal of the driving transistor T3', the first terminal of the third transistor T4', and the second terminal of the fourth transistor T5'. Both the third transistor T4' and the fourth transistor T5' are connected to the control terminal of the driving transistor T3'. During the light-emitting phase of one driving cycle, due to the voltage difference between the first and second terminals of the third transistor T4' and the fourth transistor T5', leakage current is generated in the third transistor T4' and the fourth transistor T5' as time increases. This causes the potential of the control terminal of the driving transistor T3', which is electrically connected to the third transistor T4' and the fourth transistor T5', to become unstable. The voltage difference ΔV between the gate and source of the driving transistor T3' decreases, resulting in a reduced turn-on degree of the driving transistor T3' and a decrease in the driving current. Therefore, the brightness of the light-emitting element decreases during the light-emitting phase. Figure 2 As shown, when the display panel uses pulse width modulation to adjust the brightness and displays a frame, there are multiple light-emitting stages. The brightness of these multiple light-emitting stages will decrease in a regular manner, causing screen flickering.

[0044] In view of this, the present invention provides a display panel and a display device to improve the problem of screen flickering on the display panel. Specific embodiments of the display panel will be described in detail below.

[0045] Reference Figure 3 , Figure 4 , Figure 5 and Figure 6 , Figure 3 This invention provides a display panel. Figure 4 yes Figure 3 A schematic diagram of the structure of the mid-pixel circuit. Figure 5 This is a layout diagram of a pixel circuit provided by the present invention. Figure 6 This is a driving timing diagram of a display panel provided by the present invention, such as... Figure 3 As shown, the display panel 100 of this embodiment includes a substrate 01, a plurality of pixel circuits 10 located on one side of the substrate 01, and light-emitting elements 20 electrically connected to the pixel circuits 10.

[0046] Combination Figure 4 and Figure 5 The pixel circuit 10 includes a driving transistor T3, the gate of which is electrically connected to the first node N1 and provides driving current to the light-emitting element 20.

[0047] The first transistor T1 is connected in series between the driving transistor T3 and the data line 6, and in response to the first scan signal S2, it transmits the data signal Vdata transmitted by the data line 6 to the driving transistor T3.

[0048] The second transistor T2 is electrically connected between the driving transistor T3 and the light-emitting element 20, and transmits driving current to the light-emitting element 20 in response to the light-emitting control signal EM.

[0049] The first capacitor Cst has its first plate electrically connected to the first node N1, and its second plate electrically connected to the first power supply voltage line 5; the first node N1 is located on the side of the second plate away from the substrate.

[0050] One drive cycle K00 of the display panel 100 includes a display scanning area K01 and a front and rear corridor area K02;

[0051] Multiple pixel circuits 10 are arranged in M ​​rows and N columns, where N≥2 and M≥2;

[0052] Data line 6 transmits data signal Vdata. In the display scanning area K01, at least one data signal Vdata includes a first level V1. In the front and rear corridor areas K02, the data signal Vdata includes a second level V2, wherein V1 ≠ V2.

[0053] Specifically, the display panel 100 provided in this embodiment can be an organic light-emitting display panel 100, or it can be any other display panel 100 that provides a driving current to the light-emitting element 20 by controlling the driving transistor T3 in the pixel circuit 10. The light-emitting element 20 in this embodiment can be an organic light-emitting diode, or in some other optional embodiments, the light-emitting element 20 can also be a micro light-emitting diode or a sub-millimeter light-emitting diode. This embodiment does not limit this. This embodiment takes an organic light-emitting diode display panel 100 as an example for illustration.

[0054] The display panel 100 of this embodiment includes multiple pixel circuit rows, and each pixel circuit row includes multiple pixel circuits 10. Optionally, the multiple pixel circuits 10 in this embodiment can be arranged in an array, that is, N pixel circuits 10 are arranged along the first direction X to form a pixel circuit row, M pixel circuit rows are arranged along the second direction Y, and multiple pixel circuits 10 are arranged along the second direction Y to form a pixel circuit column; wherein the first direction X and the second direction Y can be understood as intersecting or perpendicular to each other in a direction parallel to the plane where the display panel 100 is located. Alternatively, in some other optional embodiments, the light-emitting elements of the multiple sub-pixels 00 in the display panel 100 can also be arranged in other ways, such as a diamond arrangement, where the pixel circuits 10 are arranged in rows and the corresponding light-emitting elements 20 are arranged in two rows, with a misalignment between the pixel circuits 10 and the light-emitting elements 20. This embodiment does not limit this. Figure 3 This example only illustrates the arrangement of multiple sub-pixels 00. During operation, the display panel 100 scans the pixel circuit rows one by one.

[0055] The display panel 100 also includes a light-emitting element 20 electrically connected to the pixel circuit 10, which controls the light-emitting element 20 to emit light. Since the light-emitting element 20 in the organic light-emitting diode display panel 100 can generally be an organic light-emitting diode, and organic light-emitting diodes are current-driven devices, a corresponding pixel circuit 10 needs to be set to provide driving current to the light-emitting element 20 so that the light-emitting element 20 can emit light.

[0056] Figure 3 The diagram shows the first scan signal line 1, the second scan signal line 2, the reset signal line 3, the first power supply voltage line 5, and the light emission control signal line 4, combined with... Figures 3 to 6 The first scan signal line 1 is used to transmit the first scan signal S2. The first transistor T1 is turned on in response to the valid signal of the first scan signal S2. The second scan signal line 2 is used to transmit the second scan signal S1. The reset signal line 3 transmits the reset signal VREF. The light emission control signal line 4 transmits the light emission control signal EM. This is only for illustrative purposes. Figure 3The diagram also shows a first gate driving circuit 301, a second gate driving circuit 302, and a third gate driving circuit 303. The driver chip IC sends a start signal STV_S1 (not shown) to the first stage of the first gate driving circuit 301. The first gate driving circuit 301 can provide a second scan signal S1 to the pixel circuit 10 stage by stage. The driver chip IC sends a start signal STV_S2 (not shown) to the first stage of the second gate driving circuit 302. The second gate driving circuit 302 can provide a first scan signal S2 to the pixel circuit 10 stage by stage. The driver chip IC sends a start signal STV_E (not shown) to the first stage of the third gate driving circuit 303. The third gate driving circuit 303 can provide a light emission control signal EM to the pixel circuit 10 stage by stage. The first power supply voltage line 5, which provides the first power supply voltage VPvdd, the second power supply voltage VPvee, and the reset signal VREF to the pixel circuit, can also be provided by the driver chip IC.

[0057] Figure 4 and Figure 5 The pixel circuit 10 also shows a third transistor T4, a fourth transistor T5, a fifth transistor T6, and a sixth transistor T7. When the third transistor T4 is turned on, it resets the gate of the driving transistor T3. When the fourth transistor T5 and the first transistor T1 are turned on, they perform threshold compensation on the driving transistor T3. The fifth transistor T6 is connected in series between the reset signal terminal and the anode of the light-emitting element 20 to reset the anode of the light-emitting element 20. The sixth transistor T7 is connected between the first power supply voltage terminal PVDD and the second node N2 to control whether the first power supply voltage terminal PVDD and the second node N2 are connected.

[0058] Figure 4This illustration uses only P-type transistors (T1, T2, and T3) as an example; however, they can also be N-type transistors. When T1 is a P-type transistor, it conducts when the effective signal of the first scan signal S2 is low; when T1 is an N-type transistor, it conducts when the effective signal of the first scan signal S2 is high. Similarly, when T2 is a P-type transistor, it conducts when the effective signal of the second scan signal S1 is low; when T2 is an N-type transistor, it conducts when the effective signal of the second scan signal S1 is high. Taking a P-type transistor as an example, when the third transistor T4 is turned on, a reset signal is transmitted to the gate of the driving transistor T3. This reset signal can be at a low potential to reset the gate of the driving transistor T3. When the driving transistor T3 is an N-type transistor, when the third transistor T4 is turned on, a reset signal is transmitted to the gate of the driving transistor T3. This reset signal can be at a high potential.

[0059] like Figure 3 As shown, multiple pixel circuits 10 are arranged in M ​​rows and N columns, where N≥2 and M≥2, combined with Figure 6A driving cycle K00 of the display panel of the present invention includes a display scanning area K01 and front and rear corridor areas K02. Within the display scanning area K01, the second gate driving circuit 302 sequentially transmits corresponding first scanning signals S2 to multiple first scanning lines, scanning each row of pixel circuits 10 line by line. That is, the first scanning signals S2 are written to the pixel circuits 10 line by line, specifically to the first to Mth rows of pixel circuits 10. Optionally, the display scanning area K01 begins with the first scanning signal S2 being written to the first row of pixel circuits 10 and ends with the first row of pixel circuits 10 being written to. In other words, for a single frame of display, the moment when the first scan signal S2 received by the first row pixel circuit 10 controls the first transistor T1 to turn on and begin transmitting the data signal Vdata to the driving transistor T3 is the start time of the display scan area K01. That is, the moment when the first scan signal S2 corresponding to the first row pixel circuit 10 changes from an enabled level to an enabled level is the start time of the display scan area K01. The moment when the first scan signal S2 received by the Nth row pixel circuit 10 changes from an enabled level to an enabled level is the end time of the display scan area K01. The front and back corridor areas K02 of the current frame are adjacent to the display scan area K01. The time between the writing of the data signal to the Mth row pixel circuit 10 and the writing of the first scan signal S2 of the next frame to the 1st row pixel circuit 10 is the time of the front and back corridor areas K02. In other words, the moment when the first scan signal S2 received by the M-th row pixel circuit 10 in a display frame changes from an enabled level to an disabled level is the start time of the front and rear corridor area K02, and the moment when the first scan signal S2 received by the first row pixel circuit 10 in the next display frame changes from an disabled level to an enabled level is the end time of the front and rear corridor area K02.

[0060] Typically, the display panel 100 can display at either a high or low frequency. Frequency adjustment for the same display device is usually achieved using a Long V method. For example, the display panel 100 may have two refresh rates: 120Hz and 60Hz. Long V means that the refresh time for each frame is the same for both 60Hz and 120Hz. However, when the display panel operates at a 60Hz refresh rate, a blank frame is included after each frame, resulting in an actual display effect equivalent to 60Hz. For the front and rear corridor areas K02, also known as the Porch area or Blank area, this is the remaining time after all line scans are completed within a frame. During this time, the driver chip performs internal configuration to prepare the signals required for the next frame. For example, if the display is performed at a refresh rate of 120Hz and 60Hz, at a frequency of 120Hz, the duration of the display area in the driving cycle K00 of each frame is M1 and the duration of the Porch area is N1, where N1 is a preset value. At a frequency of 60Hz, the duration of the display area in the driving cycle K00 of each frame is M2 and the duration of the Porch area is N2. Therefore, within 1 second, the refresh rate of 120Hz = 1 / (M1+N1) and the refresh rate of 60Hz = 1 / (M2+N2), where N2 = M1+N1. In related technologies, the duration of the front and rear corridor regions K02 is relatively short. In existing technologies, since M1 is small, it typically occupies only 1 / 100 of the time in a frame, so M1 can be ignored. Ignoring M1, the duration N2 of the Porch region at a refresh rate of 60Hz is approximately equal to M1. Understandably, in related technologies, leakage current occurs in the third transistor T4 and the fourth transistor T5 connected to the first node N1. This causes instability in the gate potential of the driving transistor T3, reduces the gate-source voltage difference of the driving transistor T3, and decreases the driving current, resulting in flickering of the brightness of the light-emitting element 20.

[0061] In this embodiment, the data line 6 extends along the second direction Y. In related technologies, the data signal transmitted by the data line is only written to the gate of the driving transistor T3 during the scanning phase. In this invention, the data line 6 transmits data signals. Within one driving cycle of the display panel, at least one data signal includes a first level V1. In the display scanning area K01, the first transistor T1 is turned on, transmitting the first level V1 of the data signal transmitted by the data line 6 to the driving transistor T3 for data writing and threshold capture, N1 = Vdata - |Vth|. Moreover, in the front and rear corridor areas K02, the data signal also includes a second level V2, V2 ≠ V1. Optionally, in the scanning display area K01, after at least one pixel circuit 10 in the Mth row of pixel circuits receives the enable level of the first scanning signal S2, it controls the first transistor T1 to turn on, transmitting the data signal transmitted on the data line 6 connected to the pixel circuit 10 to the driving transistor T3. The pixel circuit 10 performs data signal writing and threshold compensation operations. At this time, the data signal level transmitted to the driving transistor T3 can be the first level V1. In the pixel circuit layout design of this application, there is an electric field between the data line 6 and the first node N1. When the signal transmitted on the data line 6 changes, the potential of the first node N1 will be affected by the coupling effect, which in turn will affect the gate voltage of the driving transistor T3. For example, when the data signal transmitted on the data line 6 jumps from the first level V1 to the second level V2, it will affect the potential of the first node N1, causing the gate-source voltage Vgs of the driving transistor T3 to change, changing the turn-on amplitude of the driving transistor T3, and further affecting the driving current generated by the driving transistor T3. This reduces the initial luminous brightness of the light-emitting element 20 in the front and rear corridor regions K02. With the initial luminous brightness reduced, the brightness change amplitude of the light-emitting element at the start and end of the front and rear corridor regions K02 will be smaller than that when the initial brightness is high, thus balancing the brightness difference and interfering with the effect of leakage current on flicker, thereby improving the flicker problem.

[0062] In some alternative embodiments, reference continues to be made to... Figure 6 The total duration of the scanned area K01 is t1, and the total duration of the front and rear corridor areas K02 is t2, where t1 < t2.

[0063] In related technologies, when the display panel displays at a low frequency, if the total duration of the display scanning area K01 is shortened and the total duration of the front and rear corridor areas K02 is extended, then as the total duration of the front and rear corridor areas K02 increases, the degree of leakage current will also increase, and the brightness difference of the front and rear corridor areas K02 (the stage of maintaining light emission) will be greater, and the flickering will be more obvious.

[0064] In this invention, when the display panel displays at a low frequency, the total duration t2 of the front and rear corridor areas K02 is greater than the duration t1 of the display scanning area K01. This means the duration of the front and rear corridor areas K02 is extended, and the light-emitting element 20 maintains its light emission for a longer period. Because the signal transitions on the data lines in the front and rear corridor areas K02 couple to the first node N1, when the data signal transitions from the first level V1 to the second level V2, it affects the potential of the first node N1, thereby reducing the brightness of the light-emitting element 20 in the initial stage of the front and rear corridor areas K02 (the stage of maintaining light emission). The brightness difference is reduced. This invention utilizes the transition of data signals between the display scanning area K01 and the front and rear corridor areas K02. When switching from the display scanning area K01 to the front and rear corridor areas K02, the initial luminous brightness of the light-emitting element 20 in the front and rear corridor areas K02 is reduced. With the initial luminous brightness reduced, compared to the prior art where the initial brightness of the front and rear corridor areas K02 is high and the brightness at the end is low, resulting in a large brightness variation, this invention reduces the brightness variation of the light-emitting element at the beginning and end of the front and rear corridor areas K02, thereby balancing the brightness difference. This reduction in brightness variation can improve flicker. Of course, the longer the front and rear corridor areas K02 time, the better the effect on flicker.

[0065] In some alternative embodiments, reference continues to be made to... Figure 6 t1:t2=1 / 3, or t1:t2=1 / 4; or t1:t2=1 / 5.

[0066] Understandable Figure 6 The diagram only schematically shows the case where t1:t2=1 / 3. Of course, t1:t2=1 / 4 and t1:t2=1 / 5 are also possible. In this case, the total duration t2 of the front and rear corridor areas K02 is much greater than the duration t1 of the display scanning area K01, which means that the data writing time is shortened and the duration of the front and rear corridor areas K02 is extended, which means that the time for the light-emitting element 20 to keep emitting light is extended.

[0067] As mentioned above, in the related technologies, when the display panel displays at a low frequency, if the total duration of the display scanning area K01 is shortened and the total duration of the front and rear corridor areas K02 is extended, then as the total duration of the front and rear corridor areas K02 increases, the degree of leakage current will also increase, and the brightness difference of the front and rear corridor areas K02 (the stage of maintaining light emission) will be greater, and the flickering will be more obvious.

[0068] In this invention, t1:t2 = 1 / 3, or t1:t2 = 1 / 4, or t1:t2 = 1 / 5, which shortens the data writing time and extends the time of the front and rear corridor areas K02. That is, the time for the light-emitting element 20 to keep emitting light is extended. Although there will still be leakage current, the coupling effect of the data signal in the front and rear corridor areas K02 on the first node N1, the second level V2 of the data signal will affect the potential of the first node N1. This invention utilizes the jump of the data signal between the display scanning area K01 and the front and rear corridor areas K02. When the display scanning area K01 switches to the front and rear corridor areas K02, the initial luminous brightness of the light-emitting element 20 in the front and rear corridor areas K02 is reduced. With the initial luminous brightness reduced, the brightness of the front and rear corridor areas K02 is higher at the beginning and lower at the end compared to the prior art. The brightness change of the light-emitting element between the beginning and end of the front and rear corridor areas K02 is larger, which may be recognized by the user and affect the user experience. In this invention, the brightness variation of the light-emitting element in the front and rear corridor regions K02 is reduced at the beginning and end. The reduction in brightness variation can improve flicker. Of course, the longer the front and rear corridor regions K02 are, the more serious the leakage current of the driving transistor gate in the prior art becomes. The greater the difference in brightness variation of the light-emitting element 20 in the front and rear corridor regions K02 at the beginning and end, the more obvious the flicker becomes. In this invention, since the initial light emission brightness of the light-emitting element 20 in the front and rear corridor regions K02 is reduced, the brightness variation of the light-emitting element 20 in the front and rear corridor regions K02 at the beginning and end is smaller, the brightness difference is smaller, and the effect of improving flicker is more obvious.

[0069] In some alternative embodiments, reference continues to be made to... Figures 3 to 5 and reference Figure 7 , Figure 7 This is a driving timing diagram of another display panel provided by the present invention. The display panel 100 includes M rows of pixel circuits 10 arranged along the first direction X; the first scan signal S2 includes a valid signal and an invalid signal. When the first scan signal S2 is a valid signal, the first transistor T1 is turned on.

[0070] The display panel 100 includes a first driving cycle K001 and a second driving cycle K002 adjacent to the first driving cycle K001;

[0071] The start time of the display scan area K01 is the start time of the effective signal of the first scan signal S2 corresponding to the first row pixel circuit 10 in the first driving cycle K001, and the end time of the display scan area K01 is the end time of the effective signal of the first scan signal S2 corresponding to the M row pixel circuit 10 in the first driving cycle K001.

[0072] The start time of the front and rear corridor areas K02 is the time when the effective signal of the first scan signal corresponding to the Mth row pixel circuit 10 in the first driving cycle K001 is cut off, and the cutoff time of the front and rear corridor areas K02 is the start time of the effective signal of the first scan signal S2 corresponding to the 1st row pixel circuit 10 in the second driving cycle K002.

[0073] like Figure 3 As shown, the display panel 100 includes M rows of pixel circuits 10 arranged along the first direction X. The specific number of M is not limited here; M can be a positive integer greater than or equal to 2. Combined with... Figure 4 and Figure 7 The first scan signal S2 includes a valid signal and an invalid signal. When the first scan signal S2 is a valid signal, the first transistor T1 is turned on. Figure 4 The first transistor T1 is a P-type transistor. When the first scan signal S2 is at a low potential, it is an effective signal, and the first transistor T1 is turned on, and the data signal (first level V1) is written to the second node N2. Of course, when the first transistor T1 is an N-type transistor, when the first scan signal S2 is at a high potential, it is an effective signal, the first transistor T1 is turned on, and the data signal (first level V1) is written to the second node N2.

[0074] Multiple pixel circuits 10 are arranged in M ​​rows and N columns, where N≥2 and M≥2. The number of rows and columns of pixel circuits 10 are not specifically limited here. One driving cycle K00 of the display panel 100 of the present invention includes a display scanning area K01 and a front and rear corridor area K02. In the display scanning area K01, the first scanning signal S2 scans each row of pixel circuits 10 row by row. The first scanning signal S2 writes to the pixel circuits 10 row by row, that is, it writes to the first to the Mth rows of pixel circuits 10. The display scanning area K01 starts with the first scanning signal S2 writing to the first row of pixel circuits 10 and ends with the first scanning signal S2 writing to the Mth row of pixel circuits 10. Then comes the front and rear corridor area K02 of the current frame. The time between the writing of the data signal to the Mth row of pixel circuits 10 and the writing of the first scanning signal S2 to the first row of pixel circuits 10 in the next frame is the front and rear corridor area K02.

[0075] The display panel 100 includes a first driving cycle K001 and a second driving cycle K002 adjacent to the first driving cycle K001. That is, when displaying two adjacent frames, the first frame is the first driving cycle K001 and the second frame is the second driving cycle K002. Of course, the first driving cycle K001 and the second driving cycle K002 still include the display scanning area K01 and the front and rear corridor areas K02, as mentioned above. Here, the front and rear corridor areas K02 refer to the light emission maintenance stage, which is the remaining time after all line scanning is completed within one frame. During this time, the driving chip performs internal configuration.

[0076] The start time of the display scan area K01 is the start time of the effective signal of the first scan signal S2 corresponding to the first row pixel circuit 10 in the first driving cycle K001, and the end time of the display scan area K01 is the end time of the effective signal of the first scan signal S2 corresponding to the M row pixel circuit 10 in the first driving cycle K001. Similarly, for the second driving cycle K002, the start time of the display scan area K01 is the start time of the effective signal of the first scan signal S2 corresponding to the first row pixel circuit 10 in the second driving cycle K002, and the end time of the display scan area K01 is the end time of the effective signal of the first scan signal S2 corresponding to the M row pixel circuit 10 in the first driving cycle K001.

[0077] The start time of the front and rear corridor areas K02 is the time when the effective signal of the first scan signal corresponding to the Mth row pixel circuit 10 in the first driving cycle K001 is cut off (e.g. Figure 7 The first pulse of S2(M) ends), and the cutoff time of the front and rear corridor areas K02 is the start time of the effective signal of the first scan signal S2 corresponding to the first row pixel circuit 10 in the second driving cycle K002 (e.g., Figure 7 (Start of the second pulse of S2(1)), during which the front and rear corridor areas K02 are illuminated, during which the first frame of the display panel 100 remains illuminated.

[0078] As mentioned above, in related technologies, leakage current occurs in the third transistor T4 and the fourth transistor T5 connected to the first node N1. This causes instability in the gate potential of the driving transistor T3, reduces the gate-source voltage difference of the driving transistor T3, and decreases the driving current, resulting in flickering of the brightness of the light-emitting element 20. In this invention, combined with... Figure 7 In the front and rear corridor areas K02, the data signal is at the second level V2. Because the data line 6 couples with the first node N1, it affects the potential of the first node N1, thereby reducing the initial brightness of the light-emitting element 20 in the front and rear corridor areas K02. As a result, the brightness difference between the front and rear corridor areas K02 is reduced, thus improving flicker.

[0079] In some alternative embodiments, reference continues to be made to... Figure 7 The duration of the scanned area K01 is P1, and the duration of the front and rear corridor areas K02 is P2, where P1 / (P1+P2)≤1 / 4.

[0080] In this embodiment, P1 / (P1+P2)≤1 / 4, which is equivalent to shortening the data writing time and extending the K02 time of the front and rear corridors. That is, the time for the light-emitting element 20 to maintain light emission is extended. Although there will still be leakage current, the coupling effect of the data signal to the first node N1 in the K02 of the front and rear corridors will affect the potential of the first node N1, thereby reducing the brightness of the light-emitting element 20 in the K02 of the front and rear corridors (the stage of maintaining light emission). As a result, the brightness difference between the K02 of the front and rear corridors (the stage of maintaining light emission) will be reduced, thereby improving flicker. Of course, the longer the K02 time of the front and rear corridors, the more obvious the coupling effect and leakage current effect will be, and the better the effect of interfering with the leakage current effect on the flicker.

[0081] In some alternative embodiments, combined with Figures 3 to 7 The display panel 100 includes M rows of pixel circuits 10 and M light-emitting control signal lines 4. The light-emitting control signal lines 4 are electrically connected to the gate of the second transistor T2 and transmit the light-emitting control signal EM, where N is a positive integer greater than 2.

[0082] Reference Figure 12 , Figure 12 This invention provides a working cycle timing diagram for a pixel circuit. The light emission control signal EM includes K valid pulses and K invalid pulses, with invalid pulses and valid pulses alternating. K is a positive integer greater than 2.

[0083] In one working cycle B00 of the M-row pixel circuit 10, there are a data writing stage D1 and a light-emitting holding stage D2. The data writing stage D1 includes the first pulse group, and the light-emitting holding stage D2 includes the second to the Kth pulse groups.

[0084] It should be noted that one working cycle B00 of the M-row pixel circuit 10 includes a data writing phase D1 and a light-emitting holding phase D2. The data writing phase D1 includes the first pulse group, and the light-emitting holding phase D2 includes the second to the Kth pulse groups. Optionally, the M-row pixel circuit 10 can be a pixel circuit row in the middle of the display panel, or it can be the last pixel circuit row of the display panel.

[0085] Combination Figure 3 , Figure 4 and Figure 5The light-emitting control signal line 4 is electrically connected to the gate of the second transistor T2. The light-emitting control signal EM is transmitted to the gate of the second transistor T2 through the light-emitting control signal line 4. The light-emitting control signal EM includes K valid pulses and K invalid pulses, which are arranged alternately. When the light-emitting control signal EM is a valid pulse, the second transistor T2 is turned on, and the driving current generated by the driving transistor T3 is transmitted to the light-emitting element 20 through the second transistor T2, and the light-emitting element 20 emits light. When the light-emitting control signal EM is an invalid pulse, the second transistor T2 is turned off, and the driving current generated by the driving transistor T3 cannot be transmitted to the light-emitting element 20 through the second transistor T2, and the light-emitting element 20 does not emit light.

[0086] Combination Figure 8 , Figure 9 , Figure 10 and Figure 11 Explain the working principle of a single pixel circuit. Figure 8 This is a schematic diagram of another pixel circuit provided by the present invention. Figure 9 This is a schematic diagram of the pixel circuit during the reset phase. Figure 10 This is a schematic diagram of the pixel circuit during the data signal writing stage. Figure 11 This is a schematic diagram of the pixel circuit during the light-emitting stage. Figure 8 The diagram also shows a fifth transistor T6 and a sixth transistor T7. The fifth transistor T6 is connected in series between the reset signal terminal and the anode of the light-emitting element 20 to reset the anode of the light-emitting element 20. The sixth transistor T7 is connected between the first power supply voltage terminal PVDD and the second node N2 to control whether the first power supply voltage terminal PVDD and the second node N2 are connected.

[0087] Specifically, one light-emitting cycle of pixel circuit 10 begins with the reset phase C1, referring to... Figure 9 The effective signal of the second scan signal S1 controls the third transistor T4 to turn on, and the reset signal VREF is written to the first node N1 to initialize the gate of the driving transistor T3; the effective signal of the second scan signal S1 controls the fifth transistor T6 to turn on, and the reset signal VREF is written to the anode of the light-emitting element 20 to reset the anode of the light-emitting element 20. Of course, during the reset phase C1, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T5, and the sixth transistor T7 are all turned off.

[0088] Following the reset phase C1 is the data signal writing phase C2, see below. Figure 10During the data signal writing phase C2, the second scan signal S1 transmitted to the gate of the third transistor T4 is invalid, and the third transistor T4 is turned off. Since the reset signal VREF was written to the first node N1 during the reset phase C1, the driving transistor T3 is turned on. The valid signal of the first scan signal S2 is transmitted to the gate of the first transistor T1, turning on the first transistor T1. The first voltage V1 of the data signal Vdata is written. The valid signal of the first scan signal S2 is transmitted to the gate of the fourth transistor T5, turning on the fourth transistor T5. Therefore, the data signal Vdata is written to the first node N1 via the first transistor T1, the driving transistor T3, and the fourth transistor T5. The voltage of the second node N2 is equal to the data signal, N2 = Vdata. The voltages of the first node N1 and the third node N3 are equal to the difference between the data signal and the threshold voltage of the driving transistor T3, N1 = N3 = Vdata - Vth. Of course, during the data signal writing phase C2, the second transistor T2, the third transistor T4, the fifth transistor T6, and the sixth transistor T7 are all turned off.

[0089] Following the data signal writing stage C2 is the light emission stage C3, as shown in the reference. Figure 11 The first capacitor Cst maintains the potential of the first node N1, driving transistor T3 to remain on, and the second transistor T2 and the sixth transistor T7 turn on in response to the effective signal of the light emission control signal EM. The current generated by the driving transistor T3 is transmitted to the light emission element 20, and the light emission element 20 emits light.

[0090] It is understood that the data writing stage D1 in this embodiment includes a pulse group, including an invalid pulse and a valid pulse. During the invalid pulse, the pixel circuit is in the reset stage C1 and the data signal writing stage C2 of the light emission cycle. During the valid pulse, the pixel circuit is in the light emission stage C3.

[0091] In this embodiment, during one working cycle B00 of the M-row pixel circuit 10, the data writing stage D1 includes the first pulse group, and the light-emitting holding stage D2 includes the second to the Kth pulse groups. Each pulse group includes one valid pulse and one invalid pulse. Optionally, the brightness of the display panel can be adjusted using PWM (Pulse Width Modulation). When PWM is applied, the data writing stage D1 and the light-emitting holding stage D2 have multiple pulse groups. When the display panel displays at a low frequency, the total light-emitting time of a frame can be controlled by repeatedly brightening and dimming the light-emitting element at a high frequency, thereby controlling the brightness of the image. It is understood that in this embodiment, the light-emitting holding stage D2 includes the second to the Kth pulse groups, thus forcing the light-emitting element 20 to blink multiple times. In this invention, the data signal Vdata couples to the voltage of the first node N1 during the light-holding phase D2, reducing the gate-source voltage Vgs of the driving transistor T3. At this time, the turn-on amplitude of the driving transistor T3 decreases, resulting in a decrease in the driving current, which in turn reduces the brightness of the light-emitting element 20. Meanwhile, the light-holding phase D2 of this invention includes the second to the Kth pulse groups, thus forcing the light-emitting element 20 to flash multiple times. Although there will be leakage current, the brightness of the light-emitting element 20 is reduced in the early stage of the light-holding phase D2. Therefore, the brightness is basically the same during multiple flashes, which is not easily detected by the human eye, and the flashing is not obvious.

[0092] In some alternative embodiments, reference continues to be made to... Figure 12 and reference Figure 13 and Figure 14 , Figure 13 This is another timing diagram of the working cycle of a pixel circuit provided by the present invention. Figure 14 This is another working cycle timing diagram of a pixel circuit provided by the present invention, where K=4, 5 or 6.

[0093] Figure 12 The example shown is for K=4; you can also refer to [the example provided]. Figure 13 K=5, or refer to Figure 14 K=6. It's understandable that the light-holding phase D2 includes the 2nd to the Kth pulse groups. The more pulse groups K has, the more times D2 is forced to flash during the light-holding phase; the fewer pulse groups K have, the fewer times D2 is forced to flash during the light-holding phase. K should not be too large or too small. If K is too small, the number of flashes during the light-holding phase D2 is too few, making the brightness change easily perceptible to the human eye. If K is too large, the time occupied by the light-holding phase D2 is too long, further reducing the data writing time and causing a deterioration in data writing performance, potentially leading to insufficient image writing and poor display quality.

[0094] In this embodiment, K=4, 5 or 6. The K value is within a reasonable range. The number of times D2 flickers during the light-emitting holding stage is reasonable. The brightness change is not easily detected by the human eye. Moreover, it will not cause insufficient data signal writing and will not affect the display effect.

[0095] In some alternative embodiments, reference continues to be made to... Figure 3 , Figures 12 to 14 The display panel 100 includes M rows of pixel circuits 10 and M light-emitting control signal lines 4. The light-emitting control signal lines 4 are electrically connected to the gate of the second transistor T2 to transmit the light-emitting control signal EM; where N is a positive integer greater than 2.

[0096] The light emission control signal EM consists of multiple invalid pulses and multiple valid pulses, with invalid pulses and valid pulses arranged alternately.

[0097] In one working cycle B00 of the pixel circuit 10, the total duration of the effective pulse is T1, and the total duration of the invalid pulse is T2, where 10%≤T1 / (T1+T2)≤50%.

[0098] It is understood that the display panel 100 includes M rows of pixel circuits 10 and M light-emitting control signal lines 4. The light-emitting control signal lines 4 are electrically connected to the gate of the second transistor T2 and transmit the light-emitting control signal EM. The light-emitting control signal EM includes multiple valid pulses and multiple invalid pulses. When the light-emitting control signal EM is a valid pulse, the second transistor T2 is turned on; when the light-emitting control signal EM is an invalid pulse, the second transistor T2 is not turned on. When the second transistor T2 is a P-type transistor, the valid pulse of the light-emitting control signal EM is at a low level; when the second transistor T2 is an N-type transistor, the valid pulse of the light-emitting control signal EM is at a high level. This embodiment is only illustrated using the example of the second transistor T2 being a P-type transistor, with the valid pulse of the light-emitting control signal EM being at a low level and the invalid pulse being at a high level.

[0099] During the light-holding phase D2, multiple valid and invalid pulses are arranged alternately in the order of valid pulse-invalid pulse-valid pulse-invalid pulse-valid pulse-invalid pulse. The light-emitting element 20 starts to emit light during the first valid pulse, and does not emit light during the invalid pulse. This causes the light-emitting element 20 to flicker during the light-holding phase D2. Because the potential of the first node N1 will jump high (for a P-type transistor for the driving transistor T3) or low (for an N-type transistor for the driving transistor T3) under the coupling effect of the second level of the data signal V2, the brightness of the light-emitting element 20 will decrease. The flickering during the light-holding phase D2 is not easily recognized by the human eye, thereby improving the problem of the regular flickering of the light-emitting element 20.

[0100] In one working cycle B00 of the pixel circuit 10, the total duration of the effective pulse is T1, and the total duration of the invalid pulse is T2. Among them, 10%≤T1 / (T1+T2)≤50%, that is, the duty cycle of the light emission control signal EM in this embodiment is between 10% and 50%. Optionally, it can be modulated by PWM. When the duty cycle is between 10% and 50%, the brightness peak is obvious. The easier it is to adjust the peak brightness, the more obvious the flicker optimization effect is. Due to limited tuning precision, when using PWM to modulate the display panel, the tuning of the luminous emission control signal EM must be an integer multiple of the period of its associated CK (clock signal). Furthermore, the smaller the duty cycle of the luminous emission control signal EM, the shorter the pixel emission time, thus allowing for greater flexibility in adjusting the display panel brightness. For example, when the luminous emission control signal EM has a 10% duty cycle and four pulse groups (effective and ineffective pulses), with each pulse group having 2.5% of its time as emission time, then under a tuning precision of 0.16% [the period of the CK signal associated with the EM signal divided by the time of one frame], the tuning significantly impacts the Pulse brightness and more noticeably improves the flicker value.

[0101] In some alternative embodiments, reference continues to be made to... Figures 12 to 14 In the front and rear corridor areas K02, the data signal is maintained at the second level V2.

[0102] It is understandable that in the front and rear corridor areas K02, the data signal is maintained at the second level V2. The data signal remains unchanged in the front and rear corridor areas K02 and is always different from the first level V1. Thus, for the first node N1, the second level V2 continues to couple to the first node N1, and the gate-source voltage Vgs of the driving transistor T3 decreases. At this time, the opening amplitude of the driving transistor T3 decreases, and the driving current generated decreases, thereby reducing the brightness of the light-emitting element 20. In addition, during the light-emitting holding phase D2, there are multiple effective pulses and ineffective pulses arranged alternately, causing the light-emitting element 20 to flicker multiple times during the light-emitting holding phase D2. For the same frame, the flickering of the light-emitting element 20 after the brightness decreases during the light-emitting holding phase D2 is not easily perceived by the human eye, thereby improving the problem of regular flickering in different frames of the display panel 100.

[0103] In some alternative embodiments, reference continues to be made to... Figure 4 , Figure 5 The driving transistor T3 is a P-type transistor, and the first level V1 of the data signal is less than the second level V2 of the data signal.

[0104] Alternatively, the driving transistor T3 can be an N-type transistor, and the first level V1 of the data signal is greater than the second level V2 of the data signal.

[0105] Figure 4 and Figure 5Taking a P-type transistor as an example, when the driving transistor T3 is a P-type transistor, the first level V1 of the data signal is less than the second level V2 of the data signal. That is, the data signal is higher in the front and rear corridor areas K02, which couples to the first node N1, pulling up the potential of the first node N1. The gate-source voltage Vgs of the driving transistor T3 decreases. At this time, the opening amplitude of the driving transistor T3 decreases, and the driving current generated decreases, thereby reducing the brightness of the light-emitting element 20. In addition, during the light-emitting holding stage, there are multiple effective pulses and ineffective pulses arranged alternately, causing the light-emitting element 20 to flicker multiple times during the light-emitting holding stage. For the same frame, the flickering of the light-emitting element 20 after the brightness decreases during the light-emitting holding stage is not easily perceived by the human eye, thereby improving the problem of regular flickering in different frames of the display panel 100.

[0106] When the driving transistor T3 is an N-type transistor, the first level V1 of the data signal is greater than the second level V2 of the data signal. That is, the data signal is lower in the front and rear corridor regions K02, which couples to the first node N1, pulling down the potential of the first node N1. The gate-source voltage Vgs of the driving transistor T3 decreases. At this time, the turn-on amplitude of the driving transistor T3 decreases, and the driving current generated decreases, thereby reducing the brightness of the light-emitting element 20. In addition, during the light-emitting holding phase, there are multiple effective pulses and ineffective pulses arranged alternately, causing the light-emitting element 20 to flicker multiple times during the light-emitting holding phase. For the same frame, the flickering of the light-emitting element 20 after the brightness decreases during the light-emitting holding phase is not easily perceived by the human eye, thereby improving the problem of regular flickering in different frames of the display panel 100.

[0107] In some alternative embodiments, combined with Figure 8 and reference Figure 15 , Figure 15 This is another timing diagram of the working cycle of a pixel circuit provided by the present invention. Figure 15 In the H-th row pixel circuit 10, one working cycle B00 includes a data writing stage D1 and a light-emitting holding stage D2. The data writing stage D1 includes the first pulse group, and the light-emitting holding stage D2 includes the second to the Kth pulse groups. When the pulse group is the (K-1)th pulse, the second level of the data signal is V21. When the pulse group is the Kth pulse, the second level of the data signal is V22, and V21 < V22.

[0108] It should be noted that the H-row pixel circuit can be either the middle row or the last row of pixel circuits; both are applicable here.

[0109] Figure 15Taking the light-emitting holding phase D2, which includes the 2nd to 6th pulse groups, as an example, the light-emitting control signal EM includes multiple invalid pulses and multiple valid pulses, which are arranged alternately. During the light-emitting holding phase D2, when the pulse group is the 4th pulse, the second level of the data signal is V21; when the pulse group is the 6th pulse, the second level of the data signal is V22, where V21 < V22. It can be understood that due to leakage current, the brightness of the light-emitting element 20 corresponding to the 2nd to 6th valid pulses shows a decreasing trend. At the 5th valid pulse, the data signal jumps... When the voltage is low (V21 < V22), the first node N1 can be coupled, pulling down its potential. This increases the gate-source voltage Vgs of the driving transistor T3, increasing the turn-on amplitude of the driving transistor T3. Consequently, the current input to the first power supply voltage terminal increases, leading to higher brightness. This means increasing the brightness of the light-emitting element 20 corresponding to the 5th effective pulse. In other words, it reduces the brightness of the earlier pulses in a frame and increases the brightness of the later pulses in a frame, thus mitigating the downward trend in a frame and minimizing the brightness difference between multiple pulses in a frame, thereby improving the display effect.

[0110] In some alternative embodiments, reference continues to be made to... Figure 15 When the pulse group consists of the 2nd to K-2nd pulses, the second level of the data signal is V23, where V22 < V23.

[0111] Figure 15 Taking the light-emitting holding phase D2, which includes the 2nd to 6th pulse groups, as an example, the light-emitting control signal EM includes multiple invalid pulses and multiple valid pulses, which are arranged alternately. During the light-emitting holding phase D2, when the second valid pulse occurs, the data signal jumps high, V23 > V22, and of course, V23 > V1. The data signal couples to the first node N1, pulling up the potential of the first node N1. The driving transistor T3 is a P-type transistor, and the gate-source voltage Vgs of the driving transistor T3 decreases, the turn-on amplitude of the driving transistor T3 decreases, the current input to the first power supply voltage terminal decreases, and the brightness decreases. In this way, the brightness of the light-emitting element 20 corresponding to the second valid pulse is close to the brightness of the light-emitting element 20 corresponding to the third valid pulse. That is, the brightness of the forced flashing of the light-emitting element 20 is basically close, which is not easily recognized by the human eye.

[0112] In some alternative embodiments, reference continues to be made to... Figures 4 to 15 The pixel circuit 10 also includes a third transistor T4, which is connected in series between the first node N1 and the first reset signal line. It is turned on in response to the second scan signal S1 and transmits the signal of the first reset signal line to the gate of the driving transistor T3.

[0113] The first scan signal S2 includes a valid signal and an invalid signal, and the second scan signal S1 includes a valid signal and an invalid signal; the cutoff time of the valid signal of the second scan signal S1 is before the start time of the valid signal of the first scan signal S2.

[0114] It is understandable that the function of the third transistor T4 is to reset the gate voltage of the driving transistor, so the first node N1 must be reset first, and then data is written.

[0115] Specifically, in one light-emitting cycle of the pixel circuit 10, the first stage is the reset phase C1. The effective signal of the second scan signal S1 controls the third transistor T4 to turn on, and the reset signal is written to the first node N1 to initialize the gate of the driving transistor T3. The effective signal of the second scan signal S1 controls the fifth transistor T6 to turn on, and the reset signal is written to the anode of the light-emitting element 20 to reset the anode of the light-emitting element 20.

[0116] In one light-emitting cycle of pixel circuit 10, after the reset phase C1 is the data signal writing phase C2. In the data signal writing phase C2, the second scan signal S1 transmitted to the gate of the third transistor T4 is an invalid signal, and the third transistor T4 is turned off. Since the reset signal was written to the first node N1 in the reset phase C1, the driving transistor T3 is turned on, the valid signal of the first scan signal S2 is transmitted to the gate of the first transistor T1, the first transistor T1 is turned on, the first voltage V1 of the data signal is written, and the valid signal of the first scan signal S2 is transmitted to the gate of the fourth transistor T5, the fourth transistor T5 is turned on. Therefore, the data signal is written to the first node N1 through the first transistor T1, the driving transistor T3, and the fourth transistor T5. The voltage of the second node N2 is equal to the data signal, N2=Vdata. The voltage of the first node N1 and the third node N3 is equal to the difference between the data signal and the threshold voltage of the driving transistor T3, N1=N3=Vdata-|Vth|.

[0117] The cutoff time of the valid signal of the second scan signal S1 is before the start time of the valid signal of the first scan signal S2. Therefore, the first node N1 is reset first to prevent the residual charge on the gate of the driving transistor T3 from affecting the current frame when displaying the previous frame.

[0118] In some alternative embodiments, reference continues to be made to... Figures 8 to 12 The pixel circuit 10 also includes a fourth transistor T5, which is connected in series between the first node N1 and the drain of the driving transistor T3. It is turned on in response to the first scan signal S2 and transmits the signal from the drain of the driving transistor T3 to the gate of the driving transistor T3.

[0119] Specifically, the gate of the fourth transistor T5 receives the first scan signal S2 and is turned on when the first scan signal S2 is valid. The signal from the drain of the driving transistor T3 is transmitted to the gate of the driving transistor T3 through the fourth transistor T5. This stage is the data signal writing stage C2. During the data signal writing stage C2, the second scan signal S1 transmitted to the gate of the third transistor T4 is invalid, and the third transistor T4 is turned off. Since the reset signal is written to the first node N1 during the reset stage C1, the driving transistor T3 is turned on, and the valid signal of the first scan signal S2 is transmitted to the gate of the first transistor T1. When the circuit is turned on, the first voltage V1 of the data signal is written, and the effective signal of the first scan signal S2 is transmitted to the gate of the fourth transistor T5. The fourth transistor T5 is turned on, and the signal at the drain of the driving transistor T3 is transmitted to the gate of the driving transistor T3 through the fourth transistor T5. Therefore, the data signal is written to the first node N1 through the first transistor T1, the driving transistor T3, and the fourth transistor T5. The voltage of the second node N2 is equal to the data signal, N2=Vdata. The voltages of the first node N1 and the third node N3 are equal to the difference between the data signal and the threshold voltage of the driving transistor T3, N1=N3=Vdata-|Vth|.

[0120] In some alternative embodiments, reference continues to be made to... Figures 8 to 12 The pixel circuit 10 also includes a fifth transistor T6, which is connected in series between the anode of the light-emitting element 20 and the second reset signal line. It is turned on in response to the second scan signal S1 and transmits the signal transmitted by the second reset signal line to the anode.

[0121] The fifth transistor T6 is connected in series between the second reset signal line and the anode of the light-emitting element 20 to reset the anode of the light-emitting element 20. Here, the second reset signal line and the first reset signal line can be the same signal line, thereby reducing the wiring within the display panel 100. Of course, the second reset signal line and the first reset signal line can also be set separately, thereby allowing different reset voltages to be input.

[0122] The fifth transistor T6 is turned on in response to the valid signal of the second scan signal S1. The reset signal VREF2 on the second reset signal line is transmitted to the anode of the light-emitting element 20 to reset the anode of the light-emitting element 20. This can prevent the residual charge on the anode of the light-emitting element 20 when displaying the previous frame from affecting the current frame.

[0123] In some alternative embodiments, reference continues to be made to... Figure 6 The driving frequency of the display panel 100 includes a first driving frequency, which is less than or equal to 60Hz.

[0124] Understandably, the first driving frequency is a low frequency. At low frequencies, due to the presence of the front and rear corridor areas K02, leakage current is more severe, the brightness difference between the front and rear corridor areas K02 is greater, and flickering is more pronounced. Specifically, the display panel 100 displays at both high and low frequencies. Frequency adjustment for the same display device is typically achieved using Long V. Long V means that the refresh time for each frame is the same at 60Hz and 120Hz, but when operating at a 60Hz refresh rate, each frame is followed by a blank frame, so the actual display effect is equivalent to 60Hz. In this embodiment, the first driving frequency is less than or equal to 60Hz. Due to the presence of the front and rear corridor regions K02, leakage current exists in the front and rear corridor regions K02, causing flickering in different frames. In this invention, the front and rear corridor regions K02, the data line 6 and the first node N1 will be coupled. The second level V2 of the data signal will affect the potential of the first node N1, causing the gate-source voltage Vgs of the driving transistor T3 to decrease. At this time, the opening amplitude of the driving transistor T3 decreases, the driving current generated decreases, thereby reducing the brightness of the light-emitting element 20. This superimposed leakage current effect interferes with the effect of leakage current on flickering, thus improving the flickering problem.

[0125] In some alternative embodiments, reference continues to be made to... Figure 5 It also includes a second capacitor 8;

[0126] The first node N1 includes a first part 81, and the data line 6 includes a second part 82; there is a gap between the orthographic projection of the first part 81 on the substrate 01 and the orthographic projection of the second part 82 on the substrate 01.

[0127] The first part 81 is reused as the first plate of the second capacitor 8, and the second part 82 is reused as the second plate of the second capacitor 8.

[0128] Specifically, the second capacitor 8 is a parasitic capacitor. There is a gap between the orthographic projection of the first part 81 on the substrate 01 and the orthographic projection of the second part 82 on the substrate 01. The first part 81 of the first node N1 overlaps with the second part 82 of the data line 6 in the first direction X. As a result, the first part 81 and the second part 82 generate parasitic capacitance. The first part 81 is multiplexed as the first plate of the second capacitor 8, and the second part 82 is multiplexed as the second plate of the second capacitor 8. When the data line 6 transmits data signals, the voltage of the data line 6 changes, and the voltage of the second part 82 also changes. When the potential of the second plate of the second capacitor 8 changes, the potential of the first plate of the second capacitor 8 also changes, thereby changing the potential of the first node N1. In this invention, the first part 81 is reused as the first plate of the second capacitor 8, and the second part 82 is reused as the second plate of the second capacitor 8. In the front and rear corridor areas K02, the second voltage V2 transmitted by the data line 6 is transmitted to the second part 82. According to the principle of capacitive coupling, the potential of the first node N1 is changed, which reduces the gate-source voltage Vgs of the driving transistor T3. At this time, the opening amplitude of the driving transistor T3 is reduced, and the driving current generated is reduced, thereby reducing the brightness of the light-emitting element 20. This superimposed leakage current effect interferes with the effect of leakage current on flickering and improves the flickering problem.

[0129] In some alternative embodiments, please refer to Figure 16 , Figure 16 This is a schematic diagram of the planar structure of a display device provided in an embodiment of the present invention. The display device 1000 provided in this embodiment includes the display panel 100 provided in the above embodiment of the present invention. Figure 16 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device 1000 provided in this embodiment can be any other display device 1000 with display functions, such as a computer, television, or vehicle-mounted display device; this invention does not impose specific limitations on this. The display device 1000 provided in this embodiment has the beneficial effects of the display panel 100 provided in this embodiment. For details, please refer to the specific descriptions of the display panel 100 in the above embodiments; these will not be repeated here.

[0130] As can be seen from the above embodiments, the display panel and display device provided by the present invention achieve at least the following beneficial effects:

[0131] In the display panel of the present invention, the pixel circuit includes: a driving transistor, the gate of which is electrically connected to a first node and provides driving current to a light-emitting element; a first transistor connected in series between the driving transistor and a data line, which transmits a data signal to the driving transistor in response to a first scan signal; a second transistor electrically connected between the driving transistor and a light-emitting element, which transmits driving current to the light-emitting element in response to a light-emitting control signal; a first capacitor, the first plate of which is electrically connected to the first node, and the second plate of which is electrically connected to a first power supply voltage line; the first node is located on the side of the second plate away from the substrate; one driving cycle of the display panel includes a display scan area. The system includes front and rear corridor areas; multiple pixel circuits are arranged in M ​​rows and N columns, where N≥2 and M≥2; data lines transmit data signals. In the display scanning area, at least one data signal includes a first level V1, and in the front and rear corridor areas, the data signal includes a second level V2, where V1≠V2. In the front and rear corridor areas, the data lines will be coupled with the first node. The second level V2 of the data signal will affect the potential of the first node, causing the gate-source voltage Vgs of the driving transistor to decrease. At this time, the opening amplitude of the driving transistor decreases, the driving current generated decreases, and thus the brightness of the light-emitting element decreases. This superimposed leakage current effect interferes with the effect of leakage current on flicker, thereby improving the flicker problem.

[0132] While specific embodiments of the invention have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a substrate, a plurality of pixel circuits located on one side of the substrate, and light-emitting elements electrically connected to the pixel circuits. The pixel circuit includes: A driving transistor, the gate of which is electrically connected to the first node and provides driving current to the light-emitting element; A first transistor, connected in series between the driving transistor and the data line, transmits a data signal to the driving transistor in response to a first scan signal; The second transistor is electrically connected between the driving transistor and the light-emitting element, and transmits driving current to the light-emitting element in response to the light-emitting control signal; A first capacitor, wherein the first plate of the first capacitor is electrically connected to the first node, and the second plate of the first capacitor is electrically connected to the first power supply voltage line; the first node is located on the side of the second plate away from the substrate. One driving cycle of the display panel includes a display scanning area and a front and rear corridor area; The plurality of pixel circuits are arranged in M ​​rows and N columns, where M ≥ 2; The display panel includes M light-emitting control signal lines, which are electrically connected to the gate of the second transistor to transmit the light-emitting control signal, where N is a positive integer greater than 2; the light-emitting control signal includes K valid pulses and K invalid pulses, which are arranged alternately, where K is a positive integer greater than 2; In one working cycle of the pixel circuit in the Mth row, there are a data writing stage and a light-emitting holding stage. The data writing stage includes the first pulse group, and the light-emitting holding stage includes the second to the Kth pulse groups. The data line transmits data signals. In the display scanning area, at least one of the data signals includes a first level V1. In the front and rear corridor areas, the data signal includes a second level V2, wherein V1 ≠ V2, and the data signal is maintained at the second level V2. The driving transistor is a P-type transistor, and the first level V1 of the data signal is less than the second level V2 of the data signal; or, the driving transistor is an N-type transistor, and the first level V1 of the data signal is greater than the second level V2 of the data signal.

2. The display panel according to claim 1, characterized in that, The total duration of the display scanning area is t1, and the total duration of the front and rear corridor areas is t2, where t1 < t2.

3. The display panel according to claim 2, wherein t1:t2 = 1 / 3, or t1:t2 = 1 / 4; or t1:t2 = 1 / 5.

4. The display panel according to claim 2, characterized in that, The display panel includes M rows of pixel circuits arranged along a first direction; the first scan signal includes a valid signal and an invalid signal, and when the first scan signal is a valid signal, the first transistor is turned on; The display panel includes a first driving cycle and a second driving cycle adjacent to the first driving cycle; The start time of the display scanning area is the start time of the effective signal of the first scanning signal corresponding to the pixel circuit in the first row of the first driving cycle, and the end time of the display scanning area is the end time of the effective signal of the first scanning signal corresponding to the pixel circuit in the M row of the first driving cycle. The start time of the front and rear corridor areas is the time when the effective signal of the first scan signal corresponding to the pixel circuit in the Mth row of the first driving cycle ends, and the end time of the front and rear corridor areas is the start time of the effective signal of the first scan signal corresponding to the pixel circuit in the 1st row of the second driving cycle.

5. The display panel according to claim 4, characterized in that, The duration of the display scanning area is P1, and the duration of the front and rear corridor areas is P2, where P1 / (P1+P2)≤1 / 4.

6. The display panel according to claim 1, characterized in that, K = 4, 5, or 6.

7. The display panel according to claim 1, characterized in that, In one working cycle of the pixel circuit, the total duration of the effective pulse is T1, and the total duration of the invalid pulse is T2, wherein 10%≤T1 / (T1+T2)≤50%.

8. The display panel according to claim 1, characterized in that, In one working cycle of the pixel circuit in row H, there is a data writing stage and a light-emitting holding stage. The data writing stage includes the first pulse group, and the light-emitting holding stage includes the second to the Kth pulse groups. When the pulse group is the (K-1)th pulse, the second level of the data signal is V21. When the pulse group is the Kth pulse, the second level of the data signal is V22. V21 < V22, and 1 < H < M.

9. The display panel according to claim 8, wherein when the pulse group is the 2nd to K-2nd pulse, the second level of the data signal is V23, where V22 < V23.

10. The display panel according to claim 1, characterized in that, The pixel circuit further includes a third transistor connected in series between the first node and the first reset signal line, which is turned on in response to the second scan signal to transmit the signal of the first reset signal line to the gate of the driving transistor. The first scan signal includes a valid signal and an invalid signal, and the second scan signal includes a valid signal and an invalid signal; the cutoff time of the valid signal of the second scan signal is before the start time of the valid signal of the first scan signal.

11. The display panel according to claim 1, characterized in that, The pixel circuit further includes a fourth transistor connected in series between the first node and the drain of the driving transistor. The fourth transistor is turned on in response to the first scan signal to transmit the signal from the drain of the driving transistor to the gate of the driving transistor.

12. The display panel according to claim 1, characterized in that, The pixel circuit further includes a fifth transistor, which is connected in series between the anode of the light-emitting element and the second reset signal line. The fifth transistor is turned on in response to the second scan signal and transmits the signal transmitted by the second reset signal line to the anode.

13. The display panel according to claim 1, characterized in that, The driving frequency of the display panel includes a first driving frequency, which is less than or equal to 30Hz.

14. The display panel according to claim 1, characterized in that, It also includes a second capacitor; The first node includes a first part, and the data line includes a second part; there is a gap between the orthographic projection of the first part on the substrate and the orthographic projection of the second part on the substrate; The first part is reused as the first plate of the second capacitor, and the second part is reused as the second plate of the second capacitor.

15. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 14.

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