A hall current regulating circuit and a hall sensor

Abstract

The application discloses a Hall current adjusting circuit and a Hall sensor. The adjusting circuit comprises a negative temperature coefficient current adjusting module, a positive temperature coefficient current adjusting module, a first adjusting code end and a first switch module. The negative temperature coefficient current adjusting module is connected with a negative temperature coefficient current signal to generate a target negative temperature coefficient current signal; the positive temperature coefficient current adjusting module is connected with a positive temperature coefficient current signal to generate a target positive temperature coefficient current signal; the first adjusting code end is connected with a first adjusting code value; and the first switch module is used for controlling the negative temperature coefficient current adjusting module to output the target negative temperature coefficient current signal and the positive temperature coefficient current adjusting module to output the target positive temperature coefficient current signal according to the first adjusting code value. In this way, the target negative temperature coefficient current signal and the target positive temperature coefficient current signal are combined to obtain a larger temperature coefficient adjustment range, so that the temperature coefficient adjustment of the Hall current under different processes can be adapted.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a Hall current regulation circuit and a Hall sensor. Background Technology

[0002] Hall sensors can detect magnetic fields and their changes, and can be used in various magnetic field-related applications. Based on the Hall effect, a Hall sensor is an integrated sensor consisting of a Hall element and its associated circuitry. Hall sensors have a wide range of applications in industrial production, transportation, and daily life.

[0003] Hall sensors can be powered by various methods, with a constant current bias power supply providing more stable sensitivity. However, due to variations in Hall element characteristics under different manufacturing processes and the effects of magnet degradation at high temperatures, the Hall current under the constant current bias power supply method requires temperature coefficient adjustment.

[0004] In related technologies, a single negative temperature coefficient current signal or a positive temperature coefficient current signal is used to adjust the temperature coefficient of Hall current. This results in a small range of temperature coefficient adjustment, which means that the Hall current with a fixed current value cannot achieve the best effect under various processes. Summary of the Invention

[0005] To solve the above-mentioned technical problems, the present invention provides a Hall current adjustment circuit and a Hall sensor.

[0006] The present invention provides a technical solution for a Hall current adjustment circuit as follows:

[0007] A negative temperature coefficient current regulation module is connected to a negative temperature coefficient current signal and is used to generate a target negative temperature coefficient current signal based on the negative temperature coefficient current signal.

[0008] A positive temperature coefficient current regulation module is connected to a positive temperature coefficient current signal and is used to generate a target positive temperature coefficient current signal based on the positive temperature coefficient current signal.

[0009] The first adjustment code terminal is used to input the first adjustment code value;

[0010] The first switching module is connected to the first adjustment code terminal, the negative temperature coefficient current adjustment module, and the positive temperature coefficient current adjustment module. It is used to control the negative temperature coefficient current adjustment module to output the target negative temperature coefficient current signal according to the first adjustment code value, and to control the positive temperature coefficient current adjustment module to output the target positive temperature coefficient current signal.

[0011] The beneficial effects of the Hall current regulation circuit of the present invention are as follows:

[0012] This invention increases the temperature coefficient adjustment range by combining a target negative temperature coefficient current signal and a target positive temperature coefficient current signal, so that the temperature coefficient adjustment of Hall current can achieve the best results under different process characteristics.

[0013] In one alternative embodiment, the negative temperature coefficient current adjustment module includes at least one set of first P-tube current mirrors; the first P-tube current mirrors are used to receive the negative temperature coefficient current signal to generate the target negative temperature coefficient current signal.

[0014] The positive temperature coefficient current adjustment module includes at least one set of first N-tube current mirrors; the first N-tube current mirrors are used to receive the positive temperature coefficient current signal to generate the target positive temperature coefficient current signal.

[0015] The first switching module includes at least one set of first switching units. Each first switching unit includes an inverter, a first PMOS transistor, and a first NMOS transistor. The input terminal of the inverter is connected to the first adjustment code terminal, and the output terminal of the inverter is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is connected to the first P-transistor current mirror. The gate of the first NMOS transistor is connected to the first adjustment code terminal, the drain is connected to the first N-transistor current mirror, and the source is connected to the drain of the first PMOS transistor.

[0016] The inverter and the first PMOS transistor control the first P-transistor current mirror to output the target negative temperature coefficient current signal according to the first adjustment code value; the first NMOS transistor controls the first N-transistor current mirror to output the target positive temperature coefficient current signal according to the first adjustment code value.

[0017] In one alternative embodiment, the adjustment circuit further includes at least one set of second N-channel current mirrors, the input terminals of which are connected to the drain of the first PMOS transistor and the source of the first NMOS transistor. The second N-channel current mirrors are used to output the target negative temperature coefficient current signal and the target positive temperature coefficient current signal.

[0018] In one alternative embodiment, the adjustment circuit further includes a current amplitude adjustment module, comprising at least one set of second N-tube current mirrors, at least one set of second switching units, and a second adjustment code terminal for accessing a second adjustment code value;

[0019] The second N-tube current mirror is connected to the negative temperature coefficient current adjustment module and the positive temperature coefficient current adjustment module through the first switching module; the second switching unit is connected to the second adjustment code terminal and the second N-tube current mirror.

[0020] The second switching unit generates a target current amplitude adjustment signal based on the second adjustment code value, the target negative temperature coefficient current signal, and the target positive temperature coefficient current signal.

[0021] In one alternative embodiment, the adjustment circuit further includes a zero temperature coefficient current adjustment module, which receives a zero temperature coefficient current signal and is connected to the input terminal of the second N-tube current mirror, for generating a target zero temperature coefficient current signal based on the zero temperature coefficient current signal, and outputting it to the second N-tube current mirror.

[0022] In one alternative approach, the number of groups of the first P-tube current mirrors is matched with the number of the inverters and the first PMOS transistors.

[0023] In one alternative approach, the number of groups of the first N-channel current mirrors is matched with the number of NMOS transistors.

[0024] In one alternative, at least one set of the first P-tube current mirrors includes two symmetrical and parallel-connected second PMOS transistors, one of which is used to receive the negative temperature coefficient current signal, and the other is used to connect to the first PMOS transistor.

[0025] In one alternative, at least one set of the first N-channel current mirrors includes two symmetrically connected and parallel second NMOS transistors, one of which is used to receive the positive temperature coefficient current signal, and the other is used to connect to the first NMOS transistor.

[0026] The present invention also provides a Hall sensor. The Hall sensor includes a Hall current adjustment circuit.

[0027] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0028] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0029] Figure 1 A circuit block diagram of a Hall current regulation circuit provided by the present invention is shown;

[0030] Figure 2 Another circuit block diagram of a Hall current regulation circuit provided by the present invention is shown;

[0031] Figure 3 for Figure 2 A circuit diagram of a Hall current regulation circuit according to one embodiment is shown.

[0032] Figure 4 for Figure 2 The circuit diagram shown illustrates the generation of negative temperature coefficient current signals, positive temperature coefficient current signals, and zero temperature coefficient current signals in the Hall current regulation circuit of one embodiment. Detailed Implementation

[0033] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0034] Figure 1 A circuit block diagram of a Hall current adjustment circuit provided by the present invention is shown. Figure 1As shown, the Hall current adjustment circuit 10 includes a negative temperature coefficient current adjustment module 11, a positive temperature coefficient current adjustment module 12, a first adjustment code terminal 13, and a first switch module 14. The negative temperature coefficient current adjustment module 11 receives a negative temperature coefficient current signal and is used to generate a target negative temperature coefficient current signal based on the negative temperature coefficient current signal. The negative temperature coefficient current signal is provided by an external circuit. The positive temperature coefficient current adjustment module 12 receives a positive temperature coefficient current signal and is used to generate a target positive temperature coefficient current signal based on the positive temperature coefficient current signal. The negative temperature coefficient current signal is also provided by an external circuit. The first adjustment code terminal 13 is used to receive a first adjustment code value. This first adjustment code value is a temperature coefficient adjustment code value, which can be 0 or 1, where 0 represents a low-level signal and 1 represents a high-level signal. The first switch module 14 is connected to the first adjustment code terminal 13, the negative temperature coefficient current adjustment module 11, and the positive temperature coefficient current adjustment module 12. It is used to control the negative temperature coefficient current adjustment module 11 to output the target negative temperature coefficient current signal and the positive temperature coefficient current adjustment module 12 to output the target positive temperature coefficient current signal according to the first adjustment code value. In this embodiment, the first switch module 14 is turned on or off according to the received first adjustment code value. When the first adjustment code value is a high-level signal, the first switch module 14 is turned on, connecting the negative temperature coefficient current adjustment module 11, causing it to output the target negative temperature coefficient current signal. Simultaneously, it also connects the positive temperature coefficient current adjustment module 12, causing it to output the target positive temperature coefficient current signal. When the first adjustment code value is a low-level signal, the first switch module 14 is turned off, causing the negative temperature coefficient current adjustment module 11 to not output (at which point the target negative temperature coefficient current signal is 0) and the positive temperature coefficient current adjustment module 12 to not output (at which point the target negative temperature coefficient current signal is also 0).

[0035] In this embodiment, the first switch module 14 turns the current on or off according to the first adjustment code value. When the first switch module 14 is turned on, the positive temperature coefficient current adjustment module 12 and the negative temperature coefficient current adjustment module 11 are simultaneously combined to output the target positive temperature coefficient current signal and the target negative temperature coefficient current signal. In this way, the temperature coefficient adjustment range is increased so that the optimal effect can be obtained for the temperature coefficient adjustment of the Hall current under different process characteristics.

[0036] Figure 2 This is another circuit block diagram for a Hall current regulation circuit. (Example) Figure 2 As shown, the negative temperature coefficient current adjustment module 11 includes at least one set of first P-tube current mirrors 110; the first P-tube current mirrors 110 are used to receive the negative temperature coefficient current signal to generate the target negative temperature coefficient current signal.

[0037] The positive temperature coefficient current adjustment module 12 includes at least one set of first N-tube current mirrors 120; the first N-tube current mirrors 120 are used to receive the positive temperature coefficient current signal to generate the target positive temperature coefficient current signal.

[0038] The first switching module 14 includes at least one set of first switching units 140, each of which includes an inverter 141, a first PMOS transistor 142, and a first NMOS transistor 143.

[0039] The inverter 141 has its input terminal connected to the first adjustment code terminal 13 and its output terminal connected to the gate of the first PMOS transistor 142. The source of the first PMOS transistor 142 is connected to the first P-channel current mirror 110. The gate of the first NMOS transistor 142 is connected to the first adjustment code terminal 13, its drain is connected to the first N-channel current mirror 120, and its source is connected to the drain of the first PMOS transistor 142.

[0040] The inverter 141 and the first PMOS transistor 142 control the first P-tube current mirror 110 to output the target negative temperature coefficient current signal according to the first adjustment code value; the first NMOS transistor 143 controls the first N-tube current mirror 120 to output the target positive temperature coefficient current signal according to the first adjustment code value.

[0041] In this embodiment, when the negative temperature coefficient current adjustment module 11 includes a set of first P-tube current mirrors 110 and the positive temperature coefficient current adjustment module 12 includes a set of first N-tube current mirrors 120, the first switching module 14 includes a set of first switching units 140. The first P-tube current mirrors 110 and 120 are respectively connected to the first switching units 140. When the negative temperature coefficient current adjustment module 11 includes multiple sets of first P-tube current mirrors 110 and the positive temperature coefficient current adjustment module 12 includes multiple sets of first N-tube current mirrors 120, the first switching module 14 includes multiple sets of first switching units 140. Each set of first P-tube current mirrors 110, each set of first N-tube current mirrors 120, and each set of first switching units 140 are connected in parallel. Each set of first P-tube current mirrors 110 and each set of first N-tube current mirrors 120 are respectively connected to each set of first switching modules 14.

[0042] In this embodiment, when the first adjustment code value is low, the inverter 141 converts the low level to a high level and sends it to the first PMOS transistor 142. According to the characteristics of the PMOS transistor, the first PMOS transistor 142 turns off when it receives a high level. According to the characteristics of the NMOS transistor, the first NMOS transistor 143 turns off when it receives a low level. At this time, no current flows through the first PMOS transistor 142 and the first NMOS transistor 143, so that the target negative temperature coefficient current signal and the target positive temperature coefficient current signal will not be output. When the first adjustment code value is high, the inverter 141 converts the high level to a low level and sends it to the first PMOS transistor 142. According to the characteristics of the PMOS transistor, the first PMOS transistor 142 turns on when it receives a low level; according to the characteristics of the NMOS transistor, the first NMOS transistor 143 turns on when it receives a high level. At this time, current flows through both the first PMOS transistor 142 and the first NMOS transistor 143, so that the first P-tube current mirror 110 outputs the target negative temperature coefficient current signal and the first N-tube current mirror 120 outputs the target positive temperature coefficient current signal.

[0043] In this embodiment, an inverter is further utilized, and based on the respective conduction characteristics of the PMOS and NMOS transistors, the PMOS and NMOS transistors can be simultaneously turned off or on. Thus, when the PMOS and NMOS transistors can be turned on simultaneously, the target negative temperature coefficient current signal and the target positive temperature coefficient current signal can be output simultaneously, thereby increasing the temperature coefficient adjustment range. This ensures that the optimal effect can be obtained for adjusting the temperature coefficient of the Hall current under different process characteristics.

[0044] In some embodiments, the adjustment circuit 10 further includes at least one set of second N-channel current mirrors 16, the input terminal of the second N-channel current mirror 16 being connected to the drain of the first PMOS transistor 142 and the source of the first NMOS transistor 143, and the second N-channel current mirror 16 being used to output the target negative temperature coefficient current signal and the target positive temperature coefficient current signal.

[0045] When the second N-channel current mirror 16 is in a group, the input terminal of the second N-channel current mirror 16 is connected to the drain of the first PMOS transistor 142 and the source of the first NMOS transistor 143; when there are multiple groups of second N-channel current mirrors 16, the multiple groups of second N-channel current mirrors 16 are arranged in parallel, and the input terminal of each group of second N-channel current mirrors 16 is connected to the drain of the first PMOS transistor 142 and the source of the first NMOS transistor 143 respectively.

[0046] In this embodiment, a second N-tube current mirror 16 is provided to more accurately replicate the target negative temperature coefficient current signal and the target positive temperature coefficient current signal, and as an output terminal, the output target negative temperature coefficient current signal and the target positive temperature coefficient current signal remain constant without being affected by process and temperature.

[0047] In some embodiments, the adjustment circuit 10 further includes a current amplitude adjustment module 15, which includes at least one set of second N-tube current mirrors 16, at least one set of second switching units 17, and a second adjustment code terminal 18 for accessing a second adjustment code value.

[0048] The second N-tube current mirror 16 is connected to the negative temperature coefficient current adjustment module 11 and the positive temperature coefficient current adjustment module 12 through the first switch module 14; the second switch unit 17 is connected to the second adjustment code terminal 18 and the second N-tube current mirror 16.

[0049] The second switching unit 17 generates a target current amplitude adjustment signal based on the second adjustment code value, the target negative temperature coefficient current signal, and the target positive temperature coefficient current signal.

[0050] The current amplitude adjustment module 15 is used to adjust the amplitude of the Hall current flowing into the second N-transistor current mirror 16. Specifically, the current amplitude adjustment module 15 generates a target current amplitude adjustment signal by using at least one set of second N-transistor current mirrors 16 and at least one set of second switching units 17 connected to the second adjustment code value, that is, to adjust the amplitude of the Hall current flowing into the second N-transistor current mirror 16.

[0051] In this embodiment, the second adjustment code value is the numerical value corresponding to the digital control signal, used to control the current amplification factor of the sum of the target negative temperature coefficient current signal and the target positive temperature coefficient current signal to the target current amplitude adjustment signal. The value of the second adjustment code is either 0 or 1.

[0052] The technical solution of this embodiment further incorporates a second N-tube current mirror 16, a second adjustment code terminal 18, and a first switch module 14 in the adjustment circuit to adjust the amplitude of the original Hall current, thereby improving the anti-interference capability of the Hall current in the circuit. Furthermore, the adjustment circuit of this invention achieves optimal results in adjusting the temperature coefficient of the Hall current under different process characteristics, while also improving the anti-interference capability of the Hall current, thus enhancing the overall performance of the adjustment circuit. Moreover, the temperature coefficient adjustment and current amplitude adjustment are independent of each other, reducing the workload of adjustment.

[0053] In some embodiments, the adjustment circuit 10 further includes a zero temperature coefficient current adjustment module 19, which receives a zero temperature coefficient current signal and is connected to the input terminal of the second N-tube current mirror 16, for generating a target zero temperature coefficient current signal based on the zero temperature coefficient current signal, and outputting it to the second N-tube current mirror 16.

[0054] In this embodiment, the zero temperature coefficient current signal is a constant current signal. The zero temperature coefficient current adjustment module 19 generates a target zero temperature coefficient current signal, which is used to ensure that the second N-tube current mirror 16 always has current flowing through it when both the target negative temperature coefficient current signal and the target positive temperature coefficient current signal output 0, so as to ensure that the adjustment circuit can still realize the amplitude adjustment of the Hall current.

[0055] In some embodiments, the regulating circuit 10 may further include: a negative temperature coefficient current input terminal 20, a positive temperature coefficient current input terminal 21, and a zero temperature coefficient current input terminal 22.

[0056] The negative temperature coefficient current input terminal 20 is connected to the negative temperature coefficient current adjustment module 11 and outputs a negative temperature coefficient current signal; the positive temperature coefficient current input terminal 21 is connected to the positive temperature coefficient current adjustment module 12 and outputs a positive temperature coefficient current signal; the zero temperature coefficient current input terminal 22 is connected to the zero temperature coefficient current adjustment module 19 and outputs a zero temperature coefficient current signal.

[0057] In some embodiments, the number of groups of the first P-tube current mirror 110 matches the number of the inverters 141 and the first PMOS transistors 142. Specifically, each group of the first P-tube current mirror 110 corresponds to one inverter 141 and one first PMOS transistor 142, thus enabling the inverters 141 and the first PMOS transistors 142 to effectively control the output of the first P-tube current mirror 110 to produce the target negative temperature coefficient current signal.

[0058] In some embodiments, the number of groups of the first N-channel current mirror 120 is matched with the number of the first NMOS transistors 143. Specifically, each group of the first N-channel current mirror 120 corresponds to one first NMOS transistor 143. This makes it easier for the first NMOS transistors 143 to control the output of the first N-channel current mirror 120 to output the target positive temperature coefficient current signal.

[0059] In some embodiments, at least one set of the first P-tube current mirrors 110 includes two symmetrically connected second PMOS transistors, one of which is used to receive the negative temperature coefficient current signal, and the other is used to connect to the first PMOS transistor 142. In this embodiment, two symmetrical second PMOS transistors are used to achieve the output of the target negative temperature coefficient current signal, thus making the output target negative temperature coefficient current signal constant, which is beneficial for temperature coefficient adjustment.

[0060] In some embodiments, at least one set of the first N-channel current mirrors 120 includes two symmetrically connected second NMOS transistors, one of which is used to receive the positive temperature coefficient current signal, and the other is used to connect to the first NMOS transistor 143. In this embodiment, two symmetrical second NMOS transistors are used to achieve the output of the target positive temperature coefficient current signal, thus making the output target positive temperature coefficient current signal constant, which is beneficial for temperature coefficient adjustment.

[0061] Figure 3 for Figure 2 The circuit diagram shown is a circuit diagram of a Hall current adjustment circuit according to one embodiment. Figure 3 As shown, the negative temperature coefficient current adjustment module 11 may include four sets of first P-tube current mirrors 110. Specifically, the four sets of first P-tube current mirrors 110 include a first P-tube PM0, a second P-tube PM1, a third P-tube PM2, a fourth P-tube PM3, and a fifth P-tube PM4 connected in parallel. Specifically, the first P-tube PM0 and the second P-tube PM1 form the first set of first P-tube current mirrors 110; the first P-tube PM0 and the third P-tube PM2 form the second set of first P-tube current mirrors 110; the first P-tube PM0 and the fourth P-tube PM3 form the third set of first P-tube current mirrors 110; and the first P-tube PM0 and the fifth P-tube PM4 form the fourth set of first P-tube current mirrors 110.

[0062] The positive temperature coefficient current adjustment module 12 may include four sets of first N-tube current mirrors 120. Specifically, the four sets of first N-tube current mirrors 120 include a first N-tube NM0, a second N-tube NM1, a third N-tube NM2, a fourth N-tube NM3, and a fifth N-tube NM4 connected in parallel. Among them, the first N-tube NM0 and the second N-tube NM1 form the first set of first N-tube current mirrors 120, the first N-tube NM0 and the third N-tube NM2 form the second set of first N-tube current mirrors 120, the first N-tube NM0 and the fourth N-tube NM3 form the third set of first N-tube current mirrors 120, and the first N-tube NM0 and the fifth N-tube NM4 form the fourth set of first N-tube current mirrors 120.

[0063] The first switching module 14 may include four sets of first switching units 140. Specifically, the first set of first switching units 140 includes a first inverter 3411, a sixth P-transistor PM5, and a sixth N-transistor NM5. The second set of first switching units 140 includes a second inverter 3421, a seventh P-transistor PM6, and a seventh N-transistor NM6. The third set of first switching units 140 includes a third inverter 3431, an eighth P-transistor PM7, and an eighth N-transistor NM7. The fourth set of first switching units 140 includes a fourth inverter 3441, a ninth P-transistor PM8, and a ninth N-transistor NM8.

[0064] The adjustment circuit includes a first adjustment code terminal group 33. The first adjustment code terminal group 33 includes a first adjustment code terminal 331, a second adjustment code terminal 332, a third adjustment code terminal 333, and a fourth adjustment code terminal 334.

[0065] In this configuration, the input terminal of the first inverter 3411 is connected to the first adjustment code terminal 331, and the output terminal of the first inverter 3411 is connected to the gate of the sixth P-type transistor PM5; the source of the sixth P-type transistor PM5 is connected to the second P-type transistor PM1; the gate of the sixth N-type transistor NM5 is connected to the first adjustment code terminal 331, the drain is connected to the second N-type transistor NM1, and the source is connected to the drain of the sixth P-type transistor PM5; the input terminal of the second inverter 3421 is connected to the second adjustment code terminal 331, and the output terminal of the second inverter 3421 is connected to the gate of the seventh P-type transistor PM6; the source of the seventh P-type transistor PM6 is connected to the third P-type transistor PM2; the gate of the eighth N-type transistor NM6 is connected to the second adjustment code terminal 332, the drain is connected to the third N-type transistor NM2, and the source is connected to the drain of the seventh P-type transistor PM6. The input terminal of the third inverter 3431 is connected to the third adjustment code terminal 333, and the output terminal of the third inverter 3431 is connected to the gate of the eighth P-type transistor PM7; the source of the eighth P-type transistor PM7 is connected to the fourth P-type transistor PM3; the gate of the eighth N-type transistor NM7 is connected to the third adjustment code terminal 333, the drain is connected to the fourth N-type transistor NM3, and the source is connected to the drain of the eighth P-type transistor PM7; the input terminal of the fourth inverter 3441 is connected to the fourth adjustment code terminal 334, and the output terminal of the fourth inverter 3441 is connected to the gate of the ninth P-type transistor PM8; the source of the ninth P-type transistor PM8 is connected to the fifth P-type transistor PM4; the gate of the ninth N-type transistor NM8 is connected to the fourth adjustment code terminal 334, the drain is connected to the fifth N-type transistor NM4, and the source is connected to the drain of the ninth P-type transistor PM8.

[0066] The first inverter 3411 and the sixth P-tube PM5 control the second P-tube PM1 to output a first negative temperature coefficient current signal according to the first adjustment code value; the sixth N-tube NM5 controls the second N-tube NM1 to output a first positive temperature coefficient current signal according to the first adjustment code value; the second inverter 3421 and the seventh P-tube PM6 control the third P-tube PM2 to output a second negative temperature coefficient current signal according to the second adjustment code value; the seventh N-tube NM6 controls the third N-tube NM2 to output a second positive temperature coefficient current signal according to the second adjustment code value; the... The third inverter 3431 and the eighth P-tube PM7 control the fourth P-tube PM3 to output the third negative temperature coefficient current signal according to the third adjustment code value; the eighth N-tube NM7 controls the fourth N-tube NM4 to output the third positive temperature coefficient current signal according to the third adjustment code value; the fourth inverter 3441 and the ninth P-tube PM8 control the fifth P-tube PM4 to output the fourth negative temperature coefficient current signal according to the fourth adjustment code value; the ninth N-tube NM8 controls the fifth N-tube PM5 to output the fourth positive temperature coefficient current signal according to the fourth adjustment code value.

[0067] The sum of the first, second, third, and fourth negative temperature coefficient current signals constitutes the target negative temperature coefficient current signal; similarly, the sum of the first, second, third, and fourth positive temperature coefficient current signals constitutes the target positive temperature coefficient current signal. By combining multiple sets of negative and positive temperature coefficient current signals and adjustment code values, the final target negative temperature coefficient current signal can have a wider temperature coefficient adjustment range, resulting in better temperature coefficient adjustment of the Hall current.

[0068] The current amplitude adjustment module 15 includes five sets of second N-tube current mirrors 16. Specifically, the five sets of second N-tube current mirrors 16 include a tenth N-tube NM9, an eleventh N-tube NM10, a twelfth N-tube NM11, a thirteenth N-tube NM12, a fourteenth N-tube NM13, and a fifteenth N-tube NM14 connected in parallel. Among them, the tenth N-tube NM9 and the eleventh N-tube NM10 form the first set of second N-tube current mirrors 16, the tenth N-tube NM9 and the twelfth N-tube NM11 form the second set of second N-tube current mirrors 16, the tenth N-tube NM9 and the thirteenth N-tube NM12 form the third set of second N-tube current mirrors 16, the tenth N-tube NM9 and the fourteenth N-tube NM13 form the fourth set of second N-tube current mirrors 16, and the tenth N-tube NM9 and the fifteenth N-tube NM14 form the fifth set of second N-tube current mirrors 16. Among them, the tenth N tube NM9 and the eleventh N tube NM10 form the first group of second N tube current mirrors 16, which simultaneously serve as the output current mirror of the sum of the target negative temperature coefficient current signal and the target positive temperature coefficient current signal.

[0069] The input terminals of the tenth N transistor NM9, the eleventh N transistor NM10, the twelfth N transistor NM11, the thirteenth N transistor NM12, the fourteenth N transistor NM13, and the fifteenth N transistor NM14 are all connected between the drain of the sixth P transistor PM5 and the source of the sixth N transistor NM5, between the drain of the seventh P transistor PM6 and the source of the seventh N transistor NM6, between the drain of the eighth P transistor PM7 and the source of the eighth N transistor NM7, and between the drain of the ninth P transistor PM8 and the source of the ninth N transistor NM8.

[0070] The current amplitude adjustment module 35 also includes four sets of second switch units 17 and a second adjustment code terminal group 38. The four sets of second switch units 17 respectively include the sixteenth N transistor NM15, the seventeenth N transistor NM16, the eighteenth N transistor NM17, and the nineteenth N transistor NM18. The second adjustment code terminal group 38 includes the fifth adjustment code terminal 381, the sixth adjustment code terminal 382, ​​the seventh adjustment code terminal 383, and the eighth adjustment code terminal 384.

[0071] Specifically, the sixteenth N-transistor NM15 generates a first current amplitude adjustment signal based on the fifth adjustment code value of the fifth adjustment code terminal 381, the target negative temperature coefficient current signal, and the target positive temperature coefficient current signal; the seventeenth N-transistor NM16 generates a second current amplitude adjustment signal based on the sixth adjustment code value of the sixth adjustment code terminal 382, ​​the target negative temperature coefficient current signal, and the target positive temperature coefficient current signal; the eighteenth N-transistor NM17 generates a third current amplitude adjustment signal based on the seventh adjustment code value of the seventh adjustment code terminal 383, the target negative temperature coefficient current signal, and the target positive temperature coefficient current signal; and the nineteenth N-transistor NM18 generates a fourth current amplitude adjustment signal based on the eighth adjustment code value of the eighth adjustment code terminal 384, the target negative temperature coefficient current signal, and the target positive temperature coefficient current signal.

[0072] The sum of the first, second, third, and fourth current amplitude adjustment signals constitutes the target current amplitude adjustment signal. By combining multiple sets of negative temperature coefficient current signals, multiple sets of positive temperature coefficient current signals, and multiple sets of adjustment codes, the final target current amplitude adjustment signal achieves a better effect in adjusting the amplitude of the original Hall current.

[0073] The zero temperature coefficient current regulation module 19 includes two symmetrical and parallel connected tenth P transistors PM9 and eleventh P transistors PM10, which are connected to the zero temperature coefficient current signal and connected to the input terminals of the first P transistor current mirror 110 and the tenth N transistors NM9, eleventh N transistors NM10, twelfth N transistors NM11, thirteenth N transistors NM12, fourteenth N transistors NM13 and fifteenth N transistors NM14, for generating a target zero temperature coefficient current signal based on the zero temperature coefficient current signal.

[0074] Additionally, it should be noted that the first P-tube PM0 has 1 PMOS transistor, the second P-tube PM1 has 1 PMOS transistor, the third P-tube PM2 has 2 PMOS transistors, the fourth P-tube PM3 has 4 PMOS transistors, and the fifth P-tube PM5 has 8 PMOS transistors; the first N-tube NM0 has 1 NMOS transistor, the second N-tube NM1 has 1 NMOS transistor, the third N-tube NM2 has 2 NMOS transistors, the fourth N-tube NM3 has 4 NMOS transistors, and the fifth N-tube NM4 has 8 NMOS transistors; the tenth P-tube PM9 has 1 PMOS transistor, and the eleventh P-tube PM10 has 1 PMOS transistor.

[0075] The tenth N-transistor NM9 has 1 NMOS transistor, the eleventh N-transistor NM10 has 1 NMOS transistor, the twelfth N-transistor NM11 has 2 NMOS transistors, the thirteenth N-transistor NM12 has 4 NMOS transistors, the fourteenth N-transistor NM13 has 8 NMOS transistors, and the fifteenth N-transistor NM14 has M0 NMOS transistors (the number is set according to requirements).

[0076] Specifically, if the negative temperature coefficient current signal is NTAT, the positive temperature coefficient current signal is PTAT, and the zero temperature coefficient current signal is ZTAT, then the sixth P-tube PM5 receives the first adjustment code value T_sel1, and according to the negative temperature coefficient current signal NTAT and the number of PM1, obtains the first negative temperature coefficient current signal: NTAT × T_sel1; the seventh P-tube PM6 receives the second adjustment code value T_sel2, and according to the negative temperature coefficient current signal NTAT and the number of PM2, obtains the second negative temperature coefficient current signal: 2 × NTAT × T_sel2; the eighth ...1, and according to the second adjustment code value T_sel1, obtains the second negative temperature coefficient current signal: NTAT × T_sel1; the seventh P-tube PM6 receives the second adjustment code value T_sel2, and according to the second adjustment code value T_sel1, obtains the second negative temperature coefficient current signal: NTAT × T_sel1; the eighth P-tube PM6 receives the second adjustment code value T_sel1, and according to the second adjustment code value T_sel1, obtains the second negative temperature coefficient current signal: NTAT × T_sel1; the eighth P-tube PM6 receives the second adjustment code PM7 receives the third adjustment code value T_sel3 and, based on the negative temperature coefficient current signal NTAT and the number of PM7s, obtains the third negative temperature coefficient current signal: 4×NTAT×T_sel3; the ninth P-tube PM8 receives the fourth adjustment code value T_sel4 and, based on the negative temperature coefficient current signal NTAT and the number of PM8s, obtains the fourth negative temperature coefficient current signal: 8×NTAT×T_sel4; the final target negative temperature coefficient current signal is: NTAT×(T_sel1+2×T_sel2+4×T_sel3+8×T_sel4).

[0077] At this time, the sixth N-transistor NM5 receives the first adjustment code value T_sel1, and according to the positive temperature coefficient current signal PTAT and the number of NM1, obtains the first positive temperature coefficient current signal: -PTAT×T_sel1; the seventh N-transistor NM6 receives the second adjustment code value T_sel2, and according to the positive temperature coefficient current signal NTAT and the number of NM2, obtains the second positive temperature coefficient current signal: -2×PTAT×T_sel2; the eighth N-transistor NM7 receives the third adjustment code value T_sel3, and according to the positive temperature coefficient current signal PTAT and the number of NM1, obtains the second positive temperature coefficient current signal: -2×PTAT×T_sel2; The coefficient current signal is determined by the number of NTAT and NM7, resulting in the third positive temperature coefficient current signal: -4×PTAT×T_sel3; the ninth N transistor NM8 receives the fourth adjustment code value T_sel4, and based on the positive temperature coefficient current signal being NTAT and the number of NM8, obtains the fourth positive temperature coefficient current signal: -8×PTAT×T_sel4; the final target positive temperature coefficient current signal is: -PTAT×(T_sel1+2×T_sel2+4×T_sel3+8×T_sel4).

[0078] Since PM9 and PM10 each have one PMOS transistor, the target zero temperature coefficient current signal is: ZTAT.

[0079] The final current signal flowing to the tenth transistor NM9 is: I NM9 =(NTAT-PTAT)×(T_sel1+2×T_sel2+4×T_sel3+8×T_sel4)+ZTAT;

[0080] to I NM9 The derivative yields the expression for the target temperature coefficient as: (KN - KP) × (T_sel1 + 2 × T_sel2 + 4 × T_sel3 + 8 × T_sel4); where KN is a negative temperature coefficient (KN < 0), and KP is a positive temperature coefficient (KP > 0). KN and KP are determined by the process characteristics. Therefore, the final target temperature coefficient is smaller than KN and smaller than -KP.

[0081] The sixteenth NMOS transistor NM15 receives the fifth adjustment code value A_sel1, and according to I... NM9 And the number of NM10, to obtain the first current amplitude adjustment signal: I NM9 ×A_sel1; The seventeenth NMOS transistor NM16 receives the sixth adjustment code value A_sel2, and according to I NM9 And the number of NM11, to obtain the second current amplitude adjustment signal: 2×I NM9 ×A_sel2; The eighteenth NMOS transistor NM17 receives the seventh adjustment code value A_sel3, and according to I NM9 And the number of NM12, to obtain the second current amplitude adjustment signal: 4×I MM9 ×A_sel3; The nineteenth NMOS transistor NM18 receives the eighth adjustment code value A_sel4, and according to I NM9 And the number of NM13, to obtain the second current amplitude adjustment signal: 8×I NM9 ×A_sel4; then the target current amplitude adjustment signal is I. hall =I NM9 ×(A_sel1+2×A_sel2+4×A_sel3+8×A_sel4). The current amplitude of the Hall effect circuit is adjusted based on the values ​​of A_sel1 to A_sel4. Furthermore, if the current values ​​of PTAT and NTAT are equal at room temperature, then I... hall Temperature coefficient adjustment and current amplitude adjustment are independent of each other.

[0082] It should be noted that, as Figure 4As shown, the startup circuit consists of R0, NM21, NM22, and NM20. When the chip is powered on, the enable signal ENB transitions from a high to a low potential, and the gate potential of NM22 also transitions from a high to a low potential. When the gate voltage of NM22 is sufficiently low, the current mirror composed of PM20 and PM21 starts working and generates PTAT. After PTAT is established, the gate voltage of NM22 becomes sufficiently low, and NM22 is turned off.

[0083] The principle of PTAT generation is as follows: the currents of NPN1 and NPN2 are provided by a pair of current mirrors PM20 and PM21 respectively, and the currents of the two mirrors are equal, but the ratio of the number of NPN1 to NPN2 is 1:m; according to the circuit principle, the voltage drop across R2 is V. T If ln(m), then the current flowing through R1 is: In the above formula, V T Since the current has a positive temperature coefficient and the other parameters have zero temperature coefficients, the current is positive temperature coefficient. The current mirrors connected to the gate of PM1 are all PTAT currents, which are positive temperature coefficient current signals.

[0084] The principle of NTAT generation is as follows: The voltage across R2 is the gate-source voltage of NPN3, which is the voltage VBE of a PN junction. Therefore, the current flowing through R2 is: In the above formula, V BE Since R2 has a negative temperature coefficient and R2 has a zero temperature coefficient, this current is a negative temperature coefficient current signal.

[0085] The current mirrors connected to the gate of PM22 are all NTAT currents. The NTAT current generation circuit includes a negative feedback stabilization loop, which is composed of R2, NPN3, NM23, PM24, PM22, C0, and R3. Among them, C0 and R3 are Miller feedback.

[0086] Based on the temperature characteristics of PTAT and NTAT, by selecting appropriate coefficients x and y, ZTAT can be obtained: ZTAT=x×PTAT+y×NTAT.

[0087] The present invention provides a Hall sensor, including the Hall current adjustment circuit of the present invention. For details, please refer to the parameters and modules in any embodiment of the Hall current adjustment circuit described above, which will not be repeated here.

[0088] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. Similarly, for the sake of brevity and to aid in understanding one or more aspects of the invention, in the description of exemplary embodiments of the invention above, various features of the embodiments are sometimes grouped together in a single embodiment, figure, or description thereof. The claims, which follow the detailed description, are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of the invention.

[0089] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A Hall current regulating circuit, characterized in that, include: A negative temperature coefficient current regulation module is connected to a negative temperature coefficient current signal and is used to generate a target negative temperature coefficient current signal based on the negative temperature coefficient current signal. A positive temperature coefficient current regulation module is connected to a positive temperature coefficient current signal and is used to generate a target positive temperature coefficient current signal based on the positive temperature coefficient current signal. The first adjustment code terminal is used to input the first adjustment code value; The first switch module is connected to the first adjustment code terminal, the negative temperature coefficient current adjustment module and the positive temperature coefficient current adjustment module, and is used to control the negative temperature coefficient current adjustment module to output the target negative temperature coefficient current signal according to the first adjustment code value, and to control the positive temperature coefficient current adjustment module to output the target positive temperature coefficient current signal. The negative temperature coefficient current adjustment module includes at least one set of first P-tube current mirrors; the first P-tube current mirrors are used to receive the negative temperature coefficient current signal to generate the target negative temperature coefficient current signal. The positive temperature coefficient current regulation module includes at least one set of first N-tube current mirrors; The first N-tube current mirror is used to receive the positive temperature coefficient current signal in order to generate the target positive temperature coefficient current signal. The first switching module includes at least one set of first switching units. Each first switching unit includes an inverter, a first PMOS transistor, and a first NMOS transistor. The input terminal of the inverter is connected to the first adjustment code terminal, and the output terminal of the inverter is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is connected to the first P-transistor current mirror. The gate of the first NMOS transistor is connected to the first adjustment code terminal, the drain is connected to the first N-transistor current mirror, and the source is connected to the drain of the first PMOS transistor. The inverter and the first PMOS transistor control the first P-transistor current mirror to output the target negative temperature coefficient current signal according to the first adjustment code value; the first NMOS transistor controls the first N-transistor current mirror to output the target positive temperature coefficient current signal according to the first adjustment code value.

2. The Hall current regulating circuit according to claim 1, characterized in that, The adjustment circuit further includes at least one set of second N-channel current mirrors. The input terminal of the second N-channel current mirror is connected to the drain of the first PMOS transistor and the source of the first NMOS transistor. The second N-channel current mirror is used to output the target negative temperature coefficient current signal and the target positive temperature coefficient current signal.

3. The Hall current adjustment circuit according to claim 1, characterized in that, The adjustment circuit further includes a current amplitude adjustment module, which includes at least one set of second N-tube current mirrors, at least one set of second switching units, and a second adjustment code terminal for receiving the second adjustment code value. The second N-tube current mirror is connected to the negative temperature coefficient current adjustment module and the positive temperature coefficient current adjustment module through the first switching module; the second switching unit is connected to the second adjustment code terminal and the second N-tube current mirror. The second switching unit generates a target current amplitude adjustment signal based on the second adjustment code value, the target negative temperature coefficient current signal, and the target positive temperature coefficient current signal.

4. The Hall current regulating circuit according to claim 2, characterized in that, The adjustment circuit also includes a zero temperature coefficient current adjustment module, which receives a zero temperature coefficient current signal and is connected to the input terminal of the second N-tube current mirror. It is used to generate a target zero temperature coefficient current signal based on the zero temperature coefficient current signal and output it to the second N-tube current mirror.

5. The Hall current regulating circuit according to claim 1, characterized in that, The number of groups of the first P-tube current mirrors is matched with the number of the inverters and the first PMOS transistors.

6. The Hall current adjustment circuit according to claim 1, characterized in that, The number of groups of the first N-channel current mirrors matches the number of NMOS transistors.

7. The Hall current regulating circuit according to claim 1, characterized in that, At least one set of the first P-tube current mirrors includes two symmetrical and parallel-connected second PMOS transistors, one of which is used to receive the negative temperature coefficient current signal, and the other is used to connect to the first PMOS transistor.

8. The Hall current adjustment circuit according to claim 1, characterized in that, At least one set of the first N-channel current mirrors includes two symmetrical and parallel-connected second NMOS transistors, one of which is used to receive the positive temperature coefficient current signal, and the other is used to connect to the first NMOS transistor.

9. A Hall sensor, characterized in that, Includes a Hall current regulating circuit as described in any one of claims 1-8.

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