Method for manufacturing a semiconductor structure and structure thereof

Abstract

The embodiment of the present disclosure relates to the field of semiconductor, and provides a manufacturing method of a semiconductor structure and a structure thereof, wherein the manufacturing method of the semiconductor structure comprises the following steps: providing a substrate, the substrate comprising an array region and a peripheral region; forming an insulating layer on the surface of the substrate in the array region; forming a conductive layer on the top surface of the insulating layer and the top surface of the substrate in the peripheral region; forming a protective layer covering the top surface of the conductive layer, the thickness of the protective layer in the array region is less than the thickness of the protective layer in the peripheral region, and the top surface of the protective layer in the array region is flush with the top surface of the protective layer in the peripheral region; and patterning the protective layer, the conductive layer and the insulating layer in the same step to form a bit line in the array region and a gate in the peripheral region. The bit line in the array region and the gate in the peripheral region can be formed in the same step.

Description

1.1.1 Technical Field This disclosure relates to the field of semiconductors, and in particular to a method for fabricating a semiconductor structure and the structure thereof. 1.1.2 Background Technology Generally, semiconductor structures are divided into different regions according to their functions. For example, semiconductor structures are divided into core regions, peripheral regions, array regions, etc.

[0003] The core area is the region used to form the core circuit, which generally includes the core PMOS transistor, the core NMOS transistor, and the corresponding circuits that control the corresponding transistors; the peripheral area is the region used to form the peripheral circuit, which generally includes the peripheral PMOS transistor, the peripheral NMOS transistor, and the corresponding circuits that control the corresponding transistors; the array area is the region used to form the memory array, which generally includes word lines, bit lines, and memory capacitors.

[0004] However, currently, when forming semiconductor structures, the peripheral region structure is usually formed first, and then the array region structure is formed. 1.1.3 Summary of the Invention This disclosure provides a method for fabricating a semiconductor structure, which can at least form the bit lines of the array region and the gate of the peripheral region in the same step.

[0006] According to some embodiments of this disclosure, one aspect of this disclosure provides a method for fabricating a semiconductor structure, including providing a substrate, the substrate including an array region and a peripheral region; forming an insulating layer located on the surface of the substrate in the array region; forming a conductive layer located on the top surface of the insulating layer and the top surface of the substrate in the peripheral region; forming a protective layer covering the top surface of the conductive layer, the thickness of the protective layer located in the array region being less than the thickness of the protective layer located in the peripheral region, and the top surface of the protective layer located in the array region being flush with the top surface of the protective layer located in the peripheral region; and simultaneously patterning the protective layer and the conductive layer to form bit lines in the array region and gates in the peripheral region.

[0007] In some embodiments, the conductive layers formed in the peripheral region and the array region have the same thickness, and the top surface of the conductive layer in the array region is higher than the top surface of the conductive layer in the peripheral region.

[0008] In some embodiments, the thickness difference between the protective layer located in the peripheral region and the protective layer located in the array region is 3~40nm.

[0009] In some embodiments, the step of patterning the protective layer and the conductive layer includes: forming a first hard mask layer located on the top surface of the protective layer; forming a first intermediate layer located on the top surface of the first hard mask layer; forming a first mask pattern located on the top surface of the first intermediate layer, wherein the first mask pattern located in the array region is different from the first mask pattern located in the peripheral region; and patterning the protective layer and the conductive layer using the first mask pattern as a mask.

[0010] In some embodiments, the method of forming the first mask pattern includes: forming a second mask pattern located on the surface of the first intermediate layer; forming an initial mask layer covering the sidewalls and top surface of the second mask pattern, and the initial mask layer also covering the surface of the first intermediate layer exposed by the second mask pattern; etching the initial mask layer to retain the initial mask layer on the sidewalls of the second mask pattern as the first mask pattern.

[0011] In some embodiments, before patterning the initial mask layer, the method further includes: forming a third hard mask layer that covers the surface of the initial mask layer; removing the third hard mask layer located in the peripheral region; depositing the initial mask layer material; and increasing the thickness of the initial mask layer located in the peripheral region.

[0012] In some embodiments, the method of forming the second mask pattern includes: forming a second hard mask layer covering the top surface of the first intermediate layer; forming a second intermediate layer covering the top surface of the second hard mask layer; and etching the second hard mask layer and the second intermediate layer to form the second mask pattern.

[0013] In some embodiments, etching the second hard mask layer and the second intermediate layer includes: forming a first pattern layer, the first pattern layer being located on the surface of the second intermediate layer, and the pattern of the first pattern layer located in the array region being different from the pattern of the first pattern layer located in the peripheral region; patterning the second hard mask layer and the second intermediate layer using the first pattern layer as a mask until the surface of the first intermediate layer is exposed, the remaining second hard mask layer and the second intermediate layer constituting the second mask pattern.

[0014] In some embodiments, the method of forming the insulating layer includes: sequentially forming a first insulating layer, a pad layer, and a second insulating layer on the surface of the substrate; removing a portion of the first insulating layer, a portion of the pad layer, and all of the second insulating layer; and retaining the first insulating layer and the pad layer located in the array region.

[0015] In some embodiments, a method for removing the second insulating layer and the padding layer and the first insulating layer located in the peripheral region includes: forming a second patterned layer that covers the surface of the second insulating layer in the array region; removing the second insulating layer and the padding layer located in the peripheral region; removing the second patterned layer; and removing the second insulating layer located in the array region and the first insulating layer located in the peripheral region in the same step.

[0016] In some embodiments, the total thickness of the formed padding layer and the first insulating layer is 3~40 nm.

[0017] In some embodiments, the thickness of the protective layer located in the peripheral region is a first thickness, and the thickness of the protective layer located in the array region is a second thickness. The difference between the first thickness and the second thickness is equal to the total thickness of the padding layer and the first insulating layer.

[0018] In some embodiments, before forming the conductive layer, the method further includes forming a gate dielectric layer located on the substrate surface of the peripheral region.

[0019] In some embodiments, the method of forming the gate dielectric layer includes: oxidizing the substrate of the peripheral region, or forming the gate dielectric layer by atomic layer deposition, wherein the thickness of the gate dielectric layer is 1~3 nm.

[0020] According to some embodiments of this disclosure, another aspect of this disclosure also provides a semiconductor structure that can be formed using the above-described method.

[0021] The technical solution provided by the embodiments of this disclosure has at least the following advantages: after forming the conductive layer, a protective layer with a flush top surface is formed. By forming a protective layer with a thickness smaller than that of the protective layer of the outer region, the protective layer of the array region can be completely etched in the subsequent etching process, while the protective layer of the outer region is partially retained. Thus, when the conductive layer of the array region is etched, the protective layer of the outer region is still being etched, resulting in different etching selectivity ratios between the outer region and the array region. By controlling the etching process, the bit lines of the array region and the gate of the outer region can be formed in the same step, thereby reducing the process time of the entire semiconductor structure fabrication method. 1.1.4 Attached Figure Description One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figures 1 to 11 This is a schematic diagram of the steps in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure. 1.1.5 Detailed Implementation Currently, when forming semiconductor structures, the gate is usually formed in the peripheral region first, and then the bit lines of the array region are formed. However, this method requires separate deposition of masks and separate exposure and etching, which results in many process steps, long process time, and high production cost.

[0025] This disclosure provides a semiconductor fabrication method. By forming protective layers of different heights in the array region and the peripheral region, and by forming a protective layer in the array region with a thickness lower than that in the peripheral region, after the protective layer in the array region is etched during the subsequent bit line and gate formation process, a portion of the protective layer remains in the peripheral region, resulting in different etch selectivity ratios. By controlling the etching process, bit lines can be formed simultaneously with the gate formation, thereby reducing the number of process steps and the overall process time.

[0026] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the disclosure. However, the technical solutions claimed in this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0027] refer to Figure 1 , Figure 1 This is a top view of a semiconductor structure provided in an embodiment of the present disclosure.

[0028] For details, please refer to Figure 1A substrate 100 is provided, comprising an array region 101 and a peripheral region 102. The array region 101 includes: active regions 110 spaced apart on the substrate 100; bit lines 120 spaced apart along the AA direction on the substrate 100 and extending perpendicularly to the AA direction; and word lines 130 spaced apart along the AA direction on the substrate 100 and extending perpendicularly to the AA direction. The peripheral region 102 does not have a specific structure. Figure 1 The illustration is shown below.

[0029] refer to Figure 2 and Figure 3 , Figure 2 For along Figure 1 The sectional views along the AA direction and the BB direction are shown. It should be noted that the sectional view along the AA direction is the sectional view of the array region 101 structure, and the sectional view along the BB direction is the sectional view of the outer region 102 structure. Figure 3 In order to be in Figure 2 The process steps are based on the above. An insulating layer 140 is formed, which is located on the surface of the substrate 100 of the array region 101.

[0030] For details, please refer to Figure 2 In some embodiments, the method of forming the insulating layer 140 includes: sequentially forming a first insulating layer 141, a pad layer 142, and a second insulating layer 143 on the surface of the substrate 100. The first insulating layer 141 covers the sidewalls and top surface of the active region 110 of the peripheral region 102, and the first insulating layer 141 also fills the gaps between adjacent active regions 110 within the array region 101. The pad layer 142 and the second insulating layer 143 are sequentially formed on the surface of the first insulating layer 141. The first insulating layer 141 can be used to isolate the memory cells in the array region 101 to prevent the memory cells from being too close to each other and causing them to conduct to each other, which would lead to a decrease in the performance of the semiconductor structure. The pad layer 142 is used to isolate the circuit structure in the circuit region (not shown in the figure) to prevent the circuit structure from being interconnected, thereby preventing the data disorder caused by the interconnection of the circuit structure from affecting the performance of the semiconductor structure. The second insulating layer 143 can be used to fill the semiconductor structure, thereby making the semiconductor structure have a better morphology. The second insulating layer 143 can also isolate adjacent active regions 110, thereby forming discrete active regions 110.

[0031] In some embodiments, the first insulating layer 141 and the second insulating layer 143 can be made of the same material, which is silicon oxide; the padding layer 142 can be made of silicon nitride or silicon oxynitride, etc. By forming the first insulating layer 141, the padding layer 142 and the second insulating layer 143, an ONO (Oxide-Nitride-Oxide) structure can be formed, that is, an oxide-nitride-oxide structure. Forming an ONO structure can provide a higher relative permittivity, a higher breakdown electric field and a lower leakage current characteristic.

[0032] refer to Figure 3 Part of the first insulating layer 141, part of the padding layer 142 and all of the second insulating layer 143 are removed, while the first insulating layer 141 and the padding layer 142 located in the array region 101 are retained.

[0033] In some embodiments, the method of removing the padding layer 142 and the first insulating layer 141 located in the second insulating layer 143 and the peripheral region 102 includes: forming a second patterned layer (not shown) covering the surface of the second insulating layer 143 in the array region 101; removing the second insulating layer 143 and the padding layer 142 located in the peripheral region 102; removing the second patterned layer; and removing the second insulating layer 143 in the array region 101 and the first insulating layer 141 in the peripheral region 102 in the same step.

[0034] By forming a second patterned layer covering the array region 101, it is possible to avoid removing the second insulating layer 143 and the pad layer 142 located in the array region 101 during the removal of the second insulating layer 143 and the pad layer 142 in the peripheral region 102, and then removing the second patterned layer. In the same step, the second insulating layer 143 of the array region 101 and the first insulating layer 141 located in the peripheral region 102 are removed, which can reduce the process steps of the semiconductor structure fabrication method.

[0035] It is understood that the second insulating layer 143 and the pad layer 142 of the peripheral region 102 can be removed by etching, and the pad layer 142 can be used as an etching stop layer for etching the second insulating layer 143, and the first insulating layer 141 can be used as an etching stop layer for etching the pad layer 142.

[0036] In some embodiments, the total thickness of the formed pad layer 142 and the first insulating layer 141 is 3-40 nm, for example, 5 nm, 15 nm, or 25 nm. When the total thickness of the pad layer 142 and the first insulating layer 141 is less than 3 nm, the thickness difference is too small when forming the protective layer, making it difficult to form the bit lines of the array region 101 and the gate of the peripheral region 102. When the total thickness of the pad layer 142 and the first insulating layer 141 is greater than 40 nm, the thickness difference is too large when forming the protective layer, which may result in the bit lines of the array region 101 being formed before the gate of the peripheral region 102 is completed. As etching continues, some active regions 110 may be damaged. In other embodiments, the total thickness of the formed pad layer 142 and the first insulating layer 141 can also be other dimensions, which can be adjusted according to the actual situation.

[0037] refer to Figure 4 and Figure 5 A second mask pattern 150 is formed, which is located on the surface of the first intermediate layer 160. The second mask pattern 150 provides a process basis for subsequent patterning of gate and bit lines.

[0038] refer to Figure 4 A conductive layer 170 is formed, which is located on the top surface of the insulating layer 140 and the top surface of the substrate 100 of the peripheral region 102.

[0039] In some embodiments, before forming the conductive layer 170, a portion of the insulating layer 140 and a portion of the active region 110 are etched away, thereby providing a process basis for the subsequent formation of the bit line contact structure. During the formation of the conductive layer 170, the conductive layer 170 fills the depression formed by etching the insulating layer 140 and the active region 110.

[0040] In some embodiments, the conductive layer 170 may include a first conductive layer 171, a diffusion barrier layer 172, and a second conductive layer 173. The first conductive layer 171 is located on the top surface of the insulating layer 140 and fills the recess formed by etching the insulating layer 140 and the active region 110. The diffusion barrier layer 172 covers the top surface of the first conductive layer 171, and the second conductive layer 173 covers the top surface of the diffusion barrier layer 172. By providing the first conductive layer 171, it is possible to avoid direct transmission of electrical signals from the semiconductor material to the metal material during subsequent signal transmission, thus preventing abnormalities during signal transmission. The first conductive layer 171 can act as a transition layer, thereby improving the reliability of the semiconductor structure. By providing the diffusion barrier layer 172, it is possible to prevent metal ions from the metal material of the second conductive layer 173 from diffusing into the first conductive layer 171 and the substrate 100, thereby preventing contamination of the first conductive layer 171 and the substrate 100.

[0041] In some embodiments, the material of the first conductive layer 171 may be a semiconductor material, such as polycrystalline silicon; the material of the diffusion barrier layer 172 may be titanium nitride; and the material of the second conductive layer 173 may be a metallic material, such as tungsten.

[0042] In some embodiments, the conductive layer 170 formed in the peripheral region 102 and the array region 101 has the same thickness, and the top surface of the conductive layer 170 in the array region 101 is higher than the top surface of the conductive layer 170 in the peripheral region 102. It is understood that the conductive layer 170 is deposited simultaneously in the peripheral region 102 and the array region 101 during its formation. Therefore, under the same deposition rate and within the same time frame, the conductive layer 170 has the same thickness. Since the conductive layer 170 in the array region 101 is deposited on the surface of the insulating layer 140, even with the same thickness in both the peripheral region 102 and the array region 101, the top surface of the conductive layer 170 in the array region 101 is higher than the top surface of the conductive layer 170 in the peripheral region 102. By setting the thickness of the conductive layer 170 formed in the peripheral region 102 and the array region 101 to be the same, it is easier to control subsequent etching processes, allowing for the formation of bit lines and gates in the same step.

[0043] In some embodiments, before forming the conductive layer 170, a gate dielectric layer 230 is formed, the gate dielectric layer 230 being located on the surface of the substrate 100 of the peripheral region 102. Forming the gate dielectric layer 230 can prevent subsequent formation of a gate that directly contacts the substrate, thus avoiding semiconductor structure abnormalities.

[0044] In some embodiments, the method for forming the gate dielectric layer 230 includes: oxidizing the substrate 100 of the peripheral region 102, or forming the gate dielectric layer 230 by atomic layer deposition, wherein the thickness of the gate dielectric layer 230 is 1-3 nm. Atomic layer deposition allows for better control of the thickness of the formed gate dielectric layer 230 and results in better uniformity. Oxidation provides higher density and better performance. It is understood that when the thickness of the gate dielectric layer 230 is less than 1 nm, leakage or breakdown problems may occur; when the thickness of the gate dielectric layer 230 is greater than 3 nm, it may lead to an increase in the turn-on voltage. In other embodiments, the thickness of the formed gate dielectric layer can also be other dimensions, which can be adjusted according to actual conditions.

[0045] In some embodiments, the system further includes a protective layer 180 covering the top surface of the conductive layer 170. The thickness of the protective layer 180 located in the array region 101 is less than the thickness of the protective layer 180 located in the peripheral region 102, and the top surface of the protective layer 180 located in the array region 101 is flush with the top surface of the protective layer 180 located in the peripheral region 102.

[0046] In some embodiments, the formation of the protective layer 180 further includes: forming an initial protective layer in which, under the same deposition rate and within the same time period, the initial protective layer located in the array region 101 has the same thickness as the initial protective layer located in the peripheral region 102, and the top surface height of the initial protective layer located in the array region 101 is higher than the top surface height of the initial protective layer located in the peripheral region 102; and removing part of the initial protective layer by chemical mechanical polishing so that the thickness of the protective layer 180 located in the array region 101 is less than the thickness of the protective layer 180 located in the peripheral region 102, and the top surface of the protective layer 180 located in the array region 101 is flush with the top surface of the protective layer 180 located in the peripheral region 102. By forming a protective layer 180 with a thickness less than that of the protective layer 180 in the peripheral region 102, a process basis can be provided for the subsequent formation of bit lines and gates in the same step. By forming protective layers 180 with different thicknesses, after the protective layer 180 in the array region 101 is etched during the subsequent etching process, a portion of the protective layer in the peripheral region 102 will still exist, thereby compensating for the time taken to form the bit line contact structure in the array region 101. This allows the bit line structure and bit line contact structure of the array region 101 to be formed simultaneously with the formation of the gate in the peripheral region 102.

[0047] In other words, during the formation of conductive layer 170, a portion of insulating layer 140 and a portion of substrate 100 are etched to form bit line contact structures. Therefore, during the formation of the first conductive layer 171, a portion of the first conductive layer 171 also fills the grooves formed by etching insulating layer 140 and a portion of substrate 100. This portion of the first conductive layer 171 filling the grooves can be used to form bit line contact structures. Thus, during the formation of the first conductive layer 171, the thickness of the first conductive layer 171 located on the surface of substrate 100 in array region 101 is greater than the thickness of the first conductive layer 171 in the peripheral region, and the thickness of the first conductive layer 171 located on the surface of insulating layer 140 is equal to the thickness of the first conductive layer 171 in the peripheral region. Subsequently, during the etching process to form bit lines, the etching time required for the first conductive layer 171 in array region 101 is relatively high. Therefore, by setting a thicker protective layer 180 in peripheral region 102, bit lines and gates can be formed in the same step by controlling the different etching selectivity ratios.

[0048] In some embodiments, the thickness difference between the protective layer 180 located in the peripheral region 102 and the protective layer 180 located in the array region 101 is 3-40 nm. It is understood that when the thickness difference between the protective layer 180 in the peripheral region 102 and the protective layer 180 in the array region 101 is less than 3 nm, the thickness of the protective layer 180 used to control the etching selectivity is too thin. Due to the structural differences between the peripheral region 102 and the array region 101, the gate of the peripheral region 102 may have been formed, while the conductive layer 170 of the array region 101 may not have been completely etched. To complete the etching process of the array region 101, the structure of the peripheral region 102 may be damaged. When the thickness difference between the protective layer 180 in the peripheral region 102 and the protective layer 180 in the array region 101 is greater than 40 nm, the bit lines of the array region 101 may have been etched, while the conductive layer 170 of the peripheral region 102 may not have been completely etched. To complete the etching process of the peripheral region 102, the structure of the array region 101 may be damaged. In other embodiments, the thickness difference between the protective layer 180 of the outer perimeter region 102 and the protective layer 180 of the array region 101 can also be other dimensions, which can be adjusted according to the actual situation.

[0049] In some embodiments, the thickness of the protective layer 180 located in the peripheral region 102 is a first thickness, and the thickness of the protective layer 180 located in the array region 101 is a second thickness. The difference between the first thickness and the second thickness is equal to the total thickness of the pad layer 142 and the first insulating layer 141. By setting the difference between the first thickness and the second thickness to be equal to the total thickness of the pad layer 142 and the first insulating layer 141, the top surface of the protective layer 180 of the array region 101 can be flush with the top surface of the protective layer 180 of the peripheral region 102. This allows the peripheral region 102 to still have a portion of the protective layer after the protective layer 180 of the array region 101 is etched during the subsequent etching process. This controls the etching selectivity ratio between the peripheral region 102 and the array region 101, so that the bit lines of the array region and the gate of the peripheral region are formed as simultaneously as possible in the same step.

[0050] In some embodiments, after forming the protective layer 180, the method further includes: forming a first hard mask layer 190, the first hard mask layer 190 being located on the top surface of the protective layer 180; and forming a first intermediate layer 160, the first intermediate layer 160 being located on the top surface of the first hard mask layer 190.

[0051] In some embodiments, the method further includes: forming a second hard mask layer 200, the second hard mask layer 200 covering the top surface of the first intermediate layer 160; and forming a second intermediate layer 210, the second intermediate layer 210 covering the top surface of the second hard mask layer 200. The formation of the second hard mask layer 200 and the second intermediate layer 210 provides a process basis for forming the second mask pattern.

[0052] In some embodiments, the second hard mask layer 200 is made of the same material as the first hard mask layer 190, which can be a spin-coated hard mask material, and the second intermediate layer 210 is made of the same material as the first intermediate layer 160, which can be silicon oxynitride.

[0053] In some embodiments, the method further includes forming a first patterning layer 220, which is located on the surface of the second intermediate layer 210, and the pattern of the first patterning layer 220 located in the array region 101 is different from the pattern of the first patterning layer 220 located in the peripheral region 102. Forming the first patterning layer 220 can provide a process basis for the subsequent formation of the second mask pattern.

[0054] refer to Figure 5 The second hard mask layer 200 and the second intermediate layer 210 are etched to form the second mask pattern 150. The formation of the second mask pattern 150 provides a process basis for the subsequent formation of the first mask pattern.

[0055] In some embodiments, etching the second hard mask layer 200 and the second intermediate layer 210 includes: patterning the second hard mask layer 200 and the second intermediate layer 210 using the first patterning layer 220 as a mask until the surface of the first intermediate layer 160 is exposed, and the remaining second hard mask layer 200 and the second intermediate layer 210 constitute the second mask pattern 150. Etching the second hard mask layer 200 and the second intermediate layer 210 through a mask can make the formed second mask pattern 150 more precise.

[0056] refer to Figures 6 to 11 In the same step, the protective layer 180 and the conductive layer 170 are patterned to form bit lines 290 in the array region 101 and gates 240 in the peripheral region 102.

[0057] For details, please refer to Figures 6 to 9 The steps of patterning the protective layer 180, conductive layer 170, and insulating layer 140 include: forming a first mask pattern 250, the first mask pattern 250 being located on the top surface of the first intermediate layer 160, and the first mask pattern 250 located in the array region 101 being different from the first mask pattern 250 located in the peripheral region 102. Forming different first mask patterns 250 provides mask patterns for subsequent formation of bit lines and gates.

[0058] refer to Figure 6 An initial mask layer 260 is formed, which covers the sidewalls and top surface of the second mask pattern 150, and also covers the surface of the first intermediate layer 160 exposed by the second mask pattern 150. The formation of the initial mask layer 260 provides a process basis for the subsequent formation of the first mask pattern.

[0059] In some embodiments, after forming the initial mask layer 260, the method further includes forming a third hard mask layer 270, which covers the surface of the initial mask layer 260. Forming the third hard mask layer 270 can provide a process basis for subsequently forming the first mask pattern required for the peripheral region 102.

[0060] In some embodiments, after forming the initial mask layer 260, the method further includes forming a third pattern layer 280 on the surface of the third hard mask layer 270 in the array region 101. The third hard mask layer 270 can be used as a mask for subsequent etching of the third hard mask layer 270 in the peripheral region 102.

[0061] refer to Figure 7 Using the third pattern layer 280 as a mask, the third hard mask layer 270 located in the peripheral region 102 is etched to remove the third hard mask layer 270 located in the peripheral region 102, thereby exposing the surface of the initial mask layer 260 in the peripheral region 102. By etching the third hard mask layer 270 in the peripheral region 102, the third hard mask layer 270 of the array region 101 is retained, so that the film thickness of the array region 101 will not increase during the subsequent deposition of the initial mask layer material. It can be understood that the initial mask layer 260 serves as the base for the subsequent formation of the first mask pattern. Since the thickness of the initial mask layer 260 is the width of the first mask pattern, the width of the bit line to be formed in the array region 101 is different from the width of the gate to be formed in the peripheral region 102. Therefore, it is necessary to increase the thickness of the initial mask layer 260 in the peripheral region 102, but not the thickness of the initial mask layer 260 in the array region 101. Therefore, by forming a third hard mask layer 270 on the array region 101, the thickness of the initial mask layer 260 in the peripheral region 102 is not affected at the same time.

[0062] In some embodiments, mask etching is performed on the third hard mask layer 270 located in the peripheral region 102 to expose the surface of the initial mask layer 260 of the peripheral region 102. The third pattern layer 280 is removed before mask etching is performed on the third hard mask layer 270 located in the peripheral region 102.

[0063] refer to Figure 8 The initial mask layer 260 material is deposited to increase the thickness of the initial mask layer 260 located in the peripheral region 102. Increasing the thickness of the initial mask layer 260 in the peripheral region 102 provides a process basis for the subsequent formation of the first mask pattern in the peripheral region 102.

[0064] In some embodiments, when the thickness of the initial mask layer 260 located in the peripheral region 102 is increased, an initial mask layer 260 is also formed on the top surface of the third hard mask layer 270 in the array region 101.

[0065] refer to Figure 9The initial mask layer 260 is etched, and the initial mask layer 260 on the sidewall of the second mask pattern 150 is retained as the first mask pattern 250. The formation of the first mask pattern 250 provides a process basis for the subsequent formation of bit lines and gates.

[0066] In some embodiments, after forming the first mask pattern 250, the method further includes removing the initial mask layer 260 and the third hard mask layer 270 from the top surface of the third hard mask layer 270 of the array region 101.

[0067] refer to Figure 10 and Figure 11 Using the first mask pattern 250 as a mask, a patterned protective layer 180 and a conductive layer 170 are formed.

[0068] refer to Figure 10 During the etching of the protective layer 180, the protective layer 180 of the array region 101 is completely etched, while the peripheral region 102 retains a portion of the protective layer 180. Thus, when the array region 101 etches the conductive layer 170, the peripheral region 102 is still etching the protective layer 180, thereby creating a difference in the etching selectivity between the peripheral region 102 and the array region 101. Furthermore, since the array region 101 also needs to etch a portion of the conductive layer 170 used to form the bit line contact structure, the gate of the peripheral region and the bit line of the array region can be formed simultaneously by controlling the difference in the thickness of the protective layer 180 and the difference in the etching selectivity.

[0069] refer to Figure 11 This forms bit line 290 and gate 240.

[0070] In some embodiments, the process of forming the gate 240 may include etching the gate dielectric layer 230; in other embodiments, the gate dielectric layer 230 may not be etched.

[0071] This embodiment of the invention forms a protective layer 180 with its top surface flush with the conductive layer 170. By forming a protective layer 180 with a thickness smaller than that of the protective layer 180 of the outer region 102, the protective layer 180 of the outer region 102 is still being etched during the etching of the conductive layer 170 of the array region 101. This results in different etching selectivity ratios for the outer region 102 and the array region 101. By controlling the etching process, the bit line 290 of the array region 101 and the gate 240 of the outer region 102 can be formed in the same step. This reduces the number of process steps in the entire semiconductor structure fabrication method, thereby reducing the overall process time of the semiconductor structure.

[0072] Another embodiment of this disclosure also provides a semiconductor structure that can be formed using some or all of the above steps.

[0073] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of the embodiments of this disclosure. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the embodiments of this disclosure; therefore, the scope of protection of the embodiments of this disclosure should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region and a peripheral region; An insulating layer is formed on the substrate surface of the array region; A conductive layer is formed, the conductive layer being located on the top surface of the insulating layer and on the top surface of the substrate in the peripheral region; A protective layer is formed, which covers the top surface of the conductive layer. The thickness of the protective layer located in the array region is less than the thickness of the protective layer located in the peripheral region, and the top surface of the protective layer located in the array region is flush with the top surface of the protective layer located in the peripheral region. In the same step, the protective layer and the conductive layer are patterned to form bit lines in the array region and gates in the peripheral region.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The conductive layers formed in the peripheral region and the array region have the same thickness, and the top surface of the conductive layer in the array region is higher than the top surface of the conductive layer in the peripheral region.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The thickness difference between the protective layer located in the peripheral region and the protective layer located in the array region is 3 to 40 nm.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The steps of graphically representing the protective layer and the conductive layer include: A first hard mask layer is formed, which is located on the top surface of the protective layer; A first intermediate layer is formed, which is located on the top surface of the first hard mask layer; A first mask pattern is formed, the first mask pattern is located on the top surface of the first intermediate layer, and the first mask pattern located in the array region is different from the first mask pattern located in the peripheral region; Using the first mask pattern as a mask, the protective layer and the conductive layer are patterned.

5. The method for fabricating a semiconductor structure according to claim 4, characterized in that, The method for forming the first mask pattern includes: A second mask pattern is formed, the second mask pattern being located on the surface of the first intermediate layer; An initial mask layer is formed, which covers the sidewalls and top surface of the second mask pattern, and also covers the surface of the first intermediate layer exposed by the second mask pattern; The initial mask layer is etched, leaving the initial mask layer on the sidewall of the second mask pattern as the first mask pattern.

6. The method for fabricating a semiconductor structure according to claim 5, characterized in that, Before graphically representing the initial mask layer, the method further includes: forming a third hard mask layer that covers the surface of the initial mask layer; removing the third hard mask layer located in the peripheral region; depositing the initial mask layer material; and increasing the thickness of the initial mask layer located in the peripheral region.

7. The method for fabricating a semiconductor structure according to claim 5, characterized in that, The method of forming the second mask pattern includes: forming a second hard mask layer, the second hard mask layer covering the top surface of the first intermediate layer; A second intermediate layer is formed, which covers the top surface of the second hard mask layer; The second hard mask layer and the second intermediate layer are etched to form the second mask pattern.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, Etching the second hard mask layer and the second intermediate layer includes: A first pattern layer is formed, which is located on the surface of the second intermediate layer, and the pattern of the first pattern layer located in the array region is different from the pattern of the first pattern layer located in the peripheral region. The second hard mask layer and the second intermediate layer are patterned using the first pattern layer as a mask until the surface of the first intermediate layer is exposed. The remaining second hard mask layer and the second intermediate layer constitute the second mask pattern.

9. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The method of forming the insulating layer includes: sequentially forming a first insulating layer, a pad layer and a second insulating layer on the surface of the substrate, removing a portion of the first insulating layer, a portion of the pad layer and all of the second insulating layer, and retaining the first insulating layer and the pad layer located in the array region.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, A method for removing the padding layer and the first insulating layer located in the second insulating layer and the peripheral region includes: forming a second patterned layer that covers the surface of the second insulating layer in the array region; Remove the second insulating layer and the padding layer located in the peripheral area; Remove the second graphics layer; In the same step, the second insulating layer located in the array region and the first insulating layer located in the peripheral region are removed.

11. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The total thickness of the formed padding layer and the first insulating layer is 3 to 40 nm.

12. The method for fabricating a semiconductor structure according to claim 11, characterized in that, The thickness of the protective layer located in the peripheral area is a first thickness, and the thickness of the protective layer located in the array area is a second thickness. The difference between the first thickness and the second thickness is equal to the total thickness of the padding layer and the first insulating layer.

13. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Before forming the conductive layer, the method further includes forming a gate dielectric layer located on the substrate surface of the peripheral region.

14. The method for fabricating a semiconductor structure according to claim 13, characterized in that, The method of forming the gate dielectric layer includes: oxidizing the substrate of the peripheral region, or forming the gate dielectric layer by atomic layer deposition, wherein the thickness of the gate dielectric layer is 1 to 3 nm.

15. A semiconductor structure, characterized in that, The semiconductor structure is formed using the fabrication method described in any one of claims 1 to 14.

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