Method for reducing random telegraph noise in nonvolatile memory by grouping and screening memory cells

Abstract

The present invention discloses a method for programming a memory device, the memory device comprising a plurality of memory cell groups, wherein each of the memory cell groups comprises N non-volatile memory cells, wherein N is an integer greater than or equal to 2. For each memory cell group, the method comprises: programming each of the non-volatile memory cells in the memory cell group to a specific programming state; performing a plurality of read operations on each of the non-volatile memory cells in the memory cell group; identifying one of the non-volatile memory cells in the memory cell group that exhibits a lowest read change during the plurality of read operations; deeply programming all of the non-volatile memory cells in the memory cell group except the identified non-volatile memory cell; and programming the identified non-volatile memory cell in the memory cell group with user data.

Description

[0001] Related patent applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 208,093, filed on June 8, 2021, and U.S. Patent Application No. 17 / 482,095, filed on September 22, 2021. Technical Field

[0003] The present invention relates to non-volatile memory devices, and more particularly to improving the stability of memory cell current during a read operation. Background Art

[0004] Non-volatile memory devices are well known in the art. See, for example, U.S. Patent 7,868,375, which discloses a quad-gate memory cell configuration and is incorporated herein by reference for all purposes. Specifically, the present application Figure 1 A split gate memory cell 10 is shown having spaced-apart source and drain regions 14 and 16 formed in a silicon semiconductor substrate 12. The source region 14 may be referred to as a source line SL (because it is typically connected to other source regions of other memory cells in the same row or column), and the drain region 16 is typically connected to a bit line through a bit line contact 28. A channel region 18 of the substrate is defined between the source / drain regions 14 and 16. A floating gate 20 is vertically disposed over and insulated from (and controls the conductivity of) a first portion of the channel region 18 (and is partially vertically located over and insulated from the source region 14). A control gate 22 is vertically disposed over and insulated from the floating gate 20. A select gate 24 is vertically disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18. An erase gate 26 is vertically disposed over and insulated from the source region 14 and is laterally adjacent to the floating gate 20. A plurality of such memory cells may be arranged in rows and columns to form a memory cell array.

[0005] Various combinations of voltages are applied to the control gate 22, the select gate 24, the erase gate 26, and / or the source region 14 / drain region 16 to program the split gate memory cell 10 (i.e., inject electrons onto the floating gate), erase the split gate memory cell 10 (i.e., remove electrons from the floating gate), and read the split gate memory cell 10 (i.e., measure or detect the conductivity of the channel region 18 to determine the programmed state of the floating gate 20).

[0006] The split gate memory cell 10 can be operated in a digital mode, where the split gate memory cell 10 is set to one of only two possible states: a programmed state and an erased state. The split gate memory cell 10 is erased by applying a high positive voltage on the erase gate 26 and optionally a negative voltage on the control gate 22 to cause tunneling of electrons from the floating gate 20 to the erase gate 26 (putting the floating gate 20 in a more positively charged state - the erased state). The split gate memory cell 10 can be programmed by applying a positive voltage on the control gate 22, the erase gate 26, the select gate 24 and the source region 14 and applying a current on the drain region 16. The electrons will then flow from the drain region 16 to the source region 14 along the channel region 18, where the electrons become accelerated and heated, whereby some of them are injected onto the floating gate 20 by hot electron injection (putting the floating gate 20 in a more negatively charged state - the programmed state). The split gate memory cell 10 can be read by applying a positive voltage on the select gate 24 (turning on the portion of the channel region 18 below the select gate 24) and the drain region 16 (and optionally on the erase gate 26 and / or the control gate 22) and sensing the current flowing through the channel region 18. If the floating gate 20 is positively charged (i.e., the split gate memory cell 10 is erased), the split gate memory cell 10 will be turned on and current will flow from the drain region 16 to the source region 14 (i.e., the split gate memory cell 10 is sensed to be in its erased "1" state based on the sensed current flow). If the floating gate 20 is negatively charged (i.e., the split gate memory cell 10 is programmed), the portion of the channel region 18 below the floating gate 20 is turned off, thereby preventing measurable current from flowing (i.e., the split gate memory cell 10 is sensed to be in its programmed "0" state based on no or minimal current flow).

[0007] Table 1 provides non-limiting examples of erase, program, and read voltages for typical digital operations of a split-gate memory cell, where Vcc is the supply voltage or another positive voltage (such as 2.5V).

[0008] Table 1

[0009] WL(SG) BL(Dram) Source EG CG Erase 0V 0V 0V 11.5V 0V programming 1V IμA 4.5 4.5V 10.5V Read Vcc 0.6V 0V 0V Vcc

[0010] The split gate memory cell 10 may alternatively be operated in an analog manner, where the memory state of the split gate memory cell 10 (i.e., the amount of charge on the floating gate 20, such as the number of electrons) can be tuned to anywhere from a fully erased state (least number of electrons on the floating gate 20) to a fully programmed state (most number of electrons on the floating gate 20), or to just a portion of this range by varying one or more programming voltages, e.g., various control gate 22 (CG) programming voltages may be used for analog programming. This means that the split gate memory cell 10 storage is analog, which allows very precise and individual tuning of each split gate memory cell 10 in an array of split gate memory cells 10. Alternatively, the split gate memory cell 10 may be operated as an MLC (multi-level cell), where it is configured to be programmed to one of many discrete values, such as 16 or 64 different values. In the case of analog or MLC programming, the programming voltage is applied for a limited time or as a series of pulses until the desired programmed state is achieved. In the case of multiple programming pulses, intermediate read operations between programming pulses can be used to determine whether the desired programmed state has been achieved (in which case programming stops) or has not been achieved (in which case programming continues).

[0011] A split gate memory cell 10 operated in an analog manner or as an MLC may be more sensitive to noise and read current instability, which can adversely affect the accuracy of the split gate memory device 10. One source of read current instability in analog non-volatile memory devices is electron capture and emission by oxide traps located at and near the interface between the gate oxide and the channel region of the memory cell. The gate oxide is an insulating layer that isolates the floating gate 20 from the channel region 18 of the substrate 12. When electrons are trapped on the interface traps, they reduce the channel conductivity during a read operation and thus increase the threshold voltage Vt of the split gate memory cell 10 (i.e., the minimum voltage on the control gate 22 required to turn on the channel region 18 of the split gate memory cell 10 to produce a predetermined target current (e.g., 1 μA)). When the control gate voltage is at or above the threshold voltage Vt, a conductive path is formed between the source region 14 and the drain region 16, and a current of at least the predetermined target current flows. When the control gate voltage is below the threshold voltage Vt, no conductive path is formed, and any current between the source region 14 and the drain region 16 is considered a subthreshold or leakage current. Electrons trapped on the interface trap may be emitted from the interface trap, which lowers the threshold voltage Vt of the memory cell and thus increases the channel conductivity during a read operation. These single electron events of electron capture and emission by the interface trap appear as read current noise and are referred to as random telegraph noise (RTN). Typically, the RTN generated by a single interface trap is characterized by two states: a lower Vt state (and a higher read current state) when the electron is emitted from the interface trap and a higher Vt state (and a lower read current state) when the electron is captured by the interface trap. As described above, the instability of the split gate memory cell 10 during reading can be characterized by the threshold voltage Vt (i.e., the control gate voltage corresponding to a predetermined target current) or by the memory cell current under a given read voltage condition. The examples herein are specifically described with respect to the memory cell read instability as a threshold voltage Vt, however, it is specifically contemplated that the memory cell current is used at a given read voltage.

[0012] There are a small but non-negligible percentage of memory cells within a memory cell array, such as the split gate memory cell 10, that exhibit an intolerable amount of RTN for those applications requiring extremely high read accuracy. Memory cells susceptible to RTN increase the risk that some analog data stored in the memory cell array will be corrupted, at least to some extent, because electron emission from interface traps of such memory cells after programming will undesirably reduce the threshold voltage Vt of the memory cell (and thus undesirably increase the channel conductivity during a read operation), thus providing an inaccurate read of the desired original memory cell programmed state. Similarly, electron capture of such memory cells after programming will undesirably increase the threshold voltage Vt of the memory cell (and thus undesirably reduce the channel conductivity during a read operation), thus providing an inaccurate read of the desired original memory cell programmed state. Therefore, there is a need to address RTN in analog and MLC non-volatile memory devices to compensate for post-programmed RTN. Summary of the invention

[0013] The aforementioned problems and needs are solved by a memory device, the memory device comprising a plurality of memory cell groups, wherein each of the memory cell groups comprises N nonvolatile memory cells, wherein N is an integer greater than or equal to 2; and a control circuit. The control circuit is configured to: for each of the memory cell groups, program each of the nonvolatile memory cells in the memory cell group to a specific programming state; perform a plurality of read operations on each of the nonvolatile memory cells in the memory cell group; identify one of the nonvolatile memory cells in the memory cell group that exhibits a lowest read variation during the plurality of read operations; deeply program all of the nonvolatile memory cells in the memory cell group except the identified nonvolatile memory cell; and program the identified nonvolatile memory cell in the memory cell group with user data.

[0014] A method for programming a memory device having a plurality of memory cell groups, wherein each of the memory cell groups includes N nonvolatile memory cells, wherein N is an integer greater than or equal to 2, wherein for each memory cell group, the method comprises: programming each of the nonvolatile memory cells in the memory cell group to a specific programming state; performing a plurality of read operations on each of the nonvolatile memory cells in the memory cell group; identifying one of the nonvolatile memory cells in the memory cell group that exhibits a lowest read variation during the plurality of read operations; deep programming all of the nonvolatile memory cells in the memory cell group except the identified nonvolatile memory cell; and programming the identified nonvolatile memory cells in the memory cell group with user data.

[0015] Other objects and features will become apparent from a review of the specification, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a side cross-sectional view of a conventional memory cell.

[0017] Figure 2 is a diagram illustrating components of a memory device.

[0018] Figure 3 is a flow chart showing the steps for programming a memory cell.

[0019] Figure 4 is a flow chart showing steps for grouping, screening, and programming memory cells. DETAILED DESCRIPTION

[0020] The exemplary techniques described herein are used to reduce the RTN effect of a non-volatile memory cell array, particularly including Figure 1 The present invention relates to those nonvolatile memory cell arrays that have split-gate memory cells 10 of the type described above, but the technology is not limited to such memory cells. Specifically, the nonvolatile memory cells are logically divided into memory cell groups, each memory cell group including two or more memory cells, wherein each memory cell group is regarded as a single cell for storing user data. Within each memory cell group, only the nonvolatile memory cells exhibiting the lowest RTN are used to store user data, while the remaining nonvolatile memory cells of the memory cell group are deeply programmed to effectively knock them out, i.e., so that they do not contribute to the output of the memory cell group during a subsequent read operation.

[0021] Memory cell grouping, screening and programming are implemented as part of the configuration of control circuitry 66, which controls the various device elements of the memory array, which can be Figure 2 The architecture of the example memory device illustrated in FIG. 1 is better understood. The memory device includes an array 50 of split gate memory cells 10, which may be separated into two separate planes (Plane A 52a and Plane B 52b). The split gate memory cells 10 may be Figure 1 The type shown is arranged in a plurality of rows and columns in a semiconductor substrate 12 and is thus formed on a single chip. An address decoder (e.g., XDEC 54), a source line driver (e.g., SLDRV 56), a column decoder (e.g., YMUX 58), a high voltage row decoder (e.g., HVDEC 60), and a bit line controller (e.g., BLINHCTL 62) are adjacent to an array 50 of split gate memory cells 10 and included in the memory device, and are used to decode addresses and supply various voltages to the gates and regions of the split gate memory cells 10 during read, program, and erase operations of selected split gate memory cells 10 of the array 50. The column decoder 58 includes a sense amplifier that contains circuitry for measuring current on the bit line during a read operation. The control circuit 66 is configured to control the various device elements to perform each operation (program, erase, read) on the selected split gate memory cells 10 of the array 50, as described herein. Charge pump CHRGPMP 64 provides various voltages for reading, programming, and erasing selected split gate memory cells 10 of array 50 under the control of control circuit 66. Control circuit 66 is configured to operate the memory device to program, erase, and read selected split gate memory cells 10 of array 50. As part of these operations, control circuit 66 may be provided with access to incoming user data (which is data to be programmed into the memory cells), as well as program, erase, and read commands provided on the same or different lines. Data read from array 50 (i.e., from selected split gate memory cells 10 of array 50) is provided as outgoing data. Control circuit 66 includes, or is provided with access to, a separate memory such as random access memory (RAM) 70 for storing voltage values, as further described below.

[0022] The control circuit 66 implements the memory cell grouping, screening, and programming described herein. Thus, the control circuit 66 may be loaded with software (ie, non-transitory electronically readable instructions) or firmware to perform the following description of the memory cell grouping, screening, and programming. Figure 3 to Figure 4 The described method is thus configured. The control circuit 66 may be implemented by a microcontroller, a dedicated circuit, a processor, or a combination thereof.

[0023] According to the examples herein, the split gate memory cells 10 of the array 50 are logically divided into memory cell groups 80 with N cells in each memory cell group 80, where N is an integer greater than or equal to two. Figure 2 Four memory cell groups 80 are illustrated, each having two memory cells 10 (ie, N=2), however the number of memory cell groups 80 and the value of N may be different.

[0024] Before describing the grouping and screening of memory cells, the basics of memory cell programming are first described.

[0025] Memory cell programming involves programming the memory cell to a particular programmed state using a programming voltage pulse, with an intermediate read operation for measuring a threshold voltage parameter for the split gate memory cell 10 (i.e., a voltage pulse applied to the split gate memory cell 10 to achieve a predetermined level of source / drain current (referred to as a target current I target )). The threshold voltage parameter is the control gate threshold voltage Vtcg, which is the threshold voltage of the memory cell viewed from the control gate 22. Specifically, the control gate threshold voltage Vtcg is a voltage applied to the control gate 22, which makes the channel region 18 a conductive path when the read potential of the read operation is applied to the select gate 24 and the drain region 16, and thereby obtains a predetermined level of source / drain current through the channel, that is, the target current I target (e.g., 1 μA) to consider the split gate memory cell 10 turned on. The control gate threshold voltage Vtcg varies with the programming state of the split gate memory cell 10, but it is expected that once the split gate memory cell 10 is programmed to a particular programming state, any change in the control gate threshold voltage Vtcg over time is less than a predetermined amount.

[0026] Memory cells are programmed in Figure 3 4, which are implemented to program the split gate memory cell 10 to a desired specific programming state so that it has a target control gate threshold voltage Vtcg associated with that desired specific programming state. target The technique begins at step 1, where control circuit 66 programs a selected split gate memory cell 10 of array 50. As described above, the analog programming operation involves applying a programming voltage to the selected split gate memory cell 10 for a finite time (i.e., in at least one pulse), which causes electrons to be injected onto floating gate 20. In the programming of step 1, the voltage Veg provided from SLDRV56 and applied to control gate 22 has a control gate programming voltage Vcg programIn step 2, a read operation is performed by control circuit 66, which involves applying a read voltage from SLDRV 56 to the selected split gate memory cell 10 according to Table 1, and measuring a current I flowing through the channel region 18 of the selected split gate memory cell 10 using column decoder 58 and bit line controller 62. read In this read operation, the voltage Vcg applied to the control gate 22 is the target control gate threshold voltage Vtcg target In step 3, it is determined whether the control gate threshold voltage Vtcg of the memory cell has reached or exceeded the target control gate threshold voltage Vtcg according to the read operation of step 2. target (ie, whether the read current Lead measured by the column decoder 58 and the bit line controller 62 is less than or equal to the target current I target , where Lead is equal to the target current I target Indicates that the control gate threshold voltage Vtcg of the memory cell has reached the target control gate threshold voltage Vtcg target If the determination is no (ie, the control gate threshold voltage Vtcg is not greater than or equal to the target control gate threshold voltage Vtcg target , that is, the read current Lead is not less than or equal to the target current I target ), then in step 4, the control gate programming voltage Vcg used for programming program The control gate programming voltage Vcg is increased relative to the control gate programming voltage used in the previous step 1 programming of the memory cell, and then the increased control gate programming voltage Vcg is used. program Step 1 is repeated. Thus, in the first iteration of step 1, a first programming voltage is applied to the gate of the memory cell, and in the second iteration of step 1, in response to step 4, a second programming voltage is applied to the gate of the memory cell, wherein the second programming voltage is greater than the first programming voltage. The control circuit 66 repeats steps 1-4 in sequence until it is determined in step 3 that the control gate threshold voltage Vtcg of the memory cell has reached or exceeded the target control gate threshold voltage Vtcg target (That is, the read current Lead is less than or equal to the target current I target At this point, the memory cell is considered to be programmed to its desired programmed state (i.e., programmed to its target control gate threshold voltage Vtcg target ).

[0027] However, if the programmed memory cell exhibits RTN after programming is completed, the electrons trapped in the interface traps contribute to the measured control gate threshold voltage Vtcg of the memory cell. If / when electrons are emitted from the interface traps after programming is completed, the control gate threshold voltage Vtcg may be above the target control gate threshold voltage Vtcg. target The following decreases exceed ΔVtcgmax , where ΔVtcg max is the maximum allowable read error in terms of control gate threshold voltage Vtcg variation. The control gate threshold voltage decreases by more than ΔVtcg max is considered an intolerable error during subsequent read operations. Similarly, if / when electrons are trapped on the interface wells after programming is completed, the control gate threshold voltage Vtcg may be below the target control gate threshold voltage Vtcg target The above increase exceeds ΔVtcg max The control gate threshold voltage increases beyond ΔVtcg max are considered to be intolerable errors during subsequent read operations. Cells with intolerable error behavior can be assigned for screening. Figure 4 Memory cell grouping and screening begins at step 5 in the embodiment of the present invention. In step 5, the split gate memory cells 10 of the array 50 are logically divided into memory cell groups 80 with N cells in each memory cell group 80, where N is an integer greater than or equal to two. The N split gate memory cells 10 in each memory cell group 80 may be adjacent to each other in the same column, adjacent to each other in the same row, or not adjacent to each other.

[0028] For each memory cell group 80, the N memory split gate memory cells 10 of the memory cell group 80 are programmed to a specific programming state (step 6), i.e., as described above with respect to steps 1 to 4. Therefore, steps 1-4 may be performed before or after step 5, but are not limited thereto. In step 7, each of the N split gate memory cells 10 of the memory cell group 80 is read multiple times. In step 8, the split gate memory cells 10 in the memory cell group 80 with the lowest read variation are identified. The read variation of each split gate memory cell 10 may be a variation in the read current head and / or a variation in the control gate threshold voltage Vtcg exhibited between multiple read operations performed on the split gate memory cells 10 in step 7. The split gate memory cells 10 in the memory cell group 80 with the lowest read variation are identified in step 8. read and / or the split gate memory cell 10 with the lowest variation in Vtcg.

[0029] In step 9, the split gate memory cells 10 in the memory cell group 80 that were not identified in step 8 (i.e., all other split gate memory cells in the memory cell group 80) are deep programmed (i.e., programmed with a large number of electrons far beyond the selected MLC or analog operating range for storing user data, such that these deeply programmed split gate memory cells 10 do not contribute to any detected current from the memory cell group 80 (or any other memory cell group 80) during subsequent read operations of the split gate memory cells 10 in the memory cell group 80 (or any other memory cell group 80) for storing user data because the deeply programmed state of the floating gate with the large number of electrons effectively turns off the underlying channel region 18 and prevents current from flowing). Those skilled in the art will recognize that the operating range and the number of rows in the array 50 that contribute to the read current vary from product to product. Therefore, the specific value used for deep programming depends on the specific implementation. The greater the number of memory cells 10 in each row, the greater the I for the deeply programmed memory cells 10. read The lower the programming voltage is, the lower the memory cells 10 should be to prevent their combined contribution to the total read current for the row. In one example, deep programming of the memory cells 10 to be rejected is performed quickly (i.e., with one programming pulse and no verification) to save time, and the programming voltage used for deep screening will be the same for all screened memory cells 10.

[0030] In step 10, the one split gate memory cell 10 identified in step 8 is programmed with user data (e.g., as described above with respect to Figure 3 Step 10 may require first erasing the one split gate memory cell 10 identified in step 8 before programming it with user data. Steps 6 to 10 are performed for each of the groups of memory cells 80 in the array that are to be programmed with user data.

[0031] To read data from each memory cell group 80, all split gate memory cells 10 in the memory cell group 80 are selected, but only the split gate memory cells 10 identified in step 8 and programmed in step 10 for that memory cell group 80 contribute to the read current in the data read operation. The other split gate memory cells 10 in the memory cell group 80 do not contribute current to the read operation because they are deeply programmed. Therefore, only the split gate memory cells 10 in the memory cell group 80 identified as having the lowest read variation and therefore the lowest RTN are used to store user data and provide data in any read operation. The other split gate memory cells 10 in the memory cell group 80 are effectively culled out, thereby suppressing any RTN that would otherwise cause the split gate memory cells 10 in the memory cell group 80 exhibiting higher read variations to be used to store user data and / or contribute to data read operations. The above-described memory cell grouping and screening reduces the impact of RTN on analog programming and read accuracy.

[0032] The above technique has a number of advantages. First, it effectively culls split gate memory cells 10 that exhibit a large RTN. Second, it avoids having to cull all of the split gate memory cells 10 in a given column or row simply because a single noisy split gate memory cell 10 is found in that column or row (i.e., by replacing that column or row with a redundant column or row, as is known in the art, where redundant (spare) rows and / or columns are provided and used to replace any row or column containing a noisy memory cell). Third, while culling all but one split gate memory cell 10 in each memory cell group 80 reduces the effective density of available memory cells in the array, this density reduction can be offset by the improved accuracy of analog programming for the less noisy split gate memory cells 10, and thus the ability to allocate the read current I for a given operating range. read The improvement in programming accuracy may be partially or even completely compensated by the greater number of possible programming levels (or control gate threshold voltages Vtcg) of the memory cell. For example, if N=2 (i.e., two memory cells in each memory cell group), then if the improved programming accuracy allows twice as many possible programming states for this one split gate memory cell 10 characterized by a lower RTN, then twice as many bits can be programmed using this one split gate memory cell 10, thus providing the same memory density as a memory array that utilizes all split gate memory cells 10 in half the possible programming states for each split gate memory cell 10. Thus, using twice as many programming states for each split gate memory cell 10 as compared to a conventional array results in better read stability and reliability over time due to the reduced RTN across the memory array.

[0033] It should be understood that the above is not limited to the examples described above and shown herein, but encompasses any and all variations that fall within the scope of any claim. For example, references to the invention and examples herein are not intended to limit the scope of any claim or claim term, but only to one or more features that may be covered by one or more of the claims. The examples of materials, processes, and values ​​described above are merely exemplary and should not be considered to limit the claims. In addition, as is apparent from any claim and specification, not all method steps need to be performed in the exact order shown or required (unless otherwise stated). An example of the threshold voltage Vt used in the above technique is the control gate threshold voltage Vtcg, which is the threshold voltage of the split gate memory cell 10 viewed from the control gate 22. However, the above technique can be implemented relative to the threshold voltage Vt viewed from any one or more gates in the split gate memory cell 10 that are not floating. Finally, the examples herein can be implemented in a system having a threshold voltage Vt greater than 1000 V. Figure 1 The invention is implemented in an array of non-volatile memory cells having fewer gates (eg, no erase gates and / or control gates combined with select gates).

Claims

1. A memory device, comprising: a plurality of memory cell groups, wherein each of the memory cell groups includes N nonvolatile memory cells, wherein N is an integer greater than or equal to 2; and a control circuit configured to: for each of the memory cell groups: programming each of the nonvolatile memory cells in the group of memory cells to a specific programming state, performing a plurality of read operations on each of the non-volatile memory cells in the group of memory cells, identifying one of the nonvolatile memory cells in the group of memory cells that exhibits a lowest read variation during the plurality of read operations, deep programming all of the non-volatile memory cells in the group of memory cells except for the identified non-volatile memory cells, and Non-volatile memory cells identified in the group of memory cells are programmed with user data.

2. The memory device of claim 1 , wherein the control circuit is further configured to, for each of the memory cell groups: Nonvolatile memory cells identified in the group of memory cells are erased prior to programming the nonvolatile memory cells identified in the group of memory cells with the user data.

3. The memory device of claim 1 , wherein each of the non-volatile memory cells of the plurality of memory cell groups comprises: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the source and drain regions; a floating gate vertically disposed above a first portion of the channel region and insulated from the first portion; a select gate disposed vertically above and insulated from a second portion of the channel region; and A control gate is vertically disposed above the floating gate and insulated from the floating gate.

4. The memory device of claim 3, wherein each of the non-volatile memory cells of the plurality of memory cell groups further comprises: An erase gate is disposed above the source region and insulated from the source region.

5. The memory device of claim 1 , wherein for each of the memory cell groups, the control circuit is configured to program each of the nonvolatile memory cells in the memory cell group to the particular programming state by: applying a first programming voltage pulse to the nonvolatile memory cell; reading the nonvolatile memory cell by generating a read current using a read voltage applied to a gate of the nonvolatile memory cell equal to a target threshold voltage; as well as applying a second programming voltage pulse to the nonvolatile memory cell in response to determining that the read current is not less than or equal to a target read current; Wherein the first programming voltage pulse comprises a first programming voltage applied to the gate of the nonvolatile memory cell, and wherein the second programming voltage pulse comprises a second programming voltage applied to the gate of the nonvolatile memory cell that is greater than the first programming voltage.

6. A method of programming a memory device, the memory device comprising a plurality of memory cell groups, wherein each of the memory cell groups comprises N non-volatile memory cells, wherein N is an integer greater than or equal to 2, wherein for each memory cell group, the method comprises: programming each of the nonvolatile memory cells in the group of memory cells to a particular programmed state; performing a plurality of read operations on each of the nonvolatile memory cells in the group of memory cells; identifying one of the nonvolatile memory cells in the group of memory cells that exhibits a lowest read variation during the plurality of read operations; deep programming all of the nonvolatile memory cells in the memory cell group except for the identified nonvolatile memory cell; as well as Non-volatile memory cells identified in the group of memory cells are programmed with user data.

7. The method of claim 6, wherein for each of the groups of memory cells, the method further comprises: Nonvolatile memory cells identified in the group of memory cells are erased prior to programming the nonvolatile memory cells identified in the group of memory cells with the user data.

8. The method of claim 6, wherein each of the N non-volatile memory cells in the plurality of groups of memory cells comprises: spaced-apart source and drain regions formed in a semiconductor substrate, wherein a channel region of the substrate extends between the source and drain regions; a floating gate vertically disposed above a first portion of the channel region and insulated from the first portion; a select gate disposed vertically above and insulated from a second portion of the channel region; as well as A control gate is vertically disposed above the floating gate and insulated from the floating gate.

9. The method of claim 8, wherein each of the non-volatile memory cells further comprises: An erase gate is disposed above the source region and insulated from the source region.

10. The method of claim 6, wherein said programming each of said nonvolatile memory cells in said group of memory cells to said particular programmed state comprises: applying a first programming voltage pulse to the nonvolatile memory cell; reading the nonvolatile memory cell by generating a read current using a read voltage applied to a gate of the nonvolatile memory cell equal to a target threshold voltage; as well as In response to determining that the read current is greater than a target read current, applying a second programming voltage pulse to the nonvolatile memory cell; Wherein the first programming voltage pulse comprises a first programming voltage applied to the gate of the nonvolatile memory cell, and wherein the second programming voltage pulse comprises a second programming voltage applied to the gate of the nonvolatile memory cell that is greater than the first programming voltage.

Images