Method for manufacturing microfluidic chip

Abstract

This invention discloses a method for manufacturing a microfluidic chip, comprising: providing a semiconductor wafer including a plurality of microfluidic chips, each microfluidic chip including a protective layer and a structural layer stacked thereon, the structural layer having microfluidic channels; cutting the protective layer of the semiconductor wafer at a dicing location between two adjacent microfluidic chips to form a first groove partially penetrating the protective layer; etching on one side of the semiconductor wafer with the first groove to form a second groove penetrating the remaining protective layer and a portion of the structural layer; and cutting on the side of the semiconductor wafer opposite to the first groove, or on the side with the first groove, to form a third groove penetrating the semiconductor wafer, thereby obtaining a plurality of separate microfluidic chips. This method prevents the inlet and outlet of the microfluidic channels from being blocked or creating gaps during the cutting of the microfluidic chips, thus improving the product yield.

Description

Technical Field

[0001] This invention relates to the field of microfluidic chip manufacturing, and more particularly to a method for manufacturing microfluidic chips. Background Technology

[0002] Microfluidic chips are a technology for precisely controlling and manipulating fluids at the microscale, and have shown great potential in fields such as biology, chemistry, and medicine. The fabrication of microfluidic chips typically involves using microfabrication processes to create various microstructure units, such as fluid channels, chambers, filters, or sensors, on substrates made of materials like silicon, metals, polymers, glass, and quartz. These microstructures are then manipulated at the micrometer scale. Taking a microfluidic atomizing chip as an example, the liquid to be atomized is rectified through the microchannels, and the atomized liquid is ejected from micropores.

[0003] However, since the manufacturing of microchannel chips typically requires bonding glass / quartz plates to silicon wafers, and microchannels are formed between the glass / quartz plates and the silicon wafers, conventional dicing methods such as blade dicing and laser dicing often produce significant residue that can clog the inlet and outlet of the microchannel chip. While laser dicing produces relatively less residue, it can still potentially block the inlet and outlet. For microchannel atomizing chips, blockages at the inlet and outlet of the microchannels during the dicing process can severely impact atomization performance and efficiency, and may even lead to a complete failure to atomize. Summary of the Invention

[0004] This invention provides a method for manufacturing microfluidic chips, which aims to effectively solve the problem that in the prior art, the conventional dicing method for manufacturing microfluidic chips results in residue splashing at the dicing edge, causing blockage of the microfluidic chip inlet and outlet.

[0005] According to a first aspect of the present invention, a method for manufacturing a microchannel chip is provided, comprising: providing a semiconductor wafer, the semiconductor wafer including a plurality of microchannel chips, each microchannel chip including a protective layer and a structural layer stacked thereon, the structural layer having microchannels; cutting the protective layer of the semiconductor wafer at a dicing location between two adjacent microchannel chips to form a first groove partially penetrating the protective layer in the thickness direction; etching the semiconductor wafer on a side having the first groove to form a second groove penetrating the remaining protective layer and a portion of the structural layer in the thickness direction, and the second groove communicating with the first groove; cutting the remaining structural layer on a side of the semiconductor wafer opposite to the first groove, or on a side of the semiconductor wafer having the first groove, to form a third groove penetrating the semiconductor wafer in the thickness direction, and the third groove communicating with the second groove, to obtain a plurality of separate microchannel chips.

[0006] Furthermore, the cross-sectional width of the opening of the first groove is greater than the cross-sectional width of the opening of the second groove.

[0007] Further, the step of etching the semiconductor wafer on the side having the first groove to form a second groove penetrating the remaining protective layer and part of the structural layer in the thickness direction includes: etching the semiconductor wafer on the side having the first groove using a laser-induced etching process to form a first sub-groove penetrating the remaining protective layer in the thickness direction; and etching the semiconductor wafer on the side having the first sub-groove using a deep silicon etching process to form a second sub-groove partially penetrating the structural layer in the thickness direction.

[0008] Furthermore, when the semiconductor wafer is etched on one side of the semiconductor wafer having the first sub-groove by a deep silicon etching process to form a second sub-groove that partially penetrates the structural layer in the thickness direction, the inlet and outlet of the microchannel are formed at the junction of the protective layer and the structural layer, and the sidewall of the second sub-groove completely covers the inlet and outlet.

[0009] Furthermore, the remaining structural layer is cut on the side of the semiconductor wafer opposite to the first groove using a laser stealth dicing process, or on the side of the semiconductor wafer having the first groove, to form a third groove penetrating the semiconductor wafer in the thickness direction.

[0010] Furthermore, in the case where a third groove is formed by cutting on the side of the semiconductor wafer opposite to the first groove, the cross-sectional width of the opening of the third groove is greater than the cross-sectional width of the opening of the second groove.

[0011] Furthermore, in the case where a third groove is formed by cutting on one side of the semiconductor wafer having the first groove, the cross-sectional width of the opening of the third groove is smaller than the cross-sectional width of the opening of the second groove.

[0012] Furthermore, the protective layer is made of quartz or glass, and the structural layer is made of monocrystalline silicon.

[0013] According to a second aspect of the present invention, the present invention also provides a method for manufacturing a microchannel chip, comprising: providing a semiconductor wafer, the semiconductor wafer including a plurality of microchannel chips, each microchannel chip including a protective layer and a structural layer stacked thereon, the structural layer having microchannels; cutting the protective layer of the semiconductor wafer at a dicing location between two adjacent microchannel chips to form a first groove partially penetrating the protective layer in the thickness direction; etching the semiconductor wafer on one side having the first groove to form a second groove penetrating the remaining protective layer and the structural layer in the thickness direction, and the second groove communicating with the first groove to obtain a plurality of separate microchannel chips.

[0014] Furthermore, the cross-sectional width of the opening of the first groove is greater than the cross-sectional width of the opening of the second groove.

[0015] Further, the step of etching the semiconductor wafer on the side having the first groove to form a second groove penetrating the remaining protective layer and the structural layer in the thickness direction includes: etching the semiconductor wafer on the side having the first groove using a laser-induced etching process to form a first sub-groove penetrating the remaining protective layer in the thickness direction; and etching the semiconductor wafer on the side having the first sub-groove using a deep silicon etching process to form a second sub-groove penetrating the structural layer in the thickness direction.

[0016] Furthermore, when the semiconductor wafer is etched on one side of the semiconductor wafer having the first sub-groove by a deep silicon etching process to form a second sub-groove penetrating the structural layer in the thickness direction, the inlet and outlet of the microchannel are formed at the junction of the protective layer and the structural layer, and the sidewall of the second sub-groove completely covers the inlet and outlet.

[0017] Through one or more embodiments of the above embodiments of the present invention, at least the following technical effects can be achieved:

[0018] Near the inlet and outlet of the microfluidic chip, traditional mechanical / laser scribing processes are avoided. By combining multiple etching processes with mechanical scribing methods, microcracks and debris are not generated at the junction of the protective layer and the structural layer when the microfluidic chip is diced and separated. This ensures that the inlet and outlet of the microfluidic channel are not blocked, thereby improving the functional yield and service life of the microfluidic chip. Attached Figure Description

[0019] The technical solution and other beneficial effects of the present invention will become apparent from the following detailed description of specific embodiments of the invention, in conjunction with the accompanying drawings.

[0020] Figure 1 This is a schematic diagram of the structure of the microchannel chip provided in an embodiment of the present invention;

[0021] Figure 2 This is a plan view of the microchannel chip structure layer provided in an embodiment of the present invention;

[0022] Figure 3 A front view of the microfluidic chip provided in an embodiment of the present invention;

[0023] Figure 4 This is a rear view of the microfluidic chip provided in an embodiment of the present invention;

[0024] Figure 5 A flowchart illustrating the steps of a method for manufacturing a microchannel chip according to an embodiment of the present invention;

[0025] Figure 6 A schematic diagram of the segmented side surface formed by the microfluidic chip manufacturing method provided in an embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram of another segmented side formed by a microfluidic chip manufacturing method according to an embodiment of the present invention;

[0027] Figure 8 Another flowchart of the manufacturing method of microchannel chip provided in the embodiment of the present invention;

[0028] Figure 9 A flowchart illustrating the steps of a method for manufacturing a microchannel chip in another embodiment of the present invention;

[0029] Figure 10 A schematic diagram of a segmented side formed by a microfluidic chip manufacturing method in another embodiment of the present invention;

[0030] The meanings of the reference numerals in the attached drawings are as follows: 10-protective layer; 20-structural layer; 21-inlet; 22-filter grid; 23-outlet; 30-first groove; 40-second groove; 41-first sub-groove; 42-second sub-groove; 50-third groove; 51-joint. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0033] In the description of this application, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances. In this embodiment, the simulated display screen touch unit is connected to the head tracking unit to obtain the movement path of the sensing cursor in the display device.

[0034] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0035] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0036] This invention provides a microchannel chip, such as... Figure 1 As shown, it includes a protective layer 10 and a structural layer 20. Multiple protrusions of uniform height are provided on the surface of the structural layer 20 near the protective layer 10. The areas between the multiple protrusions form microchannels. Figure 2 This is a top view of structural layer 20, as shown below. Figure 2 As shown, the microchannel includes an inlet 21, a filter grid 22, and an outlet 23.

[0037] The microfluidic chip includes multiple equally spaced parallel protrusions on one side of the inlet 21. These protrusions can be cuboid protrusions, as seen from a top view. Figure 2 In the middle, the long side of the cuboid is set parallel to the liquid entry direction. After the protective layer 10 is bonded to the structural layer 20, the protective layer 10 is tightly attached to the top of the cuboid protrusion. Figure 3 A front view of a microfluidic chip, as shown. Figure 3 As shown, an inlet 21 is formed in the recess between the cuboid protrusions, allowing liquid to flow in. The filter grid 22 includes multiple micro-protrusions arranged in a serrated pattern. After flowing in through the inlet 21, the liquid passes through the filter grid 22, where residues or particles are blocked. The outlet 23 is located downstream of the filter grid 22. The width of the protrusion area gradually decreases from the filter grid 22 to the outlet 23, forming a funnel-shaped recessed area. Figure 4 This is a rear view of the microfluidic chip, as shown. Figure 4 As shown, at least one unclosed outlet 23 is located at the end of the funnel-shaped recessed area. Multiple cylindrical protrusions are also provided between the filter grid 22 and the outlet 23, evenly distributed within the funnel-shaped area from the end of the filter grid 22 to the outlet 23. These cylindrical protrusions are used for liquid rectification, ensuring a smooth flow of liquid.

[0038] For microchannel chips with the above structure, when dicing each microchannel chip on the wafer, conventional dicing methods such as mechanical dicing or laser cutting will generate a large amount of residue, which will block the inlet 21 and outlet 23 of the microchannel, severely affecting the microchannel atomization effect or even making atomization impossible.

[0039] To address the above problems, one embodiment of the present invention provides a method for manufacturing a microfluidic chip. Figure 5 The diagram shows a flowchart of the manufacturing method of a microchannel chip provided in an embodiment of the present invention, including steps S101 to S104.

[0040] Step S101: Provide a semiconductor wafer, the semiconductor wafer including a plurality of microchannel chips, each microchannel chip including a protective layer and a structural layer stacked together, the structural layer having microchannels.

[0041] In some embodiments, the structure of each microchannel chip is as described above. Figure 1 It includes a protective layer 10 and a structural layer 20 stacked together, and the side surface of the structural layer 20 that is in contact with the protective layer 10 has microchannels.

[0042] Step S102: Cut the protective layer of the semiconductor wafer at the dicing position between two adjacent microchannel chips to form a first groove that partially penetrates the protective layer in the thickness direction.

[0043] In some embodiments, such as Figures 6 to 7 As shown, the protective layer 10 of the semiconductor wafer is cut by mechanical cutting or laser cutting process through the cutting channel between two adjacent microchannel chips to form a first groove 30 that partially penetrates the protective layer 10 in the thickness direction. The width of the first groove 30 is greater than 100 μm, preferably greater than 170 μm.

[0044] Step S103: Etch the semiconductor wafer on one side of the semiconductor wafer with the first groove to form a second groove that penetrates the remaining protective layer and part of the structural layer in the thickness direction, and the second groove is connected to the first groove.

[0045] The second groove 40 penetrates the remaining protective layer 10 and part of the structural layer 20 in the thickness direction. That is, the sidewall of the second groove 40 completely covers the junction 51 of the protective layer 10 and the structural layer 20. The material of the protective layer 10 is quartz or glass, and the material of the structural layer 20 is monocrystalline silicon. Therefore, the second groove 40 needs to be etched with two different etching processes to etch the protective layer 10 and the structural layer 20 respectively.

[0046] In some embodiments, such as Figure 8 As shown, step S103, which involves etching the semiconductor wafer on one side of the semiconductor wafer with the first groove to form a second groove that penetrates the remaining protective layer and part of the structural layer in the thickness direction, may also include steps S1031 and S1032.

[0047] Step S1031: The semiconductor wafer is etched on one side of the semiconductor wafer having the first groove 30 by laser-induced etching process to form a first sub-groove that penetrates the remaining protective layer in the thickness direction.

[0048] Laser-Induced-Deep Etching (LIDE) process typically consists of two steps: the first step is to selectively modify the surface with laser according to the design pattern; the second step is to perform wet chemical etching on the modified area, which is etched at a much higher rate than the unmodified material.

[0049] During the formation of the first sub-groove 41, if a traditional mask wet etching method is used, although it will not produce microcracks and debris, the traditional mask wet etching is an isotropic etching process, which cannot form a deep vertical etching wall to complete the dicing. If a conventional laser cutting process is used to directly cut the protective layer 10, not only will the production capacity be low, but it will also generate hidden microcracks near the cutting surface, along with a small amount of debris and residual thermal stress. All of these disadvantages will lead to a loss of yield for the microfluidic chip or even product failure.

[0050] The LIDE process combines laser modification and wet chemical etching. During laser modification, a single laser pulse is sufficient to modify the entire thickness, significantly improving production efficiency. The laser-induced depth etching process produces smooth sidewalls without cracks, debris, or stress. Therefore, the process of using laser-induced etching to create the first sub-groove 41 does not generate debris that could clog the inlet 21 and outlet 23 of the microfluidic chip, ensuring high-yield separation of the microfluidic chip while improving efficiency.

[0051] In addition, during the atomization process, the microchannel atomizing chip generates significant pressure at the inlet 21 and outlet 23 of the microchannel, typically exceeding 30 MPa, generally between 40-50 MPa. The upper protective layer 10 can be made of glass or quartz, and is usually quite thick, exceeding 600 μm, preferably exceeding 650 μm. First, a first groove 30 is formed using a low-cost, simple mechanical or laser cutting method to reduce the thickness of the protective layer 10 to be cut. Then, a first sub-groove 41 is formed using laser-induced depth etching. The sum of the depths of the first groove 30 and the first sub-groove 41 equals the thickness of the protective layer 10, achieving complete cutting of the protective layer 10.

[0052] In some embodiments, the laser power of the laser-induced depth etching process used in step S1031 should be greater than 5W, such as... Figures 6 to 7 As shown, the cross-sectional width of the opening of the first sub-groove 41 is smaller than the cross-sectional width of the opening of the first groove 30. Preferably, the cross-sectional width of the opening of the first sub-groove 41 is 5-90 μm smaller than the cross-sectional width of the opening of the first groove 30.

[0053] Step S1032: The semiconductor wafer is etched on one side of the semiconductor wafer with the first sub-groove by a deep silicon etching process to form a second sub-groove that partially penetrates the structural layer in the thickness direction.

[0054] In some embodiments, such as Figures 6 to 7 As shown, a microchannel is formed on the side of the structural layer 20 that is in contact with the protective layer 10. The semiconductor wafer is etched on the side with the first sub-groove 41 by a deep silicon etching process to form a second sub-groove 42 that partially penetrates the structural layer in the thickness direction. When the second sub-groove 42 is formed, the inlet 21 and outlet 23 of the microchannel are formed at the junction 51 of the protective layer 10 and the structural layer 20. The sidewall of the second sub-groove 42 completely covers the inlet 21 and outlet 23.

[0055] In some embodiments, the structural layer 20 is made of monocrystalline silicon, and its thickness is similar to that of the protective layer 10, greater than 600 μm, preferably greater than 650 μm. The deep silicon etching process used is preferably ICP (Inductively Coupled Plasma) deep silicon etching. ICP deep silicon etching utilizes high-density oxygen plasma to chemically react with the surface of the silicon substrate, achieving deep etching by removing silicon material. The commonly used gases are a combination of SF6 and O2. SF6 is the main gas used for deep silicon etching, while O2 is used to remove the generated gases and oxides.

[0056] During the formation of the second sub-groove 42, the ICP deep silicon etching process is adopted, which can achieve anisotropic etching with a depth that meets the requirements for the formation of the sidewall of the second sub-groove 42. At the same time, it avoids the problems of low production capacity and hidden microcracks and a small amount of debris that occur when using laser cutting process to directly cut the protective layer 10. This ensures the product yield of the microfluidic chip and improves production efficiency.

[0057] Step S104: Cut the remaining structural layer on the side of the semiconductor wafer away from the first groove or on the side of the semiconductor wafer with the first groove to form a third groove that penetrates the semiconductor wafer in the thickness direction, and the third groove is connected to the second groove to obtain multiple separate microchannel chips.

[0058] In some embodiments, the remaining structural layers are cut on the side of the semiconductor wafer opposite to the first groove 30 by laser stealth cutting process, or on the side of the semiconductor wafer having the first groove 30, to form a third groove 50 penetrating the semiconductor wafer in the thickness direction.

[0059] In one embodiment of this example, the cross-sectional width of the opening of the third groove 50, which is formed by cutting on the side of the semiconductor wafer opposite to the first groove 30, is greater than the cross-sectional width of the opening of the second groove 40.

[0060] In the above embodiments, since deep silicon etching becomes more difficult with a larger aspect ratio, it is very difficult and costly to completely cut the thick structural layer 20 using deep silicon etching alone. Therefore, a method combining laser stealth cutting and deep silicon etching is adopted. The second sub-groove 42 is formed by deep silicon etching, and the third groove 50 is generated from the other side by laser stealth cutting, thus completely separating the structural layer 20. This method is less difficult and has lower production costs.

[0061] In one embodiment of this example, for the third groove 50 formed by cutting on one side of the semiconductor wafer having the first groove 30, the cross-sectional width of the opening of the third groove 50 is smaller than the cross-sectional width of the opening of the second groove 40.

[0062] In the above embodiments, instead of flipping and re-aligning the semiconductor wafer, laser cutting is performed directly from the side of the wafer with the first groove 30, resulting in lower process complexity and higher production efficiency.

[0063] In some embodiments, such as Figures 6 to 7As shown, the bottom center of all the grooves used to separate the microchannel chips is aligned with the cutting channel position. Although the cross-sectional widths of the grooves are not the same, they have the same center of symmetry, i.e. the cutting channel position. After the grooves are completed, they are connected to each other to separate the microchannel chips. The adjacent surfaces of each microchannel chip have the same cutting shape, which ensures the standardization of the product.

[0064] Another embodiment of the present invention provides a different method for manufacturing a microfluidic chip. Figure 9 The diagram shows a flowchart of a method for manufacturing a microchannel chip according to another embodiment of the present invention, including steps S201 to S203.

[0065] Step S201: Provide a semiconductor wafer, the semiconductor wafer including a plurality of microchannel chips, each microchannel chip including a protective layer and a structural layer stacked together, the structural layer having microchannels.

[0066] In some embodiments, the structure of each microchannel chip is as described above. Figure 1 It includes a protective layer 10 and a structural layer 20 stacked together, and the side surface of the structural layer 20 that is in contact with the protective layer 10 has microchannels.

[0067] Step S202: Cut the protective layer of the semiconductor wafer at the dicing position between two adjacent microchannel chips to form a first groove that partially penetrates the protective layer in the thickness direction.

[0068] In some embodiments, such as Figure 10 As shown, the protective layer of the semiconductor wafer is cut by mechanical cutting or laser cutting process in the cutting channel between two adjacent microchannel chips to form a first groove 30 that partially penetrates the protective layer in the thickness direction. The width of the first groove 30 is greater than 100 μm, preferably greater than 170 μm.

[0069] Step S203: Etch the semiconductor wafer on one side of the semiconductor wafer having the first groove 30 to form a second groove that penetrates the remaining protective layer and structural layer in the thickness direction, and the second groove is connected to the first groove to obtain multiple separate microchannel chips.

[0070] The second groove 40 penetrates the remaining protective layer 10 and all structural layers 20 in the thickness direction. That is, the sidewall of the second groove 40 completely covers the junction 51 of the protective layer 10 and the structural layer 20. The material of the protective layer 10 is quartz or glass, and the material of the structural layer 20 is single crystal silicon. Therefore, the second groove 40 needs to be etched with two different etching processes to etch the protective layer 10 and the structural layer 20 respectively.

[0071] In some embodiments, step S203, which involves etching the semiconductor wafer on one side of the semiconductor wafer having the first groove to form a second groove that penetrates the remaining protective layer and structural layer in the thickness direction, may further include steps S2031 and S2032.

[0072] Step S2031: The semiconductor wafer is etched on one side of the semiconductor wafer with the first groove by laser-induced etching process to form a first sub-groove that penetrates the remaining protective layer in the thickness direction.

[0073] Laser-Induced-Deep Etching (LIDE) process typically consists of two steps: the first step is to selectively modify the surface with laser according to the design pattern; the second step is to perform wet chemical etching on the modified area, which is etched at a much higher rate than the unmodified material.

[0074] During the formation of the first sub-groove 41, if a traditional mask wet etching method is used, although it will not produce microcracks and debris, the traditional mask wet etching is an isotropic etching process, which cannot form a deep vertical etching wall to complete the dicing. If a conventional laser cutting process is used to directly cut the protective layer 10, not only will the production capacity be low, but it will also generate hidden microcracks near the cutting surface, along with a small amount of debris and residual thermal stress. All of these disadvantages will lead to a loss of yield for the microfluidic chip or even product failure.

[0075] The LIDE process combines laser modification and wet chemical etching. During laser modification, a single laser pulse is sufficient to modify the entire thickness, significantly improving production efficiency. The laser-induced depth etching process produces smooth sidewalls without cracks, debris, or stress. Therefore, the process of using laser-induced etching to create the first sub-groove 41 does not generate debris that could clog the inlet 21 and outlet 23 of the microfluidic chip, ensuring high-yield separation of the microfluidic chip while improving efficiency.

[0076] In addition, during the atomization process, the microchannel atomizing chip generates significant pressure at the inlet 21 and outlet 23 of the microchannel, typically exceeding 30 MPa, generally between 40-50 MPa. The upper protective layer 10 can be made of glass or quartz, and is usually quite thick, exceeding 600 μm, preferably exceeding 650 μm. First, a first groove 30 is formed using a low-cost, simple mechanical or laser cutting method to reduce the thickness of the protective layer 10 to be cut. Then, a first sub-groove 41 is formed using laser-induced depth etching. The sum of the depths of the first groove 30 and the first sub-groove 41 equals the thickness of the protective layer 10, achieving complete cutting of the protective layer 10.

[0077] In some embodiments, the laser power of the laser-induced depth etching process used in step S2031 should be greater than 5W, such as... Figure 10 As shown, the cross-sectional width of the opening of the first sub-groove 41 is smaller than the cross-sectional width of the opening of the first groove 30. Preferably, the cross-sectional width of the opening of the first sub-groove 41 is 5-90 μm smaller than the cross-sectional width of the opening of the first groove 30.

[0078] Step S1032: The semiconductor wafer is etched on one side of the semiconductor wafer with the first sub-groove by a deep silicon etching process to form a second sub-groove that penetrates the structural layer in the thickness direction.

[0079] In some embodiments, such as Figure 10 As shown, a microchannel is formed on the side of the structural layer 20 that is in contact with the protective layer 10. The semiconductor wafer is etched on the side with the first sub-groove 41 by a deep silicon etching process to form a second sub-groove 42 that penetrates the structural layer in the thickness direction. When the second sub-groove 42 is formed, the inlet 21 and outlet 23 of the microchannel are formed at the junction 51 of the protective layer 10 and the structural layer 20. The sidewall of the second sub-groove 42 completely covers the inlet 21 and outlet 23.

[0080] In some embodiments, the structural layer 20 is made of monocrystalline silicon, and its thickness is similar to that of the protective layer 10, greater than 600 μm, preferably greater than 650 μm. The deep silicon etching process used is preferably ICP deep silicon etching. ICP deep silicon etching utilizes high-density oxygen plasma to chemically react with the surface of the silicon substrate, achieving deep etching by removing silicon material. Commonly used gases include a combination of SF6 and O2. SF6 is the main gas used for deep silicon etching, while O2 is used to remove generated gases and oxides.

[0081] During the formation of the second sub-groove 42, the ICP deep silicon etching process is adopted, which can achieve anisotropic etching with a depth that meets the requirements for the formation of the sidewall of the second sub-groove 42. At the same time, it avoids the problems of low production capacity and hidden microcracks and a small amount of debris that occur when using laser cutting process to directly cut the protective layer 10. This ensures the product yield of the microfluidic chip and improves production efficiency.

[0082] In the above embodiments, the second sub-groove 42 is formed by deep silicon etching to completely separate the structural layer 20. The resulting microchannel chip has a more vertical and smooth side surface, which increases the structural strength at the connection between the protective layer 10 and the structural layer 20. This reduces the risk of damage to the inlet 21 and outlet 23 during the atomization pressurization process and increases the service life of the entire microchannel atomization chip.

[0083] The present invention provides a method for manufacturing a semiconductor wafer, comprising: bonding a protective layer 10 to the surface of a structural layer 20 having microchannels to form a plurality of microchannel chips. Preferably, an anodic bonding process is used to bond the protective layer 10 to the structural layer 20.

[0084] Furthermore, those skilled in the art will recognize that the manufacturing method of the microchannel chip provided by the present invention is not limited to the manufacturing of microchannel atomizing chips. All microchannel chips with microchannel structures can be manufactured using the manufacturing method provided by the present invention to avoid the problem of inlet and outlet blockage caused by traditional cutting methods.

[0085] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0086] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0087] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0088] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0089] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0090] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0091] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method of manufacturing a microfluidic chip, characterized by, Comprising: providing a semiconductor wafer comprising a plurality of microfluidic chips, each of the microfluidic chips comprising a protective layer and a structure layer stacked, the structure layer having microfluidic channels; cutting the protective layer of the semiconductor wafer at a position of a cutting channel between two adjacent microfluidic chips to form a first groove partially penetrating the protective layer in a thickness direction; etching the semiconductor wafer on a side of the semiconductor wafer having the first groove to form a second groove penetrating the remaining protective layer and part of the structure layer in a thickness direction, and the second groove being in communication with the first groove; cutting the remaining structure layer on a side of the semiconductor wafer away from the first groove or on the side of the semiconductor wafer having the first groove to form a third groove penetrating the semiconductor wafer in a thickness direction, and the third groove being in communication with the second groove, to obtain a plurality of separated microfluidic chips; the etching the semiconductor wafer on the side of the semiconductor wafer having the first groove to form the second groove penetrating the remaining protective layer and part of the structure layer in a thickness direction, comprises: etching the semiconductor wafer on the side of the semiconductor wafer having the first groove by a laser-induced etching process to form a first sub-groove penetrating the remaining protective layer in a thickness direction; etching the semiconductor wafer on the side of the semiconductor wafer having the first sub-groove by a deep silicon etching process to form a second sub-groove partially penetrating the structure layer in a thickness direction; when etching the semiconductor wafer on the side of the semiconductor wafer having the first sub-groove by the deep silicon etching process to form the second sub-groove partially penetrating the structure layer in a thickness direction, an inlet and an outlet of the microfluidic channel are formed at a junction of the protective layer and the structure layer, and a sidewall of the second sub-groove completely covers the inlet and the outlet.

2. The production method according to claim 1, wherein a cross-sectional width of an opening of the first groove is greater than a cross-sectional width of an opening of the second groove.

3. The production method according to claim 1, wherein cutting the remaining structure layer on a side of the semiconductor wafer away from the first groove or on the side of the semiconductor wafer having the first groove by a laser stealth cutting process to form a third groove penetrating the semiconductor wafer in a thickness direction.

4. The production method according to claim 1, wherein for the case that the third groove is formed by cutting on the side of the semiconductor wafer away from the first groove, a cross-sectional width of an opening of the third groove is greater than a cross-sectional width of an opening of the second groove.

5. The production method according to claim 1, wherein for the case that the third groove is formed by cutting on the side of the semiconductor wafer having the first groove, a cross-sectional width of an opening of the third groove is less than a cross-sectional width of an opening of the second groove.

6. The production method according to claim 1, wherein the protective layer is of quartz material or glass material, and the structure layer is of monocrystalline silicon material.

7. A method for manufacturing a microfluidic chip, characterized by Comprising: providing a semiconductor wafer comprising a plurality of microfluidic chips, each of the microfluidic chips comprising a protective layer and a structure layer stacked, the structure layer having microfluidic channels; cutting the protective layer of the semiconductor wafer at the position of the cutting channel between two adjacent microfluidic chip to form a first groove partially penetrating the protective layer in the thickness direction; etching the semiconductor wafer on the side with the first groove to form a second groove penetrating the remaining protective layer and the structure layer in the thickness direction, and the second groove is connected with the first groove to obtain a plurality of separated microfluidic chips; the step of etching the semiconductor wafer on the side with the first groove to form a second groove penetrating the remaining protective layer and the structure layer in the thickness direction, comprises: etching the semiconductor wafer on the side with the first groove by a laser-induced etching process to form a first sub-groove penetrating the remaining protective layer in the thickness direction; etching the semiconductor wafer on the side with the first sub-groove by a deep silicon etching process to form a second sub-groove penetrating the structure layer in the thickness direction; when etching the semiconductor wafer on the side with the first sub-groove by a deep silicon etching process to form a second sub-groove penetrating the structure layer in the thickness direction, an inlet and an outlet of the microfluidic channel are formed at the junction of the protective layer and the structure layer, and the sidewall of the second sub-groove completely covers the inlet and the outlet.

8. The production method according to claim 7, wherein The cross-sectional width of the opening of the first groove is greater than the cross-sectional width of the opening of the second groove.

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