Etching method in semiconductor manufacturing process

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and is an etching method in a semiconductor manufacturing process, wherein the etching object of the etching method is a wafer, and the etching pattern includes a first area and a second area, wherein the first area of ​​the etching pattern has a first graphic density value, and the second area of ​​the etching pattern has a second graphic density value; the first graphic density value is greater than the second graphic density value; the etching method includes: forming a pattern of the first graphic density value on the surface of the wafer through a first photolithography and etching process; and forming a pattern of the second graphic density value on the surface of the wafer through a second photolithography and etching process on the pattern of the first graphic density value. The present invention can improve the load effect of sparse graphics and dense graphics after etching, and reduce the differences in morphological angles and etching depths of shallow grooves of different graphic densities formed after one exposure / etching.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to an etching method in a semiconductor manufacturing process. Background Art

[0002] As the size of devices in semiconductor manufacturing shrinks, wafer pattern etching continues to develop. Wafer pattern etching technologies include TSV (Through Silicon Via), Contact / Via (metal-to-metal connection) contact window technology, STI (Shallow Trench Isolation) technology, etc. Among them, STI technology has good isolation effects, such as process isolation effect and electrical isolation effect, and the control of its physical parameters has a crucial impact on device performance. Shallow trench isolation technology also has the advantages of reducing the area occupied on the wafer surface and increasing the integration of devices.

[0003] Taking the STI etching process as an example, in the manufacturing process using inductively coupled plasma etching, the differences in the morphology angle, etching depth, etc. of STI with different pattern densities can be optimized by adjusting parameters such as etching gas, plasma RF power supply and reaction chamber pressure. However, as the etching depth / line width ratio of the etching pattern increases, it is difficult to adjust the balance between etching polymer and physical bombardment and chemical reaction, so that the load effect caused by different pattern densities of the shallow groove formed after one exposure / etching is becoming more and more a challenge in chip manufacturing. Summary of the invention

[0004] The invention provides an etching method for semiconductor process, which can reduce the load effect caused by different pattern densities.

[0005] The present invention can be achieved by adopting the following technical solutions:

[0006] An etching method in a semiconductor process, wherein the etching object of the etching method is a wafer. The etching pattern includes a first area and a second area. The first area of ​​the etching pattern has a first graphic density value, and the second area of ​​the etching pattern has a second graphic density value. The first graphic density value is greater than the second graphic density value. The etching method includes:

[0007] Step S1: forming a pattern of the first pattern density value on the surface of the wafer through a first photolithography and etching process;

[0008] Step S2: forming a pattern of a second pattern density value on the surface of the wafer by a second photolithography and etching process on the pattern of the first pattern density value.

[0009] Specifically, the etched pattern may be a shallow trench isolation structure.

[0010] Specifically, when the etching pattern is a shallow trench isolation structure, the following steps are also included: before step S1, a first dielectric film is formed on the substrate of the wafer, wherein the first dielectric film includes an oxide layer and a grinding stop layer, and the oxide layer is attached to the surface of the wafer substrate.

[0011] The photoresist of the first photolithography process is coated on the surface of the first dielectric film.

[0012] In some embodiments, after the first etching process, the first dielectric film corresponding to the first graphic density value pattern is retained. The first dielectric film portion outside the first graphic density value pattern will be etched away. Specifically, if the etching pattern corresponding to the shallow trench isolation structure is a structure, a portion of the substrate below the first dielectric film outside the first graphic density value pattern will also be etched away.

[0013] In some embodiments, the method further includes filling a second medium on the wafer surface of the pattern of the first graphic density value formed between step S1 and step S2. The filling capacity of the second dielectric material is greater than that of the material of the first dielectric film. The second dielectric is filled to a first preset thickness higher than the first dielectric film. Before performing step S2, the second dielectric of the second preset thickness is removed so that the height difference between the second dielectric and the first dielectric film on the wafer surface is at the first preset value. This facilitates that before performing step S2, when the second etching is performed when the photoresist is applied, the height difference of the wafer surface morphology meets the requirements of the photolithography process. Preferably, the second dielectric is an organic anti-reflection material.

[0014] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0015] The present invention provides an etching method in a semiconductor manufacturing process, wherein the first area of ​​the etching pattern has a first graphic density value, and the second area of ​​the etching pattern has a second graphic density value; the first graphic density value is greater than the second graphic density value; a pattern of the first graphic density value is formed on the surface of the wafer by a first photolithography and etching process; and a pattern of the second graphic density value is formed on the pattern of the first graphic density value by a second photolithography and etching process. The etching method of the present invention decomposes a pattern with a large difference in graphic density into a pattern with a first graphic density value and a pattern with a second graphic density value, and etches away the pattern of the first graphic density value on the pattern of the first graphic density value to produce a pattern of the second graphic density value. In this way, the etching load effect caused by excessively large differences in graphic density values ​​in a single etching pattern can be greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0017] Figure 1 is a flow chart of a shallow trench etching method in an embodiment of the present invention;

[0018] Figure 2-9 is a schematic cross-sectional view of the main processes in the manufacturing process during the shallow trench formation process in an embodiment of the present invention;

[0019] The numbers in the figure are: 1-semiconductor substrate, 2-oxide layer, 3-chemical mechanical polishing stop layer, 4a-first photoresist, 41-first opening area, 411-first shallow trench, 4b-second photoresist, 42-second opening area, 421-second shallow trench, 5-second medium. DETAILED DESCRIPTION

[0020] Some of the terms involved in this specification, such as wafer, should be understood as the substrate used to make chips in the semiconductor manufacturing field. Some dielectric layers can also be deposited on the surface of the wafer, and the dielectric layers are photolithographically and etched. The growth of the dielectric layer can be by furnace tube, chemical vapor deposition or physical vapor deposition. Graphic density, understood from the perspective of etching process, is understood as the ratio of the area to be etched to the area of ​​the wafer surface used to make chips. Positions with smaller graphic density values ​​should be understood as larger etching size / area, larger spacing between graphics, and fewer graphics. Positions with larger graphic density values ​​should be understood as smaller etching size / area, smaller spacing between graphics, and more graphics.

[0021] The technical solution of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is obvious that the described embodiments are part of the embodiments of the present invention, not all of the embodiments, and the implementation of the present invention is not limited to this. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0022] The present invention discloses an etching method for a semiconductor process, wherein the etching object is a wafer. The etching pattern to be etched includes a first area and a second area, the first area of ​​the etching pattern has a first graphic density value, and the second area of ​​the etching pattern has a second graphic density value. The first graphic density value is greater than the second graphic density value. The etching method involved in the present invention mainly includes the following two main steps:

[0023] Step S1: forming a pattern of a first pattern density value on the surface of the wafer through a first photolithography and etching process;

[0024] Step S2: forming a pattern of a second pattern density value on the surface of the wafer by a second photolithography and etching process on the pattern of the first pattern density value.

[0025] The etching process involved in the present invention is to divide different regions of the etching pattern with large difference values ​​into at least two regions, a first region and a second region. The first region has a first graphic density value. The second region has a second graphic density value. Generally, the graphic density of the etching pattern will be different in different regions. Some regions have fewer patterns and the size of a single pattern is larger. According to the definition of the graphic density value given previously, the graphic density value of this pattern region is smaller. In some regions, the size of a single pattern is smaller and there are more patterns. According to the definition of the graphic density value given previously, the graphic density value is larger.

[0026] In general, the graphics of the etching pattern to be finally formed on the wafer may be difficult to be generally divided into a first area or a second area with two single different graphic density values. In some embodiments, the range of graphic density values ​​corresponding to the pattern to be finally formed can be divided into two parts, and the average values ​​of the two parts are taken as the first graphic density value and the second graphic density value, respectively. Of course, the etching load effect caused by the graphic density value range of the respective ranges of the two parts is within the acceptable range of the machine capability and / or process. Specifically, in some structures that do not affect the manufacturing of devices or circuits, idle (Dummy) patterns can also be added at some positions to change the graphic density value of individual positions, or change the area to which the position belongs.

[0027] The etching method of the present invention realizes the pattern to be completed once by photolithography and etching twice. Of course, the pattern can also be realized by disassembling it into three or more times, but the disadvantage is that the number of masks and the number of process steps are increased.

[0028] The etching method of the present invention is further specifically exemplified and described below by taking the etching pattern as a shallow trench isolation structure. Due to the high aspect ratio of the shallow trench isolation structure, the morphology and depth requirements of the shallow trench are relatively strict.

[0029] like Figure 1 As shown, a flow chart of a shallow trench etching method.

[0030] Before step S1, a first dielectric film is formed on the semiconductor wafer substrate. In this embodiment, the first dielectric film includes an oxide layer and a grinding stop layer. The oxide layer is attached to the surface of the wafer substrate.

[0031] like Figure 2As shown, the first dielectric film includes an oxide layer 2 and a grinding stop layer 3. The oxide layer 2 is attached to the surface of the wafer substrate 1, and the grinding stop layer 3 is attached to the oxide layer 2.

[0032] The material of the wafer substrate 1 can be a silicon material formed by single crystal silicon, polycrystalline silicon or amorphous silicon, or a SOI (silicon on insulator) material. In this embodiment, the wafer substrate is a silicon material for illustration. A layer of oxide silicon oxide is grown by thermal oxidation on the surface of the silicon substrate, which can serve as an isolation layer to protect the active area (located on the silicon substrate) from chemical contamination during the process of removing the grinding stop layer.

[0033] In this embodiment, the grinding stop layer is nitride. The nitride is silicon nitride (SiN) or silicon oxynitride (SiON). A layer of Si3N4 is deposited on the surface of silicon oxide by LPCVD (Low Pressure Chemical Vapor Deposition). Since silicon nitride is a strong mask material, after the oxide is filled in the STI trench, when the oxide is ground, the grinding rates of the oxide layer and the nitride layer are different during the CMP (chemical mechanical polishing) process, and the Si3N4 layer can serve as a grinding stop layer.

[0034] See also Figure 3 In this embodiment, the photoresist 4a in the first photolithography process in step S1 is coated on the surface of the first dielectric film. The first dielectric film includes an oxide layer located on the surface of the wafer substrate 1 and after development, a first opening area 41 with a pattern density D1 is formed.

[0035] See also Figure 4 , perform a first etching process, and retain the first dielectric film corresponding to the first graphic density value pattern. Specifically, using the patterned photoresist as a barrier for dry etching, the portion of the first dielectric film not covered by the photoresist will be etched away. In the embodiment of shallow trench isolation, the first photolithography and etching process is used not only to pattern the first dielectric layer, but also to further etch the wafer substrate below the first dielectric layer to form a shallow trench isolation area of ​​the first part. In other embodiments, other media may be below the first dielectric layer, and are not limited to the wafer substrate in this embodiment. The patterned wafer surface should be understood to include a dielectric layer and / or a portion of the wafer substrate on the wafer surface.

[0036] In the shallow trench isolation embodiment described herein, after the photoresist is patterned, the trench formation process undergoes one or more etching steps. Figure 4 As shown, the steps of etching the opening regions 41 of the pattern density D1 may each include plasma anisotropic etching in the form of dry reactive ion etching.

[0037] The first plasma etching can use carbon tetrafluoride (CF4 / CHF3 / Ar) etchant, trifluoromethane (CHF3 / Ar) etchant and / or (CHF3 / SF6) etchant to remove the nitride layer and the oxide layer. Specifically, in this embodiment, the nitride layer in the first opening area 41 is first removed by etching gas containing CHF3 and SF6 to form a nitride layer groove, and then the oxide layer is plasma etched at the nitride layer groove to form an oxide layer groove.

[0038] The second plasma may use carbon tetrafluoride (CF4 / Ar) etchant, CHF3 / SF6 and / or argon (Ar) etchant to remove the top portion of the silicon substrate and polymer byproducts left from etching the nitride layer and the oxide layer.

[0039] The third plasma may use Cl2 / O2 / N2, HBr / O2, Cl2 / HBr / O2, Cl2 / HBr / CF4 and / or Cl2 / O2 / SF6 etchants to perform a plasma etching process on the silicon substrate of the opening area 41. Specifically, in this embodiment, the silicon substrate is etched using an etching gas containing Cl2, O2, and SF6, and then the first shallow trench 411 is formed. The photoresist layer is removed by ashing using a gas containing O2, and then acid / alkaline cleaning may be performed to form a first shallow trench isolation area.

[0040] The etching of the first shallow trench region is completed through the above specific steps, that is, the pattern of the first pattern density value in step S1 is completed.

[0041] In this embodiment, before the main step S2 is performed, it is necessary to fill the second dielectric in the shallow isolation trench of the pattern area of ​​the first pattern density value. In this embodiment, since the shallow trench isolation structure is relatively large in depth and width, in order to prevent the filled material from having voids and causing surface defects later, the filling capacity of the second dielectric material is greater than that of the first dielectric film material.

[0042] Optionally, the second medium is an organic anti-reflection material. The organic anti-reflection material may be a hydrocarbon material. The organic anti-reflection material is a material commonly used in current semiconductor processes and can be made by spin coating. In other embodiments, the second medium may also be made of other materials. In the embodiment of the shallow trench isolation structure, it can well fill the shallow trench of the first pattern density value. Depending on the specific second medium material, the second medium may be made by different methods.

[0043] See also Figure 5 As shown, the second dielectric material 5 is filled in the shallow trench of the first pattern density value. The second dielectric material 5 completely fills the shallow trench, and the second dielectric material is filled to a first preset thickness higher than the first dielectric film. Figure 5The second medium 5 shown is an organic anti-reflection layer. Figure 5 As shown, the organic anti-reflection layer is higher than the first dielectric film and can cover the surface of the grinding stop layer in the first dielectric film. The filled organic anti-reflection layer can protect the inclination angle and depth of the shallow grooves required to form the first pattern density value from being damaged in the second etching.

[0044] See also Figure 6 , remove the second medium 5 of the second preset thickness, so that the height difference between the second medium 5 and the first medium film on the wafer surface is at the first preset value. In the embodiment shown here, the second medium 5 is slightly lower than the grinding stop layer in the first medium film. For example, the surface of the second medium and the surface of the grinding stop layer can be controlled to differ by 10% of the thickness of the grinding stop layer. In this embodiment, the material of the second medium is selected as an organic anti-reflection material. Specifically, the organic anti-reflection layer of the second preset thickness can be removed by dry etching.

[0045] In the dry etching process of the organic anti-reflection material, chlorine (Cl2 / O2) etchant, hydrogen bromide (HBr / O2) etchant, carbon tetrafluoride (CF4 / O2) etchant and / or oxygen (O2 / N2) etchant can be used to remove the organic anti-reflection material. In this embodiment, no specific limitation is made. In other embodiments, the method of removing the second dielectric material will be different depending on the characteristics of the material of the second dielectric 5. When the organic anti-reflection material of the second preset thickness is removed by the dry etching method, by adjusting the parameters such as the etching gas, the plasma RF power supply and the reaction chamber pressure, the damage of the plasma to the grinding stop layer in the first dielectric film during the back etching process can be reduced or eliminated.

[0046] The main purpose of filling the second medium in the shallow trench of the first pattern density value is to reduce the height difference of the wafer surface topography to facilitate the subsequent etching of the pattern of the second pattern density value.

[0047] The etching of the shallow trench isolation structure described above is further expanded and described. After the etching of the shallow trench isolation structure of the first pattern density value is completed, refer to Figure 7 or Figure 8 As shown, a second photoresist coating, exposure and development are performed on the basis of the shallow trench isolation structure with a first pattern density value.

[0048] The following combination Figure 7 , Figure 8 and Fig. 9 , taking the shallow trench isolation structure as an example, the second photolithography and etching process is further described.

[0049] See also Figure 7 ,by Figure 7The shallow trench isolation structure embodiment shown in the figure is described. After the etching of the pattern of the first pattern density value is completed, the photoresist 4b is coated. After the exposure of the mask of the pattern of the second pattern density value, followed by development, the pattern of the second pattern density value is transferred to the photoresist 4b. The area where the first pattern density value needs to be retained is completely covered by the photoresist 4b, and the area of ​​the second pattern density value forms a second opening area 42 with a larger size than the area of ​​the first pattern density value. In this embodiment, the first dielectric film: the oxide layer and the grinding stop layer and the part of the wafer substrate form a shallow trench of the first pattern density value.

[0050] See also Figure 8 , Figure 8 The figure shows another embodiment of the second photolithography of the shallow trench isolation structure embodiment. Figure 7 Basically the same, in this embodiment, Figure 7 The difference is that the pattern of the mask used for the second exposure may be an overall pattern obtained by combining the area of ​​the first pattern density value and the area of ​​the second pattern density value.

[0051] See also Fig. 9 , Fig. 9 for Figure 7 or Figure 8 After the second etching, a shallow trench isolation structure is finally formed on the surface of the wafer substrate. Figure 7 or Figures 8 to 9 It can be seen from the difference that the main purpose of the second etching is to further completely etch away the pattern of the first pattern density value in the position where the pattern of the second pattern density value needs to be formed. Figure 7 or Figure 8 The etching of the second pattern density value is completed by etching the first dielectric film, etching the filled organic anti-reflection layer, and etching the wafer substrate silicon at the location of the larger opening in the region of the second pattern density value. The steps of degumming and some cleaning after etching are omitted here.

[0052] Figure 7 and Figure 8 In contrast, Figure 7 and Figure 8 When the second etching is performed, Figure 8 compared to Figure 7 The organic anti-reflection material in the area with the first pattern density value is to be etched. The second dielectric material filled in the area with the first pattern density value is also a material to be etched in the area with the second pattern density value. Figure 8 and Figure 7 Both methods are acceptable. Figure 7 The method shown is relatively Figure 8 The solution shown is more optimized. Figure 7In this way, the pattern density values ​​are concentrated in the area of ​​the second pattern density value, and the uniformity of the size of the exposed pattern is high, which is conducive to improving the stability and accuracy of the photolithography process. Figure 7 As shown, when the area with the first pattern density value is etched for the second time, the difference in size between the pattern density value and the second pattern density value, as well as the difference in etching materials of the two areas, will affect the second etching process to varying degrees. In this embodiment, the second dielectric material can also be removed by other methods, and finally the following can be obtained: Fig. 9 The etched pattern shown.

[0053] The etchants used in each etching stage in the second etching process are described as follows: the nitride layer 3 and the oxide layer 2 can be removed by using carbon tetrafluoride (CF4 / CHF3 / Ar) etchant, trifluoromethane (CHF3 / Ar) etchant and / or (CHF3 / SF6) etchant. Specifically, in this embodiment, the etching gas containing CHF3 and SF6 is used to remove the portion of the nitride layer 3 and the oxide layer 2 exposed in the window pattern. The top portion of the silicon substrate and the polymer byproducts left from the etching of the nitride layer 3 and the oxide layer 2 can be removed by using carbon tetrafluoride (CF4 / Ar) etchant, CHF3 / SF6 and / or argon (Ar) etchant. Cl2 / O2 / N2, HBr / O2, Cl2 / HBr / O2, Cl2 / HBr / CF4 and / or Cl2 / O2 / SF6 etchants can be used to etch into the silicon substrate. Specifically, in this embodiment, the silicon substrate is etched using an etching gas containing Cl2, O2, and SF6.

[0054] In the formation Fig. 9 After the shallow trench is shown, an insulating oxide will be filled in the shallow trench, and the thickness of the filled insulating material will be controlled to be slightly lower than the grinding stop layer by chemical mechanical polishing. Those skilled in the art call this structure a shallow trench isolation structure. The shallow trench isolation structure affects the insulation performance between devices, and the morphology of the shallow trench etching in the shallow trench isolation structure also directly affects the electrical parameters of the device.

[0055] In the above embodiments, the etching method of the present invention is mainly described by taking the shallow trench isolation structure as an embodiment. The above embodiments split the etching pattern of the shallow trench into two different graphic density values, and perform photolithography and etching in two times, which can effectively ensure the uniformity of the depth and morphology of the shallow trench isolation structure in each area with different graphic density values. If the overall process cost is not considered, for the etching pattern with a large range of graphic density value variation, under the premise of exceeding the window of the manufacturing performance and / or process parameters of the etching machine, the pattern to be etched once can also be disassembled into three or more etchings according to the etching method provided by the present invention. Based on different process technology nodes, the process requirements are different, which will cause D1 and D2 to change with different process requirements. Therefore, in the embodiments described above, the specific values ​​of the first graphic density value and the second graphic density value are not directly given.

[0056] The above embodiments are preferred implementation modes of the present invention, but the implementation modes of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principles of the present invention should be equivalent replacement methods and are included in the protection scope of the present invention.

Claims

1. An etching method in a semiconductor process, characterized in that: The etching object of the etching method is a wafer, and a first dielectric film is formed on the surface of the wafer; The etching pattern comprises at least a first region and a second region, the first region of the etching pattern has a first pattern density value, and the second region of the etching pattern has a second pattern density value; The first pattern density value is greater than the second pattern density value; the etching method comprises: Step S1: forming a pattern of the first graphic density value on the surface of the wafer by a first photolithography and etching process; after the first etching process, retaining the first dielectric film corresponding to the pattern of the first graphic density value; Filling a second dielectric material on the wafer surface of the pattern of the first graphic density value, wherein the filling capacity of the second dielectric material is greater than that of the material of the first dielectric film; removing the second dielectric material by a second preset thickness, so that the height difference between the second dielectric material on the wafer surface and the first dielectric film is at a first preset value; Step S2: forming a pattern of the second pattern density value on the surface of the wafer by a second photolithography and etching process on the pattern of the first pattern density value; The pattern of the mask used for exposure during the second photolithography process is an overall pattern obtained by combining the area with the first pattern density value and the area with the second pattern density value.

2. The etching method in a semiconductor process according to claim 1, characterized in that: The etching pattern is a shallow trench isolation structure.

3. The etching method in a semiconductor process according to claim 1, characterized in that: The first dielectric film includes an oxide layer and a grinding stop layer, and the oxide layer is attached to the surface of the wafer.

4. The etching method in a semiconductor process according to claim 1, characterized in that: The photoresist of the first photolithography process is coated on the surface of the first dielectric film.

5. The etching method in a semiconductor process according to claim 1, characterized in that: The second medium is an organic anti-reflection material.

6. The etching method in a semiconductor process according to claim 1, characterized in that: The second dielectric material is filled to a first preset thickness higher than the first dielectric film.

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