Method for manufacturing semiconductor device, device and electronic equipment

Abstract

The present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate on which a gate structure and source / drain regions are formed, and sigma trenches are formed in the source / drain regions; etching the surface of the sigma trenches to remove the native oxide layer formed on the surface; moving the substrate after removing the native oxide layer into an epitaxial chamber while maintaining a vacuum, and H2 is introduced into the epitaxial chamber; baking the sidewalls of the sigma trenches in an environment of H2 to repair the damage to the sidewalls of the sigma trenches; and introducing a first gas to form a germanium-silicon thin film transition layer on the sidewalls of the sigma trenches, wherein the first gas includes GeH4 gas; forming a germanium-silicon seed layer and a germanium-silicon main layer in the sigma trenches; wherein the germanium content in the germanium-silicon thin film transition layer is less than the germanium content in the germanium-silicon seed layer. This technical solution improves the growth quality of the germanium-silicon seed layer.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular, to a method for manufacturing a semiconductor device, a device, and an electronic device. Background Art

[0002] With the reduction of the size of semiconductor devices and the demand for performance improvement, the performance of conventional PMOSs can no longer meet the device requirements. In order to improve the channel mobility of PMOSs, the SiGe epitaxial process is introduced. The SiGe epitaxial process has high requirements for the cleanliness and lattice integrity of the substrate. The traditional SiGe process uses the SiCoNi process to remove the native oxide layer inside the trench. The plasma of the SiCoNi process is likely to damage the substrate, resulting in dislocation defects in the growth of the germanium-silicon process; and dislocations will cause stress release of SiGe, resulting in the electrical properties of the device not meeting the requirements.

[0003] Therefore, how to improve the quality of the SiGe epitaxial layer in PMOS devices has become a key technical problem to be solved by those skilled in the art. Summary of the Invention

[0004] The present invention provides a method for manufacturing a semiconductor device, a device, and an electronic device to solve the problem of how to improve the growth quality of the germanium-silicon seed layer.

[0005] According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including:

[0006] providing a substrate, wherein a gate structure and source-drain regions are formed on the substrate, and a sigma trench is formed in the source-drain regions;

[0007] etching the surface of the sigma trench to remove the native oxide layer formed on the surface of the sigma trench;

[0008] transferring the substrate after removing the native oxide layer into an epitaxial chamber under a vacuum-maintaining condition, and H 2 is introduced into the epitaxial chamber;

[0009] baking the sidewalls of the sigma trench in an environment of H 2 to repair the damage to the sidewalls of the sigma trench; and introducing a first gas to form a germanium-silicon thin film transition layer on the sidewalls of the sigma trench, wherein the first gas includes GeH 4 gas;

[0010] A germanium-silicon seed layer and a germanium-silicon bulk layer are formed in the sigma trench; wherein, the germanium-silicon seed layer is formed on the surface of the germanium-silicon thin film transition layer, and the germanium-silicon bulk layer is formed on the surface of the germanium-silicon seed layer;

[0011] Wherein, the thickness of the germanium-silicon thin film transition layer is less than the thickness of the germanium-silicon seed layer, and the germanium content in the germanium-silicon thin film transition layer is less than the germanium content in the germanium-silicon seed layer.

[0012] Optionally, the baking treatment is carried out in parallel with the formation of the germanium-silicon thin film transition layer on the sidewall of the sigma trench.

[0013] Optionally, the baking treatment is first carried out to repair the damage to the sidewall of the sigma trench, and then the germanium-silicon thin film transition layer is formed on the sidewall of the sigma trench.

[0014] Optionally, the thickness of the germanium-silicon thin film transition layer is less than The atomic percentage of germanium in the germanium-silicon thin film transition layer is less than 10%.

[0015] Optionally, the atomic percentage of germanium in the germanium-silicon seed layer is: 25% - 33%.

[0016] Optionally, the first gas further includes dichlorosilane for adjusting the germanium concentration in the germanium-silicon thin film transition layer.

[0017] Optionally, the temperature of the baking treatment is 600 - 800 degrees, and the pressure is 10 - 200 Torr; the time of the baking treatment is 10 - 300 s, the flow rate of H 2 is 5 slm - 50 slm; the flow rate of GeH 4 is: 10 - 500 sccm.

[0018] Optionally, the flow rate of the dichlorosilane is: 0 - 200 sccm.

[0019] According to the second aspect of the present invention, there is also provided a semiconductor device prepared by using the preparation method of the semiconductor device according to any one of the first aspect of the present invention.

[0020] In addition, according to the third aspect of the present invention, there is also provided an electronic device including the semiconductor device according to the second aspect of the present invention.

[0021] The preparation method of the semiconductor device provided by the present invention bakes the sidewall of the sigma trench in an H 2 environment to repair the damage to the sidewall of the sigma trench, thereby avoiding dislocations; and introducing a gas including GeH 4The first gas of the gas is used to form a germanium-silicon thin film transition layer on the side wall of the sigma trench. On the one hand, the germanium-silicon thin film transition layer has a flat and orderly single crystal structure, which improves the repair effect; on the other hand, since there are already certain lattice changes in the grown germanium-silicon thin film transition layer, it is beneficial to the subsequent epitaxial growth of germanium-silicon; and since the content of germanium in the germanium-silicon thin film transition layer is less than the content of germanium in the germanium-silicon seed layer, and the thickness of the germanium-silicon thin film transition layer is less than the thickness of the germanium-silicon seed layer; thus, there is a transition between the substrate and the germanium-silicon seed layer, which improves the growth quality of the germanium-silicon seed layer, and further improves the growth quality of the germanium-silicon epitaxial layer; realizing the improvement of the device yield and reliability. Brief Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 is a schematic structural diagram of a traditional semiconductor device;

[0024] Figure 2 is a schematic flow chart of the manufacturing process of a traditional semiconductor device;

[0025] Figure 3 is a schematic flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0026] Figure 4 is a schematic structural diagram of a semiconductor device manufactured according to a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0027] Figure 5 is a schematic diagram of the device structures at different process stages manufactured according to a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 1 ;

[0028] Figure 6 is a schematic diagram of the device structures at different process stages manufactured according to a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 2 ;

[0029] Figure 7 is a schematic diagram of the device structures at different process stages manufactured according to a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 3 ;

[0030] Figure 8Schematic diagrams of device structures at different process stages prepared according to a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 4 ;

[0031] Figure 9 Schematic diagrams of device structures at different process stages prepared according to a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 5 ;

[0032] Figure 10 Schematic diagrams of device structures at different process stages prepared according to a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 6 ;

[0033] Figure 11 Schematic diagrams of device structures at different process stages prepared according to a method for manufacturing a semiconductor device provided by an embodiment of the present invention Figure 7 ;

[0034] Description of reference numerals:

[0035] 101 - Substrate;

[0036] 102 - Germanium silicon seed layer;

[0037] 103 - Germanium silicon main layer;

[0038] 104 - Germanium silicon germanium silicon capping layer;

[0039] 105 - Sidewall structure;

[0040] 106 - Gate oxide layer;

[0041] 107 - Gate material layer;

[0042] 108 - Gate passivation layer;

[0043] 201 - Substrate;

[0044] 202 - Mask layer;

[0045] 203 - Germanium silicon thin film transition layer;

[0046] 204 - Germanium silicon seed layer;

[0047] 205 - Germanium silicon main layer;

[0048] 206 - Germanium silicon capping layer;

[0049] 207 - Sidewall;

[0050] 208 - Gate oxide layer;

[0051] 209 - Gate material layer;

[0052] 210 - Gate passivation layer;

[0053] 211 - Native oxide layer;

[0054] 212 - Sigma trench. Detailed implementation manners

[0055] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0056] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0057] The semiconductor device in the present invention generally refers to a PMOS device, and its device structure can be as Figure 1 shown.

[0058] Combined with Figure 1 and Figure 2 , the manufacturing process of a traditional PMOS device includes the following steps:

[0059] S1: Provide a substrate 101;

[0060] S2: Form a gate structure on the substrate 101;

[0061] Among them, the gate structure can specifically include, for example: a gate oxide layer 106, a gate material layer 107, and a gate passivation layer 108 stacked in sequence along the direction away from the substrate 101; and sidewall structures 105 are formed on both sides of the gate oxide layer 106, the gate material layer 107, and the gate passivation layer 108;

[0062] S3: Form a mask layer; the mask layer is specifically formed on the surfaces of the gate passivation layer 108, the sidewall structures 105, and the substrate 101;

[0063] S4: Pattern the mask layer to expose the source / drain regions; and use the patterned mask layer as a mask to etch the source / drain regions to form U-shaped source / drain trenches.

[0064] S5: Further etch the U-shaped source / drain trenches to form sigma trenches; at this time, since the sigma trenches are exposed to the air, a natural oxide layer will be generated on their sidewalls and bottoms.

[0065] S6: Etch the natural oxide layer on the sidewalls and bottoms of the sigma trenches to expose the substrate 101 on the sidewalls and bottoms of the sigma trenches.

[0066] S7: Form a germanium-silicon seed layer 102, a germanium-silicon main layer 103, and a germanium-silicon germanium-silicon capping layer 104; wherein, the germanium-silicon seed layer 102 is formed on the surface of the substrate 101 in the exposed sigma trenches, and the germanium-silicon main layer 103 is formed on the surface of the germanium-silicon seed layer 102; the germanium-silicon germanium-silicon capping layer 104 is formed on the top of the germanium-silicon main layer 103.

[0067] In the above-mentioned existing process method of PMOS devices, in step S6, generally the SiCoNi process is used to etch the surface of the sigma trenches to remove the natural oxide layer formed on the surface of the sigma trenches, and after removing the natural oxide layer, a germanium-silicon epitaxial layer is directly formed in the sigma trenches.

[0068] However, the plasma from the SiCoNi process will damage the sidewalls of the sigma trenches, resulting in surface defects of the sigma trenches. Due to the lattice damage on the sidewalls of the sigma trenches, during the subsequent process growth of the germanium-silicon epitaxial layer, dislocations are likely to occur, and the dislocations will cause stress release of the germanium-silicon epitaxial layer, thus making the performance of the finally obtained PMOS device unable to meet the requirements.

[0069] In view of this, the inventors of the present application have carried out repeated experiments and demonstrations, and proposed a new method for manufacturing semiconductor devices, specifically as follows: Prepare a gate structure on a substrate and cover a mask layer (as shown in Figures 5 - 11 202); etch U-shaped depressions on both sides of the gate structure; perform TMAH etching on the U-shaped depressions to form sigma trenches (Σ trench structure); perform SiCoNi etching on the sigma trenches to remove the natural oxide layer; then transfer the substrate into an epitaxial chamber under a vacuum condition, and bake the sidewalls of the sigma trenches in an environment of H 2 to repair the damage to the sidewalls of the sigma trenches; and introduce a first gas of GeH 4 gas to form a germanium-silicon thin film transition layer on the sidewalls of the sigma trenches; finally, perform the SiGe epitaxial layer process.

[0070] It can be seen that in the technical solution provided by the present application, before the traditional germanium-silicon epitaxial process, the sidewalls of the sigma trenches are baked in an H 2 environment to repair the damage to the sidewalls of the sigma trenches, thereby avoiding dislocations; and a first gas including GeH 4 gas is introduced to form a germanium-silicon thin film transition layer on the sidewalls of the sigma trenches. On the one hand, the germanium-silicon thin film transition layer has a flat and orderly single crystal structure, improving the repair effect; on the other hand, since there are already certain lattice changes in the grown germanium-silicon thin film transition layer, it is beneficial to the subsequent epitaxial growth of germanium-silicon; and since the content of germanium in the germanium-silicon thin film transition layer is less than the content of germanium in the germanium-silicon seed layer, and the thickness of the germanium-silicon thin film transition layer is less than the thickness of the germanium-silicon seed layer; thus, there is a transition between the substrate and the germanium-silicon seed layer, improving the growth quality of the germanium-silicon seed layer, and further improving the growth quality of the germanium-silicon epitaxial layer; realizing the improvement of the device yield and stability.

[0071] Hereinafter, the technical solution of the present invention will be described in detail with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0072] Please refer to Figures 3 - 11 , according to an embodiment of the present invention, a method for manufacturing a semiconductor device is provided, and the method specifically includes the following steps:

[0073] S21: Provide a substrate 201, wherein a gate structure and source-drain regions are formed on the substrate 201, and sigma trenches 212 are formed in the source-drain regions, as Figure 7 shown.

[0074] Among them, a natural oxide layer 211 is formed on the sidewalls of the sigma trenches 212, as Figure 8 shown.

[0075] Among them, in one embodiment, step S21 may specifically include:

[0076] S211: Prepare a gate structure on the substrate.

[0077] Among them, as an example, the gate structure specifically includes: a gate oxide layer 208, a gate material layer 209, and a gate passivation layer 210 stacked in a direction away from the substrate; and spacers 207 are formed on both sides of the gate oxide layer 208, the gate material layer 209, and the gate passivation layer 210. Of course, this gate structure is only an example, and the present invention is not limited thereto, and other forms of gate structures can also be applied in the present invention.

[0078] S212: Form a mask layer 202, and the mask layer covers the surfaces of the substrate and the gate structure, asFigure 5 as shown

[0079] S213: Pattern the mask layer 202 to expose the substrate 201 of the source / drain region.

[0080] S214: Using the patterned mask layer 202 as a mask, etch the substrate 201 to form source / drain trenches, as Figure 6 shown

[0081] S215: Further etch the source / drain trenches to form sigma trenches 212, as Figure 7 shown

[0082] At this time, since the sigma trenches 212 will be oxidized in the air, a natural oxide layer 211 will be formed on its sidewalls and bottom, as Figure 8 shown

[0083] S22: Etch the surface of the sigma trenches 212 to remove the natural oxide layer 211 formed on the surface of the sigma trenches 212.

[0084] The device structure after removing the natural oxide layer 211 formed on the surface of the sigma trenches 212 is as Figure 9 shown. Among them, Figure 9 the position pointed by the arrow in [figure] indicates the defects formed on the surface of the sigma trenches 212 after etching the surface of the sigma trenches 212 to remove the natural oxide layer 211.

[0085] Among them, when etching the surface of the sigma trenches 212, the SiCoNi process is adopted.

[0086] S23: Transfer the substrate 201 after removing the natural oxide layer 211 into the epitaxial chamber under vacuum conditions, and H 2 is introduced into the epitaxial chamber.

[0087] Among them, in the epitaxial chamber with a reducing atmosphere of H 2 , the formation of a natural oxide layer in the sigma trenches again can be avoided, so as to ensure that the subsequent grown germanium-silicon thin film transition layer grows based on the substrate material.

[0088] S24: Bake the sidewalls of the sigma trenches 212 in an environment of H 2 to repair the damage to the sidewalls of the sigma trenches 212; and introduce a first gas to form a germanium-silicon thin film transition layer 203 on the sidewalls of the sigma trenches 212. Among them, the first gas includes GeH 4 gas; the device structure after forming the germanium-silicon thin film transition layer 203 on the sidewalls of the sigma trenches 212 is as Figure 10 shown

[0089] In one embodiment, the first gas further includes dichlorosilane, which is used to adjust the concentration of germanium in the germanium-silicon thin film transition layer 203, and further adjust the growth quality of the germanium-silicon thin film transition layer 203.

[0090] In one embodiment, the thickness of the germanium-silicon thin film transition layer 203 is less than The atomic percentage of germanium in the germanium-silicon thin film transition layer 203 is less than 10%.

[0091] Among them, due to the first gas introduced into the reduction atmosphere of H 2 , a germanium-silicon thin film transition layer 203 with a thickness less than can be grown, so that when the size of the sigma trench 212 is certain, the thickness requirement of the germanium-silicon main layer 205 can be met.

[0092] S25: Form a germanium-silicon seed layer 204 and a germanium-silicon main layer 205 in the sigma trench 212; wherein, the germanium-silicon seed layer 204 is formed on the surface of the germanium-silicon thin film transition layer 203, and the germanium-silicon main layer 205 is formed on the surface of the germanium-silicon seed layer 204, as Figure 11 shown.

[0093] Among them, the thickness of the germanium-silicon thin film transition layer 203 is less than the thickness of the germanium-silicon seed layer 204, and the content of germanium in the germanium-silicon thin film transition layer 203 is less than the content of germanium in the germanium-silicon seed layer 204.

[0094] In one embodiment, the atomic percentage of germanium in the germanium-silicon seed layer 204 is: 25% - 33%.

[0095] Among them, due to the technical solution provided by the present invention, the atomic percentage of germanium in the germanium-silicon thin film transition layer 203 is less than the atomic percentage of germanium in the germanium-silicon seed layer 204, so that a transition is formed between the Si substrate and the germanium-silicon seed layer 204, which is beneficial to growing a high-quality germanium-silicon seed layer 204 on the surface of the germanium-silicon thin film transition layer 203.

[0096] Among them, since the lattice of the substrate 201 on the side wall of the sigma groove 212 will be damaged during the process of removing the natural oxide layer 211 in the above step S23, during the subsequent epitaxial growth process of the germanium silicon seed layer 204, the damaged lattice substrate 201 is likely to cause dislocations in the germanium silicon seed layer 204. Specifically, growing a germanium silicon layer without repairing the defects of the substrate 201 can easily lead to dislocations; and since a relatively high Ge concentration (the atomic percentage of Ge is 25% to 33%) is required to grow the germanium silicon seed layer 204, if the germanium silicon seed layer is grown directly on the Si substrate, it will cause lattice mismatch between the Si substrate and the germanium silicon seed layer due to the large difference in lattice constants, which will also lead to dislocations. Therefore, the present invention achieves this goal by using H 2 The sidewalls of the sigma trench 212 are baked in an environment to repair damage to the sidewalls of the sigma trench 212; and a GeH 4 The first gas of the gas is used to form a germanium-silicon thin film transition layer 203 on the side wall of the sigma groove 212. The germanium-silicon thin film transition layer 203 repaired and grown by this process is a single crystal structure, its surface is flat and orderly, and does not require a subsequent annealing step. In addition, during the baking process, the grown germanium-silicon thin film transition layer 203 has undergone a certain lattice change (transition from the Si of the substrate to SiGe with a lower germanium content), which is beneficial to the subsequent epitaxial growth of the germanium-silicon seed layer 204. And because the germanium content in the germanium-silicon thin film transition layer 203 is low, the lattice constant between it and the Si substrate is not much different, and dislocations caused by lattice mismatch will not occur. Therefore, on the one hand, the technical solution provided by the present invention, in H 2 The sidewalls of the sigma groove 212 are baked in an environment to repair the lattice damage on the sidewall surface of the sigma groove 212, thereby achieving the technical effect of avoiding dislocations; on the other hand, a germanium-silicon thin film transition layer 203 is formed on the sidewalls of the sigma groove 212, which is beneficial to the growth of the seed layer in the subsequent step S24, thereby improving the growth quality of the germanium-silicon seed layer 204, and thereby improving the yield and reliability of the device.

[0097] Step S24 is further described in detail below:

[0098] In one embodiment, in step S24, the baking process is performed in parallel with forming the germanium-silicon thin film transition layer 203 on the sidewall of the sigma trench 212; specifically, H is introduced into the epitaxial chamber. 2 The simultaneous input includes GeH 4 The first gas of the gas, thus in H 2Under the environment of, bake the side walls of the sigma trench 212 to repair the damage to the side walls of the sigma trench 212 while forming a germanium-silicon thin film transition layer 203 on the side walls of the sigma trench 212; that is, it can be understood that when starting the baking process, simultaneously introduce H 2 gas and GeH 4 gas.

[0099] Among them, when the baking process is carried out in parallel with the formation of the germanium-silicon thin film transition layer 203 on the side walls of the sigma trench 212, a specific process is: when the flow rate of H 2 is 5 slm to 50 slm, the pressure is 10 to 200 Torr, the flow rate of GeH4 gas is 10 to 500 sccm, and the baking time is 10 to 300 s.

[0100] Of course, in this case, dichlorosilane can also be introduced while introducing GeH 4 gas, that is, while introducing GeH 4 gas with a flow rate of 10 to 500 sccm, dichlorosilane with a flow rate of 0 to 200 sccm can also be introduced.

[0101] Among them, the flow rate of dichlorosilane and the flow rate of GeH 4 gas can be specifically adjusted according to actual needs to adjust the concentration of germanium in the formed germanium-silicon transition layer.

[0102] Among them, in the technical solution provided in this embodiment, high-temperature baking simultaneously does not affect the number of wafers produced per hour (WPH, Wafer Per Hour).

[0103] In order to further improve the repair effect, in another embodiment, in step S24, first perform the baking process to repair the damage to the side walls of the sigma trench 212, and then form a germanium-silicon thin film transition layer 203 on the side walls of the sigma trench 212. Specifically: first bake the side walls of the sigma trench 212 in an environment of H 2 to repair the damage to the side walls of the sigma trench 212; after a period of time, then introduce the first gas to form a germanium-silicon thin film transition layer 203 on the side walls of the sigma trench 212, where the first gas includes GeH 4 gas. Among them, the above-mentioned period of time can be understood as the time required for complete repair of the damage, or it can be understood as the time required for partial repair of the damage. That is, in this embodiment, the damage to the side walls of the sigma trench 212 can be fully repaired first, and then GeH 4 gas is introduced; or the damage to the side walls of the sigma trench 212 can be partially repaired first, and then GeH 4Gas. Since the sidewalls of the sigma trench 212 are more fully repaired in this way, the growth quality of the germanium-silicon seed layer will be relatively better.

[0104] Among them, when the baking treatment is first performed to repair the damage to the sidewalls of the sigma trench 212, and then a germanium-silicon thin film transition layer is formed on the sidewalls of the sigma trench 212, a specific process is as follows: First, in an environment where the flow rate of H 2 is 5 slm to 50 slm, the sidewalls of the sigma trench 212 are baked at 600 to 800 degrees, and the pressure is 10 to 200 Torr to repair the damage to the sidewalls of the sigma trench 212; then a first gas is introduced to form a germanium-silicon thin film transition layer 203 on the sidewalls of the sigma trench 212. Among them, the first gas includes a flow rate of: 10 to 500 sccm of GeH 4 gas; among them, the time of the baking treatment is 10 to 300 s. Under these process conditions, the technical effect of growing a high-quality germanium-silicon seed layer 204 on the surface of the germanium-silicon thin film transition layer 203 can be achieved.

[0105] Similarly, in this case, dichlorosilane can also be introduced while introducing GeH 4 gas, that is, while introducing GeH with a flow rate of 10 to 500 sccm 4 gas, it is also necessary to simultaneously introduce the dichlorosilane with a flow rate of 0 to 200 sccm to adjust the concentration of germanium in the germanium-silicon thin film transition layer 203, and further adjust the growth quality of the germanium-silicon thin film transition layer 203.

[0106] In one embodiment, the method for manufacturing the semiconductor device further includes:

[0107] S26: Form a germanium-silicon capping layer 206; the germanium-silicon capping layer 206 is formed at the top of the germanium-silicon main layer 205; as Figure 11 shown.

[0108] S27: Remove the mask layer 202, as Figure 4 shown.

[0109] In addition, according to an embodiment of the present invention, there is also provided a semiconductor device, as Figure 4 shown, which is manufactured by using the method for manufacturing a semiconductor device according to any one of the foregoing embodiments of the present invention.

[0110] Again, according to an embodiment of the present invention, there is also provided an electronic device, including the semiconductor device according to the foregoing embodiment of the present invention.

[0111] Finally, according to an embodiment of the present invention, there is also provided a method for manufacturing an electronic device, including the method for manufacturing a semiconductor device according to any one of the foregoing embodiments of the present invention.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, comprising: providing a substrate, wherein a gate structure and source-drain regions are formed on the substrate, and a sigma trench is formed in the source-drain regions; etching the surface of the sigma trench to remove the native oxide layer formed on the surface of the sigma trench; Transfer the substrate after removing the native oxide layer into the epitaxial chamber while maintaining a vacuum. The epitaxial chamber is introduced with H 2 ; Under the condition of H 2 Bake the sidewall of the sigma groove to repair the damage to the sidewall of the sigma groove; and introduce a first gas to form a germanium-silicon thin film transition layer on the sidewall of the sigma groove, wherein the first gas includes GeH 4 gas; forming a germanium-silicon seed layer and a germanium-silicon bulk layer in the sigma trench; wherein the germanium-silicon seed layer is formed on the surface of the germanium-silicon thin film transition layer, the germanium-silicon thin film transition layer is a flat and orderly single crystal structure, and the germanium-silicon bulk layer is formed on the surface of the germanium-silicon seed layer; wherein the thickness of the germanium-silicon thin film transition layer is less than the thickness of the germanium-silicon seed layer, and the germanium content in the germanium-silicon thin film transition layer is less than the germanium content in the germanium-silicon seed layer.

2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, the baking treatment is carried out in parallel with the formation of the germanium-silicon thin film transition layer on the sidewall of the sigma trench.

3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, first carry out the baking treatment to repair the damage on the sidewall of the sigma trench, and then form the germanium-silicon thin film transition layer on the sidewall of the sigma trench.

4. The method for manufacturing a semiconductor device according to claim 1, characterized in that, wherein, The thickness of the germanium-silicon thin film transition layer is less than The atomic percentage of germanium in the germanium-silicon thin film transition layer is less than 10%.

5. The method for manufacturing a semiconductor device according to claim 4, characterized in that, the atomic percentage of germanium in the germanium-silicon seed layer is: 25% - 33%.

6. The method for manufacturing a semiconductor device according to any one of claims 1-5, characterized in that, the first gas further includes dichlorosilane for adjusting the germanium concentration in the germanium-silicon thin film transition layer.

7. The method for manufacturing a semiconductor device according to claim 6, characterized in that, The temperature used for the baking treatment is 600 to 800 degrees, and the pressure is 10 to 200 Torr; the time of the baking treatment is 10 to 300 s, and the flow rate of H 2 is 5 slm to 50 slm; the flow rate of GeH 4 is: 10 to 500 sccm.

8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, the flow rate of the dichlorosilane is: 0 - 200 sccm.

9. A semiconductor device, characterized in that, it is manufactured by using the method for manufacturing a semiconductor device according to any one of claims 1-8.

10. An electronic device, characterized in that, it includes the semiconductor device according to claim 9.

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